Data processing method, computing device, storage medium, and computer program product

Abstract

The embodiments of the present disclosure relate to the technical field of computers, and in particular relate to a data processing method, a computing device, a storage medium, and a computer program product. The data processing method comprises: receiving a data read request for target written data in a target data write unit, wherein the target data write unit belongs to a data write area, which is used for data writing, and the target written data is synchronously written into the data write area and a data read-write area, which data read-write area is used for data reading and data writing; and when it is determined that the target data write unit does not meet a preset storage condition, reading the target written data from the data read-write area.

Description

Data processing methods, computing devices, storage media and computer program products

[0001] This disclosure claims priority to Chinese Patent Application No. 202411564107.9, filed on November 4, 2024, entitled "Data Processing Method, Computing Device, Storage Medium and Computer Program Product", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of computer technology, and in particular to data processing methods, computing devices, storage media, and computer program products. Background Technology

[0003] In today's data-intensive applications, such as high-performance computing, big data analytics, real-time transaction systems, and cloud services, rapid data access is a critical requirement. Random read / write operations refer to the system's ability to randomly access any location on a storage device to read or write data as needed. Compared to sequential read / write operations, these operations place higher demands on the performance of the storage system.

[0004] However, in the current random read and write operation of data storage devices, data is being continuously written and randomly read at the same time. Since the data storage unit in the data storage device can only perform one of the write or read operations at a time, when read and write operations need to be performed simultaneously, a conflict will occur, resulting in waiting and increased latency, which will affect the data read and write performance of the data storage device. Summary of the Invention

[0005] In view of the above, embodiments of this disclosure provide a data processing method. One or more embodiments of this disclosure also relate to a data processing apparatus, a computing device, a computer-readable storage medium, and a computer program product, to address the technical deficiencies existing in the prior art.

[0006] According to a first aspect of the present disclosure, a data processing method is provided, applied to a data storage device, comprising:

[0007] Receive a data read request for target data already written in the target data writing unit, wherein the target data writing unit belongs to the data writing area, the data writing area is used for data writing, and the target data already written is synchronously written to the data writing area and the data read and write area, the data read and write area is used for data reading and data writing;

[0008] If it is determined that the target data writing unit does not meet the preset storage conditions, the target written data is read from the data read / write area.

[0009] According to a second aspect of the present disclosure, a data processing apparatus is provided, applied to a data storage device, comprising:

[0010] The receiving module is configured to receive a data read request for target data already written in the target data writing unit, wherein the target data writing unit belongs to the data writing area, the data writing area is used for data writing, and the target data already written is synchronously written to the data writing area and the data read and write area, the data read and write area is used for data reading and data writing.

[0011] The reading module is configured to read the target written data from the data read / write area when it is determined that the target data writing unit does not meet the preset storage conditions.

[0012] According to a third aspect of the present disclosure, a computing device is provided, comprising:

[0013] Memory and processor;

[0014] The memory is used to store computer programs / instructions, and the processor is used to execute the computer programs / instructions, which, when executed by the processor, implement the steps of the above-described data processing method.

[0015] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided that stores a computer program / instructions that, when executed by a processor, implement the steps of the data processing method described above.

[0016] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the steps of the data processing method described above.

[0017] One embodiment of this disclosure provides a data processing method applied to a data storage device, comprising: receiving a data read request for target written data in a target data writing unit, wherein the target data writing unit belongs to a data writing area, the data writing area is used for data writing, and the target written data is synchronously written to the data writing area and a data read / write area, the data read / write area is used for data reading and data writing; and reading the target written data from the data read / write area when it is determined that the target data writing unit does not meet preset storage conditions.

[0018] The above method divides the data storage device into a data read / write area and a data write area. The data read / write area can be used for data reading and data writing, and the data write area can be used for data writing. Therefore, after receiving a data read request for target data already written in the target data write unit, if it is determined that the target data write unit does not meet the preset storage conditions, the target data already written can be read directly from the data read / write area without affecting the data writing in the target data write unit. This ensures that there is no conflict between data reading and data writing, thereby reducing latency and ensuring the data read / write performance of the data storage device. Attached Figure Description

[0019] Figure 1 is a schematic diagram of a random read / write scenario of a data storage device according to an embodiment of this disclosure;

[0020] Figure 2 is a schematic diagram of an application scenario of a data processing method provided in an embodiment of this disclosure;

[0021] Figure 3 is a flowchart of a data processing method according to an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of the structure of a data processing device in a data processing method provided in an embodiment of this disclosure;

[0023] Figure 5 is a timing diagram of the data writing area and the data reading and writing area in a data processing method provided in an embodiment of this disclosure;

[0024] Figure 6 is a schematic diagram of data reading and writing area erasure in a data processing method provided in an embodiment of this disclosure;

[0025] Figure 7 is a schematic diagram of data writing area recycling in a data processing method provided in an embodiment of this disclosure;

[0026] Figure 8 is a schematic diagram of a data cache area in a data processing method provided in an embodiment of this disclosure;

[0027] Figure 9 is a schematic diagram of data accumulation in a data buffer in a data processing method provided by an embodiment of this disclosure;

[0028] Figure 10 is a schematic diagram of target data caching in a data processing method provided in an embodiment of this disclosure;

[0029] Figure 11 is a flowchart of a data processing method provided in an embodiment of this disclosure;

[0030] Figure 12 is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of the present disclosure;

[0031] Figure 13 is a structural block diagram of a computing device provided in an embodiment of this disclosure. Detailed Implementation

[0032] Numerous specific details are set forth in the following description to provide a full understanding of this disclosure. However, this disclosure can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this disclosure. Therefore, this disclosure is not limited to the specific implementations disclosed below.

[0033] The terminology used in one or more embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this disclosure. The singular forms “a,” “the,” and “the” as used in one or more embodiments of this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this disclosure refers to and includes any or all possible combinations of one or more associated listed items.

[0034] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this disclosure, and similarly, second may also be referred to as first. Depending on the context, the word “if” as used herein may be interpreted as “when”, “in response to a determination”, or “when…”.

[0035] Furthermore, it should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in one or more embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0036] First, the terms and concepts involved in one or more embodiments of this disclosure will be explained.

[0037] SSD: Solid-State Drive, is a data storage device that uses NAND flash memory as the storage medium to store data.

[0038] QoS: Quality of Service refers to a set of requirements in network communication or computer systems to ensure the performance of specific services or applications. QoS aims to ensure the effective utilization of network resources and provide necessary guarantees in terms of bandwidth, latency, packet loss rate, etc., for critical projects or time-sensitive applications.

[0039] Flash memory chips: Flash memory chips are the basic units used to store data in solid-state drives.

[0040] DRAM: Dynamic Random Access Memory, is one of the most commonly used types of main memory in computer systems. It is primarily used for temporary storage of data and instructions and is the main memory area directly accessed by the CPU during operation.

[0041] TLC: Triple-Level Cell, a flash memory technology, refers to a technology where each storage cell can store three bits of information. This means that each cell can represent eight different states, thus increasing storage density.

[0042] pSLC: Pseudo-Single Level Cell, a flash memory technology that uses special programming and management of multi-level cells (MLC) or triple-level cells (TLC) to make them exhibit performance and endurance similar to single-level cells (SLC).

[0043] Host: Refers to a node in a computer network, or a computer that performs the main computing tasks in a computing system. It can be a node device in the network, the main part of computer hardware, or a server or virtual machine in a cloud computing environment.

[0044] Tp: Data retrieval time.

[0045] RT: Data read latency.

[0046] Tprog: Data write latency.

[0047] RP: RAID parity, which can be understood as accumulating data.

[0048] In practical applications, SSDs, as a fundamental underlying storage component in the data processing field, have been widely used in various project scenarios. With the development and deployment of high-concurrency, high-throughput applications, the read and write operations handled by SSDs have tended towards random read and write. Currently, write caching can reduce data write latency, but data read latency still exists. The read performance of SSDs, as data storage devices, is unstable, necessitating the limitation of the probability distribution of data read latency.

[0049] Referring to Figure 1, which illustrates a random read / write scenario of a data storage device according to an embodiment of this disclosure, the data storage device (i.e., SSD) can be applied to multi-stream concurrent and mixed read / write scenarios. In Figure 1, S1, S2...Sk represent k independent data write streams from the application. These data write streams can maintain sequential write operations, but after passing through the host transmission path and entering the write cache of the data storage device, they become out of order. Therefore, the process of writing to the SSD's flash memory can be understood as a random data write process. While the application is continuously writing data, it is also randomly reading data from the SSD. Due to the characteristics of flash memory chips, the same flash memory chip can only perform one of three operations at a time: data write, data read, or data erase. Therefore, if the current data read operation is performed on a flash memory chip that is currently performing a data write or data erase operation, a wait will occur due to the conflict between data read, data write, and data erase, resulting in increased data read latency and affecting the QoS of the data read operation.

[0050] Typically, write pauses can be used to buffer high latency caused by data read / write conflicts. Specifically, a data block can be partitioned from each flash memory chip for both writing and erasing. When a read and write operation conflict, waiting for the write operation to complete incurs the write latency of the entire write operation, which is then added to the read latency, significantly increasing read latency. When the data storage device receives the read operation and confirms the read / write conflict, it can issue a write pause command to the currently running write operation and initiate the read operation, reducing read latency. The flash memory requires a transition time of Ts from issuing the write pause command to initiating the read operation. The read operation itself takes RT. After notifying the controller, the controller resumes the paused write operation. The transition time from issuing the write operation to the flash memory chip being able to continue writing is Ts. After adopting write pausing, the read latency becomes the sum of the transition time Ts and the read latency RT. This method can only improve performance slightly and cannot effectively eliminate the problem. Furthermore, since read operations issued by applications are unpredictable, pausing writes for every read-write conflict will reduce data write performance, increase write cache pressure, and thus increase the risk of data loss. Frequent use of write pausing will also significantly shorten the lifespan of flash memory and reduce the reliability of written data. Therefore, an effective technical solution is urgently needed to address these issues.

[0051] This disclosure provides a data processing method, and also relates to a data processing apparatus, a computing device, a computer-readable storage medium, and a computer program product, which will be described in detail in the following embodiments.

[0052] Referring to Figure 2, Figure 2 illustrates an application scenario of a data processing method provided according to an embodiment of the present disclosure.

[0053] As shown in Figure 2, Figure 2 includes a host 202 and a data storage device 204. The data storage device includes a data writing area and a data reading and writing area.

[0054] In practice, data operations performed by the user on the host will store the corresponding data in the data storage device. For example, if the user installs application A on the host, the data corresponding to application A will be written to the data storage device. At this time, the data storage device 204 responds to the data write request of application A and simultaneously writes the data to be written carried in the data write request to the target data write unit and the data read / write area in the data write area. When application A needs to read data, the data storage device 204 responds to the data read request of application A and, if it determines that the target data write unit is not full, reads data from the data read / write area to avoid the impact caused by data read / write conflicts.

[0055] Referring to Figure 3, Figure 3 shows a flowchart of a data processing method provided according to an embodiment of the present disclosure, applied to a data storage device, specifically including the following steps.

[0056] Step 302: Receive a data read request for the target data already written in the target data writing unit, wherein the target data writing unit belongs to the data writing area, the data writing area is used for data writing, and the target data already written is synchronously written to the data writing area and the data read / write area, the data read / write area is used for data reading and data writing.

[0057] In this context, the data storage device can be understood as an SSD. The data read / write area can be understood as the pSLC region configured within the flash memory chips of the SSD, which supports both data reading and writing. The data write area can be understood as the TLC region configured within the flash memory chips of the SSD, where data can be written but not read until the TLC region is full. The target data write unit can be understood as one of the data write units included in the data write area.

[0058] Specifically, before receiving a data read request for the target data already written in the target data writing unit, the process also includes:

[0059] In response to a data write request, the data to be written carried in the data write request is written into the target data write unit of the data read / write area and the data write area.

[0060] Based on this, in response to a data write request, the data to be written carried in the data write request can be written to both the pSLC area and the TLC area simultaneously.

[0061] In practical applications, this data write request can be sent by an application installed on the host. Specifically, the application installed on the host can send a data write request to the SSD. The data to be written carried in the data write request can be aggregated in the SSD's DRAM write cache and written to both the pSLC area and the TLC area simultaneously. Based on the characteristics of the SSD's flash memory, the TLC area can be read-only to meet the QoS requirements of the host application, while the pSLC area can be written to before reading to meet the QoS requirements of the host application.

[0062] Specifically, the data writing area includes multiple data writing units, each data writing unit includes multiple data writing blocks, the target data writing unit is any one of the multiple data writing units, the data read and write area includes multiple data read and write blocks, and the number of data writing blocks and the number of data read and write blocks are determined according to a preset ratio.

[0063] In this context, a data write block can be understood as the TLC particles included in a TLC region, a data write unit can be understood as a TLC particle group composed of multiple TLC particles, and a data read / write block can be understood as the pSLC particles included in a pSLC region. Therefore, a target data write unit can be understood as a TLC particle group composed of the currently written TLC particles.

[0064] Specifically, refer to Figure 4, which shows a schematic diagram of the structure of a data processing device in a data processing method according to an embodiment of this disclosure. As shown in Figure 4, the data processing device includes a TLC region (TLC full write-sealed area, currently written and TLC blank particles) and a pSLC region (pSLC currently written and read area). The TLC region contains multiple TLC particles, including blank TLC particles, currently written particles, and full write-sealed TLC particles. It can be understood that blank TLC particles are TLC particles that have not been written to. Data to be written can be written to the current TLC particle. After the current TLC particle is full, it is sealed to obtain a full write-sealed TLC particle, constituting a full write-sealed TLC region. The host interface can be configured with an SSD controller, which is connected to DRAM. The SSD controller is used to control the data processing device to perform dual write and single read operations.

[0065] In practice, to ensure data consistency between the TLC area and the pSLC area, the number of data writing blocks in the data writing unit and the number of data reading blocks in the data reading and writing area can be set according to a preset ratio.

[0066] In practical applications, the configuration of each region in the TLC and pSLC areas can be determined based on the application's throughput, granular capacity, and read / write performance requirements. For example, if the application requirement is 1GB / s and the read latency QoS under write throughput is 99.9% and does not exceed 200us, the following settings can be configured: TLC granule throughput is 170MB / s, and pSLC granule throughput is 540MB / s; the TLC granule capacity is 64GB, corresponding to a pSLC granule capacity of 64 / 3GB. The TLC write latency is 1.6ms, and the read latency is 110us; the pSLC write latency is 110us, and the read latency is 45us. To match the application's write throughput, six TLC granules need to be configured for parallel writing to form a TLC granule group. Therefore, 6 x 64 / (64 / 3) = 18 pSLC granules are needed as the pSLC area. The read latency of a fully written TLC region consisting of TLC chips is 110µs, while the read latency of the pSLC region is 110 + 45 = 155µs in the worst case of write-then-read, both of which meet the application requirement of no more than 200µs.

[0067] In summary, by configuring the number of particles and parameters in each region, data reading latency can be reduced, thus meeting application requirements.

[0068] Step 304: If it is determined that the target data writing unit does not meet the preset storage conditions, read the target written data from the data read / write area.

[0069] The target data writing unit can store written data, including the target data already written. Therefore, the target written data can be understood as the data already written into the target data writing unit. The preset storage condition can be understood as the target data writing unit being full.

[0070] Based on this, in response to a data read request for target data already written to the target data writing unit, if it is determined that the target data writing unit is not yet full, it can be determined that the target data writing unit is still in the current writing state. In order to avoid affecting the writing of other data in the target data writing unit, since the data is written to both the target data writing unit and the data read / write area at the same time, the target data already written can be obtained from the data read / write area.

[0071] In specific implementation, the step of reading the target written data from the data read / write area when it is determined that the target data writing unit does not meet the preset storage conditions includes:

[0072] Determine the amount of data already written in the target data writing unit;

[0073] If it is determined that the amount of data does not meet the preset data threshold, it is determined that the target data writing unit does not meet the preset storage conditions;

[0074] Read the data that has been written to the target from the data read / write area.

[0075] The preset data threshold can be understood as the data storage capacity in the target data writing unit. For example, if the data storage capacity in the target data writing unit is 50M, then the preset data threshold can also be 50M.

[0076] Based on this, the amount of data already written to the target data writing unit can be determined. If the amount of data has not reached the preset data threshold, it means that the target data writing unit is not full, which means that the target data writing unit does not meet the preset storage conditions. In this case, the target written data can be read from the data read / write area.

[0077] In summary, by setting a preset data threshold, it is possible to determine whether the target data writing unit is full, which facilitates the subsequent determination of whether to read data from the target data writing unit or from the data read / write area. Furthermore, if it is determined that the target data writing unit is not full, data is read from the data read / write area to avoid affecting other data writing in the target data writing unit.

[0078] Therefore, after responding to the data read request for the target data already written in the target data writing unit, the method further includes:

[0079] If the target data writing unit is determined to meet the preset storage conditions, the target data already written is read from the target data writing unit.

[0080] Specifically, if the amount of data already written in the target data writing unit is equal to the preset data threshold, the target data writing unit can be determined to meet the preset storage conditions, which means that the target data writing unit has been filled. At this time, the target data writing unit is in a full-filled state, and the target data already written can be read directly from the target data writing unit.

[0081] In summary, if the target data write unit is determined to be full, reading data directly from the target data write unit will not affect the data writing process, thereby reducing data reading latency caused by read-write conflicts.

[0082] In one embodiment of this disclosure, writing the data to be written carried in the data write request into the data read / write area includes:

[0083] If it is determined that the data read / write area is in the process of data reading, after the data reading is completed, the data to be written carried in the data writing request is written to the data read / write area.

[0084] Reading the target data already written from the data read / write area includes:

[0085] If it is determined that the data read / write area is in the process of writing data, the target written data is read from the data read / write area after the data writing is completed.

[0086] Specifically, if other data is being read in the data read / write area before the data to be written is written, the data to be written can be written after the other data has been read. Similarly, if other data is being written in the data read / write area before the target data has been read, the target data can be read after the other data has been written.

[0087] In practical applications, refer to Figure 5, which shows a timing diagram of the data writing area and the data read / write area in a data processing method according to an embodiment of this disclosure. As shown in Figure 5, the TLC area (i.e., the data writing area, including the TLC full-write seal area and the TLC current-write area in the figure) immediately writes data to the TLC current-write area after receiving data from the application. After the TLC current-write area is full, it is sealed as the TLC full-write seal area. The TLC full-write seal area is read-only, and the TLC current-write area is write-only. When the pSLC area (i.e., the data read / write area, including the pSLC current-write-read area in the figure, which handles both reading and writing) receives data to write, if there are no data reading or data erasure operations, it writes immediately, taking approximately 110µs (Tp). If there is a read request from the application during the writing process, the read operation is performed after the current write operation is completed, and the write pause is not performed during the writing process. If a write command is received while a read operation is still in progress, the write operation is performed after the current data read is completed. Since the Tp of the pSLC region is approximately 1 / 14 of the Tprog of the TLC region, there is a significant time window available for read operations after the write operations in the pSLC region are completed. A write operation (i.e., a write event) can be understood as data being written, and a read operation (i.e., a read request) can be understood as data being read.

[0088] In summary, by waiting for data writing and data reading in the data read / write area, the data reading latency requirement can be met without affecting data reading and data writing.

[0089] In one embodiment of this disclosure, the method further includes:

[0090] If the data read / write area meets the preset erasure conditions, the data already written in the data read / write area is erased to obtain a blank data read / write area, so that the data to be written can be written into the blank data read / write area.

[0091] The preset erase condition can be understood as the data read / write area being full. The data already written to the data read / write area can be understood as the data that has been written into the data read / write area.

[0092] Specifically, if the data read / write area is full, the data already written to the data read / write area can be erased to obtain a blank data read / write area, which will facilitate the subsequent writing of data to be written to the blank data read / write area.

[0093] Understandably, the data storage capacity of the data writing unit in the data writing area and the data storage capacity of the data reading and writing area can be the same. That is to say, when a data writing unit is full, the data reading and writing area is also full. At this time, the full data writing unit can be identified as the full and sealed data writing unit, and the full data in the data reading and writing area can be erased.

[0094] In summary, erasing the written data in the data read / write area facilitates the subsequent writing of data to the data read / write area.

[0095] In practical applications, the process of erasing the written data in the data read / write area also includes:

[0096] In response to a data write request, the data to be written carried in the data write request is written to the data write area and cached in the write cache of the data storage device;

[0097] After obtaining the blank data read / write area, the process also includes:

[0098] Write the data cached in the write cache into the blank data read / write area.

[0099] The write cache of the data storage device can be used to temporarily cache the written data, and the write cache can have power loss protection.

[0100] Based on this, during the process of erasing the written data in the data read / write area, if a data write request is received, the data to be written carried in the data write request can be written to one of the data write units in the data write area, and the data to be written can be cached in the write cache of the data storage device. After the erase of the written data in the data read / write area is completed and a blank data read / write area is obtained, the data already cached in the write cache can be written to the blank data read / write area.

[0101] For example, in response to a data write request, the data to be written can be written to data write unit 1 and data read / write area. When data write unit 1 is full, the data read / write area is also full. At this time, the written data in the data read / write area can be erased, and data write unit 1 is determined as the data write unit that is full and sealed. During the erasure process, if a data write request is received again, the data to be written can be written to data write unit 2 and write cache until the written data in the data read / write area is erased. Then, the data already cached in the write cache is written to the data read / write area.

[0102] In summary, by setting up a write cache, data writing during the data read / write area erasure process is achieved, ensuring that subsequent data readings can be performed from the write cache without having to read from the data write unit, thus ensuring that the data writing process of the data write unit is not affected.

[0103] Furthermore, the process of erasing the written data in the data read / write area also includes:

[0104] In response to a data read request for cached data in the write cache, the cached data is read from the write cache.

[0105] Specifically, during the process of erasing written data in the data read / write area, if a data read request for cached data in the write cache is received, the cached data can be read directly from the write cache.

[0106] In practical applications, refer to Figure 6, which illustrates a data processing method according to an embodiment of this disclosure, specifically the erasure of the data read / write area. As shown in Figure 6, when a TLC particle group (i.e., a data writing unit) is fully written and sealed, the corresponding pSLC area (i.e., the data read / write area) is also fully written. At this time, all pSLC particles (i.e., read / write data blocks) in the pSLC area are erased simultaneously. During the erasure process, if an application writes data, the written data is cached in the write cache with power-loss protection within the disk, and the data is simultaneously written to the newly allocated TLC particle group (another data writing unit). After the data erasure in the pSLC area is completed, the data in the write cache is quickly flushed to the pSLC area. Before the erasure of the pSLC area and the flushing of the data in the write cache are completed, if an application reads the corresponding data, it obtains it from the write cache within the disk, rather than reading it from the newly allocated TLC particle group, thereby ensuring the QoS of data reading. For example, the pSLC area erase latency is 6ms. Based on a throughput of 1GB / s, the on-disk DRAM (i.e., write cache) only needs to cache 6MB of data. After the erase is completed in the pSLC area and writing begins, the data in the cache is flushed down using its time window. Therefore, there are multiple Tp timing markers in Figure 6.

[0107] In summary, by reading the cached data directly from the write cache, and avoiding reading data from the data write unit, the data read latency is guaranteed to be unaffected by data writing and data erasure.

[0108] In one embodiment of this disclosure, the method further includes:

[0109] If it is determined that the target data writing unit meets the preset storage conditions and the preset recycling conditions, the target data is obtained from the target data writing unit;

[0110] A blank data writing unit is determined from the plurality of data writing units, and the target data is written into the blank data writing unit;

[0111] The written data in the target data writing unit is erased, and the target data writing unit obtained after erasure is determined as a blank data writing unit.

[0112] The preset recycling conditions can be understood as the presence of old data that needs to be deleted in the target data writing unit. For example, if an application on the host is uninstalled, the data stored in the data storage device for that application needs to be deleted; this data is the old data. The target data writing unit meeting the preset storage conditions can be understood as the target data writing unit being full and sealed. Target data can be understood as valid data, i.e., data that does not need to be deleted; target data can be a portion of the valid data already written to the target. The blank data writing unit can be used to write target data or to write data to be written carried in a data write request.

[0113] Based on this, for a target data writing unit that is filled with sealed data, if it is determined that there is old data that needs to be deleted in the target data writing unit, valid data can be determined from the target data writing unit according to the data mark, and a blank data writing unit can be determined from multiple data writing units. The valid data is written to the blank data writing unit, and the data already written in the target data writing unit is erased. The target data writing unit obtained after erasure is determined as a blank data writing unit and recycled, so that data can be continued to be written to the blank data writing unit in the future.

[0114] In practical applications, refer to Figure 7, which illustrates a data processing method according to an embodiment of this disclosure, specifically the data write area recycling process. As shown in Figure 7, the controller of the data storage device selects multiple TLC particle groups (i.e., source TLC particle groups) to be recycled (GC) from the TLC full-filled archive area. It reads the valid data from these groups based on data markers (e.g., color markers) and writes it in the background to the selected blank TLC particle group (i.e., the TLC blank particle group area). This destination particle group is written to but not read, while the source TLC full-filled particle group (being GC'd) is read-only. Its read operations include application reads and GC reads, with application reads having a higher priority than GC reads, ensuring that application reads meet the QoS requirements for data reading. Once all valid data in the source TLC particle group has been written to the destination particle group, and the destination TLC particle group is full and sealed, subsequent read operations will retrieve data from the GC-wrapped destination TLC particle group, while the source TLC particle group can be erased and recycled to the blank TLC particle group area.

[0115] In summary, by storing valid data and erasing invalid data, the memory of the data writing area is cleaned up.

[0116] In one embodiment of this disclosure, the data storage device further includes a data cache area, which includes a plurality of data cache blocks.

[0117] The data buffer is used to provide redundant protection for data written to the data storage device. The data buffer can be understood as a RAID protection group, and the data storage block can be understood as the RP (Resource Processing) particle within the RAID protection group.

[0118] In practical applications, refer to Figure 8, which shows a schematic diagram of a data cache area in a data processing method according to an embodiment of the present disclosure. As shown in Figure 8, the flash memory chips in the SSD are divided into two or more RAID protection groups. The RAID protection group includes multiple TLC chip groups and multiple RP chips. The multiple RP chips are used to store RAID parity (i.e., accumulated data). The multiple RP chips can be used to adapt to flash memory erasure and can adapt to the RAID parity update requirements under write characteristics.

[0119] Therefore, the method further includes:

[0120] When it is determined that the target data writing unit meets the preset storage conditions, the written data in the target data writing unit is accumulated to obtain first accumulated data, and the first accumulated data is cached in a first data cache block, wherein the first data cache block is any one of the plurality of data cache blocks.

[0121] The data already written in the target data writing unit can be understood as data that has been written into the target data writing unit, and the data already written can include the target data already written.

[0122] Specifically, when it is determined that the target data writing unit is full, the written data in the target data writing unit can be accumulated to obtain the first accumulation processing, and the first accumulated data can be cached in any one of the multiple data storage blocks.

[0123] In summary, by accumulating and caching, redundancy protection for written data is achieved.

[0124] Furthermore, after caching the first accumulated data into the first data cache block, the method further includes:

[0125] If the next target data writing unit is determined to meet the preset storage conditions, the written data in the next target data writing unit is accumulated to obtain the second accumulated data.

[0126] The first accumulated data is obtained from the first data cache block, and the first accumulated data and the second accumulated data are accumulated to obtain the target accumulated data. The target accumulated data is cached in the second data cache block, wherein the second data cache block is any one of the plurality of data cache blocks other than the first data cache block.

[0127] Specifically, when it is determined that the next target data writing unit is full, the written data in the next target data writing unit can be accumulated to obtain the second accumulated data, and the first accumulated data can be obtained from the first data cache block. The first accumulated data and the second accumulated data are accumulated to obtain the target accumulated data, and the target accumulated data is cached in the second data cache block.

[0128] To illustrate, let's take two target data writing units, Target Data Writing Unit 1 and Target Data Writing Unit 2, as an example. When Target Data Writing Unit 1 is full, the written data in Target Data Writing Unit 1 is accumulated to obtain the first accumulated data, which is then cached in the first data cache block. When the next target data writing unit, Target Data Writing Unit 2, is full, the written data in Target Data Writing Unit 2 is accumulated to obtain the second accumulated data. The first accumulated data is then retrieved from the first data cache block. The first and second accumulated data are accumulated to obtain the target accumulated data, which is then cached in the second data cache block. Finally, the first accumulated data in the first data cache block is cleared, making the first data cache block a blank data cache block, facilitating subsequent caching.

[0129] In addition, after obtaining the first accumulated data from the first data cache block, the method further includes:

[0130] The first accumulated data cached in the first data cache block is erased to obtain a blank data cache block, so that the accumulated data is cached in the blank data cache block.

[0131] In practical applications, refer to Figure 9, which illustrates a schematic diagram of data accumulation in a data processing method according to an embodiment of this disclosure. As shown in Figure 9, whenever data is written to a TLC particle group, the data is accumulated in the RAID calculation module to generate the current accumulated data (i.e., the first accumulated data), and then written to RP particle 1. When writing to the second TLC particle group, the RAID calculation function (hardware circuit or firmware program) is reused to read the first accumulated data from RP particle 1 and accumulate it together with the currently written data to generate the updated second accumulated data, which is then written to RP particle 2. After the second TLC particle group is full, RP particle 1 can be erased and recycled. This process continues, with RP particles rotating, and all data in the TLC particle groups of the RAID protection group is protected by accumulated data and stored in one RP particle. The data in the RP particle is not used for reading or writing; it is only read out to recover data in the event of a failure.

[0132] In summary, by setting up a data cache for data redundancy protection, it is easier to recover data from the data cache in the event of a subsequent host failure.

[0133] In one embodiment of this disclosure, it further includes:

[0134] If it is determined that the target data writing unit meets the preset storage conditions and the preset recycling conditions, the written data in the target data writing unit is obtained;

[0135] Determine the target data cache block corresponding to the target data writing unit, and obtain the target accumulated data from the target data cache block;

[0136] Based on the data location information of the written data, the data location information of the target accumulated data, and the data location information of the target data writing unit to the blank data writing unit in the target data writing unit, the target accumulated data is updated to obtain updated accumulated data, and the updated accumulated data is written to the next data cache block of the target data cache block.

[0137] The preset recycling conditions can be understood as the conditions for writing the target data filled with data into the unit for GC.

[0138] In practical applications, refer to Figure 10, which illustrates a target data cache in a data processing method according to an embodiment of this disclosure. As shown in Figure 10, when multiple TLC particle groups in a RAID protection group are recycled to a destination TLC particle group (a newly allocated blank TLC particle group), valid data is read and written to the destination TLC particle group. Simultaneously, all data (including valid and invalid data) in the recycled TLC particle group is read, along with the accumulated data in the RP particle. The update of the accumulated data involves two steps: First, eliminating the influence of old position data by superimposing the data from the recycled TLC particle group onto the corresponding positions of the accumulated data read from RP particle 1 to eliminate its influence, obtaining updated accumulated data. Second, according to the mapping position in the destination TLC particle group, valid data is superimposed onto the accumulated data updated in the first step to generate new accumulated data, which is then written to RP particle 2. This allows for the updating and storage of accumulated data during invalid data recycling. Furthermore, to simplify the design and improve stability, the TLC NAND flash memory in the recycled RAID protection group only handles application reads during the recycling period, while the TLC NAND flash memory in other RAID protection groups handles current application reads and writes, thereby meeting the needs of user scenarios.

[0139] In summary, by dividing and coordinating regions with different read, write, and erase characteristics, the system meets read latency distribution requirements without compromising SSD performance, lifespan, or data stability. A pSLC region erasure mechanism and write cache are designed to work in conjunction with the flush operation. The system implements data and control flow allocation during normal read and write operations, as well as garbage collection process handling. Furthermore, it incorporates data recovery protection (RAID) generation, updating, and storage based on region characteristics to overcome reliability risks in the event of a single SSD failure.

[0140] In summary, the above method divides the data storage device into a data read / write area and a data write area. The data read / write area can be used for data reading and data writing, while the data write area can be used for data writing. Therefore, after receiving a data read request for target data already written in the target data write unit, if it is determined that the target data write unit does not meet the preset storage conditions, the target data already written can be read directly from the data read / write area without affecting the data writing in the target data write unit. This ensures that there is no conflict between data reading and data writing, thereby reducing latency and ensuring the data read / write performance of the data storage device.

[0141] The following description, in conjunction with Figure 11, uses the application of the data processing method provided in this disclosure in random data read and write as an example to further illustrate the data processing method. Figure 11 shows a flowchart of the processing procedure of a data processing method provided in an embodiment of this disclosure, specifically including the following steps.

[0142] Step 1102: In response to the data write request, write the data to be written in the data write request to the target TLC particle group (TLC current write area) and pSLC area (pSLC current write read area) in the TLC area at the same time.

[0143] Step 1104: In response to a data read request for data already written to the target TLC particle group, if it is determined that the target TLC particle group is not full, read the written data from the pSLC area.

[0144] Step 1106: In response to a data read request for data already written to the target TLC particle group, if it is determined that the target TLC particle group is full, read the written data from the target TLC particle group (TLC full write-in area).

[0145] Step 1108: If the pSLC area is determined to be full, erase the pSLC area to obtain a blank pSLC area after erasure.

[0146] Step 1110: If a data write request is received during the erase process, write the data to be written carried in the data write request into another target TLC particle group and write cache.

[0147] Step 1112: After the pSLC area is erased, send the data in the write buffer to the pSLC area.

[0148] Step 1114: During the erasure operation of the pSLC area, if a data read request for data in the write cache is received, the corresponding data is retrieved from the write cache.

[0149] Step 1116: Determine valid data from the source TLC particle group, write the valid data into the destination TLC particle group, and erase the source TLC particle group and recycle it to a blank TLC particle group.

[0150] Step 1118: Accumulate the data in the TLC particle group to obtain accumulated data, and write the accumulated data into the RP particle.

[0151] Specifically, after the first TLC particle group is full of data, the data in the first TLC particle group is accumulated and written to RP particle 1; after the second TLC particle group is full of data, the accumulated data in RP particle 1 and the data in the second TLC particle group are accumulated and written to RP particle 2. And so on, so that all data can be directly retrieved from the RP particles in the event of a subsequent host failure.

[0152] In addition, for the source TLC particle group to be erased, all data in the source TLC particle group can be read before erasure, and the accumulated data in RP particle 1 can be read. All the data read from the source TLC particle group can be superimposed on the corresponding positions of the accumulated data read from RP particle 1 according to the corresponding positions. And according to the mapping position of the valid data in the destination TLC particle group, the valid data can be superimposed on the data in RP particle 2. The superimposed data is then written into RP particle 2.

[0153] In summary, by dividing and coordinating regions with different read, write, and erase characteristics, the system meets read latency distribution requirements without compromising SSD performance, lifespan, or data stability. A pSLC region erasure mechanism and write cache are designed to work in conjunction with the flush operation. The system implements data and control flow allocation during normal read and write operations, as well as garbage collection process handling. Furthermore, it incorporates data recovery protection (RAID) generation, updating, and storage based on region characteristics to overcome reliability risks in the event of a single SSD failure.

[0154] Corresponding to the above method embodiments, this disclosure also provides a data processing apparatus embodiment. FIG12 shows a schematic diagram of the structure of a data processing apparatus provided in one embodiment of this disclosure. As shown in FIG12, the apparatus includes:

[0155] The receiving module 1202 is configured to receive a data read request for target written data in the target data writing unit, wherein the target data writing unit belongs to the data writing area, the data writing area is used for data writing, and the target written data is synchronously written to the data writing area and the data read and write area, the data read and write area is used for data reading and data writing.

[0156] The reading module 1204 is configured to read the target written data from the data read / write area when it is determined that the target data writing unit does not meet the preset storage conditions.

[0157] In one optional embodiment, the data writing area includes multiple data writing units, each data writing unit includes multiple data writing blocks, the target data writing unit is any one of the multiple data writing units, the data read and write area includes multiple data read and write blocks, and the number of data writing blocks and the number of data read and write blocks are determined according to a preset quantity ratio.

[0158] In an optional embodiment, the receiving module 1202 is further configured to:

[0159] In response to a data write request, the data to be written, carried in the data write request, is written to the target data write unit in the data read / write area and the data write area.

[0160] In an optional embodiment, the receiving module 1202 is further configured to:

[0161] If it is determined that the data read / write area is in the process of data reading, after the data reading is completed, the data to be written carried in the data writing request is written to the data read / write area.

[0162] The reading module 1204 is further configured as follows:

[0163] If it is determined that the data read / write area is in the process of writing data, the target written data is read from the data read / write area after the data writing is completed.

[0164] In an optional embodiment, the device further includes an erasing module configured to:

[0165] If the data read / write area meets the preset erasure conditions, the data already written in the data read / write area is erased to obtain a blank data read / write area, so that the data to be written can be written into the blank data read / write area.

[0166] In an optional embodiment, the erasing module is further configured to:

[0167] In response to a data write request, the data to be written carried in the data write request is written to the data write area and cached in the write cache of the data storage device;

[0168] Write the data cached in the write cache into the blank data read / write area.

[0169] In an optional embodiment, the reading module 1204 is further configured to:

[0170] In response to a data read request for cached data in the write cache, the cached data is read from the write cache.

[0171] In an optional embodiment, the erasing module is further configured to:

[0172] If it is determined that the target data writing unit meets the preset storage conditions and the preset recycling conditions, the target data is obtained from the target data writing unit;

[0173] A blank data writing unit is determined from the plurality of data writing units, and the target data is written into the blank data writing unit;

[0174] The written data in the target data writing unit is erased, and the target data writing unit obtained after erasure is determined as a blank data writing unit.

[0175] In an optional embodiment, the data storage device further includes a data cache area, which includes a plurality of data cache blocks;

[0176] The device also includes a cache module configured to:

[0177] When it is determined that the target data writing unit meets the preset storage conditions, the written data in the target data writing unit is accumulated to obtain first accumulated data, and the first accumulated data is cached in a first data cache block, wherein the first data cache block is any one of the plurality of data cache blocks.

[0178] In an optional embodiment, the caching module is further configured to:

[0179] If the next target data writing unit is determined to meet the preset storage conditions, the written data in the next target data writing unit is accumulated to obtain the second accumulated data.

[0180] The first accumulated data is obtained from the first data cache block, and the first accumulated data and the second accumulated data are accumulated to obtain the target accumulated data. The target accumulated data is cached in the second data cache block, wherein the second data cache block is any one of the plurality of data cache blocks other than the first data cache block.

[0181] In an optional embodiment, the caching module is further configured to:

[0182] The first accumulated data cached in the first data cache block is erased to obtain a blank data cache block, so that the accumulated data is cached in the blank data cache block.

[0183] In an optional embodiment, the caching module is further configured to:

[0184] If it is determined that the target data writing unit meets the preset storage conditions and the preset recycling conditions, the written data in the target data writing unit is obtained;

[0185] Determine the target data cache block corresponding to the target data writing unit, and obtain the target accumulated data from the target data cache block;

[0186] Based on the data location information of the written data, the data location information of the target accumulated data, and the data location information of the target data writing unit to the blank data writing unit in the target data writing unit, the target accumulated data is updated to obtain updated accumulated data, and the updated accumulated data is written to the next data cache block of the target data cache block.

[0187] In an optional embodiment, the reading module 1204 is further configured to:

[0188] Determine the amount of data already written in the target data writing unit;

[0189] If it is determined that the amount of data does not meet the preset data threshold, it is determined that the target data writing unit does not meet the preset storage conditions;

[0190] Read the data that has been written to the target from the data read / write area.

[0191] In an optional embodiment, the reading module 1204 is further configured to:

[0192] If the target data writing unit is determined to meet the preset storage conditions, the target data already written is read from the target data writing unit.

[0193] The aforementioned device divides the data storage device into a data read / write area and a data write area. The data read / write area can be used for data reading and data writing, while the data write area can be used for data writing. Therefore, after receiving a data read request for target data already written in the target data write unit, if it is determined that the target data write unit does not meet the preset storage conditions, the target data already written can be read directly from the data read / write area without affecting the data writing in the target data write unit. This ensures that there is no conflict between data reading and data writing, thereby reducing latency and ensuring the data read / write performance of the data storage device.

[0194] The above is an illustrative scheme of a data processing apparatus according to this embodiment. It should be noted that the technical solution of this data processing apparatus and the technical solution of the data processing method described above belong to the same concept. For details not described in detail in the technical solution of the data processing apparatus, please refer to the description of the technical solution of the data processing method described above.

[0195] Figure 13 shows a structural block diagram of a computing device 1300 according to an embodiment of the present disclosure. The components of the computing device 1300 include, but are not limited to, a memory 1310 and a processor 1320. The processor 1320 is connected to the memory 1310 via a bus 1330, and a database 1350 is used to store data.

[0196] The computing device 1300 also includes an access device 1340, which enables the computing device 1300 to communicate via one or more networks 1360. Examples of these networks include Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or combinations of communication networks such as the Internet. The access device 1340 may include one or more of any type of wired or wireless network interface (e.g., a network interface controller (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) interface, a Wi-MAX (Worldwide Interoperability for Microwave Access) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, a Near Field Communication (NFC) interface, and so on.

[0197] In one embodiment of this disclosure, the aforementioned components of the computing device 1300, as well as other components not shown in FIG. 13, may also be connected to each other, for example, via a bus. It should be understood that the computing device block diagram shown in FIG. 13 is merely for illustrative purposes and is not intended to limit the scope of this disclosure. Those skilled in the art can add or replace other components as needed.

[0198] The computing device 1300 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or personal computers (PCs). The computing device 1300 can also be a mobile or stationary server.

[0199] The processor 1320 is used to execute the following computer program / instructions, which, when executed by the processor, implement the steps of the above-described data processing method.

[0200] The various embodiments in this disclosure are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the computing device embodiments are basically similar to the data processing method embodiments, so the description is relatively simple; relevant parts can be referred to the description of the data processing method embodiments.

[0201] An embodiment of this disclosure also provides a computer-readable storage medium storing a computer program / instructions that, when executed by a processor, implement the steps of the above-described data processing method.

[0202] The various embodiments in this disclosure are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the computer-readable storage medium embodiments are basically similar to the data processing method embodiments, so the description is relatively simple; relevant parts can be referred to the description of the data processing method embodiments.

[0203] An embodiment of this disclosure also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the above-described data processing method.

[0204] The above is an illustrative scheme of a computer program product according to this embodiment. It should be noted that the technical solution of this computer program product and the technical solution of the data processing method described above belong to the same concept. For details not described in detail in the technical solution of the computer program product, please refer to the description of the technical solution of the data processing method described above.

[0205] The foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0206] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or certain intermediate forms. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added or removed according to the requirements of patent practice. For example, in some regions, according to patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0207] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this disclosure are not limited to the described order of actions, because according to the embodiments of this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments of this disclosure.

[0208] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0209] The preferred embodiments disclosed above are merely illustrative of this disclosure. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments of this disclosure. These embodiments are selected and specifically described in this disclosure to better explain the principles and practical applications of the embodiments of this disclosure, thereby enabling those skilled in the art to better understand and utilize this disclosure. This disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A data processing method applied to a data storage device, comprising: Receive a data read request for target data already written in the target data writing unit, wherein the target data writing unit belongs to the data writing area, the data writing area is used for data writing, and the target data already written is synchronously written to the data writing area and the data read and write area, the data read and write area is used for data reading and data writing; If it is determined that the target data writing unit does not meet the preset storage conditions, the target written data is read from the data read / write area.

2. The method according to claim 1, wherein the data writing area includes a plurality of data writing units, each data writing unit includes a plurality of data writing blocks, the target data writing unit is any one of the plurality of data writing units, the data read / write area includes a plurality of data read / write blocks, and the number of data writing blocks and the number of data read / write blocks are determined according to a preset quantity ratio.

3. The method according to claim 2, further comprising, before receiving a data read request for target data already written in the target data writing unit: In response to a data write request, the data to be written carried in the data write request is written into the target data write unit of the data read / write area and the data write area.

4. The method according to claim 3, wherein writing the data to be written carried in the data writing request to the data read / write area comprises: If it is determined that the data read / write area is in the process of data reading, after the data reading is completed, the data to be written carried in the data writing request is written to the data read / write area. Reading the target data already written from the data read / write area includes: If it is determined that the data read / write area is in the process of writing data, the target written data is read from the data read / write area after the data writing is completed.

5. The method according to claim 3, further comprising: If the data read / write area meets the preset erasure conditions, the data already written in the data read / write area is erased to obtain a blank data read / write area, so that the data to be written can be written into the blank data read / write area.

6. The method according to claim 5, wherein the process of erasing the written data in the data read / write area further includes: In response to a data write request, the data to be written carried in the data write request is written to the data write area and cached in the write cache of the data storage device; After obtaining the blank data read / write area, the process also includes: Write the data cached in the write cache into the blank data read / write area.

7. The method according to claim 6, wherein the process of erasing the written data in the data read / write area further includes: In response to a data read request for cached data in the write cache, the cached data is read from the write cache.

8. The method according to claim 3, further comprising: If it is determined that the target data writing unit meets the preset storage conditions and the preset recycling conditions, the target data is obtained from the target data writing unit; A blank data writing unit is determined from the plurality of data writing units, and the target data is written into the blank data writing unit; The written data in the target data writing unit is erased, and the target data writing unit obtained after erasure is determined as a blank data writing unit.

9. The method according to claim 3, wherein the data storage device further includes a data cache area, the data cache area comprising a plurality of data cache blocks; The method further includes: When it is determined that the target data writing unit meets the preset storage conditions, the written data in the target data writing unit is accumulated to obtain first accumulated data, and the first accumulated data is cached in a first data cache block, wherein the first data cache block is any one of the plurality of data cache blocks.

10. The method according to claim 9, further comprising, after caching the first accumulated data into the first data cache block: If the next target data writing unit is determined to meet the preset storage conditions, the written data in the next target data writing unit is accumulated to obtain the second accumulated data. The first accumulated data is obtained from the first data cache block, and the first accumulated data and the second accumulated data are accumulated to obtain the target accumulated data. The target accumulated data is cached in the second data cache block, wherein the second data cache block is any one of the plurality of data cache blocks other than the first data cache block.

11. The method according to claim 10, further comprising, after obtaining the first accumulated data from the first data cache block: The first accumulated data cached in the first data cache block is erased to obtain a blank data cache block.

12. The method according to claim 9, further comprising: If it is determined that the target data writing unit meets the preset storage conditions and the preset recycling conditions, the written data in the target data writing unit is obtained; Determine the target data cache block corresponding to the target data writing unit, and obtain the target accumulated data from the target data cache block; Based on the data location information of the written data, the data location information of the target accumulated data, and the data location information of the target data writing unit to the blank data writing unit in the target data writing unit, the target accumulated data is updated to obtain updated accumulated data, and the updated accumulated data is written to the next data cache block of the target data cache block.

13. The method according to claim 1, wherein reading the target written data from the data read / write area when it is determined that the target data writing unit does not meet the preset storage conditions includes: Determine the amount of data already written in the target data writing unit; If it is determined that the amount of data does not meet the preset data threshold, it is determined that the target data writing unit does not meet the preset storage conditions; Read the data that has been written to the target from the data read / write area.

14. The method according to claim 1, further comprising, after receiving a data read request for target data already written in the target data writing unit: If the target data writing unit is determined to meet the preset storage conditions, the target data already written is read from the target data writing unit.

15. A computing device, comprising: Memory and processor; The memory is used to store computer programs / instructions, and the processor is used to execute the computer programs / instructions, which, when executed by the processor, implement the steps of the method according to any one of claims 1 to 14.

16. A computer-readable storage medium storing a computer program / instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 14.

17. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 14.

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