Large-area perovskite / silicon-based tandem cell structure and preparation method therefor

Abstract

The present disclosure relates to the technical field of solar cells, and in particular, to a large-area perovskite / silicon-based tandem cell structure and a preparation method therefor. The large-area perovskite / silicon-based tandem cell structure comprises: a silicon substrate cell; a first transport layer located on a side of the silicon substrate cell; a perovskite layer, located on the side of the first transport layer away from the silicon substrate cell; a second transport layer located on the side of the perovskite layer away from the silicon substrate cell; a buffer layer, located on the side of the second transport layer away from the silicon substrate cell; a transparent conductive layer, located on the side of the buffer layer away from the silicon substrate cell, the transparent conductive layer comprising at least one first transparent conductive layer and at least one second transparent conductive layer, the first transparent conductive layer being located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer being less than the density of the second transparent conductive layer; and electrodes, formed by means of screen printing or inkjet printing on the side of the transparent conductive layer away from the silicon substrate cell.

Description

Large-area perovskite / silicon-based tandem solar cell structure and its fabrication method Technical Field

[0001] This disclosure relates to the field of solar cell technology, and in particular to a large-area perovskite / silicon-based tandem cell structure and its fabrication method. Background Technology

[0002] Perovskite / silicon tandem solar cells are devices that directly convert solar energy into electrical energy. With their high photoelectric conversion efficiency, environmental friendliness, and wide range of applications, perovskite / silicon tandem solar cells have broad application prospects in modern society. Common fabrication routes for perovskite / silicon tandem solar cells include: 1. Providing a silicon substrate, such as an N-type silicon substrate; 2. Fabricating a composite layer or tunnel junction on the silicon substrate to connect the silicon substrate and the perovskite top cell in series; 3. Fabricating, from bottom to top, a hole transport layer, a perovskite light-absorbing layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, and a metal electrode on the composite layer. The commonly used electrode fabrication method for perovskite / silicon tandem solar cells is primarily through vapor deposition, rather than the screen printing used in traditional solar cells. For example, the mainstream method for fabricating small-area perovskite / silicon tandem solar cell electrodes in the laboratory is to vapor-deposit Ag, as there is no good method to achieve large areas (e.g., 166 mm²). 2 *166mm 2 This is because when depositing Ag, a mask is needed to prepare the grid lines, and currently, it is almost impossible to prepare a mask suitable for the grid lines. For example, if the grid lines are too thin, they will clog the apertures and droop, creating shadows, while if the grid lines are too wide, they will block light. These problems all affect the current collection of the tandem solar cells, and the evaporation equipment has extremely poor material utilization and excessively long cycle time, which is incompatible with the cost-first nature of the photovoltaic industry.

[0003] As the industry develops, the size requirements for perovskite / silicon-based tandem solar cells are becoming increasingly larger. The mainstream method of electrode fabrication by vapor deposition is no longer suitable for industrialization. However, the conventional electrode fabrication method for large-area perovskite / silicon-based tandem solar cells is screen printing, which involves printing Ag paste and then sintering it at high temperatures to prepare Ag grid lines. But this presents a new problem: perovskite / silicon tandem solar cells are very sensitive to temperature. At high temperatures, perovskite materials are easily deformed and the cells fail. Therefore, perovskite / silicon heterojunction tandem solar cells cannot currently be fabricated using room-temperature screen printing and require ultra-low temperature metallization technology to prepare the electrodes.

[0004] Therefore, improving the heat resistance of large-area perovskite / silicon tandem solar cells is crucial for industrialization and is an urgent problem that needs to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a large-area perovskite / silicon-based tandem solar cell structure and its fabrication method to address the problem of poor heat resistance in existing large-area perovskite / silicon-based tandem solar cells.

[0006] To achieve the above objectives, a large-area perovskite / silicon-based tandem solar cell structure is provided, comprising:

[0007] Silicon-based solar cells;

[0008] The first transport layer is located on one side of the silicon substrate cell;

[0009] A perovskite layer is located on the side of the first transport layer away from the silicon substrate cell;

[0010] The second transport layer is located on the side of the perovskite layer away from the silicon substrate cell;

[0011] A buffer layer is located on the side of the second transport layer away from the silicon substrate cell;

[0012] A transparent conductive layer is located on the side of the buffer layer away from the silicon substrate cell, and the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer. The first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than that of the second transparent conductive layer.

[0013] The electrodes are formed on the side of the transparent conductive layer away from the silicon substrate cell by screen printing or inkjet printing.

[0014] In one embodiment, the large-area perovskite / silicon-based tandem solar cell structure further includes:

[0015] The thickness of the first transparent conductive layer accounts for 5%-50% of the total thickness of the transparent conductive layer.

[0016] In one embodiment, the large-area perovskite / silicon-based tandem solar cell structure further includes:

[0017] The buffer layer includes at least one first buffer layer and at least one second buffer layer, wherein the first buffer layer is located between the second transmission layer and the second buffer layer, and the density of the first buffer layer is greater than that of the second buffer layer.

[0018] In one embodiment, the thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

[0019] In one embodiment, the materials of the first buffer layer and the second buffer layer include at least tin oxide, and the material of the supplementary buffer layer includes at least one of tin oxide, zinc oxide, tin oxide, chromium oxide, and titanium oxide.

[0020] In one embodiment, the first transport layer is an electron transport layer and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer and the second transport layer is an electron transport layer.

[0021] In one embodiment, at least one tunneling junction or composite layer is further included between the first transport layer and the silicon substrate cell, and / or at least one passivation layer is further included between the second transport layer and the perovskite layer.

[0022] On the one hand, a method for fabricating a large-area perovskite / silicon-based tandem solar cell structure is provided, comprising the following steps:

[0023] Provide silicon-based solar cells;

[0024] A first transport layer is formed on one side of the silicon substrate cell;

[0025] A perovskite layer is formed on the first transport layer;

[0026] A second transport layer is formed on the perovskite layer;

[0027] A buffer layer is formed on the second transport layer;

[0028] A transparent conductive layer is formed on the buffer layer, wherein the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer, the first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than the density of the second transparent conductive layer;

[0029] An electrode is formed on the transparent conductive layer, and a heat treatment process is required after the electrode is formed.

[0030] In one embodiment, the thickness of the first transparent conductive layer accounts for 5%-50% of the total thickness of the transparent conductive layer.

[0031] In one embodiment, the buffer layer includes at least one first buffer layer and at least one second buffer layer, the first buffer layer being located between the second transport layer and the second buffer layer, and the density of the first buffer layer being greater than the density of the second buffer layer.

[0032] In one embodiment, the thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

[0033] In one embodiment, forming an electrode on the transparent conductive layer includes:

[0034] Electrodes are formed on the side of the transparent conductive layer away from the silicon substrate cell using screen printing or inkjet printing, with the heat treatment temperature ranging from 80°C to 150°C.

[0035] In one embodiment, the first transport layer is an electron transport layer and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer and the second transport layer is an electron transport layer.

[0036] In one embodiment, before forming the first transport layer on one side of the silicon substrate cell, the process includes:

[0037] At least one tunnel junction or composite layer is formed on the silicon substrate cell;

[0038] And / or,

[0039] Before forming the second transport layer on the perovskite layer, the process includes:

[0040] At least one passivation layer is formed on the perovskite layer.

[0041] The large-area perovskite / silicon-based tandem solar cell structure and its fabrication method described in this specification have the following beneficial effects:

[0042] In the fabrication process of large-area perovskite / silicon-based stacks, electrodes are formed using screen printing or inkjet printing. A transparent conductive layer located on the side of the buffer layer away from the silicon substrate is configured as at least two layers. The first transparent conductive layer on the side closer to the silicon substrate has a lower density, while the second transparent conductive layer on the side farther from the silicon substrate has a higher density. The overall performance of the transparent conductive layer in the stack needs to balance optical and electrical properties, satisfying characteristics of high mobility, high transmittance, and low resistance. Furthermore, during thermal annealing, the first transparent conductive layer can alleviate stress during the stress release process, reducing the impact of stress on the buffer / second transport layer and thus mitigating the risk of interface delamination between the buffer and second transport layers, thereby improving the heat resistance of the large-area perovskite / silicon-based stack.

[0043] Furthermore, the large-area perovskite / silicon-based tandem solar cell structure in this specification further improves the buffer layer. By setting the buffer layer on the side of the transport layer away from the silicon substrate as a structure of at least two layers, the first buffer layer on the side closer to the silicon substrate is set as a denser buffer layer, and the second buffer layer on the side away from the silicon substrate is set as a less dense buffer layer. During thermal annealing, during the stress release process of the buffer layer, the second buffer layer can alleviate the stress released from the top transparent conductive layer, reduce the compression on the second transport layer, thereby reducing the risk of interface delamination between the buffer layer and the second transport layer, and further improving the heat resistance of the large-area perovskite / silicon-based tandem solar cell structure. At the same time, since the first buffer layer is in contact with the second transport layer, the first buffer layer needs to be prepared as a dense film layer, which, combined with the second transport layer, plays a better role in interface conduction and carrier transport. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 is a flowchart of a method for fabricating a large-area perovskite / silicon-based tandem solar cell structure provided in one embodiment;

[0046] Figure 2 is a schematic diagram of a large-area perovskite / silicon-based tandem solar cell structure provided in one embodiment;

[0047] Figure 3 is a schematic diagram of a large-area perovskite / silicon-based tandem solar cell structure provided in another embodiment.

[0048] Explanation of reference numerals in the attached figures: Large-area perovskite / silicon-based tandem solar cell structure - 100; Silicon substrate solar cell - 101; Composite layer / tunnel junction - 102; First transport layer - 103; Perovskite layer - 104; Passivation layer - 105; Second transport layer - 106; Buffer layer - 107; First buffer layer - 1071; Second buffer layer - 1072; Transparent conductive layer - 108; First transparent conductive layer - 1081; Second transparent conductive layer - 1082; Top electrode - 110; Bottom electrode - 111.

[0049] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood. Detailed Implementation

[0050] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0052] In each embodiment, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in each embodiment according to the specific circumstances.

[0053] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this embodiment, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion.

[0054] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] Embodiments of the embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures) of this specification. Variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of this specification should not be limited to the specific shapes of the regions shown herein, but should include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this embodiment.

[0057] Referring to Figure 1, in one embodiment, a method for fabricating a large-area perovskite / silicon-based tandem solar cell structure 100 is provided. The size of the large-area perovskite / silicon-based tandem solar cell structure 100 provided in this application can be no less than 166 cm². 2 *166cm 2 A cross-sectional schematic diagram of the large-area perovskite / silicon-based tandem solar cell structure 100 is shown in Figures 2 and 3. The fabrication method of the large-area perovskite / silicon-based tandem solar cell structure 100 may include the following steps:

[0058] Step S100: Provide silicon substrate cell 101.

[0059] Step S200: A first transport layer 103 is formed on one side of the silicon substrate cell 101.

[0060] Step S300: Form a perovskite layer 104 on the first transport layer 103.

[0061] Step S400: Form a second transport layer 106 on the perovskite layer 104.

[0062] Step S500: A buffer layer 107 is formed on the second transport layer 106.

[0063] Step S600: A transparent conductive layer 108 is formed on the buffer layer 107, wherein the transparent conductive layer 108 includes at least one first transparent conductive layer 1081 and at least one second transparent conductive layer 1082, the first transparent conductive layer 1081 is located between the buffer layer 107 and the second transparent conductive layer 1082, and the density of the first transparent conductive layer 1081 is less than the density of the second transparent conductive layer 1082.

[0064] Step S700: An electrode is formed on the transparent conductive layer 108, and a heat treatment process is required for the electrode after its formation.

[0065] In step S100, the silicon substrate cell 101 may include a silicon substrate cell, which may include a tunnel oxide passivating contact (TOPCon) cell, a heterojunction technology (HJT) cell, an interdigitated back contact (IBC) cell, and a heterojunction back contact (HBC) cell, etc.

[0066] In step S200, a first transport layer 103 may be formed on one side of the silicon substrate cell 101. The material of the first transport layer 103 may include carbon 60 or the like. The first transport layer 103 may include a hole transport layer or an electron transport layer.

[0067] Of course, before forming the first transport layer 103, at least one composite layer / tunneling junction 102 can also be formed on the silicon substrate cell 101. The tunneling junction is beneficial for the tunneling movement of charge carriers, thereby improving the overall effect of the large-area perovskite / silicon-based tandem cell structure 100.

[0068] In step S300, a perovskite layer 104 may be formed on the first transport layer 103. The perovskite layer 104 can be used to absorb sunlight and generate charge carriers to achieve photoelectric conversion.

[0069] In step S400, a second transport layer 106 can be formed on the perovskite layer 104. Specifically, when the first transport layer 103 is an electron transport layer, the second transport layer 106 is a hole transport layer. Alternatively, when the first transport layer 103 is a hole transport layer, the second transport layer 106 is an electron transport layer. As an example, if a hole transport layer is formed first on one side of the silicon substrate cell 101, this step can form an electron transport layer; if an electron transport layer is formed first on one side of the silicon substrate cell 101, this step can form a hole transport layer. That is, the large-area perovskite / silicon-based tandem cell structure 100 provided in this application can be a nip structure or a pin structure.

[0070] In step S500, a buffer layer 107 may be formed on the side of the second transport layer 106 away from the silicon substrate cell 101. As an example, the material of the buffer layer 107 may include atomic layer deposited tin oxide (SnO). x Ald-SnO x )wait.

[0071] As an example, the material of the buffer layer 107 may include SnO2, with a thickness between 5 nm and 30 nm. In one possible example, a layer of SnO2 prepared by atomic layer deposition (ALD) can be used as the buffer layer 107. The refractive index of the buffer layer 107 may be between 1.5 and 2.0.

[0072] Of course, before forming the buffer layer 107 on the second transport layer, at least one passivation layer 105 can be formed on the perovskite layer 104. The passivation layer 105 can improve the conversion efficiency of the battery, and can also protect the large-area perovskite / silicon-based tandem battery structure 100 and extend the service life of the large-area perovskite / silicon-based tandem battery structure 100.

[0073] In step S600, a transparent conductive layer 108 may be formed on the side of the buffer layer 107 away from the silicon substrate cell 101. The transparent conductive layer 108 may include at least one first transparent conductive layer 1081 and at least one second transparent conductive layer 1082. The first transparent conductive layer 1081 is located between the buffer layer 107 and the second transparent conductive layer 1082, and the density of the first transparent conductive layer 1081 is less than the density of the second transparent conductive layer 1082. It is understood that the density of a film layer can be used to indicate the amount of pores and defects in the film layer. In this embodiment, the lower density of the first transparent conductive layer 1081 indicates that the first transparent conductive layer 1081 has more pores, while the higher density of the second transparent conductive layer 1082 indicates that the structure of the second transparent conductive layer 1082 is more compact and has fewer pores and defects.

[0074] Specifically, the first transparent conductive layer 1081 can have a relatively loose texture, or a low refractive index. This embodiment does not impose specific limitations on the density or refractive index of the first transparent conductive layer 1081. The material of the first transparent conductive layer 1081 can include, but is not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), indium tungsten oxide (IWO), and molybdenum-doped indium oxide (IMO). The thickness of the first transparent conductive layer 1081 can be in the range of 1 nm to 50 nm.

[0075] This embodiment does not limit the preparation method of the first transparent conductive layer 1081. In the first example, the first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate cell 101 by thermal evaporation, with an evaporation rate in the range of 0.1 A / s to 10 A / s and a vacuum pressure of 1*10e -6 Pa-1*10e -2 In the second example, a first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate cell 101 by physical vapor deposition, with a vacuum pressure of 1 Pa to 1*10e. 3 In the third example, a first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate cell 101 by reactive plasma deposition, with a vacuum pressure of 1 Pa to 1*10e. 3 Within the range of Pa. In the fourth example, a first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate cell 101 by spin coating, with an annealing temperature in the range of 80°C-120°C.

[0076] Correspondingly, the second transparent conductive layer 1082 can have a denser texture. Furthermore, the density of the first transparent conductive layer 1081 is less than the density of the second transparent conductive layer 1082, or the refractive index of the first transparent conductive layer 1081 is less than the refractive index of the second transparent conductive layer 1082. This embodiment does not impose specific limitations on the density or refractive index of the second transparent conductive layer 1082.

[0077] The material of the second transparent conductive layer 1082 may include ITO, IZO, AZO, IWO, IMO, etc. The thickness of the second transparent conductive layer 1082 can be in the range of 1nm-50nm. As an example, the material of the second transparent conductive layer 1082 can be the same as that of the first transparent conductive layer 1081, and the thickness of the second transparent conductive layer 1082 can be the same as that of the first transparent conductive layer 1081. Furthermore, the thickness of the first transparent conductive layer 1081 accounts for 5%-50% of the total thickness of the transparent conductive layer. This allows the first transparent conductive layer 1081 to alleviate stress on both sides of the film layer while ensuring the conductivity of the large-area perovskite / silicon-based tandem battery structure 100, without affecting the overall electrical and optical properties of the transparent conductive layer.

[0078] This embodiment does not limit the method of preparing the second transparent conductive layer 1082. In one example, the second transparent conductive layer 1082 can be formed on the side of the first transparent conductive layer 1081 away from the silicon substrate cell 101 by physical vapor deposition, with a vacuum pressure of 1 Pa. -4 ~1*10e -1 Within the range of Pa. Furthermore, both the first transparent conductive layer 1081 and the second transparent conductive layer 1082 can be formed using physical vapor deposition to simplify the process.

[0079] As an example, the common carrier mobility of the first transparent conductive layer 1081 and the second transparent conductive layer 1082 can be less than 30 cm⁻¹. 2 / Vs, sheet resistance can be less than 200Ω / □, and absolute transmittance in the visible light band can be less than 95%.

[0080] In step S700, an electrode can be formed on the transparent conductive layer (second transparent conductive layer 1082). Specifically, the electrode can be formed by screen printing or inkjet printing. After the electrode is formed, a heat treatment process needs to be performed on it. As an example, the heat treatment may include drying, curing, etc. The curing temperature is in the range of 80°C to 150°C.

[0081] As an example, electrodes can be fabricated on the P-side and / or N-side of the large-area perovskite / silicon-based tandem solar cell structure 100. The electrodes may include a top electrode 110 and a bottom electrode 111. The electrode materials include, but are not limited to, Ag, Cu, Au, or other metallic materials and mixtures thereof. Electrode fabrication methods include, but are not limited to, vapor deposition, screen printing, and PVD. Since the tandem solar cell structure is large-area, preferably, Ag electrodes can be fabricated using screen printing or inkjet printing, with a curing temperature between 90°C and 150°C and a curing time between 5 min and 20 min.

[0082] In related technologies, the material of the second transport layer 106 (e.g., the electron transport layer) is often carbon 60, and the material of the buffer layer is often Ald-SnO. x IZO is commonly used as the material for the transparent conductive layer. However, this results in a significant decrease in the thermal efficiency of the perovskite / silicon tandem solar cell during fabrication. The inventors discovered that this is because the interfacial tensile strength between the second transport layer and the buffer layer is very low (fracture energy approximately 1.2 J / m). 2 The two layers are prone to delamination. Furthermore, when fabricating the transparent conductive layer on the side of the buffer layer away from the transport layer, physical vapor deposition (PVD) sputtering is often used. During this process, the bombardment of the buffer layer by PVD sputtering can penetrate the buffer layer and affect the transport layer, increasing the likelihood of delamination between the second transport layer and the buffer layer. Further, after annealing at a certain temperature, the stress release within the transparent conductive layer intensifies the compression between the second transport layer and the buffer layer, further worsening the delamination at the interface. This reduces the carrier conduction efficiency at the interface, resulting in a significant decrease in the efficiency of the perovskite / silicon tandem solar cell structure (for example, the fill factor (FF) of the perovskite / silicon tandem solar cell structure decreases considerably after heating).

[0083] In this embodiment, during the fabrication process of the large-area perovskite / silicon-based tandem solar cell structure 100, electrodes are formed using screen printing or inkjet printing. By setting the transparent conductive layer 108 on the side of the buffer layer 107 away from the silicon substrate solar cell 101 as at least two layers, the first transparent conductive layer 1081 on the side closer to the silicon substrate solar cell 101 is set as a transparent conductive layer with lower density, and the second transparent conductive layer 1082 on the side away from the silicon substrate solar cell 101 is set as a transparent conductive layer with higher density. The overall performance of this stacked transparent conductive layer 108 can take into account both optical and electrical performance, satisfying the characteristics of high mobility, high transmittance, and low resistance. Moreover, during thermal annealing, during the stress release process of the transparent conductive layer 108, the first transparent conductive layer 1081 can alleviate the stress, reducing the impact of stress on the compression of the buffer layer 107 / second transport layer, thereby reducing the risk of interface peeling between the buffer layer 107 and / or the second transport layer, and improving the heat resistance of the large-area perovskite / silicon-based tandem solar cell structure 100.

[0084] Specifically, in this embodiment, the high-density second transparent conductive layer 1082 ensures the conductivity of the large-area perovskite / silicon-based tandem solar cell structure 100. However, the stress released by the second transparent conductive layer 1082 is relatively high, which has a significant squeezing effect on the lower film layer (buffer layer 107 / second transport layer), making the lower film layer prone to peeling. Therefore, this embodiment also uses a low-density first transparent conductive layer 1081 to buffer the stress generated by the heat treatment process of the second transparent conductive layer 1082, thereby reducing the squeezing effect on the lower film layer (buffer layer 107 / second transport layer) and reducing the risk of peeling of the buffer layer 107 / second transport layer.

[0085] Furthermore, as mentioned in the background section, the commonly used electrode fabrication methods for perovskite / silicon tandem solar cells are primarily achieved through vapor deposition, rather than the screen printing used in traditional solar cells. The inventors further discovered that at the curing temperature of ultra-low temperature metallization technology, the low-temperature paste cannot achieve good curing results, resulting in insufficient contact density and linear density. This limits the efficiency improvement of large-area perovskite / silicon tandem solar cell structures. Moreover, heating (annealing) large-area perovskite / silicon tandem solar cell structures at certain temperatures can cause efficiency degradation, further limiting the fabrication of large-area perovskite / silicon tandem solar cell modules.

[0086] In this embodiment, by setting a first transparent conductive layer 1081 with a relatively low density, the stress generated by the heat treatment process from the second transparent conductive layer 1082 is buffered, thereby improving the heat resistance of the large-area perovskite / silicon-based tandem solar cell structure 100 and making it more advantageous to use screen printing to fabricate electrodes. After multiple experiments, the inventors found that in the fabrication method of the large-area perovskite / silicon-based tandem solar cell structure 100 provided in this embodiment, the screen printing curing temperature can be increased from 100°C to 130°C, and an increase in the efficiency (FF) of the large-area perovskite / silicon-based tandem solar cell structure 100 can also be obtained. Moreover, in the large-area perovskite / silicon-based tandem solar cell structure 100, the efficiency after lamination can be improved from a decrease of 5%-6% to a decrease of 1%-2%.

[0087] In one embodiment, the buffer layer 107 includes at least one first buffer layer 1071 and at least one second buffer layer 1072, wherein the first buffer layer 1071 is located between the second transport layer and the second buffer layer 1072, and the density of the first buffer layer 1071 is greater than the density of the second buffer layer 1072.

[0088] The second buffer layer 1072 may be located between the first buffer layer 1071 and the transparent conductive layer 108. Furthermore, the density of the second buffer layer 1072 is less than that of the first buffer layer 1071, or the refractive index of the second buffer layer 1072 is less than that of the first buffer layer 1071. This embodiment does not impose specific limitations on the density or refractive index of the first buffer layer 1071 and the second buffer layer 1072.

[0089] As an example, the material of the second buffer layer 1072 may include at least one of tin oxide, zinc oxide, tin oxide, chromium oxide, and titanium oxide, or the material of the second buffer layer 1072 may include a mixture of the above-mentioned metal oxides. Of course, the material of the first buffer layer 1071 may be the same as the material of the second buffer layer 1072, that is, the material of the first buffer layer 1071 may also include other metal oxides.

[0090] The thickness of the second buffer layer 1072 can be in the range of 5nm-30nm. As an example, the thickness of the second buffer layer 1072 can be the same as the thickness of the first buffer layer 1071. The thickness of the second buffer layer 1072 can be between 1nm-30nm, and the refractive index can be between 1.8-2.4. As an example, the thickness of the first buffer layer 1071 can be greater than 50% of the thickness of the buffer layer 107, for example, the thickness of the first buffer layer 1071 is 50%, 60%, 70%, 80%, 90%, or 100% of the thickness of the buffer layer 107, preferably 50%-90%, thereby ensuring the electrical performance transfer between the first buffer layer 1071 and the second transport layer, and thus ensuring the performance of the large-area perovskite / silicon-based tandem solar cell structure 100.

[0091] In practical embodiments, the first buffer layer 1071 and the second buffer layer 1072 can be fabricated using the same process. In this case, they can be fused into one layer to further block the influence of ion migration caused by crystallization after annealing of the transparent conductive layer. For example, the fabrication methods include, but are not limited to, chemical vapor deposition (CVD), ALD, vapor deposition, PVD, RPD, or water bath method. Furthermore, if the first buffer layer 1071 and the second buffer layer 1072 are fabricated using different methods, the fabrication methods of the second buffer layer 1072 include, but are not limited to, vapor deposition, ALD, PVD, RPD, or solution method.

[0092] In this embodiment, the buffer layer 107 located on the side of the second transport layer away from the silicon substrate cell 101 is configured as a structure of at least two layers. The first buffer layer 1071 on the side closer to the silicon substrate cell 101 is configured as a buffer layer with higher density, while the second buffer layer 1072 on the side away from the silicon substrate cell 101 is configured as a buffer layer with lower density. During thermal annealing, during the stress release process of the buffer layer 107, the second buffer layer 1072 can alleviate the stress released from the top transparent conductive layer 108, reducing the compression on the second transport layer, thereby mitigating the risk of interface delamination between the buffer layer 107 and the second transport layer, and further improving the heat resistance of the large-area perovskite / silicon-based tandem cell structure 100. Simultaneously, since the first buffer layer 1071 is in contact with the second transport layer, the first buffer layer 1071 needs to be fabricated as a film layer with higher density, combining with the second transport layer to achieve better interface conduction and carrier transport. Furthermore, the energy levels of the first buffer layer 1071 and the second buffer layer 1072 are close, which can further block the influence of ion migration caused by the crystallization after the transparent conductive layer 108 is annealed, thereby preventing the efficiency of the large-area perovskite / silicon-based tandem battery structure 100 from decreasing.

[0093] It should be understood that although the steps in the flowchart of Figure 1 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0094] Based on the same inventive concept, in one embodiment, a large-area perovskite / silicon-based tandem solar cell structure 100 is provided. The large-area perovskite / silicon-based tandem solar cell structure 100 may include a silicon substrate solar cell 101, a first transport layer 103, a perovskite layer 104, a second transport layer 106, a buffer layer 107, a transparent conductive layer 108, and an electrode 110.

[0095] The silicon substrate cell 101 may include silicon substrate cells, which may include TOPCon cells, HJT cells, IBC cells, and HBC cells, etc.

[0096] The material of the transport layer may include carbon 60, etc. The first transport layer 103 and the second transport layer 106 may respectively comprise a hole transport layer and an electron transport layer. As an example, if the first transport layer 103 is a hole transport layer, the second transport layer 106 may be an electron transport layer; conversely, if the first transport layer 103 is an electron transport layer, the second transport layer 106 may be a hole transport layer. That is, the large-area perovskite / silicon-based tandem solar cell structure 100 of this application can be a nip structure or a pin structure.

[0097] The material of the buffer layer 107 may include Ald-SnO x For example, the material of the buffer layer 107 may include SnO2, with a thickness between 5 nm and 30 nm. The refractive index of the buffer layer 107 may be between 1.5 and 2.0.

[0098] The transparent conductive layer 108 includes at least one first transparent conductive layer 1081 and at least one second transparent conductive layer 1082. The first transparent conductive layer 1081 is located between the buffer layer 107 and the second transparent conductive layer 1082, and the density of the first transparent conductive layer 1081 is less than the density of the second transparent conductive layer 1082.

[0099] The texture of the first transparent conductive layer 1081 can be relatively loose. The texture of the second transparent conductive layer 1082 can be relatively dense. Further, the density of the first transparent conductive layer 1081 is less than the density of the second transparent conductive layer 1082, or the refractive index of the first transparent conductive layer 108 is less than the refractive index of the second transparent conductive layer 1082.

[0100] The material of the second transparent conductive layer 1082 may include ITO, IZO, AZO, IWO, IMO, etc. The thickness of the second transparent conductive layer 1082 can be in the range of 1nm-50nm. The material of the first transparent conductive layer 1081 may include, but is not limited to, ITO, IZO, AZO, IWO, IMO, etc. The thickness of the first transparent conductive layer 1081 can be in the range of 1nm-50nm. As an example, the thickness of the first transparent conductive layer 1081 accounts for 5%-50% of the total thickness of the transparent conductive layer. This allows the first transparent conductive layer 1081 to alleviate stress on both sides of the film while ensuring the conductivity of the large-area perovskite / silicon-based tandem solar cell structure 100.

[0101] In this embodiment, by setting the transparent conductive layer 108 on the side of the buffer layer 107 away from the silicon substrate cell 101 as at least two layers, the first transparent conductive layer 1081 on the side closer to the silicon substrate cell 101 is set as a transparent conductive layer with a lower density, and the second transparent conductive layer 1082 on the side away from the silicon substrate cell 101 is set as a transparent conductive layer with a higher density. The overall performance of this stacked transparent conductive layer can take into account both optical and electrical performance, satisfying the characteristics of high mobility, high transmittance, and low resistance. Moreover, during the stress release process of the transparent conductive layer 108 during heat annealing, the first transparent conductive layer 1081 can alleviate the stress and reduce the impact of stress on the compression of the buffer layer 107 / second transport layer, thereby reducing the risk of interface peeling between the buffer layer 107 / second transport layer and improving the heat resistance of the large-area perovskite / silicon-based stacked cell structure 100.

[0102] In one embodiment, the buffer layer 107 includes at least one first buffer layer 1071 and at least one second buffer layer 1072, wherein the first buffer layer 1071 is located between the second transport layer and the second buffer layer 1072, and the density of the first buffer layer 1071 is greater than the density of the second buffer layer 1072.

[0103] The density of the second buffer layer 1072 is less than that of the first buffer layer 1071, or the refractive index of the second buffer layer 1072 is less than that of the first buffer layer 1071. This embodiment does not impose specific limitations on the density or refractive index of the second buffer layer 1072.

[0104] The material of the second buffer layer 1072 may include at least one of tin oxide, zinc oxide, tin oxide, chromium oxide, and titanium oxide, or the material of the second buffer layer 1072 may include a mixture of the above-mentioned metal oxides. Of course, the material of the first buffer layer 1071 may be the same as the material of the second buffer layer 1072.

[0105] The thickness of the second buffer layer 1072 can be in the range of 5nm-30nm. As an example, the thickness of the second buffer layer 1072 can be the same as the thickness of the first buffer layer 1071. The thickness of the second buffer layer 1072 can be between 1nm-30nm, and the refractive index can be between 1.8-2.4. As an example, the thickness of the first buffer layer 1071 is greater than 50% of the thickness of the buffer layer 107. Preferably, the thickness of the first buffer layer 1071 is 50%-90% of the thickness of the buffer layer 107, thereby ensuring the electrical performance transfer between the first buffer layer 1071 and the second transport layer, and thus ensuring the performance of the large-area perovskite / silicon-based tandem solar cell structure 100.

[0106] In this embodiment, the buffer layer 107 located on the side of the transport layer away from the silicon substrate cell 101 is configured as a structure of at least two layers. The first buffer layer 1071 on the side closer to the silicon substrate cell 101 is configured as a buffer layer with higher density, while the second buffer layer 1072 on the side away from the silicon substrate cell 101 is configured as a buffer layer with lower density. During thermal annealing, during the stress release process of the buffer layer 107, the second buffer layer 1072 can alleviate the stress released from the top transparent conductive layer 108, reducing the compression on the second transport layer, thereby mitigating the risk of interface delamination between the buffer layer 107 and the second transport layer, and further improving the heat resistance of the large-area perovskite / silicon-based tandem cell structure 100. Simultaneously, since the first buffer layer 1071 is in contact with the second transport layer, the first buffer layer 1071 needs to be fabricated as a film layer with higher density, combining with the second transport layer to achieve better interface conduction and carrier transport. Furthermore, the energy levels of the first buffer layer 1071 and the second buffer layer 1072 are close, which can further block the influence of ion migration caused by the crystallization after the transparent conductive layer 108 is annealed, thereby preventing the efficiency of the large-area perovskite / silicon-based tandem battery structure 100 from decreasing.

[0107] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the phrase "this embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims. The above descriptions are merely preferred embodiments of this disclosure and do not limit the patent scope of this disclosure. Any equivalent structural transformations made based on the inventive concept of this disclosure, utilizing the content of this specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A large-area perovskite / silicon-based tandem solar cell structure, characterized in that, include: Silicon-based solar cells; The first transport layer is located on one side of the silicon substrate cell; A perovskite layer is located on the side of the first transport layer away from the silicon substrate cell; The second transport layer is located on the side of the perovskite layer away from the silicon substrate cell; A buffer layer is located on the side of the second transport layer away from the silicon substrate cell; A transparent conductive layer is located on the side of the buffer layer away from the silicon substrate cell, and the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer. The first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than that of the second transparent conductive layer. The electrodes are formed on the side of the transparent conductive layer away from the silicon substrate cell by screen printing or inkjet printing.

2. The large-area perovskite / silicon-based tandem solar cell structure according to claim 1, characterized in that, The thickness of the first transparent conductive layer accounts for 5%-50% of the total thickness of the transparent conductive layer.

3. The large-area perovskite / silicon-based tandem solar cell structure according to claim 1, characterized in that, The large-area perovskite / silicon-based tandem solar cell structure also includes: The buffer layer includes at least one first buffer layer and at least one second buffer layer, wherein the first buffer layer is located between the second transmission layer and the second buffer layer, and the density of the first buffer layer is greater than that of the second buffer layer.

4. The large-area perovskite / silicon-based tandem solar cell structure according to claim 3, characterized in that, The thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

5. The large-area perovskite / silicon-based tandem solar cell structure according to claim 3, characterized in that, The materials of the first buffer layer and the second buffer layer include at least one of tin oxide, zinc oxide, chromium oxide, and titanium oxide.

6. The large-area perovskite / silicon-based tandem solar cell structure according to claim 1, characterized in that, The first transport layer is an electron transport layer and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer and the second transport layer is an electron transport layer.

7. The large-area perovskite / silicon-based tandem solar cell structure according to claim 1, characterized in that, The first transport layer and the silicon substrate cell further include at least one tunneling junction or composite layer, and / or the second transport layer and the perovskite layer further include at least one passivation layer.

8. A method for fabricating a large-area perovskite / silicon-based tandem solar cell structure, characterized in that, Includes the following steps: Provide silicon-based solar cells; A first transport layer is formed on one side of the silicon substrate cell; A perovskite layer is formed on the first transport layer; A second transport layer is formed on the perovskite layer; A buffer layer is formed on the second transport layer; A transparent conductive layer is formed on the buffer layer, wherein the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer, the first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than the density of the second transparent conductive layer; An electrode is formed on the transparent conductive layer, and a heat treatment process is required after the electrode is formed.

9. The method for fabricating a large-area perovskite / silicon-based tandem solar cell structure according to claim 8, characterized in that, The thickness of the first transparent conductive layer accounts for 5%-50% of the total thickness of the transparent conductive layer.

10. The method for fabricating a large-area perovskite / silicon-based tandem solar cell structure according to claim 8, characterized in that, The buffer layer includes at least one first buffer layer and at least one second buffer layer, wherein the first buffer layer is located between the second transmission layer and the second buffer layer, and the density of the first buffer layer is greater than that of the second buffer layer.

11. The method for fabricating a large-area perovskite / silicon-based tandem solar cell structure according to claim 10, characterized in that, The thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

12. The method for fabricating a large-area perovskite / silicon-based tandem solar cell structure according to claim 8, characterized in that, The formation of electrodes on the transparent conductive layer includes: Electrodes are formed on the side of the transparent conductive layer away from the silicon substrate cell using screen printing or inkjet printing, with the heat treatment temperature ranging from 80°C to 150°C.

13. The method for fabricating a large-area perovskite / silicon-based tandem solar cell structure according to claim 8, characterized in that, The first transport layer is an electron transport layer and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer and the second transport layer is an electron transport layer.

14. The method for fabricating a large-area perovskite / silicon-based tandem solar cell structure according to claim 8, characterized in that, Before forming the first transport layer on one side of the silicon substrate cell, the process includes: At least one tunnel junction or composite layer is formed on the silicon substrate cell; And / or, Before forming the second transport layer on the perovskite layer, the process includes: At least one passivation layer is formed on the perovskite layer.

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