Encoding method, decoding method, and communication apparatus

Abstract

Provided are an encoding method, a decoding method, and a communication apparatus. In the method, a communication apparatus obtains a parity-check matrix on the basis of a first base matrix, and then performs LDPC encoding or decoding on the basis of the parity-check matrix. The first base matrix comprises a staircase structure and non-zero sub-matrices located at a lower right corner of the first base matrix, wherein the staircase supports row-by-row encoding and sliding window decoding, and the non-zero sub-matrices are configured for producing more parity-check bits during encoding, which is conducive to performing error correction on certain information bits with low decoding accuracy, and thereby improves overall decoding performance and increases communication reliability.

Description

Encoding methods, decoding methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202411550760.X, filed with the China National Intellectual Property Administration on October 31, 2024, entitled "Encoding Method, Decoding Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of wireless communication, and in particular to an encoding method, a decoding method, and a communication device. Background Technology

[0003] Low-density parity-check (LDPC) codes are linear block codes with sparse parity-check matrices. LDPC codes not only exhibit good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure. Therefore, they have been widely used in some communication systems.

[0004] Spatial coupled (SC)-LDPC codes combine the ideas of block coding and recursive convolutional coding, and have better decoding performance than traditional LDPC block codes. Therefore, they are considered a very promising coding scheme.

[0005] However, directly applying SC-LDPC codes to wireless communication systems results in low decoding accuracy for some information bits, which affects the overall decoding performance. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, and a communication device to optimize SC-LDPC codes, improve decoding performance, and enhance communication reliability.

[0007] Firstly, an encoding method is provided, which can be applied to a first communication device having encoding capabilities. The first communication device can be a communication equipment, such as a network device or a terminal device, or a component configured within the communication equipment, such as circuits or chips inside the communication equipment (e.g., modem chips, also known as baseband chips, or system-on-chip (SoC) chips containing modem cores, or system-in-package (SIP) chips, etc.), or a logic module or software capable of implementing some or all of the functions of the first communication device, etc., and this application does not limit this.

[0008] For example, the method includes: obtaining a parity-check matrix based on a first base matrix; and performing LDPC encoding on a first bit sequence having a first length based on the parity-check matrix to obtain a second bit sequence; wherein the first base matrix includes a first sub-block, a second sub-block, and a third sub-block; the first sub-block is H B1sub Or with H B1sub The submatrix H has row and / or column transformation relationships. B1sub satisfy:

[0009] The H B1sub In the middle, B w B0 is one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; B0 includes columns corresponding to the information bits in the first bit sequence; the W submatrices are non-zero submatrices of the same dimension, where 0 indicates a submatrix with the same dimension as B0. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w The second and third sub-blocks are located in the same number of rows below the first sub-block, with the second sub-block to the left of the third sub-block and the last column of the second sub-block not exceeding the last column of the first sub-block. The first column of the third sub-block is consecutive to the last column of the first sub-block. The second sub-block includes one or more sub-matrices from the W sub-matrices, excluding B0. The third sub-block is a full-rank square matrix and does not include columns corresponding to the information bits in the first bit sequence.

[0010] In this first basis matrix, X at different positions can be the same or different; X at each position can be a submatrix of all zeros or a non-zero submatrix. This application does not impose any restrictions on this.

[0011] Since the parity-check matrix can be obtained by expanding the matrix dimension based on the first base matrix, it is used to encode the first bit sequence. For ease of explanation, the following text will sometimes refer to encoding the first bit sequence based on the parity-check matrix obtained from the first base matrix, or simply as encoding the first bit sequence based on the first base matrix.

[0012] In the first base matrix, B0 includes columns corresponding to the information bits in the first bit sequence. That is, the encoded bits obtained by encoding the first bit sequence based on B0 can include information bits and parity bits. The third sub-block does not include columns corresponding to the information bits in the first bit sequence. That is, the encoded bits obtained by encoding the first bit sequence based on the third sub-block include parity bits but not information bits.

[0013] The first bit sequence has a first length; in other words, the first bit sequence is a bit sequence of finite length. This first bit sequence may include, for example, information bits from a code block (CB), or information bits from multiple CBs. Optionally, the first bit sequence may also include one or more cyclic redundancy check (CRC) codes (hereinafter referred to as check bits) from CBs; this application does not limit this.

[0014] Secondly, a decoding method is provided, which can be applied to a second communication device having decoding capabilities. The second communication device can be a communication equipment, such as a network device or a terminal device, or a component configured within the communication equipment, such as a circuit or chip inside the communication equipment (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software capable of implementing some or all of the functions of the second communication device, etc., and this application does not limit it in any way.

[0015] For example, the method includes: obtaining a second bit sequence; obtaining a parity check matrix based on a first basis matrix; and performing LDPC decoding on the second bit sequence based on the parity check matrix to obtain a third bit sequence with a first length; wherein the first basis matrix includes a first sub-block, a second sub-block, and a third sub-block; the first sub-block is H B1sub Or with H B1sub The submatrix H has row and / or column transformation relationships. B1sub satisfy:

[0016] The H B1sub In the middle, B w B0 is one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; B0 includes columns corresponding to the information bits in the third bit sequence; the W submatrices are non-zero submatrices of the same dimension, where 0 indicates a submatrix related to B0. w A zero submatrix with the same dimensions as B, where X represents the same submatrix as B. w The second and third sub-blocks are located in the same number of rows below the first sub-block, with the second sub-block to the left of the third sub-block and the last column of the second sub-block not exceeding the last column of the first sub-block. The first column of the third sub-block is consecutive to the last column of the first sub-block. The second sub-block includes one or more sub-matrices from the W sub-matrices, excluding B0. The third sub-block is a full-rank square matrix and does not include columns corresponding to the information bits in the first bit sequence.

[0017] For an explanation of the first basis matrix, please refer to the relevant description in the first aspect, which will not be repeated here.

[0018] The third bit sequence in the second aspect corresponds to the first bit sequence in the first aspect. For ease of distinction and explanation, this paper denotes the bit sequence obtained by decoding the second bit sequence as the third bit sequence. Theoretically, if the second communication device can correctly decode the second bit sequence, the decoded third bit sequence can be consistent with the first bit sequence. Therefore, the third bit sequence is the first bit sequence obtained through decoding, or in other words, the first bit sequence received.

[0019] Based on the technical solutions provided in the first or second aspect above, the first base matrix has a ladder-like structure, enabling row-by-row encoding and sliding-window decoding. When the resulting parity-check matrix is ​​used for LDPC encoding or decoding of the first bit sequence, it can support encoding or decoding by combining the ideas of block codes and convolutional codes, resulting in lower computational complexity and improved code throughput; it also helps improve decoding accuracy, exhibiting better decoding performance. Furthermore, by encoding the third sub-block located in the lower right corner of the first base matrix, more parity bits can be generated, providing more parity bits for error correction during decoding, thereby further improving decoding accuracy, decoding performance, and communication reliability.

[0020] In conjunction with the first aspect, in some possible implementations, LDPC encoding of a first bit sequence of a first length based on the parity check matrix includes: performing LDPC encoding of the first bit sequence of a first length row by row based on the parity check matrix.

[0021] By using line-by-line encoding, the encoded output of the previous line can be used as the encoded input of the next line. The encoded output of each line can be related not only to the information bits of the current line input, but also to the information bits of the previous line, which is more conducive to improving error correction performance, that is, improving decoding performance and communication reliability.

[0022] It should be noted that each submatrix in the first basis matrix includes at least one row and at least one column. For ease of distinction and explanation, this paper refers to one or more rows belonging to a submatrix occupying the same number of rows in the first basis matrix as a horizontal group, and one or more columns belonging to a submatrix occupying the same number of columns as a vertical group. Since the first basis matrix has a ladder-like structure, each horizontal group can be regarded as a layer of the first basis matrix, or in other words, a step corresponding to the first basis matrix.

[0023] Since the parity check matrix can be obtained by expanding the matrix dimension based on the first base matrix, performing LDPC encoding on the first bit sequence row by row according to the parity check matrix is ​​equivalent to performing LDPC encoding on the first bit sequence from top to bottom, group by group, with the horizontal groups in the first base matrix as the granularity.

[0024] In conjunction with the second aspect, in some possible implementations, the second bit sequence is LDPC decoded according to the parity check matrix, including: LDPC decoding of the second bit sequence by sliding window decoding according to the parity check matrix.

[0025] Corresponding to the line-by-line encoding method in the first aspect, the second communication device can use sliding window decoding to perform LDPC decoding on the second bit sequence. On the one hand, the second communication device can perform decoding based on the decoding window as soon as it receives the last bit corresponding to the decoding window, which greatly reduces the storage space requirement; on the other hand, the second communication device can decode the second bit sequence while receiving it, thus reducing the decoding time and improving the real-time performance of the system.

[0026] In conjunction with the first or second aspect, in some possible implementations, the H B1sub Each X in the matrix is ​​a zero submatrix.

[0027] In other words, the H B1sub satisfy:

[0028] In this way, a simpler first basis matrix can be obtained, which in turn leads to a simpler parity-check matrix. From the perspective of the encoding end (i.e., the first communication device), since the encoding input of the next horizontal group can be the encoding output of the previous horizontal group when encoding based on the idea of ​​convolutional codes, setting each X in the first basis matrix to a submatrix of all zeros reduces the number of information bits in the encoding input. From the perspective of the decoding end (i.e., the second communication device), the size of the decoding window does not need to be changed during sliding window decoding, thus reducing the computational load. Therefore, overall, the computational complexity of encoding and decoding is lower, and the decoding performance is almost unaffected, which is beneficial for improving the throughput of encoding and decoding, especially suitable for bit sequences with larger lengths (i.e., a larger first length).

[0029] In conjunction with the first or second aspect, in some possible implementations, the first basis matrix further includes a fourth sub-block located to the right of the first sub-block and above the third sub-block, and this fourth sub-block is an all-zero sub-matrix.

[0030] In other words, the fourth sub-block is located to the right of the first sub-block and above the third sub-block in the first base matrix, and therefore has the same number of rows as the first sub-block and the same number of columns as the third sub-block.

[0031] In conjunction with the first or second aspect, in some possible implementations, the first basis matrix H B1 satisfy:

[0032] Among them, [0 0 … 0 B W-1 …B1] is the second sub-block, B T This refers to the third sub-block.

[0033] As can be seen, the structure of this first basis matrix is ​​based on the design of the first sub-block described above. Therefore, the structure is simpler, the encoding and decoding complexity is lower, and the decoding performance is almost unaffected, which is beneficial for improving the throughput of encoding and decoding, and is especially suitable for bit sequences with larger lengths (i.e., larger first lengths).

[0034] In conjunction with the first or second aspect, in some possible implementations, the third sub-block is: a unit diagonal matrix, or a square matrix with row and / or column transformation relationships to a unit diagonal matrix, or a double diagonal matrix, or a square matrix with row and / or column transformation relationships to a double diagonal matrix, or a lower triangular matrix, or a square matrix with row and / or column transformation relationships to a lower triangular matrix.

[0035] A unit diagonal matrix, a double diagonal matrix, and a lower triangular matrix are all square matrices that have non-zero elements below the diagonal but no non-zero elements above the diagonal. A square matrix that has row and / or column transformation relationships with a unit diagonal matrix, a double diagonal matrix, or a lower triangular matrix can be restored to a unit diagonal matrix, a double diagonal matrix, or a lower triangular matrix through row and / or column transformations. This allows for top-down row-by-row encoding when encoding based on a third sub-block, simplifying the encoding process and reducing computational complexity.

[0036] In conjunction with the first or second aspect, in some possible implementations, the first length K is related to the number of columns k in B0 corresponding to the information bits in the first bit sequence. sub Satisfy: P×Z×k sub ≥K; P is the number of B0s in the first basis matrix, P is a positive integer greater than or equal to 1; Z is the lifting size of the parity check matrix, Z is a positive integer.

[0037] Here, the first length K can represent the number of information bits contained in the first bit sequence, or in other words, the number of information bits in the first bit sequence. It can be understood that the information bits contained in the first bit sequence are also the bits to be encoded, which can include the information bits to be encoded, or the information bits to be encoded and check bits to be encoded, such as cyclic redundancy check (CRC) bits.

[0038] One possibility is that the first length K is a fixed value. For example, the first length can be determined based on the transmission resources configured for the first bit sequence. In this case, P and k sub It can be determined based on K.

[0039] Optionally, the number P of B0 in the first sub-block is predefined, configured, or indicated. For example, P is a predefined value of the protocol. Or, P is a fixed value.

[0040] Furthermore, the column number k in B0 corresponds to the information bits in the first bit sequence. sub satisfy:

[0041] It is understandable that if K is divisible by (Z×P), then P×Z×k sub =K; if K is not divisible by (Z×P), then P×Z×k sub >K.

[0042] Furthermore, since the first length K also has an upper limit K... max Therefore, k sub Also satisfies:

[0043] Among them, K max For predefined threshold values.

[0044] Optionally, the number of columns k in B0 corresponding to the information bits in the first bit sequence sub For predefined, configured, or indicated purposes. For example, k sub Values ​​predefined by the protocol. For example, k. sub It is a fixed value.

[0045] Furthermore, the number P of B0s in the first sub-block satisfies:

[0046] It is understandable that K can be (Z×k) sub When P×Z×k is divisible by 0, sub =K; where K cannot be (Z×k) sub When P×Z×k is divisible by 0, sub >K.

[0047] The above scheme is for P or k sub If one term is determined first, such as through a predefined protocol, the method for determining the other term is given, which helps to obtain a first basis matrix that can be adapted to the first length, thereby facilitating correct encoding and decoding and ensuring communication reliability.

[0048] Combining the first and second aspects, in some possible implementations, B0 in the first sub-block has a Raptor-like structure.

[0049] In other words, B0 includes a core check subarray, an extended check subarray, an all-zero subarray, and a unit subarray. The core check subarray and the extended check subarray are located in the same number of columns, with the extended check subarray located below the core check subarray. The unit subarray is a square matrix with the same number of rows as the extended check subarray. The all-zero subarray has the same number of rows as the core check subarray, and the all-zero subarray has the same number of columns as the unit subarray. The number of rows in the core check subarray increases as the code rate decreases.

[0050] By designing B0 as a submatrix with a Raptor-like structure, the bitrate can be flexibly adjusted, thereby meeting more business needs and being suitable for a wider range of business types or scenarios.

[0051] Thirdly, an encoding method is provided, which can be applied to a first communication device having encoding capabilities. The first communication device can be a communication equipment, such as a network device or a terminal device, or a component configured within the communication equipment, such as a circuit or chip inside the communication equipment (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software capable of implementing some or all of the functions of the first communication device, etc., and this application does not limit it in any way.

[0052] For example, the method includes: obtaining a parity-check matrix based on a first basis matrix; and performing LDPC encoding on a first bit sequence having a first length based on the parity-check matrix to obtain a second bit sequence; wherein the first basis matrix is ​​H B1 Or with H B1 A matrix with row and / or column transformation relationships, this H B1 satisfy:

[0053] Among them, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions.

[0054] In this first basis matrix, X at different positions can be the same or different; X at each position can be a submatrix of all zeros or a non-zero submatrix. This application does not impose any restrictions on this.

[0055] For details regarding the first bit sequence, please refer to the first section above for a detailed explanation, which will not be repeated here.

[0056] Fourthly, a decoding method is provided, which can be applied to a second communication device having decoding capabilities. The second communication device can be a communication equipment, such as a network device or a terminal device, or a component configured within the communication equipment, such as a circuit or chip inside the communication equipment (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software capable of implementing some or all of the functions of the second communication device, etc., and this application does not limit it in this regard.

[0057] For example, the method includes: obtaining a second bit sequence; obtaining a parity check matrix based on a first basis matrix; and performing LDPC decoding on the second bit sequence based on the parity check matrix to obtain a third bit sequence of a first length; wherein the first basis matrix is ​​H. B1 Or with H B1 A matrix with row and / or column transformation relationships, this H B1 satisfy:

[0058] Among them, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions.

[0059] For details regarding the first bit sequence, please refer to the first section above for a detailed explanation, which will not be repeated here.

[0060] LDPC encoding or decoding based on the first basis matrix provided in the third or fourth aspect, compared to the basis matrix of SC-LDPC codes, has fewer constraints on the lower left submatrix, thus relaxing the restrictions on the basis matrix. The submatrices at each position in the lower left corner of the first basis matrix do not need to be strictly limited to all-zero submatrices; that is, the space for constructing the basis matrix is ​​larger. Furthermore, the submatrices at each position in the lower left corner of the first basis matrix can be selected based on performance, such as choosing submatrices that improve decoding performance, thereby improving decoding performance. In addition, since this first basis matrix does not introduce a tail B... T The submatrix is ​​so that it does not increase the parity bits, which means it does not cause a loss of bit rate.

[0061] In conjunction with the third or fourth aspect, in some possible implementations, the first basis matrix H B1 Each X in H is a submatrix consisting entirely of zeros. In other words, this H... B1 satisfy:

[0062] In this way, a simpler first basis matrix can be obtained, which in turn leads to a simpler parity-check matrix. Consequently, the computational complexity of encoding and decoding is lower, and the decoding performance suffers almost no loss, which is beneficial for improving code throughput, especially for bit sequences with longer lengths (i.e., a larger first length).

[0063] Fifthly, an encoding method is provided, which can be applied to a first communication device having encoding capabilities. The first communication device can be a communication equipment, such as a network device or a terminal device, or a component configured within the communication equipment, such as a circuit or chip inside the communication equipment (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software capable of implementing some or all of the functions of the first communication device, etc., and this application does not limit it in this regard.

[0064] For example, the method includes: obtaining a parity-check matrix based on a first basis matrix; and performing LDPC encoding on a first bit sequence having a first length based on the parity-check matrix to obtain a second bit sequence; wherein the first basis matrix is ​​H B1 Or with H B1 A matrix with row and / or column transformation relationships, this H B1 satisfy:

[0065] Among them, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions, and located at the same level as H B1 The last B W-1 There exists at least one non-zero submatrix among multiple X's in one or more rows of the same H, that is, a submatrix located in the same row of the same H. B1 The last B W-1 In a horizontal group, there exists at least one non-zero submatrix among multiple X's in the same horizontal group, and a horizontal group consists of one or more rows.

[0066] Among them, the H B1 The last B W-1 That is, located at H B1 B in the bottom right corner W-1 Since these W submatrices form a ladder structure in the first basis matrix, and with the H... B1 The last B W-1 One or more identical rows can also be called the H. B1 The last step.

[0067] In this first basis matrix, X at different positions can be the same or different; except for those located at the same position as H. B1 The last B W-1 In the same horizontal group, X at each position other than at least one non-zero submatrix can be either an all-zero submatrix or a non-zero submatrix. This application does not impose any limitation on this.

[0068] For details regarding the first bit sequence, please refer to the first section above for a detailed explanation, which will not be repeated here.

[0069] Sixthly, a decoding method is provided, which can be applied to a second communication device having decoding capabilities. The second communication device can be a communication equipment, such as a network device or a terminal device, or a component configured within the communication equipment, such as a circuit or chip inside the communication equipment (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software capable of implementing some or all of the functions of the second communication device, etc., and this application does not limit it in this regard.

[0070] For example, the method includes: obtaining a second bit sequence; obtaining a parity check matrix based on a first basis matrix; and performing LDPC decoding on the second bit sequence based on the parity check matrix to obtain a third bit sequence of a first length; wherein the first basis matrix is ​​H. B1 Or with H B1 A matrix with row and / or column transformation relationships, this H B1 satisfy:

[0071] Among them, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions, and located at the same level as H B1 The last B W-1 There exists at least one non-zero submatrix among multiple X in the same horizontal group.

[0072] For details on the first basis matrix, please refer to the fifth section for a detailed explanation, which will not be repeated here.

[0073] For details regarding the first bit sequence, please refer to the first section above for a detailed explanation, which will not be repeated here.

[0074] LDPC encoding or decoding based on the first basis matrix provided in the fifth or sixth aspect, compared to the basis matrix of SC-LDPC codes, has fewer constraints on the lower left submatrix, thus relaxing the restrictions on the basis matrix. The submatrices at each position in the lower left corner of the first basis matrix do not need to be strictly limited to all-zero submatrices; that is, the space for constructing the basis matrix is ​​larger. Furthermore, the submatrices at each position in the lower left corner of the first basis matrix can be selected based on performance, such as choosing submatrices that improve decoding performance, thereby improving decoding performance. Moreover, since this first basis matrix does not introduce a tail B... T The submatrix is ​​so that it does not increase the parity bits, which means it does not cause a loss of bit rate.

[0075] In conjunction with the fifth or sixth aspect, in some possible implementations, the first basis matrix H B1 satisfy:

[0076] Among them, B T It is a non-zero submatrix.

[0077] That is, the first basis matrix H B1 Except for the X in the first column and last row, which is a non-zero submatrix, all other X positions are all-zero submatrices.

[0078] In this way, a simpler first basis matrix can be obtained, which in turn leads to a simpler parity-check matrix. Consequently, the computational complexity of encoding and decoding is lower, and the decoding performance suffers almost no loss, which is beneficial for improving code throughput, especially for bit sequences with longer lengths (i.e., a larger first length).

[0079] In conjunction with aspects one through six, in some possible implementations, the W submatrices are predefined.

[0080] The W sub-matrices can be, for example, predefined by the protocol. The first communication device can pre-store the W sub-matrices, and when there is an encoding requirement, read the W sub-matrices and then generate the first basis matrix based on the W sub-matrices.

[0081] Optionally, the W submatrices can be randomly generated, or selected from a pre-stored set of submatrices, such as according to predetermined rules, or randomly selected. This application does not impose any limitations on this.

[0082] In conjunction with aspects one through six, in some possible implementations, W is a predefined value.

[0083] For example, W can be a value predefined by the protocol. In other words, W is a fixed value.

[0084] By predefining W, both the transmitting and receiving ends can obtain the first basis matrix based on the same W, thus enabling the second communication device to decode correctly and improving decoding performance. Furthermore, the transmitting and receiving ends do not need to indicate W via signaling, thereby avoiding signaling overhead.

[0085] Optionally, W is 2. When the first basis matrix obtained by W=2 is used for encoding, it can achieve the good decoding performance of convolutional codes, while the structure of the first basis matrix is ​​simple and does not bring too high computational complexity. Therefore, W=2 can achieve a trade-off between decoding performance and computational complexity.

[0086] In conjunction with aspects one through six, in some possible implementations, the method further includes: obtaining a first basis matrix based on a second basis matrix; the second basis matrix being H B2 Or with H B2 A matrix with row and / or column transformation relationships, this H B2 satisfy:

[0087] As can be seen, the first sub-block of the first basis matrix can be a sub-matrix of the second basis matrix. By defining the second basis matrix, the first and second communication devices can obtain the first basis matrix based on it. Therefore, the first and second communication devices can pre-store the second basis matrix and generate the first basis matrix when encoding is required. This saves storage overhead.

[0088] In conjunction with aspects one through six, in some possible implementations, the method further includes: determining the use of a first basis matrix.

[0089] In some possible implementations of the first, third, or fifth aspect, the determination to use the first base matrix includes: determining the use of the first base matrix based on one or more of the following: a first length, the service type to which the first bit sequence belongs, the code rate, the capability of the first communication device, or the capability of the second communication device communicating with the first communication device.

[0090] The first communication device can choose to use or not use the first base matrix for encoding based on actual needs and equipment capabilities. Therefore, it can flexibly choose different encoding schemes to cope with different scenarios and obtain greater benefits in different scenarios.

[0091] Furthermore, the method further includes: sending first indication information, which is used to indicate the use of a first base matrix, or to indicate the first base matrix.

[0092] Accordingly, in some possible implementations of the second, fourth, or sixth aspects, the method further includes: receiving first indication information, which is used to indicate the use of a first basis matrix, or to indicate a first basis matrix; the determination to use the first basis matrix includes determining the use of the first basis matrix based on the first indication information.

[0093] That is, the first communication device determines whether to use the first base matrix, and then notifies the second communication device through the first indication information, so that the second communication device can also encode based on the same base matrix, thus avoiding decoding errors and improving communication reliability.

[0094] In some other possible implementations of the first, third, or fifth aspects, the method further includes: receiving second indication information for indicating the use of a first basis matrix, or for indicating the use of a first basis matrix; the determination of using the first basis matrix includes: determining the use of the first basis matrix based on the second indication information.

[0095] Accordingly, in some other possible implementations of the second, fourth, or sixth aspects, the determination to use the first base matrix includes: determining the use of the first base matrix based on one or more of the following: a first length, the service type to which the first bit sequence belongs, the code rate, the capability of the second communication device, or the capability of the first communication device communicating with the second communication device.

[0096] The second communication device can choose to use or not use the first basis matrix for decoding based on actual needs and equipment capabilities. Since decoding and encoding are corresponding, the second communication device's choice to use or not use the first basis matrix for decoding is also a choice to use or not use the first basis matrix for encoding. Therefore, different encoding schemes can be flexibly selected to cope with different scenarios and obtain greater benefits in different scenarios.

[0097] Furthermore, the method further includes: sending a second indication message, the second indication message being used to indicate the use of a first base matrix, or to indicate the first base matrix.

[0098] That is, the second communication device determines whether to use the first base matrix, and then notifies the first communication device through the second indication information, so that the first communication device communicating with it can also perform decoding based on the same base matrix, thus avoiding decoding errors and improving communication reliability.

[0099] Furthermore, both the first and second indication information can be used to determine the use of the first basis matrix, that is, to indicate the use of the first basis matrix. The first or second indication information can indicate the use of the first basis matrix through an indication field, thus allowing for the indication of its use with minimal indication overhead. Alternatively, the first or second indication information can directly indicate the elements included in the first basis matrix (e.g., non-zero submatrices and their positions), allowing the receiver (e.g., the second communication device receiving the first indication information or the first communication device receiving the second indication information) to avoid additionally storing the first basis matrix, thereby saving storage overhead. Indicating the use of the first basis matrix, or indicating the first basis matrix, through the first and second indication information facilitates the flexible application of the first basis matrix; for example, in the presence of multiple basis matrices, one can be indicated for use.

[0100] A seventh aspect provides an apparatus. This apparatus may include modules corresponding to each of the methods / operations / steps / actions described in any one of the first to sixth aspects, or may include modules corresponding to each of the methods / operations / steps / actions described in any one of the first to sixth aspects. The module may be hardware circuitry, software, or a combination of hardware circuitry and software implementation.

[0101] In one design, the device may include a processing module and a communication module. The communication module is used to perform the sending and receiving actions performed by the first communication device in the methods described in the first, third, or fifth aspects above, while the processing module is used to perform processing-related actions performed by the first communication device in the methods described in the first, third, or fifth aspects above.

[0102] In one design, the device may include a processing module and a communication module. The communication module is used to perform the sending and receiving actions performed by the second communication device in the methods described in the second, fourth, or sixth aspects above, while the processing module is used to perform processing-related actions performed by the second communication device in the methods described in the second, fourth, or sixth aspects above.

[0103] In one design, the device can be a terminal device, or a device, module, circuit, or chip configured in the terminal device, or a device that can be used in conjunction with the terminal device.

[0104] In one design, the device can be a network device, or a device, module, circuit, or chip configured in the network device, or a device that can be used in conjunction with the network device.

[0105] Eighthly, an apparatus is provided, including a processor and a storage medium storing instructions that, when executed by the processor, cause a method as described in any possible implementation of the first to sixth aspects to be implemented, or cause a method as described in any possible implementation of the first to sixth aspects to be implemented.

[0106] A ninth aspect provides an apparatus comprising a processing circuit for processing data and / or information such that a method as in any possible implementation of the first to sixth aspects is implemented, or that a method as in any possible implementation of the first to sixth aspects is implemented.

[0107] The processing circuit may include one or more processors, or all or part of the circuitry in one or more processors used for processing functions.

[0108] Optionally, the apparatus may further include a memory for storing programs or instructions, and the processor for running the programs or instructions to implement the methods as described in any of the possible implementations of the first to sixth aspects.

[0109] Optionally, the device may also include the transceiver circuit, or an input / output interface.

[0110] In a tenth aspect, a chip is provided, including processing circuitry for running a program or instructions to implement a method as described in any possible implementation of the first to sixth aspects.

[0111] Optionally, the chip may further include a memory for storing programs or instructions.

[0112] Optionally, the chip may also include transceiver circuitry, or input / output interfaces.

[0113] Eleventhly, a computer-readable storage medium is provided, the computer-readable storage medium including instructions that, when executed by a processor, cause the method as in any possible implementation of the first to sixth aspects to be implemented.

[0114] In a twelfth aspect, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed, cause a method as described in any possible implementation of the first to sixth aspects to be implemented.

[0115] In a thirteenth aspect, a communication system is provided, the communication system including means for performing any possible implementation of the first to sixth aspects.

[0116] It should be understood that aspects seven to thirteen of this application correspond to the technical solutions of aspects one to six of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0117] Figure 1 is a schematic diagram of a communication system applicable to the method provided in the embodiments of this application;

[0118] Figure 2 is a schematic diagram of several different communication scenarios applicable to the method provided in the embodiments of this application;

[0119] Figure 3 is a schematic diagram of the signal processing process of the physical layer provided in the embodiment of this application;

[0120] Figure 4 is a schematic block diagram of the apparatus used to implement physical layer processing;

[0121] Figure 5 is an example of a Tanner diagram provided in an embodiment of this application;

[0122] Figure 6 is an example of a ladder-type convolutional structure code provided in an embodiment of this application;

[0123] Figure 7 shows the binding basis matrix B provided in the embodiments of this application. SC Examples of horizontal and vertical groups;

[0124] Figure 8 shows the embodiment of this application based on the basis matrix B. SC A schematic diagram of sliding window decoding;

[0125] Figure 9 is a schematic flowchart of the encoding method provided in the embodiments of this application;

[0126] Figure 10 is a schematic diagram of the structure of the first basis matrix provided in an embodiment of this application;

[0127] Figure 11 is a schematic diagram of the structure of the third sub-block provided in an embodiment of this application;

[0128] Figure 12 is a stepped structure based on the first basis matrix provided in an embodiment of this application;

[0129] Figures 13A and 13B are schematic diagrams of the first basis matrix provided in the embodiments of this application;

[0130] Figures 14A and 14B are another schematic diagram of the first basis matrix provided in the embodiments of this application;

[0131] Figure 15 is a schematic diagram of a submatrix B0 with a Raptor-like structure provided in an embodiment of this application;

[0132] Figures 16 to 21 are schematic diagrams of the first basis matrix provided in the embodiments of this application;

[0133] Figure 22 is a schematic flowchart of the decoding method provided in the embodiments of this application;

[0134] Figures 23A and 23B are schematic diagrams of sliding window decoding based on the first basis matrix provided in the embodiments of this application;

[0135] Figure 24 is another schematic diagram of sliding window decoding based on the first basis matrix provided in an embodiment of this application;

[0136] Figures 25 and 26 are schematic block diagrams of a communication device provided in an embodiment of this application. Detailed Implementation

[0137] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0138] To facilitate understanding of the embodiments of this application, the following points will be explained first:

[0139] First, for ease of understanding and explanation, the terms encoder and decoder (or decoder) are introduced in this application. These names are given only to distinguish different functions and do not limit the structure of the communication device. For example, a first communication device has an encoding function, so it can be said that the first communication device includes an encoder, which can be understood as a functional module in the first communication device; a second communication device has a decoding function, so it can be said that the second communication device includes a decoder, which can be understood as a functional module in the second communication device. In specific implementations, the encoder and decoder can be implemented separately in hardware, or in software, or in a combination of hardware and software; this application does not limit this.

[0140] Of course, the first communication device may also have a decoding function, and the second communication device may also have an encoding function; that is, the first communication device may also include a decoder, and the second communication device may also include an encoder. This application does not limit this.

[0141] It is understood that the communication device in this application can also be replaced by a device or an encoding / decoding device, for example, the first communication device can be replaced by a first device or an encoding / decoding device, and the second communication device can be replaced by a second device or an encoding / decoding device.

[0142] Second, in this application, the indication includes direct indication (also known as explicit indication) and indirect indication (also known as implicit indication). Direct indication information A refers to information A; indirect indication information A can refer to indicating information A through the correspondence between information A and information B and direct indication information B; or it can refer to indicating information A through a preset rule that can be used to determine A based on B and direct indication information B. The correspondence between information A and information B, and the preset rule, can be predefined, pre-stored, pre-burned, or pre-configured.

[0143] Third, for ease of understanding, this application uses multiple accompanying drawings to describe the encoding and decoding methods provided in this application. These drawings are merely examples and should not be construed as limiting this application in any way. For example, the order of steps shown in the various drawings can be easily modified according to their functions and internal logic; furthermore, all steps in each drawing can be performed, or only a portion of them can be performed, as long as the same function as in the embodiments of this application can be achieved.

[0144] Fourth, the use of prefixes such as "first" and "second" in this application is solely for the purpose of distinguishing different things belonging to the same name category, and does not constrain the order, size, or quantity of things. For example, "first instruction information" and "second instruction information" are simply different instruction information, and there is no temporal sequence, size, or priority relationship between them; similarly, "first basis matrix" and "second basis matrix" are simply different basis matrices, and there is no temporal sequence, size, or priority relationship between them. It should be understood that such described objects can be interchanged where appropriate, so as to describe solutions other than those in the embodiments of this application.

[0145] Fifth, in this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the preceding and following related objects, but it does not exclude the possibility of indicating an "and" relationship. The specific meaning can be understood in conjunction with the context. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c; a and b; a and c; b and c; or a and b and c. Here, a, b, and c can be single or multiple.

[0146] Sixth, the use of prefixes such as "first" and "second" in this application is merely for the purpose of distinguishing and describing different things belonging to the same category of names, and does not constrain the order, size, or quantity of things. For example, "first communication device" and "second communication device" are simply different devices, and do not limit the number of devices or their priority; similarly, "first information" and "second information" are simply different information, and there is no temporal sequence, size, or priority relationship between them.

[0147] Seventh, in this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to the second communication device" can be understood as the destination of the information being the second communication device, which may include direct transmission via the air interface or indirect transmission via the air interface by other units or modules. "Receive information from the second communication device" can be understood as the source of the information being the second communication device, which may include direct reception from the second communication device via the air interface or indirect reception from the second communication device via the air interface by other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface.

[0148] In other words, sending and receiving can be done between devices, such as between a second communication device and a first communication device; or it can be done within a device, such as between components, modules, chips, software modules, or hardware modules within a device via a bus, wiring, or interface.

[0149] Eighth, in the embodiments of this application, "when," "if," and "if" all refer to the device making corresponding processing under certain objective circumstances, and are not limited to a time, nor do they require the device to make a judgment action when it is implemented, nor do they mean that there are other limitations.

[0150] Ninth, in this application, the words "example," "exemplarily," "for example," or "such as" are used to indicate that something is being described as an example, illustration, or explanation. Any embodiment or design described as "example," "exemplarily," "for example," or "such as" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "example," "exemplarily," "for example," or "such as" is intended to present the relevant concepts in a specific manner.

[0151] Tenth, to facilitate understanding of the method provided in this application, specific examples are used in several places in the following description. In the examples shown below, the row index, column index, etc., are numbered starting with 0, but this should not constitute any limitation on this application. For example, these numbers can also start with 1, or with other preset values. Therefore, this application does not limit the range of values ​​for the row index, column index, etc.

[0152] Eleventh, in the embodiments of this application, for ease of understanding and explanation, the submatrices in the basis matrix are represented by "B". w “B” T The submatrices are represented by "", "X", and "0". Each submatrix can contain one or more rows and one or more columns. For example, B w X and 0 can be m sub ×n sub submatrix, m sub and n sub All are positive integers; B T It can be m sub ×n sub The submatrix can also be m. sub ×m sub The matrix is ​​a square matrix. Therefore, in the following descriptions and diagrams of these submatrices, for ease of distinction from the rows and columns of the base matrix, the submatrices will be located in (or occupy) the same one or more columns (e.g., m) in the first base matrix. sub A column containing one or more submatrices (e.g., m columns) is called a vertical group. Groups that occupy the same one or more rows (e.g., m columns) are grouped together. sub A row containing one or more submatrices in a given base matrix is ​​called a horizontal group. A horizontal group consists of one or more columns that are identical in the base matrix (i.e., have the same column indices); and one or more rows that are identical in the base matrix (i.e., have the same row indices). For a better understanding of vertical and horizontal groups, please refer to the following explanation with reference to matrices and diagrams; it will not be elaborated upon here.

[0153] The technical solutions provided in this application can be applied to various communication systems, such as: 5th generation (5G) or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, wireless local area network (WLAN) systems, satellite communication systems, future communication systems, or integrated systems of multiple systems. The technical solutions provided in this application can also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems.

[0154] In a communication system, a device can send signals to or receive signals from another device. These signals can include information, signaling, or data. The device can also be replaced by an entity, network entity, communication equipment, communication module, node, communication node, etc.; this application uses a device as an example. For instance, a communication system can include at least one terminal device and at least one network device. The network device can send downlink signals to the terminal device, and / or the terminal device can send uplink signals to the network device. It is understood that the terminal device in this application can be replaced by a first communication device, and the network device can be replaced by a second communication device, both performing the corresponding encoding or decoding methods described in this application.

[0155] The radio access network (RAN) device in this application is a device with wireless transceiver capabilities. The RAN device can provide wireless communication services, enabling terminal devices to access the wireless network. The RAN can also be called an access network device or a network device. In the embodiments of this application, the network device can refer to a radio access network (RAN) node (or device) applied in a cellular network (or mobile network) to connect terminal devices to the wireless network. It can also be a Zigbee base station, a Bluetooth master (BT master), a Bluetooth Low Energy (BLE) master, a long-range radio (Lora) base station, or a Wi-Fi access point.

[0156] Network equipment can be a base station. The term "base station" can broadly encompass, or be interchangeable with, various names including: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or similar entities, or combinations thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device that performs base station functions in D2D, V2X, and M2M communications, or a device that performs base station functions in future communication systems. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technologies or equipment forms used in the network equipment.

[0157] In some deployments, the network devices mentioned in the embodiments of this application may be devices including CU, DU, or CU and DU, or devices with control plane CU nodes (central unit-control plane (CU-CP)) and user plane CU nodes (central unit-user plane (CU-UP)) and DU nodes. For example, the network devices may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0158] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0159] RAN nodes can support one or more types of fronthaul interfaces, each corresponding to a DU and RU with different functions. If the fronthaul interface between the DU and RU is a Common Public Radio Interface (CPRI), the DU is configured to implement one or more baseband functions, and the RU is configured to implement one or more radio frequency functions. If the fronthaul interface between the DU and RU is another type of interface, relative to CPRI, it moves some downlink and / or uplink baseband functions—for example, for downlink, one or more of precoding, beamforming (BF), or inverse fast Fourier transform (IFFT) / adding a cyclic prefix (CP)—from the DU to the RU; and for uplink, one or more of beamforming (BF), or fast Fourier transform (FFT) / removing CP—from the DU to the RU. In one possible implementation, this interface can be an enhanced common public radio interface (eCPRI). Under the eCPRI architecture, the splitting methods between DU and RU are different, corresponding to different types (category, Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, F.

[0160] Taking eCPRI Cat A as an example, for downlink transmission, layer mapping is used as the dividing line. The DU is configured to implement one or more functions preceding layer mapping (i.e., coding, rate matching, scrambling, modulation, and layer mapping itself), while other functions following layer mapping (e.g., resource element (RE) mapping, digital BF, or IFFT / CP addition) are implemented in the RU. For uplink transmission, de-RE mapping is used as the dividing line. The DU is configured to implement one or more functions preceding de-mapping (i.e., decoding, rate matching de-matching, descrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and de-RE mapping itself), while other functions following de-mapping (e.g., digital BF or FFT / CP removal) are implemented in the RU. It is understood that descriptions of the functions of the DU and RU corresponding to various types of eCPRI can be found in the eCPRI protocol and will not be elaborated upon here.

[0161] In one possible design, the processing unit in the BBU used to implement baseband functions is called the baseband high (BBH) unit, and the processing unit in the RRU / AAU / RRH used to implement baseband functions is called the baseband low (BBL) unit.

[0162] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open-RAN (O-RAN or ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules. The network device in this application can be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, general-purpose hardware can be a server, such as a cloud server.

[0163] In this embodiment, the apparatus for implementing the functions of a network device can be a network device itself; it can also be an apparatus capable of supporting the network device in implementing those functions, such as a chip system, hardware circuit, software module, or a hardware circuit plus a software module. This apparatus can be installed in the network device or used in conjunction with the network device. In this embodiment, the example of a network device being used to implement the functions of a network device is provided only and does not constitute a limitation on the solutions described in this embodiment.

[0164] The terminal equipment in this application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device.

[0165] Terminal devices can be devices that provide voice / data, such as handheld devices with wireless connectivity, in-vehicle devices, etc. Currently, examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving vehicles, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, wearable devices, terminal devices in 5G networks, or future public land mobile communication networks. Terminal devices in a network (PLMN), devices in a Zigbee network, devices in a LoRa network, Bluetooth slaves, Bluetooth Low Energy slaves, Wi-Fi stations (STAs), etc. This application does not limit the scope of the embodiments.

[0166] Terminal devices can also be terminal devices in an IoT system, also known as IoT nodes. IoT is an important component of future information technology development. Its main technical characteristic is connecting objects to networks through communication technologies, thereby realizing an intelligent network that enables human-machine interconnection and machine-to-machine interconnection. Connectivity can be achieved through broadband or narrowband technologies. IoT technology, for example, can achieve massive connectivity, deep coverage, and low terminal power consumption through narrowband (NB) technology. IoT technologies include reflective communication technology, spread spectrum technology, and ultra-wideband (UWB), which will not be elaborated further.

[0167] In addition, terminal devices may also include sensors such as smart printers, train detectors, and gas stations. Their main functions include collecting data (for some terminal devices), receiving control information and downlink data from network devices, and sending electromagnetic waves to transmit uplink data to network devices.

[0168] By way of example and not limitation, in this embodiment, the terminal device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0169] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or it can be any device capable of supporting the terminal device in implementing those functions, such as a chip system. This device can be installed in or used in conjunction with the terminal device. In this embodiment, the chip system can be composed of chips or may include chips and other discrete components. This embodiment only uses the terminal device as an example to illustrate the device for implementing the functions of the terminal device, and does not constitute a limitation on the solution of this embodiment.

[0170] The terminal device in this application can be a hardware device, a software function running on dedicated hardware, or a software function running on general-purpose hardware. It can also be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, the general-purpose hardware can be a server, such as a cloud server.

[0171] Network devices and / or terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and satellites. This application does not limit the scenario in which the network devices and terminal devices are located.

[0172] Figure 1 is a schematic diagram of the architecture of the communication system 10 applied in an embodiment of this application. Figure 1 shows a schematic diagram of a possible, non-limiting system architecture. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network 200. Optionally, the communication system 10 also includes an Internet 300. The RAN 100 may include at least one RAN node (110a and 110b in Figure 1) and at least one terminal device (120a-120j in Figure 1). The terminal device can be wirelessly connected to the radio access network device. Terminal devices and radio access network devices can be interconnected via wired or wireless means. RAN node 110a or 110b is connected to the core network 200 wirelessly or via wired means. The core network device in the core network 200 and the RAN node 110a or 110b in the RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0173] Figure 1 is just a schematic diagram. The communication system 10 may also include other network devices, such as wireless relay devices and wireless backhaul devices, which are not shown in Figure 1.

[0174] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as a 4th generation (4G), 5G mobile communication system, or a future-oriented evolution system. RAN 100 can also be an ORAN, a cloud radio access network (CRAN), a Zigbee network system, or a wireless fidelity (Wi-Fi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0175] The RAN node can be an airborne base station, such as satellite base station 110a; or an indoor base station, such as a micro base station or indoor station 110b. It should be understood that this application does not limit the specific technology or device form used in the wireless access network equipment. For ease of description, the following description uses a base station as an example of a wireless access network device.

[0176] The terminal device can be a terminal device deployed in the air, such as a helicopter or drone 120i in Figure 1; or it can be a terminal device deployed on the ground, such as mobile phones 120a, 120e, 120f and 120j, vehicle 120b, computer 120g, printer 120h, gas station 120c, smart home device 120d, etc. in Figure 1.

[0177] Alternatively, the terminal device can also be used as a RAN node. For example, the UE can act as a scheduling entity, providing sidelink signaling between terminal devices in vehicle-to-everything (V2X), device-to-device (D2D), or peer-to-peer connections.

[0178] RAN nodes and terminal devices can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; on water; or in the air on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the RAN nodes and terminal devices.

[0179] The roles of RAN nodes and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a RAN node. For terminal devices 120j that access RAN 100 through 120i, terminal device 120i is a RAN node; however, for RAN node 110a, 120i is a terminal device. That is, 110a and 120i communicate via a radio interface protocol. Of course, 110a and 120i can also communicate via an interface protocol between RAN nodes. In this case, 120i is also a RAN node relative to 110a. Therefore, RAN nodes and terminal devices can both be collectively referred to as communication devices. 110a, 110b, and 120a-120j in Figure 1 can be called communication devices with their respective corresponding functions, such as communication devices with RAN node functions or communication devices with terminal functions.

[0180] In the embodiments of this application, the functions of the RAN node can be executed by modules (such as chips) within the RAN node, or by a control subsystem that includes RAN node functions. This control subsystem, including RAN node functions, can be a control center in the aforementioned terminal application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. The functions of the terminal device can also be executed by modules (such as chips) within the terminal device, or by a device that includes terminal device functions. This application does not limit the scope of these limitations.

[0181] Figure 2 is a schematic diagram of several different communication scenarios applicable to the methods provided in the embodiments of this application. Examples include point-to-point transmission between RAN nodes and terminals or between terminals (as shown in Figure 2(a)), multi-hop transmission between RAN nodes and terminals (as shown in Figure 2(b) and (c)), dual connectivity (DC) between multiple RAN nodes and terminals (as shown in Figure 2(d)), and other scenarios. It should be noted that the specific communication application scenarios described above are merely examples and do not constitute limitations. In particular, from a business perspective, the embodiments of this application are applicable to many business scenarios, such as data encoding scenarios in extended reality (XR) services and high-capacity uplink scenarios. Furthermore, Figure 2 does not impose limitations on the network architecture applicable to this application, and this application does not limit uplink, downlink, access link, backhaul link, sidelink (SL), and other transmission methods.

[0182] Figure 3 is a schematic diagram of the signal processing process of the physical layer applicable to embodiments of this application. The signal processing of the physical layer can be divided into downlink processing and uplink processing.

[0183] Downlink processing is the process of processing information data from higher layers using the physical layer before transmitting it. For example, downlink processing includes: performing channel coding (or simply coding) on ​​the layer 2 (L2) information data, modulation, layer mapping, precoding, framing, IFFT, and frequency conversion using radio frequency (RF) or intermediate radio frequency (IRF) to process it into an air interface signal to be transmitted.

[0184] More specifically, the data transmitter can divide the data from Layer 2 into multiple TBs based on the system's supported transport block (TBS) size, and add a cyclic redundancy check (CRC) code to each TB. If the size of the TB after adding the CRC code exceeds the maximum block length, the TB can be segmented into multiple code blocks (CBs). Each segmented CB can be further CRC-coded to obtain the input to be encoded corresponding to each CB. This input to be encoded is a sequence of bits to be encoded, which may include the information bits in the corresponding CB and the check bits (i.e., the CRC code) of the CB.

[0185] The transmitter can perform channel coding on the input to be encoded, such as LDPC coding, to obtain the corresponding coded code blocks. Rate matching is then performed on the coded code blocks, and the rate-matched coded code blocks are concatenated to form a codeword (CW). The transmitter can scramble the codeword to generate scrambling bits. The scrambling bits are modulated to obtain modulation symbols. After being mapped by resource elements (REs), the modulation symbols are mapped onto multiple REs, thus obtaining the value carried on each RE. Based on the values ​​carried on these REs, the transmitter can generate a baseband signal. The baseband signal can then undergo RF or IRF processing and be transmitted by the antenna.

[0186] It should be understood that each channel coding operation at the transmitting end can be channel coding of one input to a CB (Block Controller) or channel coding of multiple inputs to CBs. In other words, each channel coding operation can target inputs corresponding to one or more CBs.

[0187] Uplink processing is the process of physical layer processing of signals received through the air interface. For example, uplink processing includes: performing RF or IRF processing on the received signal to obtain the baseband signal, and then completing physical layer signal processing through FFT, deframing, demodulation, and decoding, and then handing the obtained information data to layer 2.

[0188] More specifically, the signal receiver performs RF or IRF processing on the signal received from the antenna to obtain the baseband signal. Subsequently, the receiver's physical layer can sequentially perform RE mapping, demodulation, descrambling, rate matching de-matching, and channel decoding on the signal to obtain the bit sequence before encoding, which may specifically include information bits and parity bits.

[0189] Optionally, after completing RE mapping and before demodulation, the receiver can perform channel equalization. Channel equalization is based on the channel estimated by the channel, and the influence of the channel is removed by using an equalization algorithm, thereby ensuring correct signal demodulation.

[0190] Optionally, after modulation and before RE mapping, the transmitting end can perform layer mapping and precoding. For example, the transmitting end can map the modulation symbols to multiple layers, and the layer-mapped modulation symbols are then precoded to obtain a precoded signal. The precoded signal is then mapped to multiple REs via RE mapping. Correspondingly, after performing de-layer mapping, the receiving end performs channel equalization and then demodulation; or, the receiving end can perform de-layer mapping and then demodulation after completing channel equalization; or it can perform de-layer mapping and then channel equalization after completing deframe.

[0191] Since the specific implementation methods of each step in Figure 3 can be achieved through existing solutions or future solutions, for example, refer to the relevant chapters in the 3rd generation partnership project (3GPP) technical specification (TS) 38.211, they will not be described in detail here.

[0192] The apparatus for implementing one or more of the above-mentioned physical layer processing can be a communication device, such as a network device or terminal, or a mobile communication chip, such as a baseband chip; this application does not limit this. Based on different functions, the apparatus can be divided into multiple units (or modules). For example, FIG4 is a schematic block diagram of an apparatus for implementing physical layer processing. FIG4(a) and (b) show apparatus 400A and apparatus 400B, respectively. Apparatus 400A can be used to implement uplink processing, and apparatus 400B can be used to implement downlink processing.

[0193] As shown in Figures 4(a) and (b), devices 400A and 400B respectively include a computing unit, a control unit, and a storage unit. The computing unit is responsible for processing the logical operations of the device, specifically including encoding and / or decoding logical operations. The storage unit is responsible for storing data during the computing process, and can also store information related to encoding and decoding, such as the base map. The control unit is responsible for scheduling and controlling the computing unit and storage resources.

[0194] For example, as shown in FIG4(a), the computing unit of device 400A can be used to perform operations such as TB CRC calculation, basic graph (BG) selection, code block segmentation, CB CRC calculation, LDPC encoding, and code block concatenation. The BG selection can be made from BGs stored in the storage unit.

[0195] For example, as shown in FIG4(b), the computing unit of device 400B can be used to perform operations such as rate matching, hybrid automatic repeat request (HARQ) merging, LDPC decoding, CB CRC check, and TB CRC check.

[0196] In another possible implementation, the module in device 400A used for LDPC encoding is an encoder. In yet another possible implementation, the encoder can not only implement LDPC encoding but also perform LDPC encoding preprocessing and / or post-processing. LDPC encoding preprocessing includes, for example, one or more of the following: TB CRC calculation, BG selection, code block segmentation, or CB CRC calculation. LDPC encoding post-processing includes, for example, code block concatenation. For example, device 400A is an encoder. Of course, the encoder can also implement other functions besides LDPC encoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0197] In one possible implementation, the module in device 400B used for LDPC decoding is a decoder. In another possible implementation, the decoder can not only perform LDPC decoding, but also perform LDPC decoding preprocessing and / or post-processing. LDPC decoding preprocessing includes, for example, one or more of the following: rate matching or HARQ merging. LDPC post-processing includes, for example, one or more of the following: CB CRC or TB CRC. For example, device 400B is a decoder. Of course, the decoder can also perform other functions besides LDPC decoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0198] To facilitate understanding of the embodiments of this application, the following is a brief explanation of several terms used in this document.

[0199] Channel coding: Encoding information transmitted through unreliable channels in digital communication to improve the reliability of information transmission. In channel coding, the transmitting end (or encoder) can adopt a certain encoding type to convert the original information (such as information bits) into encoded data of a certain format and transmit it through the channel; the receiving end (or decoder) needs to decode the received data and restore the original information. The most critical part of channel coding is forward error correcting coding (FEC). The purpose of error correcting coding is to ensure that the receiving end can automatically correct errors that occur during data transmission with as little redundancy overhead as possible. At the same bit error rate, the smaller the overhead required, the higher the coding efficiency. Traditional channel coding types generally include linear block codes (LBCs) (such as Hamming codes, Gray codes, BCH codes (Bose-Chaudhuri-Hocquenghem codes), RS codes (Reed-Solomon codes), etc.), convolutional codes, and concatenated codes. These codes have their own different characteristics and performance, and are suitable for different scenarios.

[0200] Code rate: The proportion of useful information to total information in the encoded data stream. In this paper, useful information is denoted as information bits, and the encoded data stream is denoted as encoded bits. It should be understood that the information bits include the information bits from the CB (Cross-Block Controller) and the CB's check bits (i.e., CRC code), which can be considered as the information bits to be encoded; the encoded bits include the encoded information bits and check bits (or redundancy bits). The check bits in the encoded bits are generated during encoding and are different from the check bits of the CB. For example, if the information bits are K bits and the channel-coded bits are N bits, then the encoding code rate is K / N. The number of encoded bits after channel coding can also be called the code length. It can be understood that high redundancy results in a low encoding code rate and strong anti-interference capability, but low transmission efficiency; conversely, low redundancy results in a high encoding code rate and weak anti-interference capability, but high transmission efficiency.

[0201] LDPC code: A type of linear block code. Because the parity-check matrix of this linear block code has a sparse property, with elements having a value of 1 accounting for a very small proportion, it is also called an LDPC code. For an LDPC code with K information bits and a code length of N, the dimension of its parity-check matrix is ​​(N-K)×N. The process of encoding the information bits using the parity-check matrix H can be represented as:

[0202] Where c represents K information bits, that is, K bits to be encoded; w represents (N-K) check bits; This represents a column vector of length N consisting of K information bits and (N-K) parity bits.

[0203] The process of LDPC encoding based on the parity-check matrix H is to obtain the encoded output given the parity-check matrix H and the input c to be encoded. The process; the process of LDPC decoding based on the parity-check matrix H, that is, given the parity-check matrix H and the input to be decoded. The process of recovering the input c to be encoded.

[0204] Parity-check matrix: Used for LDPC encoding or decoding. In this application, the parity-check matrix is ​​denoted as a matrix H of dimension M×N. Here, M is the number of parity bits, which satisfies: M = N - K. Therefore, the dimension of the parity-check matrix can also be denoted as (N - K)×N.

[0205] In this parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and (N-K) parity-check equations correspond to (N-K) parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and N symbols correspond to N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... m,nThis indicates that the m-th check node and the n-th variable node are connected, where m can be an integer greater than or equal to 0 and less than or equal to (M-1), and n can be an integer greater than or equal to 0 and less than or equal to (N-1). The number of non-zero elements in each row of the check matrix H represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, and all variable nodes also have the same degree, the corresponding LDPC code is a regular code; otherwise, it is an irregular code.

[0206] For example, the parity-check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is as follows:

[0207] In this verification matrix H, each row includes 10 variable nodes and each column includes 5 verification nodes. If we use c0, c1, ..., c9 to represent variable nodes and p0, p1, ..., p4 to represent verification nodes, the verification matrix H can be represented by a graphical model, such as a Tanner graph, a factor graph, or a tree graph.

[0208] Figure 5 shows an example of a Tanner graph. The Tanner graph shown in Figure 5 corresponds to the parity check matrix H listed above, where the degree of a node is equal to the number of edges connected to that node in the Tanner graph. For example, h in the parity check matrix H above... 0,0 If the value is 1, then the variable node c0 and the check node p0 in the Tanner graph are connected; similarly, h in the check matrix... 1,1 If the value is 0, then the variable node c1 and the check node p1 in the Tanner graph are not connected; and so on, without further enumeration.

[0209] Spatial Coupled Codes: These have a stepped convolutional code structure. Figure 6 shows an example of a stepped convolutional code structure. The convolutional code structure shown in Figure 6 includes submatrices B0 and B1, which have the same dimensions, for example, m0 × n0, where m0 and n0 are both positive integers. For ease of understanding, each submatrix is ​​represented by a box in the figure; in fact, each box can be replaced with an m0-row, n0-column submatrix.

[0210] For ease of explanation, submatrices corresponding to the same column index will be referred to as a vertical group of the convolutional code structure, and submatrices corresponding to the same row index will be referred to as a horizontal group of the convolutional code structure. As can be seen, the stair-step convolutional code structure shown in Figure 6 includes multiple vertical groups. In two adjacent vertical groups, the vertical group on the right is offset downwards by a submatrix B0 compared to the vertical group on the left. By analogy, a stair-step convolutional code structure with infinitely expanding dimensions can be obtained. Therefore, the encoder can continue encoding indefinitely.

[0211] During the encoding process, the encoder can encode each group from top to bottom in a horizontal group-by-horizontal granularity. Since it looks like encoding in rows from the diagram, this encoding method will be referred to as line-by-line encoding in the following text. For example, the submatrix B0 of the topmost horizontal group can be used to encode the input information bit 1 to obtain encoded bit 1, which can be used as the encoding input for the submatrixes B0 and B1 of the second horizontal group; the submatrixes B0 and B1 of the second horizontal group can encode the input encoded bit 1 and information bit 2 (which can be understood as information bit 2 being an information bit in the input to be encoded that is different from information bit 1, or in other words, a new information bit) to obtain encoded bit 2, which can be used as the encoding input for the submatrixes B0 and B1 of the third horizontal group; the submatrixes B0 and B1 of the third horizontal group can encode the input encoded bit 2 and information bit 3 (which can be understood as information bit 3 being an information bit in the input to be encoded that is different from information bit 1 and information bit 2, or in other words, a new information bit) to obtain encoded bit 3, which can then be used as the encoding input for the submatrixes B0 and B1 of the fourth horizontal group, and so on, without further enumeration. It is easy to see that coded bit 2 can correct errors in both coded bit 1 (or information bit 1) and information bit 2, and coded bit 3 can correct errors in both coded bit 2 (or information bit 2) and information bit 3, and so on. Since the coded output of the previous horizontal group B0 can be used as the coded input of B1 in the next horizontal group, it can be considered that the submatrices located in the same column are coupled.

[0212] It should be understood that the convolutional code structure shown in Figure 6 is merely an example for ease of understanding and illustration, and should not constitute any limitation on this application. For example, each vertical group in Figure 6 includes at most two sub-matrices; in fact, each vertical group can include more sub-matrices, and this application does not limit this. Furthermore, row-by-row encoding is only one possible implementation, and is not limited thereto. In specific implementations, the entire convolutional code structure can also be encoded as a whole as the input to be encoded.

[0213] SC-LDPC codes combine the ideas of block coding and recursive convolutional coding. Compared to traditional LDPC block codes, SC-LDPC codes have better decoding performance and a simpler coding structure.

[0214] SC-LDPC codes are a class of finite-length LDPC convolutional codes. The basis matrix of an SC-LDPC code based on its base graph (or original graph) can be represented as matrix B. SC as follows:

[0215] The basis matrix B SCIn this context, P represents the basis matrix B. SC The number of vertical groups contained, that is, the number of the basis matrix B. SC The number of submatrices B0 contained in the matrix can be called the coupling length. W represents the basis matrix B. SC The number of submatrices contained in each vertical group can be called the coupling depth. Submatrix B w In (t), w can be a value greater than or equal to 0 and less than W, i.e., w = 0, 1, ..., W⁻¹. Submatrix B w In (t), t can be a value greater than or equal to 0 and less than P, i.e., t = 0, 1, ..., P-1. Submatrix B w The dimension of (t) can be m0×n0, where m0 and n0 are both positive integers. Therefore, the basis matrix B SC The dimension is: [m0×(W+P-1)]×(n0×P).

[0216] If the basis matrix B SC Satisfy: B w (t)=B w (t+1)=…=B w If (w+P-1), w = 0, 1, ..., W-1, then it is called a time-invariant SC-LDPC code; otherwise, it is called a time-varying SC-LDPC.

[0217] For ease of understanding, the basis matrix B in the example above SC Only the non-zero submatrices are shown; it can be seen that the basis matrix B... SC It has a stepped structure. In fact, in the basis matrix B SC The blank regions in the matrix (i.e., the positions of elements indexed by different rows and columns) also contain multiple submatrices of all zeros. In other words, the basis matrix B... SC It can also be expressed as:

[0218] Figure 7 shows the combination of this basis matrix B. SC Examples of horizontal and vertical groups are shown in Figure 7. W submatrices located in the same one or more columns belong to the same vertical group, while submatrices located in the same one or more rows belong to the same horizontal group. It can be seen that a single vertical group can contain W submatrices, and a single horizontal group can contain at most W submatrices. Based on the above discussion of the base matrix B... SC The explanation of the dimension makes it easy to see that the basis matrix B SC It includes [m0×(W+P-1)] horizontal groups and (n0×P) vertical groups.

[0219] In the encoding process of the spatially coupled code illustrated in Figure 6 above, the encoder can encode line by line. In SC-LDPC codes, the encoding of each horizontal group can be implemented using LDPC encoding, for example, encoding based on the parity-check matrix of the LDPC code.

[0220] In SC-LDPC codes, the parity-check matrix can be based on the basis matrix B. SC And the expansion factor Z is obtained. For example, the basis matrix B... SC Each element in each submatrix can be converted into a cyclic shift matrix or an all-zero matrix of dimension Z×Z. Therefore, based on the basis matrix B in the example above... SC The dimension of the parity check matrix Hsc is: [m0×(W+P-1)×Z]×(n0×P×Z).

[0221] Because SC-LDPC codes offer better decoding performance and a relatively simpler coding structure compared to traditional LDPC block codes, they are considered a very promising coding scheme, and there is hope that they can be applied to wireless communication systems. However, no specific design has yet been developed for the application of SC-LDPC codes in wireless communication systems.

[0222] Furthermore, researchers found that if the basis matrix B is directly used... SC The obtained parity-check matrix is ​​encoded, and then during the decoding process, it is compared with the base matrix B. SC The decoding performance of the encoded bits corresponding to the submatrix at the tail (i.e., at the last horizontal and vertical groups of the basis matrix) is poor. Corresponding to row-by-row encoding, the decoder can use sliding window decoding. The following uses the sliding window decoding shown in Figure 8 as an example. The basis matrix shown in Figure 8 is an example of the basis matrix shown in Equation 1 above, i.e., a basis matrix with P = 8 and W = 4. The decoding window size shown in Figure 8 is 3×3. The decoder can keep this decoding window size constant and decode from the basis matrix B... SC Starting from the top left corner, the decoding window slides sequentially to the lower right, as shown in Figure 8. The solid-line rectangle represents the decoding window, which moves towards the position indicated by the dashed rectangle. Each decoding operation can be based on a submatrix within the decoding window. It's easy to see that the decoding window typically contains multiple submatrices. Multiple submatrices within the same vertical group are coupled and can assist in decoding. However, when the decoding window slides to the tail of the base matrix, only one submatrix, B0, is used for decoding, without any other coupled submatrices to assist. Therefore, the decoding accuracy of the information bits corresponding to submatrix B0 is low, thus affecting the overall decoding performance.

[0223] Research has found that the decoding accuracy of this portion of information bits is low, possibly because during the line-by-line encoding process, when the submatrix B0 located at the tail of the base matrix encodes the input information bits, there are no other coupled submatrices to encode its output, thus preventing the acquisition of sufficient parity bits for error correction. In other words, the base matrix B... SC The protection of the information bits corresponding to the tail B0 is relatively weak.

[0224] In view of this, this application provides a method in which a communication device can obtain a parity check matrix based on a first basis matrix containing a ladder-like structure, and then perform LDPC encoding on a bit sequence (i.e., the first bit sequence below) of a certain length (i.e., the first length below) based on the parity check matrix to obtain the encoded bits to be transmitted (i.e., the second bit sequence below). Since the first basis matrix not only contains the aforementioned ladder-like structure, but also includes a non-zero submatrix located in the lower right corner of the first basis matrix, this non-zero submatrix can be used to encode more parity bits, thereby enabling error correction for information bits with low decoding accuracy, thus improving overall decoding performance and communication reliability. This method can be illustrated by Design 1 below.

[0225] This application also provides a method in which a communication device can operate on the basis matrix B of an SC-LDPC code. SC Based on this, the restriction on the all-zero submatrix in the lower left corner of the basis matrix is ​​relaxed, thereby increasing the space for constructing the basis matrix, which in turn increases the space for constructing the parity check matrix, thus improving decoding performance. This method can be illustrated by Design 2 and Design 3 below.

[0226] The method provided in this application will now be described in detail with reference to the accompanying drawings.

[0227] Figure 9 is a schematic flowchart of the encoding method 900 provided in an embodiment of this application. The method 900 can be executed by a first communication device, which can be a communication device, such as a network device or a terminal device; it can also be a component configured in the communication device, such as a circuit or chip inside the communication device (such as a modem chip, or a SoC chip or SIP chip containing a modem core, etc.); it can also be a logic module or software that can implement some or all of the functions of the communication device, etc., and this application does not limit it in this regard.

[0228] The encoding method 900 shown in Figure 9 may include steps 910 to 920. Optionally, it may also include at least one of steps 930 or 940. The various steps of method 900 are described in detail below.

[0229] In step 910, the parity check matrix is ​​obtained based on the first base matrix.

[0230] The process of obtaining the parity-check matrix based on the first basis matrix can be regarded as a process of expanding the dimension of the first basis matrix. Assuming the expansion factor is Z (Z is a positive integer), each element in the first basis matrix is ​​expanded into a cyclic shift submatrix or an all-zero submatrix with a dimension of Z×Z, thereby obtaining a parity-check matrix with a larger dimension.

[0231] For example, if the basis matrix is ​​represented as H b H b satisfy:

[0232] Based on the basis matrix H b The obtained parity-check matrix H0 satisfies:

[0233] Where M'=m b ×Z, N'=n b ×Z, where Z is the expansion factor. M', N', Z, m b and n b All are positive integers.

[0234] Each element I(r) of H0 in this verification matrix i,j ) can be a zero submatrix of dimension Z×Z or a cyclic shift submatrix of dimension Z×Z. If r i,j Greater than or equal to 0, cyclic shift submatrix (e.g., I(r) i,j )) can be a cyclic shift of an identity submatrix of dimension Z×Z by r i,j Therefore, r is also obtained from the position. i,j This is called the shift factor of the cyclic shift matrix. i,j The range of values ​​for can be -1 ≤ r i,j <Z.

[0235] Basis matrix H b The parity check matrix can include one or more elements with a value of 0 (or zero elements) and one or more elements with a value of non-zero (or non-zero elements). The value of each element can be used to determine the number of bits that its corresponding identity submatrix in the parity check matrix needs to be cyclically shifted.

[0236] In one possible design, the basis matrix H b It includes one or more elements with a value of 0 and one or more elements with a value of 1, that is, r i,j = 0 or 1, element r i,j The number of bits for cyclic shift of the identity submatrix corresponding to the parity check matrix H0 can be obtained through the transformation function g(V i,j ,Z) to determine.

[0237] For example, the transformation function g(V) i,j Z) can satisfy:

[0238] Where % represents the modulo operation. V i,j V is the cyclic shift coefficient. i,j The range is V i,j ∈[-1, Z max -1],Z max It is the maximum value of Z, Z max It can be a predefined positive integer. V i,j It can be a predefined value, for example, it can be predefined through a protocol, such as in Tables 5.3.2-2 and 5.3.2-3 of the 3rd generation partnership project (3GPP) technical specification (TS) 38.212.

[0239] Through this transformation function g(V) i,j It can be seen from Z that when V i,j When the value is -1, the element r i,j The submatrix I(r) corresponding to the verification matrix H0 i,j ) can be a submatrix of all zeros; when V i,j When r is 0, the element r i,j The submatrix I(r) corresponding to the verification matrix H0 i,j ) can be a unit submatrix, that is, a unit submatrix that is cyclically shifted by 0 bits, i.e., no shift; V i,j When the value is greater than 0, the element r i,j The submatrix I(r) corresponding to the verification matrix H0 i,j ) can be a cyclic shift of the identity submatrix V i,j %Z is obtained.

[0240] With Z=4, Z max Taking = 8 as an example, the element I(r) in the check matrix i,j The correspondence between the matrix and the cyclic shift submatrix or the all-zero submatrix is ​​as follows:

[0241] The matrix corresponding to the element "-1" That is, an all-zero matrix; elements "0" to "7" correspond to a cyclic shift matrix, where elements "0" and "4" correspond to a matrix The matrix corresponding to elements "1" and "5" The matrix corresponding to elements "2" and "6" The matrix corresponding to elements "3" and "7"

[0242] In the embodiments of this application, the elements in the first basis matrix and each Z×Z dimensional submatrix in the parity check matrix also satisfy the above-described relationship. Therefore, the parity check matrix can be obtained based on the first basis matrix in the same way. Since the first basis matrix will be described in conjunction with different designs below, it will not be detailed here.

[0243] In step 920, based on the parity check matrix, the first bit sequence with a first length is LDPC encoded to obtain the second bit sequence.

[0244] The length of the first bit sequence is a first length, meaning it is definite or known. If this first length is represented by K (K being a positive integer), where K can be in bits, then the first bit sequence of the first length can mean that it includes K information bits to be encoded. This first bit sequence can include information bits from one or more CBs. Optionally, it can also include parity bits from one or more CBs; this application does not limit this. To distinguish it from the parity bits generated during the encoding process below, the information bits and parity bits in the first bit sequence are collectively referred to as information bits to be encoded. It can be understood that the information bits to be encoded can include information bits from CBs and parity bits from CBs.

[0245] Assuming the parity check matrix has a dimension of M×N, the number of rows M and columns N of the parity check matrix can satisfy: N = M + K. Therefore, the first communication device encodes the K information bits to be encoded in the first bit sequence based on the parity check matrix of dimension M×N. That is, by encoding the K information bits to be encoded through the parity check matrix, N encoded bits can be obtained, including K information bits and M parity bits.

[0246] Since the specific encoding process will be described in conjunction with different designs of the first basis matrix below, it will not be detailed here.

[0247] Optionally, the method 900 further includes step 930, sending a second bit sequence.

[0248] After encoding the second bit sequence, the first communication device can perform operations such as scrambling, modulation, layer mapping, and precoding on the second bit sequence, and finally transmit it through the antenna after up-conversion and power amplification. It can be understood that the signal transmitted by the first communication device through the antenna can be a radio frequency signal carrying the second bit sequence; in other words, the second bit sequence is transmitted as a radio frequency signal and is not necessarily output in the form of a bit sequence.

[0249] When the first communication device is a terminal device or a network device, the first communication device can transmit a radio frequency signal carrying a second bit sequence via an antenna. Optionally, transmitting the second bit sequence includes transmitting a radio frequency signal carrying the second bit sequence.

[0250] When the first communication device is a chip or chip system, the first communication device can transmit the second bit sequence or a signal carrying the second bit sequence through input / output circuits or interface circuits.

[0251] The physical layer processing flow after encoding, as well as the specific process for transmitting radio frequency signals, can be implemented using existing technologies and will not be detailed here.

[0252] This application provides three different designs for the first basis matrix. These are described below with reference to the accompanying drawings.

[0253] Design 1: The first basis matrix comprises a first sub-block, a second sub-block, and a third sub-block. The term "sub-block" is introduced for ease of distinction and explanation. Each of the first, second, and third sub-blocks may contain one or more sub-matrices. The first basis matrix comprising the first, second, and third sub-blocks can also be described as the first matrix comprising multiple sub-matrices.

[0254] The relative positional relationship between the first, second, and third sub-blocks can be shown in Figure 10. Figure 10 is a schematic diagram of the structure of the first base matrix provided in an embodiment of this application. As shown in Figure 10, the second and third sub-blocks are located below the first sub-block. In this application, the second and third sub-blocks can be located in one or more rows below the first sub-block, that is, the submatrices in the second and third sub-blocks occupy one or more rows. The first row of the submatrices in the second sub-block (or the first row of the submatrices in the third sub-block) is continuous with the last row of the submatrices in the first sub-block, that is, the row index of the first row of the submatrices in the second (or third) sub-block is continuous with the row index of the last row of the submatrices in the first sub-block. For example, the submatrices in the first sub-block belong to one or more horizontal groups, and the submatrices in the second and third sub-blocks belong to the same horizontal group, which is located below and continuous with the one or more horizontal groups mentioned in the first sub-block.

[0255] The second sub-block is located to the left of the third sub-block. The last column of the second sub-block does not exceed the last column of the first sub-block, and the first column of the third sub-block is consecutive to the last column of the first sub-block. That is, the column index of the submatrix in the second sub-block corresponding to the first base matrix is ​​less than or equal to the column index of the submatrix in the first sub-block corresponding to the first base matrix, and the column index of the first column of the submatrix in the third sub-block is consecutive to the column index of the last column of the submatrix in the first sub-block.

[0256] The first sub-block is H.B1sub Or with H B1sub The submatrix H has row and / or column transformation relationships. B1sub satisfy:

[0257] The H B1sub In the middle, B w Let B be one of the W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1. B0 (that is, B when w is 0) w The W submatrices include columns corresponding to the information bits in the first bit sequence. These W submatrices are non-zero submatrices of the same dimension, for example, all being m. sub ×n sub The dimension, m sub and n sub All are positive integers.

[0258] 0 indicates the relationship with B w A submatrix of all zeros with the same dimensions as B. X represents a submatrix of all zeros with the same dimensions as B. w Submatrices with the same dimensions. H B1sub Each X in the matrix can be the same submatrix or different submatrixes; it can be an all-zero submatrix or a non-zero submatrix. This application does not impose any restrictions on this.

[0259] In this application, the number of B0s included in the first sub-block is denoted as P, where P is a positive integer greater than or equal to 1. Since P B0s are located on the diagonal of the first sub-block, this first submatrix belongs to P vertical groups and P horizontal groups. According to Formula 2 listed above, it is easy to see that the number of vertical groups to which the first sub-block belongs is greater than W, that is, P is a positive integer greater than W. Furthermore, since the dimension of each submatrix in the first sub-block is m... sub ×n sub Therefore, the first sub-block can include P×m sub Individual rows, P×n sub There are columns, and their dimensions are (P×m). sub )×(P×n sub ).

[0260] The second sub-block may include one or more non-zero sub-matrices, each of which has the same dimension as the aforementioned W sub-matrices, i.e., m. sub ×n subIn one possible design, the second sub-block includes one or more submatrices other than B0 from the aforementioned W submatrices. For example, if W is 2, and the aforementioned W submatrices include B0 and B1, the second sub-block may include B1; or, for example, if W is 4, and the aforementioned W submatrices include B0, B1, B2, and B3, the second sub-block may include one or more of B1, B2, or B3. This application does not limit this. Of course, the second sub-block may also include one or more other non-zero submatrices besides the W submatrices, and this application does not limit this.

[0261] Optionally, the second sub-block may also include one or more all-zero sub-matrices. In one design, the second sub-block may include all sub-matrices below the first sub-block and to the left of the third sub-block. In this case, the last column of the second sub-block is continuous with the first column of the third sub-block. In another design, the second sub-block may include all non-zero sub-matrices below the first sub-block and to the left of the third sub-block, but not all-zero sub-matrices. In this case, the last column of the second sub-block may or may not be continuous with the first column of the third sub-block. For ease of explanation, it is assumed below that the second sub-block includes all sub-matrices located below the first sub-block and to the left of the third sub-block.

[0262] One or more submatrices in the second subblock can be located in a horizontal group, that is, one or more submatrices in the second subblock occupy m sub In this case, the dimension of the second sub-block can be m. sub ×(P×n sub When the second sub-block includes multiple sub-matrices, these multiple sub-matrices can also be located in multiple horizontal groups, and this application does not limit this.

[0263] The third sub-block can be a full-rank square matrix with the same number of rows as the second sub-block. To distinguish it from the W sub-matrices mentioned earlier, this paper uses B to represent the full-rank square matrix in the third sub-block. T This indicates that when one or more submatrices in the second sub-block are located in a horizontal group, the third sub-block is also located in the same horizontal group, occupying the same m. sub There are 1 row. At this point, the dimension of the third sub-block can be m. sub ×m sub .

[0264] Optionally, the third sub-block is: a unit diagonal matrix, a square matrix with a row and / or column transformation relationship to the unit diagonal matrix, a double diagonal matrix, a square matrix with a row and / or column transformation relationship to the double diagonal matrix, a lower triangular matrix, or a square matrix that satisfies a row and / or column transformation relationship with the lower triangular matrix.

[0265] Figure 11 is a schematic diagram of several possible structures of the third sub-block. As shown in Figure 11, (a) to (e) show a 6×6 square matrix, i.e., an example where m0 is 6. Figure 11(a) shows a unit diagonal matrix, (b) shows a square matrix obtained by cyclically shifting the unit diagonal matrix in (a), and (c) shows a square matrix obtained by row and column transformations of the unit diagonal matrix in (a). It can be understood that the square matrix obtained by cyclically shifting the unit diagonal matrix can also be regarded as a square matrix obtained by column transformations of the unit diagonal matrix. Therefore, the square matrices shown in (b) and (c) have row and / or column transformation relationships with the unit diagonal matrix shown in (a). Figure 11(c) shows a double diagonal matrix, and Figure 11(e) shows a lower triangular matrix. Although square matrices with horizontal and / or column transformation relationships with double diagonal and lower triangular matrices are not shown in the figures, those skilled in the art can easily obtain them based on the above description and examples, and they will not be listed further.

[0266] As shown in Figure 10, in addition to the first, second, and third sub-blocks mentioned above, the first basis matrix also includes a blank area located to the right of the first sub-block and above the third sub-block. For ease of distinction and explanation, this area is referred to as the fourth sub-block. In this application, the fourth sub-block occupies the same number of rows and columns as the first and third sub-blocks. For example, the fourth sub-block could have a dimension of (P×m) sub )×m sub The all-zero submatrix.

[0267] It should be understood that the dimensions of each sub-block of the first basis matrix shown in Figure 10 are merely examples; for instance, the number of rows in the second and third sub-blocks could also be m. sub The number of columns in the third and fourth sub-blocks can also be m, which is an integer multiple of m. sub It must be an integer multiple of the specified value. This application does not impose any limitation on this.

[0268] In one possible design, the aforementioned W sub-matrices are predefined, such as in a protocol predefined.

[0269] As an example, the W sub-matrices are predefined. The first communication device can pre-store the W sub-matrices. When there is an encoding requirement, the W sub-matrices are read, and then the first basis matrix is ​​generated based on the W sub-matrices.

[0270] In another example, the first communication device may pre-store a first sub-block. When encoding is required, the first communication device can read the first sub-block and then generate a first basis matrix based on it. Since pre-stored first sub-block requires not only pre-stored W sub-matrices but also pre-stored information used to determine the relative positions of the W sub-matrices, pre-stored first sub-block by the first communication device can also be considered as the first communication device pre-stored the W sub-matrices. In other words, the W sub-matrices can be predefined.

[0271] In another example, the first communication device may pre-store a first basis matrix. When encoding is required, the first communication device can read the first basis matrix. Since pre-stored first basis matrix requires not only pre-stored W sub-matrices, but also pre-stored information used to determine the relative positional relationships of the W sub-matrices and the relative positional relationships between each sub-block, pre-stored first basis matrix by the first communication device can also be considered as the first communication device pre-stored the W sub-matrices. In other words, the W sub-matrices can be predefined.

[0272] In another possible design, the aforementioned W submatrices are either randomly generated, selected from a pre-stored set of submatrices (e.g., selected according to predetermined rules), or randomly selected.

[0273] For example, the W sub-matrices are randomly generated by the first communication device. The first communication device can generate the W sub-matrices itself when encoding requirements exist, and then generate the first basis matrix based on these W sub-matrices. This application does not limit the specific method by which the first communication device generates the W sub-matrices, as long as the W sub-matrices are non-zero sub-matrices and meet the encoding requirements for dimensions.

[0274] For example, the W sub-matrices are selected from a set of sub-matrices pre-stored in the first communication device, which may include multiple sub-matrices. The first communication device can randomly select or select the W sub-matrices according to a predetermined rule. This application does not limit the rule for the first communication device to select the W sub-matrices, as long as the W sub-matrices are non-zero sub-matrices and meet the encoding requirements for dimensions.

[0275] Optionally, W is a predefined value. It can be understood that the cases listed above—pre-storing W sub-matrices, pre-storing the first sub-block, or pre-storing the first basis matrix—can also be considered as possible examples of W being a predefined value. Of course, the first communication device can also randomly generate W sub-matrices based on the predefined value W.

[0276] Based on the preceding description of the first to fourth sub-blocks, the first basis matrix H can be obtained. B1 Here is an example:

[0277] Among them, [XX … XB W-1 …B1] represents the second sub-block, B T This represents the third sub-block. The first basis matrix H... B1 The dimension can be: ((P+1)×m sub )×(P×n sub +m sub That is, including (P+1)×m sub Each row, (P×n)sub +m sub ) columns.

[0278] In step 910, the first communication device can obtain the parity check matrix based on each element of the first basis matrix. The process of obtaining the parity check matrix from the first basis matrix can be found above in conjunction with the basis matrix H. b The explanation of the parity check matrix H is only H b Since the elements in the matrix are different, the elements in the obtained verification matrix H are also different, which will not be elaborated further.

[0279] For example, if we expand each submatrix in the first basis matrix, we can also obtain a basis matrix H of the form described above. b Based on the structure of H, and following the dimensional expansion method described above, the parity-check matrix can be obtained. At this point, the basis matrix H in the example above... b The dimension of the matrix is ​​the same as the dimension of the first basis matrix. In Design 1, it can be ((P+1)×m sub )×(P×n sub +m sub ), that is, m b = (P+1)×m sub n b =(P×n) sub +m sub The dimension M'×N' of the parity check matrix H0 in the example above can also be the same as the dimension M×N of the parity check matrix provided in this embodiment.

[0280] For example, the basis matrix H can also be... b As a submatrix in the first basis matrix, for example, B0 in the first basis matrix. Expanding each submatrix in the first basis matrix can also yield a larger-dimensional basis matrix H of the form described above. b The structure of H, and by following the dimensional expansion method described above, can also yield the parity check matrix. At this point, the basis matrix H... b The dimension of m can be the same as the dimension of each of the W submatrices in the first basis matrix, that is, m b =m sub n b =n sub The dimension M×N of the parity check matrix obtained based on this first basis matrix is ​​different from the dimension M'×N' of the parity check matrix H0 in the example above. More specifically, M is greater than M' and N is greater than N'.

[0281] In step 920, the first communication device may encode the first bit sequence based on the parity check matrix obtained from the first base matrix.

[0282] Since obtaining the parity-check matrix based on the first basis matrix is ​​a dimensional expansion process, each element in the first basis matrix corresponds to a Z×Z dimensional submatrix in the parity-check matrix. Therefore, encoding the first bit sequence based on the parity-check matrix obtained from the first basis matrix can also be simply referred to as encoding the first bit sequence based on the first basis matrix.

[0283] It should be noted that when P is 1, the first basis matrix described above can degenerate into a regular basis matrix form, lacking the aforementioned ladder structure. Therefore, LDPC encoding can be performed using existing methods, which will not be detailed in this paper. In this case, W can be 1. The following explanation mainly focuses on the case where P is greater than 1.

[0284] One possible encoding method is to encode each group sequentially from top to bottom, using horizontal groups as the granularity; this can also be called line-by-line encoding.

[0285] Observing Figure 10 and Equations 2 and 3, it is easy to see that the first basis matrix contains a stepped structure as shown in Equation 1. Figure 12 shows the stepped structure based on the first basis matrix shown in Equation 3, as indicated by the dashed box in the figure. Figures 13A and 13B further show the structure of the first basis matrix when P and W have different values. Figures 13A and 13B show the non-zero submatrices in the first basis matrix, but the all-zero submatrices are not shown. In the first basis matrix shown in Figure 13A, P is 4 and W is 2. In the first basis matrix shown in Figure 13B, P is 8 and W is 4. It should be understood that these figures are shown for ease of understanding only and should not constitute any limitation on this application. This application does not limit the values ​​of P and W.

[0286] As can be seen from Figures 12, 13A, and 13B, the first basis matrix contains a ladder-like structure. Therefore, the aforementioned row-by-row encoding method can be used to encode the first bit sequence.

[0287] As mentioned earlier, during line-by-line encoding, the output of the previous horizontal group can be used as the input of the next horizontal group. In this embodiment, submatrix B0 in the first base matrix includes columns corresponding to the information bits in the first bit sequence. That is, the columns in submatrix B0 corresponding to the information bits in the first bit sequence can be directly used to encode the corresponding information bits. Here, "directly used to encode the information bits" means using these information bits as the input for encoding, rather than using the encoded bits obtained after encoding these information bits once or multiple times as the input for encoding.

[0288] Assume B0 includes k corresponding to the information bits. sub For each column, based on the expansion factor Z, we can obtain the k... sub Each column can correspond to k in the first bit sequence. sub×Z information bits. This first basis matrix includes P B0s, that is, it can correspond to P×k bits in the first bit sequence. sub ×Z information bits. Therefore, the length of the first bit sequence (i.e., the first length) K can be greater than or equal to P×k. sub ×Z. For ease of explanation, let's assume here that K equals P×k. sub ×Z. That is, the P B0s in this first basis matrix can be used to represent P×k. sub Encode P×k information bits using ×Z bits. sub The ×Z information bits can be evenly divided into P groups of information bits, corresponding to P B0 bits.

[0289] Suppose the first bit sequence is denoted as: a0, a1, ..., a K-1 Following the top-to-bottom order of the first base matrix, B0 in the first horizontal group can be used to encode information bits a0, a1, ..., a7, and B0 in the second horizontal group can be used to encode information bits a8, a9, ..., a7. 15 Encoding is performed, and B0 in the third horizontal group can be used for information bit a. 13 ,a 14 ,…,a 23 Encoding is performed, and so on, until the P B0s in the first base matrix are traversed, which completes the encoding of the K information bits in the first bit sequence.

[0290] In this example, k in the first horizontal group B0 sub Each column corresponds to the information bits a0, a1, ..., a7 in the first bit sequence (that is, a group of information bits in the P groups of information bits); k in the second horizontal group B0 sub Each column corresponds to the information bits a8, a9, ..., a in the first bit sequence. 15 (That is, another set of information bits in the P group of information bits) corresponds to; k in B0 of the third horizontal group sub Each column and the information bit a in the first bit sequence 13 ,a 14 ,…,a 23 (That is, another set of information bits in the P groups of information bits) corresponds; and so on, we can obtain k in each B0. sub The correspondence between each column and each group of information bits in the first bit sequence.

[0291] For ease of understanding and explanation, the following text assumes W = 2 and P = 4, meaning that Formula 3 can be simplified to:

[0292] Assuming Z is 2, K is 32, and N is 40, then k sub For 4, n subIt is 5, m sub =1 (by n) sub -k sub (Obtained). The first bit sequence can be denoted as a0, a1, ..., a 31 Corresponding to P B0 bits, they can be divided into P groups of information bits, namely: {a0, a1, ..., a7}, {a8, a9, ..., a...}, {a0, a1, ..., a7}, {a8, a9, ..., a...}, {a0, a1, ..., a7}, {a8, a9, ..., a7 ...8, a9, ..., a7}, {a8, a9, ..., a7}, {a8, a9, ..., a7}, {a8, a9, ..., a7}, {a8, a9, ..., a7}, {a8, a9, ..., a7 15}, {a 16 ,a 17 ,…,a 23}, {a 24 ,a 25 ,…,a 31 Using these P groups of information bits as input for encoding, the P groups are encoded sequentially from top to bottom according to the first basis matrix. If each horizontal group is considered as an encoding window, the input, output, and corresponding encoding process of the encoding window, in top-to-bottom order, are illustrated below:

[0293] The input to the first encoding window is information bits a0, a1, ..., a7. B0 in the first horizontal group can be used to encode information bits a0, a1, ..., a7, resulting in encoded bits a0, a1, ..., a7, c0, c1, where c0 and c1 are parity bits. These encoded bits a0, a1, ..., a7, c0, c1 are the output of the first encoding window and can be used as the information bits encoded in the column containing B1 in the second horizontal group (B1 and B0).

[0294] The input to the second encoding window is information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 Among them, a8, a9, ..., a 15 These are newly added information bits. B0 and B1 in the second horizontal group can be used to add information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 Encode the bits to obtain the encoded bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, where c2 and c3 are additional check bits generated after the second encoding window. The encoded bits are a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2 and c3 are the outputs of the second encoding window, which can be used as the information bits encoded in the columns where X and B1 are located in the third horizontal group X, B1 and B0.

[0295] The input to the third encoding window is information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a23 , where a 16 ,a 17 ,…,a 23 These are newly added information bits. The X, B0, and B1 of the third horizontal group can be used to add information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 Encode the bits to obtain the encoded bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, where c4 and c5 are additional check bits generated after the third encoding window. The encoded bits are a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4 and c5 are the outputs of the third encoding window, which can be used as the information bits encoded in the columns where X, X, B1 and B0 are located in the fourth horizontal group.

[0296] The input to the fourth encoding window is information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 , where a 24 ,a 25 ,…,a 31 These are newly added information bits. The fourth horizontal group, X, X, B0, and B1, can be used to add information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 Encode the bits to obtain the encoded bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23c4, c5, a 24 ,a 25 ,…,a 31 c6, c7, where c6 and c7 are additional parity bits generated after the fourth encoding window. The encoded bits are a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 c6 and c7 are the outputs of the fourth encoding window, which can be used as the information bits encoded by X, X, X and B1 in the fifth horizontal group.

[0297] The input to the fifth encoding window is information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 The fifth horizontal group, X, X, X, and B1, can be used to select information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 Encode c6 and c7 to obtain encoded bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 c6, c7, c8, c9, where c8 and c9 are additional check bits generated after the fifth encoding window.

[0298] In this process, the encoding of information bits for each submatrix can be achieved through LDPC encoding. That is, the LDPC encoding process can be viewed as: treating the submatrix after dimensional expansion based on the expansion factor Z as... In H, the information bits are treated as In the case of c, solve for The process of w in the middle.

[0299] It should be understood that the first and second bit sequences are merely examples. Assuming a code length of N, the second bit sequence can include N coded bits, and this second bit sequence can be expressed in a more general form as q0, q1, ..., q N-1 To express.

[0300] As can be seen, in the second bit sequence {a0,a1,…,a7}, {a8,a9,…,a…}, ... 15}、{a 16 ,a 17 ,…,a 23}、{a 24 ,a 25 ,…,a 31 Each of these is encoded by at least one of the four B0s contained in the first base matrix, and therefore, it is related to the first k of each B0. sub Each column corresponds to one column.

[0301] Furthermore, observation reveals that the fifth horizontal group in the first base matrix in the example above is not used to encode new information bits from the first bit sequence, but rather to encode the encoded bits after some of the information bits in the first bit sequence have been encoded once or multiple times (i.e., encoded by the first to fourth horizontal groups).

[0302] As mentioned above in conjunction with Figure 8, the basis matrix B of the SC-LDPC code... SC (See Formula 1) The protection for the information bits corresponding to tail B0 is relatively weak. The first basis matrix H provided in Design 1 is... B1 Basis matrix B SC In general, a major change is that the first basis matrix H B1 This is equivalent to the basis matrix B. SC After row and column truncation, a second sub-block is added below the truncated sub-matrix, and a third sub-block is added to the right of the second sub-block. Specifically, for the base matrix B... SC The position for row and column truncation can be determined based on the number P of B0 elements in the first base matrix, such that the truncated matrix includes P B0 elements. Since the third sub-block and the second sub-block reside in one or more of the same rows, and the third sub-block is a full-rank square matrix, while the encoded input of the second sub-block is the encoded output of the previous horizontal group—both known quantities—the addition of the second and third sub-blocks is equivalent to increasing the base matrix B. SC Several check equations have been added, the number of which corresponds to the dimension of the third sub-block, i.e., m. sub ×Z bits. This increases the number of parity bits by m. sub ×Z, which is beneficial for targeting the basis matrix B.SC Error correction is performed on the corresponding information bits of the tail B0, which helps to improve decoding accuracy and decoding performance.

[0303] Furthermore, the third sub-block is: a unit diagonal matrix, a double diagonal matrix, a lower triangular matrix, or a square matrix with row and / or column transformation relationships to a unit diagonal matrix, a double diagonal matrix, or a lower triangular matrix. Since each row in the third sub-block corresponds to Z rows in the parity check matrix, it can be used to form Z parity check equations to obtain Z parity bits. Therefore, when the non-zero elements in the third sub-block are located below the diagonal, such as when it is a unit diagonal matrix, a double diagonal matrix, or a lower triangular matrix, the parity bits can be solved sequentially by row-by-row encoding, thereby simplifying the encoding and reducing computational complexity. When the third sub-block is a square matrix with row and / or column transformation relationships to a unit diagonal matrix, a double diagonal matrix, or a lower triangular matrix, the unit diagonal matrix, double diagonal matrix, or lower triangular matrix can also be recovered first by row and / or column transformation, and then the parity bits can be solved sequentially by row-by-row encoding.

[0304] Furthermore, the first basis matrix H B1 The first sub-block can also include multiple sub-matrices X. These sub-matrices X are mainly used to encode the output of the previous horizontal group again. In this application, these sub-matrices are not strictly limited to being all-zero sub-matrices. Therefore, the design space for the first basis matrix is ​​increased, which also increases the design space for the parity check matrix, thus improving decoding performance.

[0305] As seen in the example above, the size of W affects both the computational complexity of the encoding and the decoding performance. A larger W results in higher encoding complexity and correspondingly higher decoding complexity; conversely, a smaller W results in lower encoding complexity and correspondingly lower decoding complexity. A larger W leads to more coupled sub-matrices, generating more parity bits and thus better decoding performance; a smaller W results in fewer coupled sub-matrices, generating fewer parity bits and thus poorer decoding performance. Therefore, a trade-off between computational complexity and decoding performance can be achieved through the design of W. For example, a W of 2. Simulations show that while a W greater than 2 improves decoding performance, the improvement is not significant. Furthermore, a larger W results in higher computational complexity; therefore, W can be 2.

[0306] When W is 2, the first basis matrix can be simplified to:

[0307] Furthermore, as can be seen from the example of the encoding process above, the submatrix X below the diagonal of the first base matrix will bring a large amount of computation. Therefore, this submatrix can be designed as an all-zero submatrix, which can reduce the amount of computation and reduce the computational complexity.

[0308] Optionally, all X's in the first sub-block are all-zero submatrices. That is, the above H B1sub satisfy:

[0309] Accordingly, the first basis matrix H B1 satisfy:

[0310] An example, H when W is 2 B1sub satisfy:

[0311] Accordingly, the first basis matrix H B1 satisfy:

[0312] To better illustrate the ladder-like structure of the first basis matrix, Figures 14A and 14B show the structure of the first basis matrix with different values ​​of P and W. Figures 14A and 14B show the non-zero submatrices of the first basis matrix, while the all-zero submatrices are not shown. Furthermore, the third sub-blocks in the first basis matrices shown in Figures 14A and 14B are diagonal matrices, shown by diagonal lines. In the first basis matrix shown in Figure 14A, P is 4 and W is 2. In the first basis matrix shown in Figure 14B, P is 8 and W is 4. It should be understood that the examples of the first basis matrix shown above with different values ​​of P and W are given for ease of understanding only and should not constitute any limitation on this application. This application does not limit the values ​​of P and W.

[0313] Still using the first bit sequence a0, a1, ..., a from the example above 31 Let's take an example to describe encoding based on the first base matrix shown in Formula 4. The parameters are assumed as follows: W = 2, P = 4, Z = 2, K = 32, N = 40, then k... sub For 4, n sub It is 5, m sub If the value is 1, then formula 4 can be simplified to:

[0314] If we consider each horizontal group as an encoding window, then the input, output, and corresponding encoding process of the encoding window, in order from top to bottom, are illustrated below:

[0315] The input to the first encoding window is information bits a0, a1, ..., a7. B0 in the first horizontal group can be used to encode information bits a0, a1, ..., a7, resulting in encoded bits a0, a1, ..., a7, c0, c1, where c0 and c1 are parity bits. These encoded bits a0, a1, ..., a7, c0, c1 are the output of the first encoding window and can be used as the information bits encoded in the column containing B1 of B0 and B1 in the second horizontal group.

[0316] The input to the second encoding window is information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 where a8, a9, ..., a 15 For newly added information bits. B0 and B1 in the second horizontal group can be used for information bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 Encode the bits to obtain the encoded bits a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3, where c2 and c3 are additional check bits generated after the second encoding window. The encoded bits are a0, a1, ..., a7, c0, c1, a8, a9, ..., a 15 c2, c3 are the outputs of the second encoding window, where a8, a9, ..., a 15 c2 and c3 can be used as information bits encoded in the column containing B1 of B0 and B1 in the third horizontal group.

[0317] The input to the third encoding window is information bits a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 , where a 16 ,a 17 ,…,a 23 These are newly added information bits. The third horizontal group, B0 and B1, can be used to add information bits a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 Encode the bits to obtain the encoded bits a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4, c5, where c4 and c5 are additional check bits generated after the third encoding window. The encoded bits are a8, a9, ..., a 15 c2, c3, a 16 ,a 17 ,…,a 23 c4 and c5 are the outputs of the third encoding window, where a 16 ,a 17 ,…,a 23 c4 and c5 can be used as information bits encoded in the column containing B1 of B0 and B1 in the fourth horizontal group.

[0318] The input to the fourth encoding window is information bit a. 16 ,a17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 , where a 24 ,a 25 ,…,a 31 These are newly added information bits. B0 and B1 of the fourth horizontal group can be used for information bit a. 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 Encode the bits to obtain the encoded bits a. 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 c6, c7, where c6 and c7 are additional check bits generated after the fourth encoding window. This encoded bit a 16 ,a 17 ,…,a 23 c4, c5, a 24 ,a 25 ,…,a 31 c6 and c7 are the outputs of the fourth encoding window, where a 24 ,a 25 ,…,a 31 c6 and c7 can be used as information bits encoded in B1 in the fifth row group.

[0319] The input to the fifth encoding window is information bit a. 24 ,a 25 ,…,a 31 c6, c7. The fifth horizontal group, B1, can be used for information bit a. 24 ,a 25 ,…,a 31 Encode c6 and c7 to obtain encoded bits a. 24 ,a 25 ,…,a 31 c6, c7, c8, c9, this encoded bit a 24 ,a 25 ,…,a 31 c6, c7, c8, c9 are the outputs of the fifth encoding window, where c8 and c9 are additional parity bits generated after the fifth encoding window.

[0320] Each submatrix can encode information bits using LDPC encoding, as described above, and will not be repeated here.

[0321] It is easy to see that, compared with the encoding process based on the first basis matrix of Formula 3.1 mentioned above, the encoding based on the first basis matrix of Formula 4.1 reduces the amount of computation and lowers the computational complexity.

[0322] The above two examples illustrate in detail the process of encoding the first bit sequence based on the first base matrix. However, this should not be construed as limiting this application. In specific implementations, the encoding of the first bit sequence based on the first base matrix is ​​not limited to the row-by-row encoding method described above.

[0323] In another implementation, the first communication device may also encode the parity check matrix as a whole.

[0324] For example, the first communication device may perform matrix transformation on the first basis matrix or the parity check matrix to obtain a matrix satisfying the following structure: [IU], where I represents a unit diagonal submatrix and U represents a normal submatrix. The matrix transformation includes one or more of the following: row transformation, column transformation, or Gaussian transformation.

[0325] The first communication device may first perform matrix transformation on the first basis matrix, and then perform dimensional expansion based on the transformed matrix to obtain the parity check matrix, or it may perform dimensional expansion based on the first basis matrix to obtain the parity check matrix, and then perform the above matrix transformation. This application does not limit this.

[0326] The first communication device can encode the first bit sequence based on the parity matrix obtained after the above matrix transformation, and then process the encoded output based on the inverse transformation of the above matrix transformation to obtain the second bit sequence.

[0327] If the first communication device performs a matrix transformation on the first basis matrix, the dimension of the resulting unit diagonal submatrix I is ((P+1)×m). sub )×((P+1)×m sub The dimension of the submatrix U is ((P+1)×m). sub )×(P×k sub If the first communication device performs a matrix transformation on the parity check matrix, the dimension of the resulting unit diagonal submatrix I is ((P+1)×m). sub ×Z)×((P+1)×m sub ×Z); the submatrix obtained by transforming the submatrix U is ((P+1)×m) sub ×Z)×(P×k sub ×Z).

[0328] The first communication device can also skip the aforementioned matrix transformation and perform overall encoding based on the first base matrix. For example, the first communication device can obtain a parity check matrix of dimension M×N by expanding the dimensions of the first base matrix. It can be understood that in Design 1, M = (P+1)×m sub ×Z, N=(P×n) sub +m sub )×Z,K=P×(n sub -m sub The first communication device can divide the parity check matrix H into two sub-matrices H1 and H2 as follows: H = [H1 H2], where the dimension of sub-matrix H1 is M×K and the dimension of sub-matrix H2 is M×M. The process of the first communication device performing LDPC encoding on the first bit sequence can be expressed by the following formula: Where c represents a column vector consisting of K information bits in the first bit sequence. This represents a column vector consisting of N encoded bits in the second bit sequence.

[0329] It should be understood that the process of LDPC encoding the first bit sequence with the parity check matrix as a whole has been explained in the terminology section above with the formula, and will not be repeated here.

[0330] It should be understood that the above text only uses H as a starting point. B1sub As a first sub-block, the first sub-block, the first base matrix, and the encoding process based on the first base matrix have been described, but this should not constitute any limitation on this application. As mentioned above, the first sub-block can also be related to H. B1sub Submatrices with row and / or column transformation relationships. In other words, the first basis matrix is ​​not limited to the forms shown in Equations 3, 3.1, 4, and 4.1 above, as well as in Figures 13A, 13B, 14A, and 14B. It can also be derived from H shown in Equations 3.1, 4, and 4.1, as well as in Figures 13A, 13B, 14A, and 14B. B1sub Perform row and / or column transformations to obtain the transformed sub-blocks, and then combine them with the second and third sub-blocks to obtain other forms of the first basis matrix. For the sake of simplicity, no examples are given here.

[0331] Understandably, in the case of H B1sub After row and / or column transformations, the first sub-block no longer has a regular ladder structure, so LDPC encoding can be performed based on the parity-check matrix as a whole.

[0332] In this embodiment, the first bit sequence can be a bit sequence with a first length K. The first length K can be determined based on the resource size allocated by the network side for transmitting the first bit sequence. Therefore, when the resource size is fixed, the first length K can be considered a fixed value. As can be seen from the encoding process described above, during the encoding of the first bit sequence, the number of encoded information bits, the number of B0 elements P in the first base matrix, and the number of columns k corresponding to the information bits in B0 are all related. sub Related. Due to k in each B0 sub Columns can be used for k sub Encoding ×Z information bits, therefore, P B0s can be used to encode P×k. sub Encoding is performed using ×Z information bits. Therefore, the first length K is related to P and k. sub The following condition can be satisfied: K≥P×k sub ×Z. If K is P×k sub If the sum of the integers of ×Z is an integer multiple of K, then K = P × k sub ×Z; if K is not P×k sub If the value is an integer multiple of ×Z, then one or more zero bits can be added after (or before) the information bits of the first bit sequence by padding with zeros. Therefore, K > P × k sub ×Z.

[0333] Given a fixed K, P or k sub One of them can be predefined, configured, or indicated, so it can be determined first, and the other can be determined based on K and the first determined one.

[0334] Optionally, the number P of B0 in the first sub-block is predefined, configured, or indicated. For example, P is a predefined value of the protocol. Or, for another example, P is a fixed value.

[0335] For example, P is determined by the first communication device according to a mapping relationship, which may indicate the correspondence between P and one or more of the following: the length of the first bit sequence (i.e., the first length K), the code rate R or code length (i.e., N) indicated by the modulation coding scheme (MCS). This mapping relationship may be predefined, or it may be determined according to a predefined rule, such as the rule that P satisfies: α is a predefined value. This application does not impose any restrictions on the above mapping relationship.

[0336] For example, P is indicated by the second communication device. The second communication device can determine P based on the above mapping relationship and notify the first communication device via signaling.

[0337] For example, P is determined by the second communication device and notified to the first communication device via signaling. For example, the second communication device may determine P based on one or more of the following: a first length K, a code length N, or a code rate R indicated by the MCS.

[0338] Furthermore, the method also includes: receiving third indication information from a second communication device, the third indication information being used to indicate the number P of B0 in the first sub-block.

[0339] With both P and K determined, we can proceed according to the relationship between K and P, k above. sub The relationship between them yields k sub satisfy:

[0340] It is understandable that when K is not divisible by Z×P, k sub This can be determined by rounding up. In this case, the K information bits in the first bit sequence are insufficient to form a complete P group of information bits, so padding bits can be added to the first bit sequence.

[0341] One possible approach is to uniformly add bits to the first bit sequence. Then, add padded bits (e.g., bits with a value of 0), and divide the first bit sequence after adding padded bits into P groups, each group including... Each of the P groups of information bits is associated with the first k bits of each of the P groups of B0. sub Each column corresponds to a specific column; this method can be simply referred to as a uniform distribution method.

[0342] Another possible approach is to allocate the K information bits to the first (P-1) groups first, and the remaining information bits to the last group, adding padding bits (such as bits with values ​​of 0) to fill any gaps, resulting in the last group. In other words, add bits to the end of the first bit sequence. The first bit sequence after adding padding bits is divided into P groups, each group consisting of... Each of the P groups of information bits is associated with the first k bits of each of the P groups of B0. sub Each column corresponds to a specific column. This method can be simply referred to as a non-uniform distribution method.

[0343] Optionally, the number of columns k in B0 corresponding to the information bits in the first bit sequence sub For predefined, configured, or indicated.

[0344] For example, k sub Values ​​predefined by the protocol. For example, k. sub It is a fixed value.

[0345] For example, ksub It is determined by the first communication device based on the mapping relationship. Regarding the first communication device determining k based on the mapping relationship... sub The process can be understood by referring to the process of the first communication device determining P based on the mapping relationship in the above text, and will not be repeated here.

[0346] For example, k sub This is indicated by the second communication device. The second communication device can, for example, determine k based on the above mapping relationship. sub The method further includes receiving fourth indication information from a second communication device, which indicates the column number k in B0 corresponding to the information bits in the first bit sequence. sub .

[0347] In K and k sub If all are determined, then we can refer to the above discussion of K and P, k sub Between these conditions, we obtain that P satisfies:

[0348] It is understandable that K cannot be multiplied by Z×k. sub If the data is divisible by integers, P can be determined by rounding up. In this case, the K information bits in the first bit sequence are insufficient to form a complete set of P information bits, so padding bits can be added to the first bit sequence. The specific method for adding padding bits can be found above and will not be repeated here.

[0349] Because the system may impose a limit on the maximum value of the first length K, for example, K max K does not exceed K max Or, in other words, K≤K max Therefore, k sub It can also satisfy: P can also satisfy:

[0350] It should be understood that in P and k sub When both indications are provided by the second communication device via indication information, the third and fourth indication information can be indication information carried in the same signaling, such as different fields carried in the same signaling; or they can be indication information carried in different signaling. This application does not limit this.

[0351] Of course, the first length K can be predefined, such as fixed, or it can be variable, such as configured or indicated. As the size of the resources allocated by the network side changes, the actual number of bits of information that the first communication device needs to send changes, and so on, the first length K can also be flexibly adjusted. For example, it can be determined by the first communication device or by the second communication device and notified to the first communication device via signaling; this application does not limit this.

[0352] In real-world scenarios, the required bitrate may vary depending on the type of business. As seen in the encoding process described above for line-by-line encoding, the number of columns k corresponding to the information bits in B0... sub It is related to the length of the actual encoded information bits. To allow for flexible adjustment of the code rate, B0 can satisfy a Raptor-like structure.

[0353] For example, Figure 15 is a schematic diagram of B0 with a Raptor-like structure. B0 may include a core check submatrix, an extended check submatrix, an all-zero submatrix, and a unit submatrix. The core check submatrix and the extended check submatrix are located in the same number of columns, with the extended check submatrix located below the core check submatrix. The unit submatrix is ​​a square matrix with the same number of rows as the extended check submatrix. The all-zero submatrix has the same number of rows as the core check submatrix, and the all-zero submatrix has the same number of columns as the unit submatrix. For example, the dimension of the core check submatrix can be m. core ×n core The dimension of the extended check subarray can be m. rex ×n rex The dimension of an all-zero subarray can be m. core ×n diag The dimension of the identity subarray can be n. diag ×n diag And the dimensions of each subarray satisfy: m core +m rex =m sub ;n core +n diag =n sub m core n core m rex n rex and n diag All are positive integers greater than 1.

[0354] The core subarray corresponds to the information bits in the first bit sequence. The check subarray can be considered as an extended subarray generated based on the core subarray. Subject to n sub =k sub +m subUnder the constraint that each row added to the extended submatrix allows for the addition of one column to the submatrix B0, the submatrix can be expanded. To achieve different code rates, the core submatrix can be expanded. As the number of rows and columns increases, the number of parity bits and the code length also increase, while the code rate decreases. Therefore, based on this Raptor-like structure of the submatrix B0, the first communication device can determine the dimension m of the submatrix according to the encoding requirements of different code rates. sub ×n sub .

[0355] Design 2: The first basis matrix is ​​H B1 Or with H B1 A matrix H has row and / or column transformation relationships. B1 satisfy:

[0356] Among them, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions.

[0357] In this first basis matrix, X at different positions can be the same or different; X at each position can be a submatrix of all zeros or a submatrix of non-all zeros. This application does not impose any restrictions on this.

[0358] As can be seen, the dimension of the first basis matrix shown in Formula 5 can be: ((P+W-1)×m sub )×((P+W-1)×n sub That is, including (P+W-1)×m sub One row, (P+W-1)×n sub There are 1 column, or in other words, (P+W-1) horizontal groups and (P+W-1) vertical groups.

[0359] In step 910, the first communication device can obtain the parity check matrix based on each element of the first basis matrix. The process of obtaining the parity check matrix from the first basis matrix can be found above in conjunction with the basis matrix H. b The explanation of the parity check matrix H is only H b Since the elements in the matrix are different, the elements in the obtained verification matrix H are also different, which will not be elaborated further.

[0360] For example, if we expand each submatrix in the first basis matrix, we can also obtain a basis matrix H of the form described above. b Based on the structure of H, and following the dimensional expansion method described above, the parity-check matrix can be obtained. At this point, the basis matrix H in the example above...b The dimension of the matrix is ​​the same as that of the first basis matrix. In Design 2, it can be ((P+W-1)×m sub )×((P+W-1)×n sub ), that is, m b = (P + W - 1) × m sub n b = (P + W - 1) × n sub The dimension M'×N' of the parity check matrix H0 in the example above can also be the same as the dimension M×N of the parity check matrix provided in this embodiment.

[0361] For example, the basis matrix H can also be... b As a submatrix in the first basis matrix, for example, B0 in the first basis matrix. Expanding each submatrix in the first basis matrix can also yield a larger-dimensional basis matrix H of the form described above. b The structure of H, and by following the dimensional expansion method described above, can also yield the parity check matrix. At this point, the basis matrix H... b The dimension of m can be the same as the dimension of each of the W submatrices in the first basis matrix, that is, m b =m sub n b =n sub The dimension M×N of the parity check matrix obtained based on this first basis matrix is ​​different from the dimension M'×N' of the parity check matrix H0 in the example above. More specifically, M is greater than M' and N is greater than N'.

[0362] It can be understood that, based on this first basis matrix and the expansion factor Z, the dimension of the parity check matrix H is ((P+W-1)×m). sub ×Z)×((P+W-1)×n sub If the parity-check matrix is ​​represented as an M×N dimension matrix, then M = (P + W - 1) × m sub ×Z, N=(P+W-1)×n sub ×Z, K=(P+W-1)×(n sub -m sub )×Z=(P+W-1)×k sub ×Z.

[0363] In step 920, the first communication device may encode the first bit sequence based on the parity check matrix obtained from the first base matrix.

[0364] Similar to Design 1, since obtaining the parity-check matrix based on the first basis matrix is ​​a dimensional expansion process, each element in the first basis matrix corresponds to a Z×Z dimensional submatrix in the parity-check matrix. Therefore, encoding the first bit sequence based on the parity-check matrix obtained from the first basis matrix can also be simply referred to as encoding the first bit sequence based on the first basis matrix.

[0365] As mentioned above in conjunction with Figure 8, the basis matrix B of the SC-LDPC code... SC (See Formula 1) The protection for the information bits corresponding to the tail B0 is relatively weak. The first basis matrix H provided in Design 2 B1 Basis matrix B SC One or more non-zero submatrices are added below the diagonal. Through this design, the first basis matrix H... B1 It not only includes a ladder structure, but also one or more non-zero submatrices located below the diagonal. Because these non-zero submatrices are located below the diagonal, although they can form a parity check equation, the solution to the parity check equation cannot be directly obtained, thus preventing the acquisition of more parity bits.

[0366] Therefore, the first communication device can communicate via the first basis matrix H B1 Perform matrix transformations to obtain a matrix that satisfies the following structure (e.g., denoted as H). B1 '): [IU], where I represents a unit diagonal submatrix and U represents a common submatrix. The matrix transformation includes one or more of the following: row transformation, column transformation, or Gaussian transformation. Furthermore, based on this matrix H... B1 The obtained parity-check matrix is ​​used to perform LDPC encoding on the first bit sequence. Alternatively, the first communication device can first base the encoding on the first basis matrix H. B1 The parity check matrix is ​​obtained, and then matrix transformation is performed on the parity check matrix to obtain a matrix that satisfies the above structure. This application does not limit this process.

[0367] Alternatively, the first communication device may not perform the above matrix transformation, but instead perform overall encoding based on the parity check matrix. For example, the parity check matrix H with dimension M×N obtained based on the first base matrix is ​​divided into two sub-matrices H1 and H2 as follows: H=[H1 H2], the dimension of sub-matrix H1 is M×K, and the dimension of sub-matrix H2 is M×M.

[0368] The process of LDPC encoding the first bit sequence based on the parity-check matrix has already been explained in the terminology section and in Design 1, along with the formulas, and will not be repeated here. It should be noted that in Design 2, the dimension of the first basis matrix is ​​((P+W-1)×m). sub )×((P+W-1)×n sub Therefore, the dimension of the unit diagonal submatrix I can be ((P+W-1)×m).sub )×((P+W-1)×m sub The dimension of the ordinary submatrix U can be ((P+W-1)×m). sub )×((P+W-1)×k sub ).

[0369] Since K is not necessarily divisible by Z, padding bits can be added to the first bit sequence if K is not divisible by Z. For example, padding bits can be added to the end of the K information bits. The application does not limit the specific implementation method for adding padding bits (e.g., bits with a value of 0).

[0370] Optionally, the first basis matrix H B1 Each X in the matrix is ​​a zero submatrix.

[0371] In other words, the H B1 satisfy:

[0372] The first basis matrix shown in Equation 5.1 contains fewer non-zero submatrices than the first basis matrix shown in Equation 5. Therefore, encoding based on the first basis matrix shown in Equation 5.1 requires less computation and has lower computational complexity than encoding based on the first basis matrix shown in Equation 5.

[0373] Furthermore, the first basis matrix shown in Equation 5.1 is equivalent to Equation 3, except that the third and fourth sub-blocks have been removed and some sub-matrices have been cyclically shifted.

[0374] Figures 16 to 19 show two examples of the first basis matrix determined by Equation 5.1. Figures 16 to 19 show the non-zero submatrices in the first basis matrix, while the all-zero submatrices are not shown.

[0375] In the first basis matrix shown in Figures 16 and 17, P is 4 and W is 2. Figure 16 shows the structure of the first basis matrix determined by Equation 5.1, P being 4, and W being 2. Figure 17 further shows how to obtain the first basis matrix shown in Figure 16 by cyclically shifting some submatrices of the first basis matrix determined by Equation 3, P being 4, and W being 2 (as shown in Figure 14A). In Figure 17(a), the third sub-block in the first basis matrix shown in Figure 14A can first be removed, and then B0 in the first horizontal group (shown in the figure with a dashed box) can be cyclically shifted upwards to obtain the first basis matrix shown in Figure 16. In Figure 17(b), the third sub-block in the first basis matrix shown in Figure 14A can be removed first. Then, following the rule of the ladder structure, the end of the last horizontal group is filled in so that the last horizontal group after filling in includes W sub-matrices (2 sub-matrices in the figure). One possible way is to add B0 from the first horizontal group to the end of the last horizontal group, and then cyclically shift the added sub-matrix (B0 shown in the figure with a dashed box) to the right, which can also obtain the first basis matrix shown in Figure 16.

[0376] In the first basis matrix shown in Figures 18 and 19, P is 8 and W is 4. Figure 18 shows the structure of the first basis matrix given by Equation 5.1, with P = 8 and W = 4. Figure 19 further shows how to obtain the first basis matrix shown in Figure 18 by cyclically shifting some submatrices of the first basis matrix determined by Equation 3, with P = 8 and W = 4 (as shown in Figure 14B). In Figure 19(a), the third sub-block in the first basis matrix shown in Figure 14B can be removed first. Then, keeping the relative positions between the submatrices unchanged, the submatrices in the first three horizontal groups (B0, B1, and B2 shown in dashed boxes in the figure) are cyclically shifted upwards to obtain the first basis matrix shown in Figure 18. In Figure 19(b), the third sub-block in the first basis matrix shown in Figure 14B can be removed first. Then, following the rule of the ladder structure, the ends of the last three horizontal groups are filled in so that each horizontal group in the last three horizontal groups after filling in includes W sub-matrices (4 sub-matrices in the figure). Then, the added sub-matrices (B0, B1 and B2 shown in the figure with dashed boxes) are cyclically shifted to the right to obtain the first basis matrix shown in Figure 18.

[0377] It should be understood that the foregoing description, in conjunction with Figures 14A, 17, 14B, and 19, illustrates the difference between the first basis matrix in Design 2 and the first basis matrix in Design 1. The actions introduced in the description are merely illustrative for ease of understanding and should not constitute any limitation on this application. The first communication device does not necessarily perform these operations during the process of obtaining the first basis matrix.

[0378] It should also be understood that the examples of the first basis matrix shown above with different values ​​of P and W are given for ease of understanding only and should not constitute any limitation on this application. This application does not limit the values ​​of P and W.

[0379] It should also be understood that Formula 5.1 and the first basis matrix shown in Figures 16 to 19 are merely examples, and the first basis matrix of Design 2 is not limited to these. For example, in Figures 17 and 19 above, the number of bits for cyclic shift can also be varied, and is not limited to the examples shown in the figures. For the sake of simplicity, no further figures will be provided.

[0380] Observing Formula 5, Formula 5.1, and Figures 16 to 19, it can be found that, unlike Design 1, the first basis matrix of Design 2 does not include the tail submatrix B. T Therefore, encoding based on this first basis matrix will not introduce a submatrix B due to the addition of a tail. T The increase in parity bits introduced by this design does not result in a loss of code rate when encoding based on the first basis matrix of Design 2. Furthermore, simulations show that encoding based on the first basis matrix of Design 2, compared to the basis matrix B of the SC-LDPC code, results in a higher code rate. SC In other words, it can also improve decoding performance.

[0381] It should be understood that the above text uses H B1 The first basis matrix and the LDPC encoding of the first bit sequence based on the first basis matrix have been described in detail, but this should not be construed as limiting this application. As mentioned above, the first basis matrix can also be H B1 A matrix with row and / or column transformation relationships. In other words, the first basis matrix is ​​not limited to the forms shown in Equations 5, 5.1, and Figures 16 to 19 above, but can also be derived from H shown in Equations 5, 5.1, and Figures 16 to 19. B1 Performing row and / or column transformations yields other forms of the first basis matrix; for simplicity, these are not illustrated here. And through H... B1 The first basis matrix obtained by performing row and / or column transformations is also applicable to LDPC encoding in the manner described above, and has the same technical effect, so it will not be repeated here.

[0382] Design 3: The first basis matrix is ​​H B1 Or with H B1 A matrix with row and / or column transformation relationships, this H B1 satisfy:

[0383] Among them, B wLet be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions, and located within H B1 There exists at least one non-zero submatrix among the multiple X's in the last row.

[0384] In this first basis matrix, X at different positions can be the same or different; X at each position can be a submatrix of all zeros or a non-zero submatrix. This application does not impose any restrictions on this.

[0385] As can be seen, the dimension of the first basis matrix shown in Formula 6 can be: ((P+W-1)×m sub )×(P×n sub That is, including (P+W-1)×m sub One row, P×n sub There are 1 column, or in other words, (P+W-1) horizontal groups and P vertical groups.

[0386] In step 910, the first communication device can obtain the parity check matrix based on each element of the first basis matrix. The process of obtaining the parity check matrix from the first basis matrix can be found above in conjunction with the basis matrix H. b The explanation of the parity check matrix H is only H b Since the elements in the matrix are different, the elements in the obtained verification matrix H are also different, which will not be elaborated further.

[0387] For example, if we expand each submatrix in the first basis matrix, we can also obtain a basis matrix H of the form described above. b Based on the structure of H, and following the dimensional expansion method described above, the parity-check matrix can be obtained. At this point, the basis matrix H in the example above... b The dimension of the matrix is ​​the same as the dimension of the first basis matrix. In Design 3, it can be ((P+W-1)×m sub )×(P×n sub ), that is, m b = (P + W - 1) × m sub n b =P×n sub The dimension M'×N' of the parity check matrix H0 in the example above can also be the same as the dimension M×N of the parity check matrix provided in this embodiment.

[0388] For example, the basis matrix H can also be... b As a submatrix in the first basis matrix, for example, B0 in the first basis matrix. Expanding each submatrix in the first basis matrix can also yield a larger-dimensional basis matrix H of the form described above.b The structure of H, and by following the dimensional expansion method described above, can also yield the parity check matrix. At this point, the basis matrix H... b The dimension of m can be the same as the dimension of each of the W submatrices in the first basis matrix, that is, m b =m sub n b =n sub The dimension M×N of the parity check matrix obtained based on this first basis matrix is ​​different from the dimension M'×N' of the parity check matrix H0 in the example above. More specifically, M is greater than M' and N is greater than N'.

[0389] Similar to Design 2, Design 3 provides the first basis matrix H. B1 Basis matrix B SC It also adds one or more non-zero submatrices located below the diagonal, the difference being that it designs three pairs of basis matrices B. SC The basic structure remains unchanged, and the added non-zero submatrices differ from those in Design 2. In Design 3, the first basis matrix may include one or more non-zero submatrices located below the diagonal, and the last horizontal group of the first basis matrix includes at least one non-zero submatrix. These one or more non-zero submatrices may be randomly generated, and are not limited to those from the aforementioned W submatrices.

[0390] It can be understood that, based on this first basis matrix and the expansion factor Z, the dimension of the parity check matrix H is ((P+W-1)×m). sub ×Z)×(P×n sub If the parity-check matrix is ​​represented as an M×N dimension matrix, then M = (P + W - 1) × m sub ×Z, N=P×nsub×Z, K=(P×(n sub -m sub )-(W-1)×m sub )×Z.

[0391] In step 920, the first communication device may encode the first bit sequence based on the parity check matrix obtained from the first base matrix.

[0392] Since the one or more non-zero submatrices are located below the diagonal of the first basis matrix, although they can form a parity check equation, the solution to the parity check equation cannot be directly obtained to obtain more parity bits. Therefore, the solution can be obtained by modifying the first basis matrix H. B1 Perform matrix transformations to obtain a matrix that satisfies the following structure (e.g., denoted as H). B1 '): [IU], and then based on the matrix H B1The obtained parity-check matrix is ​​used to perform LDPC encoding on the first bit sequence. Alternatively, the first communication device may not perform matrix transformation on the first base matrix, but directly divide the parity-check matrix into submatrices H1 and H2 as follows: H = [H1 H2]. For a more detailed explanation of [IU] obtained from the matrix transformation, and submatrices H1 and H2, please refer to the explanation of the encoding method in conjunction with Design 1 and Design 2 above, which will not be repeated here. Since the dimension of the first base matrix in Design 3 is different from that of the first base matrix in Design 1 and Design 2, the dimensions of the corresponding unit diagonal submatrices I and U are also different. In Design 3, the dimension of the first base matrix is ​​((P+W-1)×m sub )×(P×n sub The dimension of the unit diagonal submatrix I can be ((P+W-1)×m) sub )×((P+W-1)×m sub The dimension of the submatrix U can be ((P+W-1)×m) sub )×(P×k sub -(W-1)×m sub (This will not be elaborated further.)

[0393] The process of LDPC encoding the first bit sequence based on the parity-check matrix has been explained in the terminology section above with the formula, and will not be repeated here.

[0394] It should be understood that since Design 3 is similar to Design 2, more detailed explanations of steps 910 and 920 can be found in the above description of Design 2, and will not be repeated here.

[0395] Optionally, the first basis matrix H B1 satisfy:

[0396] Among them, B T It is a non-zero submatrix.

[0397] That is, the first basis matrix H B1 Except for the X in the first vertical group and the last horizontal group, which are non-zero submatrices, all other X positions are all-zero submatrices.

[0398] The first basis matrix shown in Equation 6.1 contains fewer non-zero submatrices than the first basis matrix shown in Equation 6. Therefore, encoding based on the first basis matrix shown in Equation 6.1 requires less computation and has lower computational complexity than encoding based on the first basis matrix shown in Equation 6.

[0399] Figures 20 and 21 show two examples of the first basis matrix determined by Equation 6.1. Figures 20 and 21 respectively show the non-zero submatrices in this first basis matrix, while the all-zero submatrices are not shown. In the first basis matrix shown in Figure 20, P is 4 and W is 2. In the first basis matrix shown in Figure 21, P is 8 and W is 4. It should be understood that the above examples of the first basis matrix with different values ​​of P and W are given for ease of understanding only and should not constitute any limitation on this application. This application does not limit the values ​​of P and W.

[0400] It should also be understood that the first basis matrix shown in Equation 6.1 and Figures 20 and 21 is merely an example, and the first basis matrix of Design 3 is not limited to this. For example, the first basis matrix may include more non-zero submatrices below the diagonal. Another example is B in the first basis matrix. T It can also be located in other vertical groups. This application does not limit this.

[0401] Observing Formula 6, Formula 6.1, and Figures 20 to 21, it can be found that, unlike Design 1, the first basis matrix of Design 3 does not include the tail submatrix B. T Therefore, encoding based on this first basis matrix will not introduce a submatrix B due to the addition of a tail. T The increase in parity bits introduced by this design does not result in a loss of code rate when encoding based on the first basis matrix of Design 3. Furthermore, simulations show that encoding based on the first basis matrix of Design 3, compared to the basis matrix B of the SC-LDPC code, results in a higher code rate. SC In other words, it can also improve decoding performance.

[0402] It should be understood that the above text uses H B1 The first basis matrix and the LDPC encoding of the first bit sequence based on the first basis matrix have been described in detail, but this should not be construed as limiting this application. As mentioned above, the first basis matrix can also be H B1 A matrix with row and / or column transformation relationships. In other words, the first basis matrix is ​​not limited to the forms shown in Equations 6, 6.1, and Figures 20 and 21 above, but can also be derived from H shown in Equations 6, 6.1, and Figures 20 and 21. B1 Performing row and / or column transformations yields other forms of the first basis matrix; for simplicity, these are not illustrated here. And through H... B1 The first basis matrix obtained by performing row and / or column transformations is also applicable to LDPC encoding in the manner described above, and has the same technical effect, so it will not be repeated here.

[0403] The foregoing section has provided a detailed explanation of the first basis matrix and the encoding process based on it, using three different designs. The first basis matrix is ​​illustrated in various designs with numerous figures and formulas; these examples are provided for ease of understanding only and should not be construed as limiting the scope of this application.

[0404] In the embodiments of this application, the first basis matrix may be predefined, such as a protocol predefined matrix, or it may be pre-stored in the first communication device. The first communication device can read the first basis matrix when there is an encoding requirement. Alternatively, the first basis matrix may be generated by the first communication device when there is an encoding requirement. For example, the first communication device can generate the first basis matrix based on a predefined second basis matrix. Or, the first basis matrix may also be indicated by the second communication device. This application does not limit this.

[0405] Optionally, the method further includes: obtaining a first basis matrix based on a second basis matrix; the second basis matrix is ​​H. B2 Or with H B2 A matrix with row and / or column transformation relationships, this H B2 satisfy:

[0406] As can be seen, the ladder-like structures contained in the first basis matrix shown in Designs 1, 2, and 3 can all be obtained by extracting rows and / or columns from the second basis matrix. In other words, the ladder-like structures contained in the first basis matrix are submatrices of the second basis matrix. Therefore, the first communication device can pre-store the second basis matrix and generate the first basis matrix when encoding is required. This saves storage overhead.

[0407] In the embodiments of this application, whether the first communication device uses the first base matrix can be pre-configured.

[0408] For ease of distinction and explanation, the scheme that obtains the parity check matrix based on the first base matrix and then performs encoding and decoding will be referred to as Scheme 1, and the scheme that obtains the parity check matrix based on other base matrices (such as BG 1 or BG 2) and then performs encoding and decoding will be referred to as Scheme 2.

[0409] If the first communication device is pre-configured to execute Scheme 1 but not Scheme 2, for example, if a computer program for executing Scheme 1 is installed but a computer program for executing Scheme 2 is not installed, or if it has circuitry for executing Scheme 1 but not for executing Scheme 2, then when there is an encoding requirement, the first communication device can directly perform LDPC encoding based on the aforementioned process (as shown in steps 910 to 930). If the first communication device is pre-configured to execute Scheme 2 but not Scheme 1, for example, if a computer program for executing Scheme 2 is installed but a computer program for executing Scheme 1 is not installed, or if it has circuitry for executing Scheme 2 but not for executing Scheme 1, then when there is an encoding requirement, the first communication device can obtain a parity check matrix based on other base matrices instead of the first base matrix, and then perform encoding based on the obtained parity check matrix.

[0410] The first communication device may also be configured to perform both Scheme 1 and Scheme 2, for example, by installing computer programs that can perform Scheme 1 and Scheme 2, or by having circuitry that can perform Scheme 1 and Scheme 2. In this case, the communication device can determine whether to use the first base matrix before step 910, and if it is determined that the first base matrix should be used, perform the aforementioned process.

[0411] Optionally, prior to step 910, the method further includes step 940, determining the use of a first basis matrix.

[0412] Accordingly, step 910 specifically includes: if it is determined that the first base matrix is ​​to be used, obtaining the parity matrix based on the first base matrix.

[0413] The first communication device can determine whether to use the first basis matrix on its own, or it can determine whether to use the first basis matrix based on instructions from the second communication device. The following will describe these two possible implementations in detail.

[0414] In one possible implementation, step 940 specifically includes: determining the use of a first base matrix based on one or more of the following: a first length, the service type to which the first bit sequence belongs, the code rate, the capability of a first communication device, or the capability of a second communication device communicating with the first communication device.

[0415] Here, the first length refers to the length of the first bit sequence. When the first bit sequence is long, encoding based on the aforementioned first basis matrix can simplify the encoding and reduce computational complexity. Therefore, the use of the first basis matrix can be determined based on the first length. For example, if the first length is greater than or equal to a first threshold, the first basis matrix is ​​used; if the first length is less than the first threshold, other basis matrices are used, such as the basis matrices defined in current standards, such as BG 1 and BG 2 defined in 3GPP TS38.212, without limitation.

[0416] The first communication device can also determine whether to use the first base matrix based on the code rate. When the code rate indicated by the MCS is low, encoding can be performed based on the first base matrix. For example, if the first length is greater than or equal to a first threshold and the code rate indicated by the MCS is less than or equal to a second threshold, the first base matrix is ​​determined to be used; if the first length is less than the first threshold or the code rate indicated by the MCS is greater than the second threshold, other base matrices, such as BG 1 or BG 2 mentioned above, are used without limitation.

[0417] The first communication device can also determine whether to use the first basis matrix based on the service type to which the first bit sequence belongs. For example, for latency-sensitive services and / or services with many large packets, such as streaming media services, the first basis matrix can be used; for services with high reliability requirements, latency-insensitive services, or services with many small packets, other basis matrices can be used, such as BG 1 or BG 2 mentioned above, without limitation. The size of the packet (large or small) can be determined based on the data volume. The data volume can be characterized by, for example, the length of the bit sequence (e.g., the length of the first bit sequence, i.e., the first length) or the code length. Data packets with larger data volumes can be called large packets, and data packets with smaller data volumes can be called small packets. Large and small packets can be determined by a preset threshold, which is not limited in this application.

[0418] The first communication device may also determine whether to use the first base matrix based on the capabilities of the first communication device and / or the capabilities of the second communication device.

[0419] The second communication device may be configured to execute Scheme 1 without executing Scheme 2, or to execute Scheme 2 without executing Scheme 1, or to be configured to perform both Scheme 1 and Scheme 2. Therefore, the first communication device can determine whether to use the first base matrix based on the capabilities of the second communication device.

[0420] For example, if the second communication device is configured to execute Scheme 1 instead of Scheme 2, the first communication device can determine whether to use the first base matrix. As another example, if both the first and second communication devices are configured to execute both Scheme 1 and Scheme 2, the first communication device can also determine whether to use the first base matrix by considering other factors, such as one or more of the first length, code rate, or the service type to which the first bit sequence belongs. Yet another example, if the first communication device is configured to execute both Scheme 1 and Scheme 2, and the second communication device is configured to execute Scheme 2 instead of Scheme 1, the first communication device can determine not to use the first base matrix.

[0421] Optionally, the method further includes: receiving capability information of the second communication device, the capability information being used to indicate the coding capabilities of the second communication device. The coding capabilities may include, but are not limited to, the capabilities listed above, i.e., including but not limited to: being configured to execute Scheme 1 without executing Scheme 2, or being configured to execute Scheme 2 without executing Scheme 1, or being configured to simultaneously execute Scheme 1 and Scheme 2.

[0422] If the first communication device determines that a first base matrix should be used, it may instruct the second communication device to use the first base matrix via an instruction message. Optionally, the method may further include: sending first instruction message, which is used to instruct the use of the first base matrix, or to indicate the first base matrix.

[0423] For example, the first communication device is a terminal device, and the first indication information can be an indication bit in the uplink control information (UCI). When the indication bit is 1, it indicates that the first base matrix is ​​used; when the indication bit is 0, it indicates that other base matrices are used instead of the first base matrix. Therefore, the first indication information can also be said to indicate whether the first base matrix is ​​used.

[0424] For example, the first communication device can indicate the first base matrix through first indication information, such as indicating the parameters used to generate the first base matrix, like the number of horizontal groups, the number of vertical groups, P, W, etc., included in the first base matrix. This makes it easier for the second communication device to use the same first base matrix for decoding.

[0425] In another possible implementation, the first communication device can determine whether to use the first basis matrix based on the instruction information from the second communication device. That is, the second communication device determines whether to use the first basis matrix.

[0426] Optionally, the method further includes: receiving second indication information, the second indication information being used to indicate the use of a first basis matrix, or to indicate the first basis matrix. Accordingly, step 940 specifically includes: determining the use of the first basis matrix based on the second indication information.

[0427] The second instruction message has a similar function to the first instruction message, except that the sender and receiver of the instruction message are different. Therefore, the content of the second instruction message can be understood by referring to the relevant description of the first instruction message above, and will not be repeated here.

[0428] Based on the above scheme, the first communication device can determine whether to use the first basis matrix to obtain the parity check matrix according to actual needs and / or equipment capabilities. This allows for more flexible selection of different schemes to address different scenarios and achieve greater benefits in different scenarios.

[0429] The encoding method provided in this application has been described in detail above with reference to several accompanying drawings. The decoding method provided in this application will now be described in detail below with reference to the accompanying drawings. It is understood that the decoding method provided in this application can be used to decode a bit sequence obtained by encoding based on the encoding method provided in the above embodiments. In this embodiment, the bit sequence can be the aforementioned second bit sequence, possessing the characteristics of a second bit sequence. Exemplarily, the second bit sequence is obtained by LDPC encoding the first bit sequence based on a parity-check matrix obtained from the first base matrix. By performing LDPC decoding on the second bit sequence, a third bit sequence corresponding to the first bit sequence can be obtained.

[0430] In one possible implementation, the decoding method can correspond to the encoding method and can be used to decode the bit sequence obtained by the encoding method provided above.

[0431] Figure 22 is a schematic flowchart of the decoding method 2200 provided in an embodiment of this application. The method 2200 can be executed by a second communication device, which can be a communication equipment, such as a network device or a terminal device; it can also be a component configured in the communication equipment, such as a circuit or chip inside the communication equipment (e.g., a modem chip, or a SoC chip or SIP chip containing a modem core); it can also be a logic module or software capable of implementing some or all of the functions of the second communication device, etc., and this application does not limit it in this regard.

[0432] The decoding method 2200 shown in Figure 22 may include steps 2210 to 2230. Optionally, it may also include step 2240. The various steps in method 2200 are described in detail below.

[0433] In step 2210, the second bit sequence is obtained.

[0434] As can be seen from the physical layer processing described above in conjunction with Figure 3 and the encoding method described in Figure 8, the second bit sequence includes multiple encoded bits. These multiple encoded bits can be obtained based on the encoding method shown in Figure 9 above, and for example, can include N encoded bits, denoted as p0, p1, ..., p N-1 .

[0435] Optionally, obtaining the second bit sequence includes:

[0436] Receive a signal carrying a second bit sequence; and

[0437] The second bit sequence is obtained from the signal.

[0438] When the second communication device is a terminal device or a network device, it can receive a second bit sequence from the first communication device via an antenna. As mentioned earlier, the first communication device can carry the second bit sequence via a radio frequency (RF) signal, and the second communication device can receive the RF signal carrying the second bit sequence via an antenna. In other words, after receiving the RF signal, the second communication device can obtain the second bit sequence through operations corresponding to those of the first communication device. Obtaining the second bit sequence may specifically include operations such as down-conversion, de-layer mapping, demodulation, descrambling, and rate matching of the RF signal, without limitation.

[0439] When the second communication device is a chip or chip system, the second communication device can receive the second bit sequence through input / output circuits or interface circuits.

[0440] For a more detailed explanation of the second bit sequence, please refer to the relevant explanation in step 930 of method 900 above, which will not be repeated here.

[0441] In step 2220, the parity check matrix is ​​obtained based on the first base matrix.

[0442] The specific process by which the second communication device obtains the parity matrix based on the first base matrix is ​​similar to that of the first communication device. It can be understood by referring to the descriptions in step 920, Design 1, Design 2 and Design 3 above, and will not be repeated here.

[0443] In step 2230, the second bit sequence is LDPC decoded based on the parity check matrix to obtain the third bit sequence.

[0444] Corresponding to the encoding method, the second communication device can also use a variety of different methods for LDPC decoding.

[0445] Since obtaining the parity-check matrix based on the first basis matrix is ​​a dimensional expansion process, each element in the first basis matrix corresponds to a Z×Z dimensional submatrix in the parity-check matrix. Therefore, decoding the second bit sequence based on the parity-check matrix obtained from the first basis matrix can also be simply referred to as decoding the second bit sequence based on the first basis matrix.

[0446] Corresponding to line-by-line encoding, one possible decoding method is sliding window decoding, which uses the decoding window as the granularity, sliding from the top left corner to the bottom right corner of the parity check matrix, and decoding is performed based on the submatrices of the parity check matrix that fall within the decoding window.

[0447] The sliding window decoding is described below using the first basis matrix shown in Figure 14A as an example. Figures 23A and 23B are schematic diagrams of sliding window decoding corresponding to the first basis matrix shown in Figure 14A. Since each element in the first basis matrix can be expanded into a Z×Z dimension submatrix in the parity check matrix, and this application mainly involves improvements to the basis matrix, Figures 23A and 23B directly show the decoding window sliding on the first basis matrix. The sliding method of the decoding window on the parity check matrix is ​​the same. Each submatrix in Figures 23A and 23B (e.g., B) is used to represent the decoding window. w B T The dimensions have been expanded, so no further illustrations are needed.

[0448] The first basis matrix shown in Figure 23A is an example of the first basis matrix in Design 1, where P is 4 and W is 2. The decoding window shown in Figure 23A is a 3×3 decoding window. The second communication device can perform decoding based on the submatrix within each decoding window. It can be seen that by sliding from the upper left corner to the lower right corner of the first basis matrix, the submatrixes in the first basis matrix are successively divided into 6 submatrixes by the decoding window. These 6 submatrixes can be used to decode the input encoded bits respectively. For ease of distinction and explanation, the submatrix within each decoding window will be referred to as the decoding window below, to distinguish it from the submatrix B mentioned above. w B T Distinguishing between the two. The input to each decoding window can be a subset of the N coded bits included in the second bit sequence. For ease of distinction and explanation, the log-likelihood ratio (LLR) of the N coded bits obtained by demodulation of the signal received by the second communication device is denoted as: y0, y1, ..., y N-1These are also the initial values ​​of the posterior information for each variable node. The N encoded bits are input into the decoding windows. Decoding windows ① and ② are used for iteration and do not output decision results; decoding windows ③, ④, ⑤, and ⑥ can be used for iteration and output decision results. Specifically, decoding window ③ outputs the decision result corresponding to the information bit corresponding to B0 in the first horizontal group of the first basis matrix; decoding window ④ outputs the decision result corresponding to the information bit corresponding to B0 in the second horizontal group of the first basis matrix; decoding window ⑤ outputs the decision result corresponding to the information bit corresponding to B0 in the third horizontal group of the first basis matrix; and decoding window ⑥ outputs the decision result corresponding to the information bit corresponding to B0 in the fourth horizontal group of the first basis matrix.

[0449] It should be understood that the sliding window decoding shown in Figure 23A is only an example, and the decoding window can be adjusted. For example, in Figure 23B, decoding window ① can be 1×1, decoding window ② can be 2×2, and decoding window ④ can be 4×4. This application does not limit this.

[0450] The second communication device can employ existing decoding algorithms to perform LDPC decoding within each decoding window. Examples include the sum-product algorithm (SPA) and its simplified min-sum algorithm, etc., without limitation.

[0451] It should be understood that the sliding window decoding shown in Figures 23A and 23B are only two examples. As can be seen in method 900, the lower left corner of the first basis matrix may also include one or more non-zero submatrices, as shown in Equation 3. In this case, if sliding window decoding is still used, the size of the decoding window can be adjusted during the sliding process. For example, as the decoding window slides from the upper left corner to the lower right corner, the decoding window gradually increases in size.

[0452] For example, Figure 24 is a schematic diagram of sliding window decoding corresponding to the first basis matrix in Figure 13A. As shown, sliding from the upper left corner to the lower right corner of the first basis matrix, the submatrices in the first basis matrix are successively divided into five submatrices by decoding windows ① to ⑤. These five submatrices can be used to decode the input encoded bits respectively. It can be seen that as the decoding window slides down, the decoding window gradually becomes larger, because there may be a non-zero submatrix in the lower left corner of the first basis matrix.

[0453] In another implementation, the second communication device may also decode the parity check matrix as a whole. For example, the second communication device may perform matrix transformations on the first basis matrix or the parity check matrix to obtain a matrix with the following structure: a unit diagonal submatrix on the left and a regular submatrix on the right. The matrix transformations may include one or more of the following: row transformations, column transformations, or Gaussian transformations.

[0454] The first communication device can first perform a matrix transformation on the first basis matrix to obtain a matrix with the following structure: [IU], and then obtain the parity check matrix based on the transformed matrix. Alternatively, it can obtain the parity check matrix based on the first basis matrix and then perform a matrix transformation. Or, the first communication device can also directly divide the parity check matrix into sub-matrices H1 and H2 without performing a matrix transformation on the first basis matrix, as follows: H = [H1 H2]. This application does not limit this approach. For a more detailed explanation of [IU] obtained by the matrix transformation, and the sub-matrices H1 and H2, please refer to the explanation of the encoding method above in conjunction with Design 1 and Design 2, which will not be repeated here.

[0455] The process of performing LDPC decoding on the second bit sequence using the parity-check matrix as a whole can be the same as the process of performing LDPC encoding on the first bit sequence using the parity-check matrix as a whole. LDPC decoding can be implemented using existing decoding algorithms, such as the SPA algorithm, the Min-Sum algorithm, and so on.

[0456] For example, the SPA algorithm utilizes the connection relationships between variable nodes and check nodes in the check matrix to iteratively update the posterior information y0, y1, ..., y of each variable node (corresponding to the received bit). N-1 Finally, the decision result for each variable node (i.e., the received encoded bits) is obtained based on the posterior information. For a more detailed explanation of the decoding algorithm, please refer to existing technologies; this article will not elaborate further.

[0457] The second bit sequence p0, p1, ..., p in method 900 above N-1 For example, the second bit sequence is composed of the first bit sequence a0, a1, ..., a 31 The encoding is obtained. Based on the parity-check matrix obtained from the first basis matrix, LDPC decoding is performed on the second bit sequence to obtain the third bit sequence as follows: As can be seen, the information bits in the third bit sequence correspond to those in the first bit sequence, and can be understood as the recovered value of the first bit sequence. Since the first bit sequence includes k from P B0s. sub The information bits corresponding to each column, the third bit sequence also includes k from the P B0s. sub Each column corresponds to a set of information bits.

[0458] In the embodiments of this application, the first basis matrix may be predefined, such as a protocol predefined matrix, or it may be pre-existing in the second communication device; alternatively, the first basis matrix may be generated by the second communication device when there is an encoding requirement, for example, the first communication device may generate the first basis matrix based on a predefined second basis matrix; or, the first basis matrix may be indicated by the first communication device. This application does not limit this.

[0459] Optionally, the method further includes: obtaining a first basis matrix based on a second basis matrix; the second basis matrix is ​​H. B2 Or with H B2 A matrix with row and / or column transformation relationships, this H B2 satisfy:

[0460] Referring to the first basis matrix shown in Designs 1, 2, and 3 of Method 900, it can be seen that the ladder-like structures contained in the first basis matrix can all be obtained by truncating rows and / or columns from the second basis matrix. In other words, the ladder-like structures contained in the first basis matrix are submatrices of the second basis matrix. Therefore, the second communication device can pre-store the second basis matrix and generate the first basis matrix when decoding is required. This can save some storage overhead.

[0461] In the embodiments of this application, whether the second communication device uses the first base matrix can be pre-configured.

[0462] For ease of distinction and explanation, the scheme that obtains the parity check matrix based on the first base matrix and then performs encoding and decoding will be referred to as Scheme 1, and the scheme that obtains the parity check matrix based on other base matrices (such as BG 1 or BG 2) and then performs encoding and decoding will be referred to as Scheme 2.

[0463] If the second communication device is pre-configured to execute Scheme 1 but not Scheme 2, for example, if it has a computer program installed to execute Scheme 1 but not Scheme 2, or if it has circuitry for executing Scheme 1 but not Scheme 2, then when there is a decoding requirement, the second communication device can directly perform LDPC decoding based on the aforementioned process (as shown in steps 2210 to 2230). If the second communication device is pre-configured to execute Scheme 2 but not Scheme 1, for example, if it has a computer program installed to execute Scheme 2 but not Scheme 1, or if it has circuitry for executing Scheme 2 but not Scheme 1, then when there is a decoding requirement, the second communication device can obtain the parity check matrix based on other base matrices instead of the first base matrix, and then perform decoding based on the obtained parity check matrix.

[0464] Optionally, prior to step 2210, the method further includes step 2240, determining the use of a first basis matrix.

[0465] Accordingly, step 2210 specifically includes: if it is determined that the first base matrix is ​​to be used, obtaining the parity matrix based on the first base matrix.

[0466] The second communication device can determine whether to use the first base matrix on its own, or it can determine whether to use the first base matrix based on an instruction from the first communication device.

[0467] In one possible implementation, step 2240 specifically includes: determining the use of a first base matrix based on one or more of the following: a first length, the service type to which the first bit sequence belongs, the code rate, the capability of the second communication device, or the capability of the first communication device communicating with the second communication device.

[0468] For a more detailed explanation of step 2240, please refer to the relevant description in step 940 of method 900, which will not be repeated here.

[0469] Optionally, the method further includes: receiving capability information of the first communication device, the capability information being used to indicate the coding capabilities of the first communication device. The coding capabilities may include, but are not limited to, the capabilities listed above, i.e., including but not limited to: being configured to execute Scheme 1 without executing Scheme 2, or being configured to execute Scheme 2 without executing Scheme 1, or being configured to simultaneously execute Scheme 1 and Scheme 2.

[0470] Optionally, the method further includes: sending a second indication message, the second indication message being used to indicate the use of a first base matrix, or to indicate the first base matrix.

[0471] In another possible implementation, the second communication device may also determine whether to use the first basis matrix based on the instruction information from the first communication device. That is, the first communication device determines whether to use the first basis matrix.

[0472] Optionally, the method further includes: receiving first indication information, which is used to indicate the use of a first basis matrix, or to indicate a first basis matrix. Accordingly, step 2240 specifically includes: determining the use of a first basis matrix based on the first indication information.

[0473] The specific method by which the second communication device determines whether to use the first base matrix is ​​similar to that of the first communication device. For a more detailed explanation of step 2240, please refer to the relevant description in step 940 of method 900, which will not be repeated here.

[0474] Based on the above scheme, the first communication device can determine whether to use the first basis matrix to obtain the parity check matrix according to actual needs and / or equipment capabilities. This allows for more flexible selection of different schemes to address different scenarios and achieve greater benefits in different scenarios.

[0475] The methods provided in the embodiments of this application have been described in detail above with reference to several accompanying drawings. The apparatus provided in the embodiments of this application will now be described with reference to the accompanying drawings.

[0476] As examples, Figures 25 and 26 are schematic block diagrams of possible apparatuses provided in embodiments of this application. These apparatuses can be used to implement the functions of the communication apparatus in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0477] Figure 25 is a schematic block diagram of a communication device provided in an embodiment of this application. The device 2500 shown in Figure 25 may include a processing module 2510 and a communication module 2520.

[0478] In one possible design, device 2500 can be used to implement the encoding method implemented by the first communication device in the embodiment shown in FIG9. For example, processing module 2510 is used to implement the processing-related steps such as obtaining the parity check matrix and encoding performed by the first communication device in steps 910 to 940 of method 900, and communication module 2520 can be used to implement the sending and / or receiving steps performed by the first communication device in method 900, such as sending a second bit sequence, sending first indication information, or receiving second indication information.

[0479] For example, the processing module 2510 can be used to: obtain a parity check matrix based on the first base matrix; and perform LDPC encoding on the first bit sequence having a first length based on the parity check matrix to obtain a second bit sequence. Optionally, the communication module 2520 can be used to transmit the second bit sequence.

[0480] Optionally, the processing module 2510 is also used to determine the use of the first basis matrix.

[0481] Optionally, the processing module 2510 is further configured to determine the use of the first base matrix based on one or more of the following: the first length, the service type to which the first bit sequence belongs, the code rate, the capability of the communication device 2500, or the capability of the second communication device communicating with the communication device 2500.

[0482] Optionally, the communication module 2520 is further configured to send first indication information, which is used to indicate the use of a first base matrix, or to indicate the first base matrix.

[0483] Optionally, the communication module 2520 is further configured to receive second indication information, which is used to indicate the use of the first base matrix, or to indicate the first base matrix.

[0484] Optionally, the processing module 2510 is also configured to determine the use of the first base matrix based on the second instruction information.

[0485] A more detailed description of the processing module 2510 and the communication module 2520 can be obtained directly from the relevant description in the method embodiment shown in Figure 9, and will not be repeated here.

[0486] In another possible design, device 2500 can be used to implement the decoding method implemented by the second communication device in the embodiment shown in FIG22. For example, processing module 2510 is used to implement the processing-related steps such as obtaining the parity check matrix and encoding performed by the second communication device in steps 2210 to 2240 of method 2200, and communication module 2520 can be used to implement the sending and / or receiving steps performed by the second communication device in method 2200, such as receiving the second bit sequence, receiving the first indication information, or sending the second indication information.

[0487] For example, the processing module 2510 can be used to: acquire a second bit sequence; obtain a parity check matrix based on a first base matrix; and perform LDPC decoding on the first bit sequence having a first length based on the parity check matrix to obtain a third bit sequence. Optionally, the communication module 2520 can be used to receive the second bit sequence.

[0488] Optionally, the processing module 2510 is also used to determine the use of the first basis matrix.

[0489] Optionally, the processing module 2510 is further configured to determine the use of the first base matrix based on one or more of the following: the first length, the service type to which the first bit sequence belongs, the code rate, the capability of the communication device 2500, or the capability of the second communication device communicating with the communication device 2500.

[0490] Optionally, the communication module 2520 is further configured to receive first indication information, which is used to indicate the use of a first base matrix, or to indicate the first base matrix.

[0491] Optionally, the processing module 2510 is further configured to determine the use of a first base matrix based on the first indication information. Optionally, the communication module 2520 is further configured to send second indication information, which is used to indicate the use of the first base matrix, or to indicate the first base matrix.

[0492] A more detailed description of the processing module 2510 and the communication module 2520 can be obtained directly from the relevant description in the method embodiment shown in Figure 22, and will not be repeated here.

[0493] It should be noted that the communication module can also be called a transceiver module, transceiver unit, transceiver, transceiver device, or transceiver apparatus, etc. The processing module can also be called a processor, processing board, processing unit, or processing apparatus, etc. Optionally, the communication module is used to execute the sending and receiving operations of the first or second communication device in the above method. The device in the communication module that implements the receiving function can be considered as the receiving module, and the device in the communication module that implements the sending function can be considered as the sending module; that is, the communication module can include both a receiving module and a sending module.

[0494] It should also be noted that, in one possible design, the aforementioned processing module and / or communication module can be implemented through virtual modules. For example, the processing module can be implemented through software functional units or virtual devices, and the communication module can be implemented through software functions or virtual devices. In another possible design, the processing module or communication module can also be implemented through physical devices. For example, if the device is implemented using a chip / chip circuit, the communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module can be an integrated processor, a microprocessor, or an integrated circuit.

[0495] The module division in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional modules in the various examples of this embodiment can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0496] Figure 26 is a schematic diagram of the structure of a communication device provided in another embodiment of this application. As shown in Figure 26, the device 2600 includes a processing circuit 2610 and a communication circuit 2620. The processing circuit 2610 and the communication circuit 2620 are coupled to each other.

[0497] It can be understood that the processing circuit 2610 can be one or more processors, or it can be all or part of the processing functions of one or more processors.

[0498] Understandably, the communication circuit 2620 can be a transceiver or an input / output interface.

[0499] Optionally, the device 2600 may further include a memory 2630 for storing instructions executed by the processing circuit 2610, or storing input data required for the running instructions of the processing circuit 2610, or storing data generated after the running instructions of the processing circuit 2610.

[0500] It is understood that the memory 2630 may be located outside the processing circuit 2610, or inside the processing circuit 2610.

[0501] As an example, the processing circuit 2610 is used to implement the functions of the processing module 2510, and the communication circuit 2620 is used to implement the functions of the communication module 2520.

[0502] As an example, device 2600 can be a communication device or a chip used in a communication device.

[0503] When device 2600 is a communication device, the communication circuit can be a transceiver; when device 2600 is a chip, the communication circuit can be an input / output circuit, a bus, pins, or other types of communication interfaces. The input circuit in the input / output circuit can be used for receiving, and the output interface can be used for transmitting.

[0504] In some embodiments of this application, a computer program product is also provided. When the computer program product is run on a processor, it can implement the encoding method implemented by the first communication device or the decoding method implemented by the second communication device in the above method embodiments.

[0505] In some embodiments of this application, a computer-readable storage medium is also provided, which contains computer instructions that, when executed on a processor, can implement the encoding method implemented by the first communication device or the decoding method implemented by the second communication device in the above method embodiments.

[0506] In some embodiments of this application, a communication system is also provided, including the aforementioned first communication device and second communication device. The first communication device can be used to implement the encoding method in the aforementioned method embodiments, and the second communication device can be used to implement the decoding method in the aforementioned method embodiments.

[0507] It is understood that the processor in the embodiments of this application may be any of the following devices or all or part of the circuitry used for processing functions: a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor or any conventional processor.

[0508] The terms “unit”, “module”, etc., used in this specification may be used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution.

[0509] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0510] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0511] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0512] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0513] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0514] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. This computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0515] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. The above descriptions are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

An encoding method, characterized in that, include: Based on the first basis matrix, obtain the parity check matrix; Based on the parity matrix, a first bit sequence of a first length is encoded using low-density parity-check (LDPC) to obtain a second bit sequence. The first base matrix includes a first sub-block, a second sub-block, and a third sub-block; the first sub-block is H. B1sub Or with H B1sub A submatrix having row and / or column transformation relationships, wherein H B1sub satisfy: The H B1sub In the middle, B w B0 is one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; B0 includes columns corresponding to the information bits in the first bit sequence; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates a submatrix related to B0. w Submatrices with all zeros of the same dimension; The second sub-block and the third sub-block are located in the same multiple rows below the first sub-block. The second sub-block is located to the left of the third sub-block, and the last column of the second sub-block does not exceed the last column of the first sub-block. The first column of the third sub-block is continuous with the last column of the first sub-block. The second sub-block includes one or more sub-matrices other than B0 among the W sub-matrices. The third sub-block is a full-rank square matrix, and the third sub-block does not include columns corresponding to information bits in the first bit sequence. The method as described in claim 1, characterized in that, The method is applied to a first communication device, and the method further includes: The first base matrix is ​​determined to be used based on one or more of the following: the first length, the service type to which the first bit sequence belongs, the code rate, the capability of the first communication device, or the capability of the second communication device communicating with the first communication device. The method as described in claim 1 or 2, characterized in that, The method further includes: Send a first indication message, which is used to indicate the use of the first base matrix, or to indicate the first base matrix. The method as described in claim 1, characterized in that, The method further includes: Receive second indication information, which is used to indicate the use of the first base matrix, or to indicate the first base matrix. The method according to any one of claims 1 to 4, characterized in that, The step of performing LDPC encoding on a first bit sequence of a first length based on the parity-check matrix includes: Based on the parity check matrix, the first bit sequence with the first length is LDPC encoded row by row. A decoding method, characterized in that, include: Obtain the second bit sequence; Based on the first basis matrix, obtain the parity check matrix; Based on the parity check matrix, the second bit sequence is subjected to low-density parity check (LDPC) decoding to obtain a third bit sequence with a first length. The first base matrix includes a first sub-block, a second sub-block, and a third sub-block; the first sub-block is H. B1sub Or with H B1sub A submatrix having row and / or column transformation relationships, wherein H B1sub satisfy: The H B1sub In the middle, B w B0 is one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; B0 includes columns corresponding to the information bits in the third bit sequence; the W submatrices are non-zero submatrices of the same dimension, where 0 indicates a submatrix related to B0. w Submatrices with all zeros of the same dimension; The second sub-block and the third sub-block are located in the same multiple rows below the first sub-block. The second sub-block is located to the left of the third sub-block, and the last column of the second sub-block does not exceed the last column of the first sub-block. The first column of the third sub-block is continuous with the last column of the first sub-block. The second sub-block includes one or more sub-matrices other than B0 among the W sub-matrices. The third sub-block is a full-rank square matrix, and the third sub-block does not include columns corresponding to the information bits in the third bit sequence. The method as described in claim 6, characterized in that, The method is applied to a second communication device, wherein determining the use of the first base matrix includes: The first base matrix is ​​determined to be used based on one or more of the following: the first length, the service type to which the first bit sequence belongs, the code rate, the capability of the second communication device, or the capability of the first communication device communicating with the second communication device. The method as described in claim 6 or 7, characterized in that, The method further includes: Send a second indication message, which is used to indicate the use of the first base matrix, or to indicate the first base matrix. The method as described in claim 6, characterized in that, The method further includes: Receive first indication information, which is used to indicate the use of the first base matrix or to indicate the second base matrix. The method as described in any one of claims 6 to 9, characterized in that, The step of performing LDPC decoding on the second bit sequence based on the parity-check matrix includes: Based on the parity-check matrix, the second bit sequence is LDPC decoded using sliding window decoding. The method as described in any one of claims 1 to 10, characterized in that, The first basis matrix satisfies: Among them, [0 0 … 0 B W-1 …B1] is the second sub-block, B T This refers to the third sub-block. The method as described in any one of claims 1 to 11, characterized in that, The third sub-block is: a unit diagonal matrix, or a square matrix with row and / or column transformation relationships to a unit diagonal matrix, or a double diagonal matrix, or a square matrix with row and / or column transformation relationships to a double diagonal matrix, or a lower triangular matrix, or a square matrix with row and / or column transformation relationships to a lower triangular matrix. The method as described in claim 11 or 12, characterized in that, The first length K and the number of columns k corresponding to the information bits in the first bit sequence in B0 sub Satisfy: P×Z×k sub ≥K; P is the number of B0s in the first base matrix, where P is a positive integer greater than or equal to 1; Z is the expansion factor of the parity check matrix, where Z is a positive integer. The method as described in claim 13, characterized in that, The column number k in B0 corresponds to the information bits in the first bit sequence. sub satisfy: The method according to any one of claims 1 to 14, characterized in that, W is a predefined value. The method as described in any one of claims 1 to 15, characterized in that, The value of W is 2. The method as described in any one of claims 1 to 16, characterized in that, The number of B0s in the first sub-block is predefined, configured, or indicated. The method as described in claim 17, characterized in that, The column number k in B0 corresponding to the information bits sub satisfy: Among them, K max K is a predefined threshold value. max Z is a positive integer; Z is the expansion factor of the check matrix, Z is a positive integer; P is the number of B0s in the first sub-block, P is a positive integer greater than 1. The method as described in any one of claims 1 to 18, characterized in that, The number of columns in B0 corresponding to the information bits is predefined, configured, or indicated. The method as described in claim 19, characterized in that, The number P of B0 in the first sub-block satisfies: Where K is the first length, and K is a positive integer; Z is the expansion factor of the verification matrix, and Z is a positive integer; k sub k is the column number in B0 corresponding to the information bit. sub It is a positive integer. The method according to any one of claims 1 to 20, characterized in that, The B0 has a Raptor-like structure. An encoding method, characterized in that, include: Based on the first basis matrix; Obtain the verification matrix; Based on the parity matrix, a first bit sequence of a first length is encoded using low-density parity-check (LDPC) to obtain a second bit sequence. Wherein, the first basis matrix is ​​H B1 Or with H B1 A matrix having row and / or column transformation relationships, wherein H B1 satisfy: The H B1 In the middle, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions. An encoding method, characterized in that, include: Based on the first basis matrix, obtain the parity check matrix; Based on the parity matrix, a first bit sequence of a first length is encoded using low-density parity-check (LDPC) to obtain a second bit sequence. Wherein, the first basis matrix is ​​H B1 Or with H B1 A matrix having row and / or column transformation relationships, wherein H B1 satisfy: The H B1 In the middle, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices having the same dimensions and located at the same level as H B1 The last B W-1 There exists at least one non-zero submatrix among multiple X in one or more identical rows. The method as described in claim 22 or 23, characterized in that, The method is applied to a first communication device, and the method further includes: The first base matrix is ​​determined to be used based on one or more of the following: the first length, the service type to which the first bit sequence belongs, the code rate, the capability of the first communication device, or the capability of the second communication device communicating with the first communication device. The method as described in any one of claims 22 to 24, characterized in that, The method further includes: Send a first indication message, which is used to indicate the use of the first base matrix, or to indicate the first base matrix. The method as described in claim 22 or 23, characterized in that, The method further includes: Receive second indication information, which is used to indicate the use of the first base matrix, or to indicate the first base matrix. The method as described in any one of claims 22 to 26, characterized in that, The step of performing LDPC encoding on a first bit sequence of a first length based on the parity-check matrix includes: Based on the parity check matrix, the first bit sequence with the first length is LDPC encoded row by row. A decoding method, characterized in that, include: Obtain the second bit sequence; Based on the first basis matrix, obtain the parity check matrix; Based on the parity check matrix, the second bit sequence is subjected to low-density parity check (LDPC) decoding to obtain a third bit sequence with a first length. Wherein, the first basis matrix is ​​H B1 Or with H B1 A matrix having row and / or column transformation relationships, wherein H B1 satisfy: The H B1 In the middle, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices with the same dimensions. A decoding method, characterized in that, include: Obtain the second bit sequence; Based on the first basis matrix, obtain the parity check matrix; Based on the parity check matrix, the second bit sequence is subjected to low-density parity check (LDPC) decoding to obtain a third bit sequence with a first length. Wherein, the first basis matrix is ​​H B1 Or with H B1 A matrix having row and / or column transformation relationships, wherein H B1 satisfy: The H B1 In the middle, B w Let be one of W submatrices, where w is a positive integer greater than or equal to 0 and less than W, and W is a positive integer greater than 1; the W submatrices are non-zero submatrices of the same dimension, and 0 indicates that is the same as B. w A submatrix of all zeros with the same dimensions; X represents a submatrix of all zeros with B. w Submatrices having the same dimensions and located at the same level as H B1 The last B W-1 There exists at least one non-zero submatrix among multiple X in one or more identical rows. The method as described in claim 28 or 29, characterized in that, The method is applied to a second communication device, wherein determining the use of the first base matrix includes: The first base matrix is ​​determined to be used based on one or more of the following: the first length, the service type to which the first bit sequence belongs, the code rate, the capability of the second communication device, or the capability of the first communication device communicating with the second communication device. The method as described in any one of claims 28 to 30, characterized in that, The method further includes: Send a second indication message, which is used to indicate the use of the first base matrix, or to indicate the first base matrix. The method as described in claim 28 or 29, characterized in that, The method further includes: Receive first indication information, which is used to indicate the use of the first base matrix or to indicate the second base matrix. The method as described in any one of claims 28 to 32, characterized in that, The step of performing LDPC decoding on the second bit sequence based on the parity-check matrix includes: Based on the parity-check matrix, the second bit sequence is LDPC decoded using sliding window decoding. A communication device, characterized in that, It includes functional modules for implementing the method as described in any one of claims 1 to 33. A communication device, characterized in that, include: One or more processors and communication circuitry, the communication circuitry being used by the communication device to perform at least one of signal input or output; the one or more processors being used to implement the method as described in any one of claims 1 to 33. The apparatus as claimed in claim 35, characterized in that, The communication device is a network device or a terminal device, or a chip used in the network device or the terminal device. A readable storage medium, characterized in that, Used to store programs or instructions, which, when executed, are implemented as described in any one of claims 1 to 33. A program product, characterized in that, Includes a program or instructions, which, when executed, implement the method as described in any one of claims 1 to 33.

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