Photodetection element and electronic apparatus

Abstract

The present technology relates to a photodetection element and an electronic apparatus that make it possible to suppress variations in response time and improve distance measurement accuracy. The present invention comprises a photodetection element which comprises, in order from the light incident surface side, a first photoelectric conversion unit (122) for performing photoelectric conversion, a multiplication region (128) for multiplying carriers by means of a high electric field region, and a second photoelectric conversion unit (121) for performing photoelectric conversion. The multiplication region (128) has a three-layer structure of P-type-N-type-P-type conductivity types or a three-layer structure of N-type-P-type-N-type conductivity types. Alternatively, the multiplication region (128) has a two-layer structure of P-type-N-type conductivity types. The present technology can be applied to a photodetection element included in a distance measurement device that measures the distance to a prescribed object.

Description

Optical detection element, electronic device

[0001] The present technology relates to an optical detection element and an electronic device, and for example, relates to an optical detection element and an electronic device configured to improve ranging accuracy.

[0002] An avalanche photodiode (APD) has a Geiger mode in which it operates at a bias voltage higher than the breakdown voltage and a linear mode in which it operates at a slightly higher bias voltage near the breakdown voltage. The Geiger mode avalanche photodiode is also called a single photon avalanche diode (SPAD).

[0003] An SPAD is a device that can detect one photon per pixel by multiplying carriers generated by photoelectric conversion in a high electric field PN junction region provided for each pixel. (See Patent Document 1)

[0004] Japanese Patent Application Laid-Open No. 2018-088488

[0005] The PN junction region for multiplying carriers is arranged on the surface opposite to the light incident surface side. The distance that electrons photoelectrically converted near the light incident surface move before flowing into the PN junction region becomes long, and there is a possibility that the response time becomes long. The ranging accuracy may decrease due to the increase in the response time.

[0006] The present technology has been made in view of such a situation, and is intended to improve ranging accuracy.

[0007] An optical detection element according to one aspect of the present technology is an optical detection element including, in order from the light incident surface side, a first photoelectric conversion unit that performs photoelectric conversion, a multiplication region that multiplies carriers by a high electric field region, and a second photoelectric conversion unit that performs photoelectric conversion.

[0008] An electronic device according to one aspect of the present technology is an electronic device including an optical detection element including, in order from the light incident surface side, a first photoelectric conversion unit that performs photoelectric conversion, a multiplication region that multiplies carriers by a high electric field region, and a second photoelectric conversion unit that performs photoelectric conversion, and a processing unit that processes a signal from the optical detection element.

[0009] Furthermore, electronic devices may be independent devices or internal blocks that make up a single device.

[0010] This figure shows an example configuration of an imaging device to which this technology is applied. This figure shows an example of the planar configuration of the pixel array and pixels. This figure shows an example of the configuration of SPAD pixels in the first embodiment. This figure shows an example of the cross-sectional configuration of SPAD pixels. This figure shows an example of the planar configuration of SPAD pixels. This figure is for explaining the potential distribution. This figure is for explaining the configuration of the cathode electrode. This figure is for explaining the configuration of the cathode electrode. This figure is for explaining the manufacturing of SPAD pixels. This figure is for explaining the manufacturing of SPAD pixels. This figure shows an example of the configuration of SPAD pixels in the second embodiment. This figure is for explaining the potential distribution. This figure shows an example of the configuration of SPAD pixels in the third embodiment. This figure shows an example of the configuration of SPAD pixels in the fourth embodiment. This figure is for explaining the planar configuration of SPAD pixels. This figure shows an example of the configuration of SPAD pixels in the fifth embodiment. This figure is for explaining the planar configuration of SPAD pixels. This figure shows an example of the configuration of SPAD pixels in the sixth embodiment. This figure is for explaining the arrangement of wiring. This figure is for explaining the arrangement of wiring. This figure is for explaining the planar configuration of SPAD pixels. This figure is for explaining the potential distribution. This is a block diagram showing an example of the schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the external information detection unit and the imaging unit.

[0011] The following describes the embodiments for implementing this technology.

[0012] <Example of Imaging Device Configuration> Figure 1 is a block diagram showing an example configuration of an imaging device to which this technology is applied. Since this technology can be applied to imaging devices as electronic equipment, we will explain it using an imaging device as an example.

[0013] The imaging device 10 is an image sensor that captures incident light from a subject, converts the amount of light of the incident light formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs it as a pixel signal.

[0014] In Figure 1, the imaging device 10 is configured to include a pixel array unit 21, a control circuit 22, and a readout circuit 23.

[0015] The pixel array section 21 arranges multiple SPAD (Single Photon Avalanche Diode) pixels in a two-dimensional (matrix) arrangement. Here, SPAD pixels are pixels containing single-photon avalanche photodiodes (SPADs) and function as photodetectors that detect light. This single-photon avalanche photodiode has a structure in which an avalanche multiplication region is created within the semiconductor so that one photon can be detected, and electrons converted from one photon by photoelectric conversion pass through this region, resulting in a multiplication (amplification) of tens of thousands of electrons.

[0016] The control circuit 22 controls the operation of each part of the imaging device 10. The control circuit 22 controls the driving of multiple SPAD pixels arranged in two dimensions in the pixel array section 21 by outputting drive signals (pulses) to drive the SPAD pixels via pixel drive lines. For example, the control circuit 22 controls the driving of multiple SPAD pixels arranged in two dimensions in the pixel array section 21 based on the illumination detection result.

[0017] The readout circuit 23 sequentially scans a plurality of SPAD pixels arranged in two dimensions in the pixel array section 21 and reads out the pixel signal generated by each SPAD pixel via a signal line. The readout circuit 23 outputs the readout pixel signal to a subsequent signal processing unit (not shown).

[0018] An imaging device 10 having such a configuration can be used as a distance measuring device for measuring the distance to a predetermined object.

[0019] <First Embodiment> As shown in Figure 2, SPAD pixels 41 are arranged in an array on the XY plane in the pixel array section 21. In the following description, the horizontal direction is the X-axis direction and the vertical direction is the Y-axis direction in the figure. SPAD pixels 41 are arranged in the pixel array section 21, and peripheral parts 31 around the pixel array section 21 are arranged, for example, a control circuit 22 and a readout circuit 23.

[0020] Figure 2 shows a magnified view of one SPAD pixel 41, which is one of the pixels arranged in the pixel array section 21. The SPAD pixel 41 is formed, for example, as a square, and is configured such that an inter-pixel separation section 123 is provided between adjacent SPAD pixels 41. The inter-pixel separation sections 123 are arranged in a grid pattern in the pixel array section 21. Anode electrodes 131 are formed at the two corners of the SPAD pixel 41.

[0021] Figure 3 shows an example of the cross-sectional configuration of the SPAD pixel 41 along the line segment A-A' in Figure 2, and Figure 4 shows an example of the cross-sectional configuration of the SPAD pixel 41 along the line segment B-B' in Figure 2. The SPAD pixel 41 shown in Figure 3 has a laminated structure in which a wiring layer 101 and a sensor substrate 102 are stacked. The wiring layer 101 can also be configured to have a logic circuit (not shown) stacked on top of it.

[0022] The sensor substrate 102 is, for example, a semiconductor substrate obtained by thinly slicing single-crystal silicon, in which the concentration of P-type or N-type impurities is controlled, and SPAD pixels 41 are formed on it. In Figure 3, the upper surface of the sensor substrate 102 is used as a light-receiving surface, and a wiring layer 101 is laminated on the surface opposite to the light-receiving surface.

[0023] The wiring layer 101 has wiring formed for supplying voltage to be applied to the SPAD pixel 41, and wiring for extracting carriers (electrons or holes) generated by the SPAD pixel 41 from the sensor substrate 102.

[0024] The SPAD pixel 41 has a configuration that includes a well region 120, a P-type semiconductor region 125, an N-type semiconductor region 127, and a P-type semiconductor region 126 formed on the sensor substrate 102. The N-type semiconductor region 127 is provided approximately in the center of the well region 120 of the SPAD pixel 41, the P-type semiconductor region 125 is provided above the N-type semiconductor region 127 (on the light incident surface side), and the P-type semiconductor region 126 is provided below the N-type semiconductor region 127 (on the wiring layer 101 side).

[0025] A depletion layer formed in the region where the P-type semiconductor region 125 and the N-type semiconductor region 127 connect forms a multiplication region 128-1, and a depletion layer formed in the region where the P-type semiconductor region 126 and the N-type semiconductor region 127 connect forms a multiplication region 128-2. Hereinafter, we will continue the explanation assuming that multiplication regions 128-1 and 128-2 are formed, but it is also possible to treat multiplication regions 128-1 and 128-2 as a single multiplication region.Hereafter, when it is not necessary to distinguish between multiplication regions 128-1 and 128-2 individually, or when multiplication regions 128-1 and 128-2 are treated as a single multiplication region, they will be referred to as multiplication region 128.

[0026] In the SPAD pixel 41 shown in Figure 3, we will continue our explanation using the example where a semiconductor region with conductivity type P-N-P is located approximately in the center of the well region 120. However, this technology can also be applied when the conductivity type is in the order N-P-N.

[0027] The well region 120 is formed by controlling the impurity concentration of the sensor substrate 102 to an n-type, and forms an electric field that transfers electrons (carriers) generated by photoelectric conversion in the SPAD pixel 41 to the multiplication region 128. Alternatively, the well region 120 may be formed as a P-well by controlling the impurity concentration of the sensor substrate 102 to a p-type. Here, we will continue the explanation using the case of a P-well as an example.

[0028] A cathode electrode 129 is formed in the N-type semiconductor region 127, which is connected to wiring in the wiring layer 101 for supplying a negative voltage to form a multiplication region 128. This cathode electrode 129 is connected to wiring 130 formed in the well region 120, and through this wiring 130, it is connected to wiring 112 in the wiring layer 101. Wiring 112 is connected to a power source that supplies a negative voltage (not shown).

[0029] The cathode electrode 129 can be formed in a high-concentration N-type impurity region (N++ contact region) made of polysilicon, and the wiring 130 can be formed as a metal wiring made of metal.

[0030] The multiplication region 128 is a high-electric-field region formed at the interface between the P-type semiconductor region 125 and the N-type semiconductor region 127, and at the interface between the P-type semiconductor region 126 and the N-type semiconductor region 127, by a large negative voltage applied to the N-type semiconductor region 127, and multiplies the electrons (e-) generated by one photon incident on the SPAD pixel 41. Electrons are generated in the upper well region 120 of the multiplication region 128 and in the lower well region 120 of the multiplication region 128, respectively.

[0031] The SPAD pixel 41 shown in Figure 3 has photoelectric conversion units that convert incident light into photoelectric energy, one on the light incident surface side of the multiplication region 128 and the other on the wiring layer 101 side. The photoelectric conversion unit located on the light incident surface side of the SPAD pixel 41, in other words, on the upper side of the multiplication region 128, is referred to as photoelectric conversion unit 122. The photoelectric conversion unit located on the wiring layer 101 side of the SPAD pixel 41, in other words, on the lower side of the multiplication region 128, is referred to as photoelectric conversion unit 121.

[0032] When the photoelectric conversion unit 121 and the photoelectric conversion unit 122 are formed to be approximately the same size, the multiplication region 128, which is formed in the order of P-type-N-type-P-type, is located in the approximate central region of the well region 120. When the photoelectric conversion unit 121 is formed to be larger than the photoelectric conversion unit 122, the multiplication region 128, which is formed in the order of P-type-N-type-P-type, is located in the region above the center of the well region 120. When the photoelectric conversion unit 121 is formed to be smaller than the photoelectric conversion unit 122, the multiplication region 128, which is formed in the order of P-type-N-type-P-type, is located in the region below the center of the well region 120.

[0033] The position of the multiplication region 128 within the well region 120 should be optimally positioned according to the potential gradient within the well region 120, and as described above, the sizes of the photoelectric conversion units 121 and 122 should be set appropriately and optimally. Here, we will continue the explanation using the example of the case where the multiplication region 128 is positioned approximately in the center of the well region 120.

[0034] In the well region 120, a P-type semiconductor region 124 is provided on the side surface of the inter-pixel separation portion 123. The P-type semiconductor region 124 is a P-type diffusion layer formed to surround the outer periphery of the well region 120.

[0035] The P-type semiconductor region 124 functions as a hole storage region. The P-type semiconductor region 124 (hole storage region) is formed in the area where different materials are in contact. In the example shown in Figure 3, the inter-pixel separation region 123 is made of, for example, a silicon oxide film and is a different material from the well region 120, so the P-type semiconductor region 124 is formed to suppress the dark current generated at the interface.

[0036] The P-type semiconductor region 124 is provided with an anode electrode 131 for electrical connection to the anode of the SPAD pixel 41. The P-type semiconductor region 124 is provided in a state where it is electrically connected to the anode electrode 131. The anode electrode 131 is connected to the wiring 111 formed in the wiring layer 101. The anode electrode 131 is a region with a high concentration of P-type impurities (P++ region).

[0037] The sensor substrate 102 is provided with inter-pixel isolation sections 123 formed between adjacent SPAD pixels 41 to separate each SPAD pixel 41. As explained with reference to Figure 2, the inter-pixel isolation sections 123 are arranged in a grid pattern on the pixel array section 21. The inter-pixel isolation sections 123 electrically and optically separate adjacent SPAD pixels 41.

[0038] For example, the inter-pixel isolation section 123 is formed to penetrate from the back surface to the front surface of the sensor substrate 102. The inter-pixel isolation section 123 can also be a double-layered structure consisting of a metal film and an insulating film (see Figure 10, which will be described later). In the case of a double-layered structure consisting of a metal film and an insulating film, the metal film can be a film made of a metal that reflects light (for example, tungsten), and the insulating film can be an insulating film such as SiO2.

[0039] An on-chip lens 103 is formed on the light incident surface side of the well region 120. A fixed charge film 132 is provided between the on-chip lens 103 and the well region 120. The fixed charge film 132 is a P-type impurity region. A P-type diffusion layer 133 is provided between the wiring layer 101 and the well region 120. The P-type diffusion layer 133 is formed by ion implantation. The fixed charge film 132 and the P-type diffusion layer 133 are provided to form a potential between them and the multiplication region 128.

[0040] Figure 4 shows an example of the cross-sectional configuration of the SPAD pixel 41 along the line segment B-B' in Figure 2. In the SPAD pixel 41 along the line segment B-B' in Figure 2, the multiplication region 128 is not formed in this region, and therefore the multiplication region 128 is not formed within the well region 120. The other configurations are the same as the example of the cross-sectional configuration of the SPAD pixel 41 shown in Figure 3.

[0041] Figure 5A shows an example of the planar configuration of the SPAD pixel 41 in the line segment C-C' of Figure 3, and Figure 5B shows an example of the planar configuration of the SPAD pixel 41 in the line segment D-D' of Figure 3. Referring to Figure 5A, a cathode electrode 129 is placed in the central part of the SPAD pixel 41, and an N-type semiconductor region 127 is formed surrounding the cathode electrode 129. A P-type semiconductor region 124 is formed surrounding the N-type semiconductor region 127, and a well region 120 exists between the N-type semiconductor region 127 and the P-type semiconductor region 124.

[0042] Referring to Figure 5B, the SPAD pixel 41 has a well region 120 in its central part, surrounded by a P-type semiconductor region 125, and the P-type semiconductor region 125 is surrounded by an inter-pixel separation region 123.

[0043] Referring to Figure 6, the potential distribution of the well region 120 of a SPAD pixel 41 having two photoelectric conversion units 121 and 122 will be explained. The right side of Figure 6 shows the cross-sectional configuration of the SPAD pixel 41 shown in Figure 3, and the left side of Figure 6 shows a graph representing the potential distribution of the well region 120 of the SPAD pixel 41. In the left side of Figure 6, the horizontal axis represents the potential intensity, and the vertical axis represents the depth of the sensor substrate 102 (silicon substrate).

[0044] In the depth direction from the on-chip lens 103 toward the multiplication region 128 (the direction from the upper side to the center in the graph), the potential distribution is such that the potential increases toward the multiplication region 128. Similarly, in the depth direction from the wiring layer 101 toward the multiplication region 128 (the direction from the lower side to the center in the graph), the potential distribution is such that the potential increases toward the multiplication region 128.

[0045] The potential distribution in the well region 120 is such that the electrons generated by the photoelectric conversion in the photoelectric conversion unit 122 have a potential distribution toward the multiplication region 128, and the electrons generated by the photoelectric conversion in the photoelectric conversion unit 121 also have a potential distribution toward the multiplication region 128. The potential distribution in the well region 120, for the electrons generated in the photoelectric conversion unit 122 provided above the multiplication region 128 and the electrons generated in the photoelectric conversion unit 121 provided below the multiplication region 128, both have a potential distribution toward the multiplication region 128.

[0046] Here, consider a SPAD pixel 41 where the multiplication region 128 is provided on the wiring layer 101 side and only the photoelectric conversion unit 122 exists. When the distance from the electrons generated at a position close to the light incident surface of the photoelectric conversion unit 122 to the multiplication region 128 is defined as distance a, and the distance from the electrons generated at a position close to the multiplication region 128 of the photoelectric conversion unit 122 to the multiplication region 128 is defined as distance b, then distance a > distance b. Due to this difference in distance, the time to reach the multiplication region 128 will be different, and the variation in the arrival time may reduce the ranging accuracy.

[0047] In the SPAD pixel 41 having the potential distribution shown in FIG. 6 and provided with the photoelectric conversion units 121, 121 above and below the multiplication region 128, and when the multiplication region 128 is arranged at the center of the well region 120, the distance from the photoelectric conversion unit 121 to the multiplication region 128 is equal to the distance from the photoelectric conversion unit 122 to the multiplication region 128, and that distance is approximately half the distance compared to the above-mentioned SPAD pixel 41 where the multiplication region 128 is provided on the wiring layer 101 side and only the photoelectric conversion unit 122 exists.

[0048] By shortening the distance to the multiplication region 128, the time it takes for the photoelectrically converted electrons to reach the multiplication region 128 can be shortened. Even if there is variation in the arrival time, the variation is small, and it is possible to suppress a decrease in the ranging accuracy.

[0049] By providing the photoelectric conversion units 121 and 122 above and below the multiplication region 128, it is possible to perform ranging that absorbs the above-described variation in the arrival time while securing the region of the photoelectric conversion unit without reducing the size of the photoelectric conversion unit. Also in this regard, it is possible to suppress a decrease in the ranging accuracy.

[0050] <Configuration of Other SPAD Pixels> Fig. 7 shows another cross-sectional configuration example of the SPAD pixel 41. The basic configuration of the SPAD pixel 41 shown in Fig. 7 is the same as the configuration of the SPAD pixel 41 shown in Fig. 3, but the wiring 130 connecting the cathode electrode 129 and the wiring 112 is formed of polysilicon instead of metal.

[0051] In the SPAD pixel 41 shown in Fig. 7, the cathode electrode 129 formed of polysilicon formed in the multiplication region 128 extends as it is to the wiring layer 101 side and is connected to the wiring 112 in the wiring layer 101. Thus, the cathode electrode 129 may be an ohmic contact composed of polysilicon and metal as shown in Fig. 3, or may be a Schottky contact composed only of polysilicon as shown in Fig. 7.

[0052] As shown in Fig. 8, when the cathode electrode 129 is formed by, for example, solid-phase diffusion, it is formed larger than the cathode electrode 129 of the SPAD pixel 41 shown in Fig. 3. When the cathode electrode 129 is formed by a method such as solid-phase diffusion, ion implantation, or epitaxial growth, since it is formed by diffusion of impurities, the cathode electrode 129 tends to be larger than when formed by other methods. The cathode electrode 129 may be formed by any method.

[0053] As shown in Figure 8, when the cathode electrode 129 is formed by a method of diffusing impurities, the wiring 130 is formed in such a way that it partially penetrates the cathode electrode 129. In this way, various methods can be applied to the joining of the cathode electrode 129 and the wiring 130.

[0054] <Regarding the manufacturing of SPAD pixels 41> Referring to Figures 9 and 10, the manufacturing of the SPAD pixels 41 shown in Figure 3 will be explained.

[0055] In step S11, a sensor substrate 102, for example, a silicon (Si) substrate, is prepared, and a P-type semiconductor region 124 and a P-type semiconductor region 125 are formed by ion implantation of P-type impurities.

[0056] In step S12, an N-type semiconductor region 127 is formed below the P-type semiconductor region 125 by ion implantation of N-type impurities. The anode electrode 131 is formed in the P-type semiconductor region 124 by ion implantation of P-type impurities. The anode electrode 131 (or its contacts) is formed as a high-concentration P-type impurity region (P++ region).

[0057] In step S13, a P-type semiconductor region 126 is formed below the N-type semiconductor region 127 by ion implantation of P-type impurities.

[0058] In step S14, a trench 201 is formed for forming the cathode electrode 129.

[0059] In step S15, N-type impurities are ion-implanted into the N-type semiconductor region 127, where the trench 201 is formed, thereby creating an N++ region with a high concentration of N-type impurities. This N++ region becomes the cathode electrode 129.

[0060] In step S16 (Figure 10), an oxide film 202 for cathode contacts is formed on the side wall inside the trench 201. In step S17, metal is filled into the trench 201 where the oxide film 202 has been formed, thereby forming the wiring 130.

[0061] In step S18, the side of the sensor substrate 102 on which the on-chip lens 103 is provided is polished and flattened by CMP (Chemical Mechanical Polishing) until the P-type semiconductor region 124 is exposed. A wiring layer 101 is also formed on the sensor substrate 102.

[0062] In step S19, a trench 211 is formed in the region that will become the inter-pixel separation portion 123. In step S20, for example, an oxide film 221 is formed in the formed trench 211, and a metal is filled into the formed oxide film 221 to form a metal film 222. After this, the SPAD pixel 41 shown in Figure 3 is manufactured through processes such as the formation of an on-chip lens 103.

[0063] <Second Embodiment> Figure 11 is a diagram showing an example of the cross-sectional configuration of the SPAD pixel 41 in the second embodiment. In the SPAD pixel 41 in the second embodiment shown in Figure 11, the same reference numerals are used for parts that are the same as those in the SPAD pixel 41 in the first embodiment shown in Figure 3 or Figure 8, and their descriptions are omitted as appropriate.

[0064] The SPAD pixel 41 in the second embodiment shown in Figure 11 differs from the SPAD pixel 41 in the first embodiment shown in Figure 3 in that a P-type impurity region 301 is added within the well region 120 of the photoelectric conversion unit 121, but is otherwise the same.

[0065] The photoelectric conversion unit 121 is provided with wiring 130 connected to the cathode electrode 129. Since a predetermined voltage is applied to this wiring 130, the well region 120 near the wiring 130 may be affected by the wiring 130 and a barrier may be generated. This will be explained with reference to Figure 12.

[0066] Figure 12 is a graph, similar to the potential distribution shown in the left diagram of Figure 6, where the vertical axis represents the depth of the sensor substrate 102 and the horizontal axis represents the potential [V]. Of the graphs shown in Figure 12, the solid line represents the ideal graph, while the dotted line represents the graph when a barrier occurs due to the influence of the wiring 130. Referring to the potential distribution shown in Figure 12, there is a place where a barrier occurs and the potential is high, below the multiplication region 128, i.e., in the photoelectric conversion section 121.

[0067] The presence of these areas with high potential (barriers) may hinder the smooth flow of electrons generated in the photoelectric conversion unit 121 to the multiplication region 128. To bring the graph shown in dotted lines closer to the graph shown in solid lines, P-type impurities are locally injected into the areas where barriers may occur to counteract them, thereby creating a P-type impurity region 301.

[0068] In the example shown in Figure 11, a p-type impurity region 301 is provided below the p-type semiconductor region 126 that constitutes the multiplication region 128, and around a part of the wiring 130. By providing the p-type impurity region 301, the influence of the wiring 130 can be reduced, and the generation of a barrier can be suppressed. By providing the p-type impurity region 301 in the photoelectric conversion unit 121, the charge collection efficiency of the photoelectric conversion unit 121 can be improved.

[0069] In Figure 11, an example is shown in which the photoelectric conversion unit 121 is provided with a P-type impurity region 301. However, the P-type impurity region 301 can also be provided in the photoelectric conversion unit 122, or in both the photoelectric conversion unit 121 and the photoelectric conversion unit 122. The P-type impurity region 301 can be provided in at least one of the photoelectric conversion unit 121 and the photoelectric conversion unit 122. By providing the P-type impurity region 301, the potential distribution can be adjusted, and a more appropriate potential distribution can be designed.

[0070] <Third Embodiment> Figure 13 shows an example of a cross-sectional configuration of the SPAD pixel 41 in the third embodiment. In the SPAD pixel 41 in the third embodiment shown in Figure 13, the same reference numerals are used for parts that are the same as those in the SPAD pixel 41 in the first embodiment shown in Figure 3 or Figure 8, and their descriptions are omitted as appropriate.

[0071] The SPAD pixel 41 in the third embodiment shown in Figure 13 differs from the SPAD pixel 41 in the first embodiment shown in Figure 3 in that a P-type impurity wall 311 is added within the well region 120 of the photoelectric conversion unit 121, but is otherwise the same.

[0072] The P-type impurity wall 311 is the side wall of the trench where the wiring 151 is formed, and is formed within the well region 120. The wiring 151 is formed within the trench 201, which is formed during manufacturing, as described with reference to Figure 10. When the trench 201 is formed, a hole is made in the sensor substrate 102 (silicon substrate), which may cause damage to the silicon substrate and disrupt the crystal arrangement.

[0073] If there is a scratch in the silicon substrate, electrons may enter the wiring 130 side through that scratch. To prevent this, for example, a P-type impurity is ion-implanted into the silicon substrate on the wiring 130 side, forming a P-type impurity wall 311. This P-type impurity wall 311 and the P-type semiconductor region 126 that forms the multiplication region 128 are formed so that they do not come into contact with each other.

[0074] By providing P-type impurity walls 311 in areas of the silicon substrate where scratches may be present, the dark frame characteristics can be improved.

[0075] The third embodiment can also be applied in combination with the second embodiment.

[0076] <Fourth Embodiment> Figure 14 shows an example of the cross-sectional configuration of the SPAD pixel 41 in the fourth embodiment. In the SPAD pixel 41 in the fourth embodiment shown in Figure 14, the same reference numerals are used for parts that are the same as those in the SPAD pixel 41 in the first embodiment shown in Figure 3 or Figure 8, and their descriptions are omitted as appropriate.

[0077] The SPAD pixel 41 in the fourth embodiment shown in Figure 14 differs from the SPAD pixel 41 in the first embodiment shown in Figure 8 in that the N-type semiconductor region 127 contains a mixture of regions with high and low concentrations of N-type impurities, but is otherwise similar.

[0078] In the fourth embodiment shown in Figure 14, the N-type semiconductor region 127 of the SPAD pixel 41 is composed of an N-type semiconductor region 127a and an N-type semiconductor region 127b in which the concentration of N-type impurities is higher than that of the N-type semiconductor region 127a. The N-type semiconductor region 127b with a higher concentration of N-type impurities is located in the region between the P-type semiconductor region 125 and the P-type semiconductor region 126.

[0079] A configuration can be provided in which multiplication regions 128-1 and 128-2 are provided between the N-type semiconductor region 127b and the P-type semiconductor region 125, and multiplication regions 128-3 and 128-4 are provided between the N-type semiconductor region 127b and the P-type semiconductor region 126. The number of multiplication regions can be increased by providing an N-type semiconductor region 127b with a high concentration of N-type impurities.

[0080] Figure 15 shows an example of the planar configuration of the SPAD pixel 41 in the line segment A-A' of Figure 14. In the example of the planar configuration of the SPAD pixel 51 shown in A of Figure 15, a cathode electrode 129 is provided in the center, and an N-type semiconductor region 127a is provided surrounding the cathode electrode 129. An N-type semiconductor region 127b is provided surrounding the N-type semiconductor region 127a, and a well region 120 is provided surrounding this N-type semiconductor region 127b. A P-type semiconductor region 124 is provided surrounding the well region 120, and an inter-pixel separation portion 123 is provided surrounding this P-type semiconductor region 124.

[0081] In the example of the planar configuration of the SPAD pixel 41 shown in Figure 15A, the N-type semiconductor region 127a and the N-type semiconductor region 127b are formed in a quadrilateral shape with the same center point.

[0082] Figure 15B shows another example of a planar configuration of the SPAD pixel 41 in the line segment A-A' of Figure 14. In the planar configuration example shown in Figure 15B, N-type semiconductor regions 127b are arranged in a cross shape around the cathode electrode 129 located in the center. Rectangular N-type semiconductor regions 127b are arranged above, below, to the left, and to the right of the cathode electrode 129. An N-type semiconductor region 127a is provided to surround the cathode electrode 129, and N-type semiconductor regions 127b are arranged at four locations within the N-type semiconductor region 127a.

[0083] Figure 15C shows another example of a planar configuration of the SPAD pixel 41 in the line segment A-A' of Figure 14. In the planar configuration example shown in Figure 15C, N-type semiconductor regions 127b are arranged in an X shape around the cathode electrode 129 located in the center. Rectangular N-type semiconductor regions 127b are located at the upper left, upper right, lower left, and lower right of the cathode electrode 129. An N-type semiconductor region 127a is provided to surround the cathode electrode 129, and N-type semiconductor regions 127b are located at the four corners of the N-type semiconductor region 127a.

[0084] In the fourth embodiment, by dividing the multiplication region into multiple parts (by providing multiple multiplication regions), the distance to reach the multiplication region can be further shortened, and the variation in response time can be further reduced. By physically increasing the number of multiplication regions, the variation in characteristics can also be statistically reduced.

[0085] The fourth embodiment can also be applied in combination with the second embodiment and / or the third embodiment.

[0086] <Fifth Embodiment> Figure 16 is a diagram showing an example of the cross-sectional configuration of the SPAD pixel 41 in the fifth embodiment. In the SPAD pixel 41 in the fifth embodiment shown in Figure 16, the same reference numerals are used for parts that are the same as those in the SPAD pixel 41 in the first embodiment shown in Figure 3 or Figure 8, and their descriptions are omitted as appropriate.

[0087] In the first to fourth embodiments described above, the SPAD pixel 41 was explained using the case where there is one cathode electrode 129 as an example. However, it is also possible to have a configuration in which multiple cathode electrodes 129 are provided, as in the SPAD pixel 41 of the fifth embodiment shown in Figure 16.

[0088] The SPAD pixel 41 in the fifth embodiment shown in Figure 16 comprises a cathode electrode 129-1 and a cathode electrode 129-2. The SPAD pixel 41 also comprises a wiring 130-1 for connecting the cathode electrode 129-1 to the wiring formed in the wiring layer 101, and a wiring 130-2 for connecting the cathode electrode 129-2 to the wiring formed in the wiring layer 101. Here, the case where two cathode electrodes 129 are provided is given as an example, but a configuration in which three or more cathode electrodes 129 are provided is also possible.

[0089] Figure 17 shows examples of the planar configuration of the SPAD pixel 41 in line segments A-A' and B-B' of Figure 16. In Figures A to D of Figure 17, the left figure shows an example of the planar configuration of the SPAD pixel 41 in line segment A-A' of Figure 16, mainly showing an example of the arrangement of the cathode electrode 129, and the right figure shows an example of the planar configuration of the SPAD pixel 41 in line segment B-B' of Figure 16, mainly showing an example of the arrangement of the anode electrode 131.

[0090] Figure 17A shows an example in which one cathode electrode 129 and one anode electrode 131 are arranged. The planar configuration example shown in Figure 17A is an example of the arrangement of the cathode electrode 129 and anode electrode 131 that can be applied to the SPAD pixel 41 in the first to fourth embodiments. As shown in the left figure of Figure 17A, when one cathode electrode 129 is provided for one SPAD pixel 41, the cathode electrode 129 can be provided in the center of the SPAD pixel 41. As shown in the right figure of Figure 17A, when one anode electrode 131 is provided for one SPAD pixel 41, the anode electrode 131 can be provided in one corner of the well region 120.

[0091] Figure 17B shows an example where two cathode electrodes 129 and two anode electrodes 131 are arranged. As shown in the left diagram of Figure 17B, when two cathode electrodes 129 are provided in one SPAD pixel 41, the cathode electrodes 129 can be provided at the two corners of the N-type semiconductor region 127 located in the center of the SPAD pixel 41. As shown in the right diagram of Figure 17B, when two anode electrodes 131 are provided in one SPAD pixel 41, the anode electrodes 131 can be provided at the two corners of the well region 120.

[0092] Figure 17C shows an example where four cathode electrodes 129 and four anode electrodes 131 are arranged. As shown in the left diagram of Figure 17C, when four cathode electrodes 129 are provided in one SPAD pixel 41, the cathode electrodes 129 can be provided at each of the four corners of the N-type semiconductor region 127 located in the center of the SPAD pixel 41. As shown in the right diagram of Figure 17C, when four anode electrodes 131 are provided in one SPAD pixel 41, the anode electrodes 131 can be provided at each of the four corners of the well region 120.

[0093] Figure 17D shows another example in which four cathode electrodes 129 and four anode electrodes 131 are arranged. As shown in the left diagram of Figure 17D, when four cathode electrodes 129 are provided in one SPAD pixel 41, the cathode electrodes 129 can be provided at the center of each of the four sides of the N-type semiconductor region 127 located in the center of the SPAD pixel 41. As shown in the right diagram of Figure 17C, when four anode electrodes 131 are provided in one SPAD pixel 41, the cathode electrodes 129 can be provided at the center of each of the four sides of the well region 120.

[0094] The configurations shown in Figure 17A through D may be applied in combination. For example, it is possible to apply the left diagram of Figure 17A to the cathode electrode 129 and the right diagram of Figure 17B to the anode electrode 131. The number of cathode electrodes 129 and anode electrodes 131 do not have to be the same; it is possible to configure them to have different numbers.

[0095] The cathode electrode 129 and the anode electrode 131 do not necessarily have to be in the same relative position; they may be in different relative positions. For example, the cathode electrode 129 can be positioned at one of the four corners, as shown in the left diagram of Figure 17C, while the anode electrode 131 can be positioned in the center of one of the sides, as shown in the right diagram of Figure 17D.

[0096] By providing multiple cathode electrodes 129 and / or anode electrodes 131, if one electrode malfunctions, the other electrodes can compensate. Increasing the number of electrodes makes it possible to take measures against defects in electrodes during manufacturing, for example. By providing multiple electrodes and applying voltage from multiple electrodes, it becomes possible to form a uniform potential within the SPAD pixel 41.

[0097] In addition, there is an embodiment in which the part referred to as the cathode electrode 129 in the above description is replaced with the anode electrode 131, and the part referred to as the anode electrode 131 is replaced with the cathode electrode 129. In this case, the embodiment can be implemented by replacing the cathode electrode 129 with the anode electrode 131 and the anode electrode 131 with the cathode electrode 129.

[0098] The fifth embodiment can also be applied in combination with any one or more of the first to fourth embodiments.

[0099] <Sixth Embodiment> Figure 18 is a diagram showing an example of the cross-sectional configuration of the SPAD pixel 41 in the sixth embodiment. In the SPAD pixel 41 in the sixth embodiment shown in Figure 18, the same reference numerals are used for parts that are the same as those in the SPAD pixel 41 in the first embodiment shown in Figure 3 or Figure 8, and their descriptions are omitted as appropriate.

[0100] In the first to fifth embodiments described above, the SPAD pixel 41 was explained using the case where the photoelectric conversion unit 121 and the photoelectric conversion unit 122 have the same polarity, specifically the case where the polarity is P-type and electrons are generated. However, it is also possible to have a structure in which the photoelectric conversion unit 121 and the photoelectric conversion unit 122 have different polarities, with one generating electrons and the other generating holes.

[0101] The photoelectric conversion unit 121 of the SPAD pixel 41 shown in Figure 18 has N-type polarity and generates holes (carriers). The photoelectric conversion unit 122 of the SPAD pixel 41 shown in Figure 18 has P-type polarity and generates electrons (carriers). This configuration will be explained as an example.

[0102] Figure 18 shows two adjacent SPAD pixels 41-1 and 41-2. Since SPAD pixels 41-1 and 41-2 have similar configurations, the explanation will continue using SPAD pixel 41-1 as an example. In the configuration of SPAD pixel 41-1, parts that are the same as those in SPAD pixel 41 in the first embodiment shown in Figure 3 are denoted by the same reference numerals, and their explanations will be omitted as appropriate.

[0103] The SPAD pixel 41 comprises an N-type semiconductor region 401 with a high concentration of N-type impurities and a P-type semiconductor region 402 with a high concentration of P-type impurities. The N-type semiconductor region 401 and the P-type semiconductor region 402 are stacked to form a multiplication region 410. The lower region of the multiplication region 410 in the figure is designated as the well region 120a, and the upper region of the multiplication region 410 in the figure is designated as the well region 120b. The region including the well region 120a is the photoelectric conversion unit 121, and the region including the well region 120b is the photoelectric conversion unit 122.

[0104] Between the well region 120a and the inter-pixel separation region 123, an N-type semiconductor region 403 is provided in the region surrounding the well region 120a, where N-type impurities are diffused. The N-type semiconductor region 403 and the N-type semiconductor region 401 are formed in a connected state. An N-type fixed charge layer 405 is provided on the wiring layer 101 side of the photoelectric conversion unit 121.

[0105] A P-type semiconductor region 404, in which P-type impurities are diffused, is provided in the region between the well region 120b and the inter-pixel separation region 123, and surrounding the well region 120b. The P-type semiconductor region 404 and the P-type semiconductor region 402 are formed in a connected state. A P-type fixed charge layer 406 is provided on the on-chip lens 103 side of the photoelectric conversion unit 121.

[0106] A cathode electrode 421 (or its contact region) is provided on the wiring layer 101 side of the N-type semiconductor region 403. The cathode electrode 421 is formed as an N++ contact region with a high concentration of N-type impurities. The cathode electrode 421 is connected to the wiring 411 within the wiring layer 101.

[0107] An anode electrode 422 (contact region) is provided on the on-chip lens 103 side of the P-type semiconductor region 404. The anode electrode 422 is formed as a P++ contact region with a high concentration of P-type impurities. The anode electrode 422 is connected to a wiring 423. The wiring 423 connects the anode electrodes 422 of adjacent SPAD pixels 41. The wiring 423 is formed on the inter-pixel separation portion 123.

[0108] Figure 19 shows an example of the planar configuration of the pixel array section 21 and an enlarged view of a part of the pixel array section 21 showing an example of the planar configuration of the SPAD pixels 41. Wiring 423 is formed on the inter-pixel separation section 123. Since the inter-pixel separation section 123 is formed in a grid pattern, the wiring 423 is also formed in a grid pattern. Of the wiring 423, the wiring 423 arranged in the lateral direction in the figure extends to the peripheral section 31 outside the pixel array section 21.

[0109] The wiring 423 provided in the peripheral portion 31 is connected to a supply unit that supplies a predetermined voltage (not shown). Voltage is supplied to the anode electrode 422 from outside the pixel array portion 21. In the example shown in Figure 19, the anode electrode 422 is located at the point where the inter-pixel separation portions 123 intersect, and is provided at the corner of the SPAD pixel 41. When looking at a single SPAD pixel 41, anode electrodes 422 are provided at two diagonally opposite corners. For each SPAD pixel 41, the anode electrodes 422 are located at the locations adjacent to the SPAD pixels 41.

[0110] Figure 20 shows another example of the arrangement of the anode electrodes 422. Figure 20 shows 16 SPAD pixels 41 arranged in a 4x4 grid in the pixel array 21. The anode electrodes 422 are placed for every two SPAD pixels 41. When looking at a single SPAD pixel 41, one anode electrode 422 is provided at one corner.

[0111] If an anode electrode 422 is provided for every two SPAD pixels 41, then the wiring 423 is also arranged for every two SPAD pixels 41. Although not shown in Figure 20, as explained with reference to Figure 19, the wiring 423 extends to the peripheral portion 31 and is connected to a voltage supply unit that supplies voltage in the peripheral portion 31.

[0112] An example of the planar configuration of SPAD pixels 41 in the line segment A-A' of Figure 18 is shown in Figure 21A, an example of the planar configuration of SPAD pixels 41 in the line segment B-B' is shown in Figure 21B, and an example of the planar configuration of SPAD pixels 41 in the line segment C-C' is shown in Figure 21C.

[0113] Referring to Figure 21A, a well region 120b is located in the center, a P-type semiconductor region 402 is provided surrounding the well region 120b, and an inter-pixel separation region 123 is provided surrounding the P-type semiconductor region 402.

[0114] Referring to Figure 21B, a well region 120a is located in the center, an N-type semiconductor region 401 is provided so as to surround the well region 120a, and an inter-pixel separation region 123 is provided so as to surround the N-type semiconductor region 401.

[0115] Referring to C in Figure 21, a well region 120a is located in the center, and an inter-pixel separation section 123 is provided to surround the well region 120a. Cathode electrodes 421 are provided at the two corners of the well region 120a.

[0116] Refer to the potential distribution diagram in Figure 22. The well region 120a of the photoelectric conversion unit 121 of the SPAD pixel 41-1 has a potential distribution such that holes generated by photoelectric conversion are directed toward the multiplication region 410. The well region 120b of the photoelectric conversion unit 122 of the SPAD pixel 41-1 has a potential distribution such that electrons generated by photoelectric conversion are directed toward the multiplication region 410.

[0117] Electrons converted photoelectrically in the photoelectric conversion unit 121 are discharged at the cathode electrode 421, and holes are avalanche multiplied in the multiplication region 410. The electrons generated there are transferred to the cathode electrode 421 and detected. Meanwhile, holes are discharged at the anode electrode 422.

[0118] The holes converted photoelectrically in the photoelectric conversion unit 122 are discharged to the anode electrode 422, and the electrons are avalanche multiplied in the multiplication region 410. The electrons generated there are transferred to the cathode electrode 421 and detected. Meanwhile, the holes are discharged at the anode electrode 422.

[0119] In the sixth embodiment, the SPAD pixel 41 has a multiplication region 410 formed with an N-type-P-type two-layer structure or a P-type-N-type two-layer structure. While the multiplication region 128 in the first to fifth embodiments had a three-layer structure, the multiplication region 410 in the sixth embodiment has a two-layer structure, resulting in a simpler structure and easier design of the potential.

[0120] Since it is not necessary to form the anode electrode and cathode electrode within the same SPAD pixel 41, there are advantages in terms of miniaturization rules and potential design.

[0121] <Examples of application to mobile devices> The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0122] Figure 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0123] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0124] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0125] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0126] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0127] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0128] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0129] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0130] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0131] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0132] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 23, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0133] Figure 24 shows an example of the installation position of the imaging unit 12031.

[0134] In Figure 24, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0135] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0136] Figure 24 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0137] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0138] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0139] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0140] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0141] In this specification, "system" refers to an entire apparatus composed of multiple devices.

[0142] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0143] It should be noted that the embodiments of this technology are not limited to those described above, and various modifications are possible without departing from the spirit of this technology.

[0144] Furthermore, this technology can also take the following configurations: (1) A photodetector comprising, in order from the light incident surface side, a first photoelectric conversion unit that performs photoelectric conversion, a multiplication unit that multiplies carriers by a high electric field region, and a second photoelectric conversion unit that performs photoelectric conversion. (2) The photodetector according to (1), wherein the multiplication unit has a P-type-N-type-P-type three-layer structure or an N-type-P-type-N-type three-layer structure. (3) The photodetector according to (1), wherein the multiplication unit has a P-type-N-type two-layer structure. (4) The photodetector according to any one of (1) to (3), wherein the multiplication unit is provided at a position where the size of the first photoelectric conversion unit and the second photoelectric conversion unit are approximately equal. (5) The photodetector element according to any one of (1) to (4), further comprising: an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region; a wiring layer laminated on the second photoelectric conversion unit; a second wiring connecting the electrode and the first wiring in the wiring layer; and a region of a second conductivity type different from the first conductivity type surrounding a part of the second wiring. (6) The photodetector element according to any one of (1) to (4), further comprising: an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region; and a region of a second conductivity type different from the first conductivity type in at least one of the first photoelectric conversion unit and the second photoelectric conversion unit. (7) The photodetector element according to any one of (1) to (5), further comprising: an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region; a wiring layer laminated on the second photoelectric conversion section; a second wiring connecting the electrode and the first wiring in the wiring layer; and a region of a second conductivity type different from the first conductivity type on the side surrounding the second wiring. (8) The photodetector element according to any one of (1) to (6), further comprising: an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region, wherein the region of the first conductivity type is composed of a first region with a high concentration of the first conductivity type and a second region with a lower concentration of the first conductivity type than the first region. (9) The photodetector element according to (8), wherein the electrode is provided in the first region.(10) A photodetector according to any one of (1) to (9), further comprising a plurality of electrodes for applying a predetermined voltage to the multiplication region. (11) A photodetector according to (3), wherein one of the first photoelectric conversion unit and the second photoelectric conversion unit converts to electrons and the other converts to holes. (12) A photodetector according to (3) or (11), wherein the cathode electrode or anode electrode is connected to wiring provided on an inter-pixel separation unit that separates pixels, and the wiring extends outside the pixel array and is connected to a power source that supplies a predetermined voltage in a region outside the pixel array. (13) An electronic device comprising, in order from the light incident surface side, a first photoelectric conversion unit that performs photoelectric conversion, a multiplication region that multiplies carriers by a high electric field region, a second photoelectric conversion unit that performs photoelectric conversion, and a processing unit that processes signals from the photodetector.

[0145] 10 Imaging device, 21 Pixel array section, 22 Control circuit, 23 Readout circuit, 31 Peripheral section, 41 SPAD pixel, 51 SPAD pixel, 101 Wiring layer, 102 Sensor substrate, 103 On-chip lens, 111 Wiring, 112 Wiring, 120 Well region, 121 Photoelectric conversion section, 122 Photoelectric conversion section, 123 Inter-pixel separation section, 124, 125, 126 P-type semiconductor region, 127 N-type semiconductor region, 128 Multiplication region, 129 Cathode electrode, 130 Wiring, 131 Anode electrode, 132 Fixed charge film, 133 P-type diffusion layer, 151 Wiring, 201 Trench, 202 Oxide film, 211 Trench, 221 Oxide film, 222 Metal film, 301 P-type impurity region, 311 P-type impurity wall, 401 N-type semiconductor region, 402 P-type semiconductor region, 403 N-type semiconductor region, 404 P-type semiconductor region, 405 Fixed charge layer, 406 Fixed charge layer, 410 Multiplication region, 411 Wiring, 421 Cathode electrode, 422 Anode electrode, 423 Wiring

Claims

1. A photodetector comprising, in order from the light incident surface side, a first photoelectric conversion unit that performs photoelectric conversion, a multiplication region that multiplies carriers by a high electric field region, and a second photoelectric conversion unit that performs photoelectric conversion.

2. The photodetector according to claim 1, wherein the multiplication region has a P-type-N-type-P-type three-layer structure or an N-type-P-type-N-type three-layer structure.

3. The photodetector according to claim 1, wherein the multiplication region has a two-layer structure with a P-type conductivity and an N-type conductivity.

4. The photodetector according to claim 1, wherein the multiplication region is provided at a position where the sizes of the first photoelectric conversion unit and the second photoelectric conversion unit are substantially equal.

5. The photodetector element according to claim 1, further comprising: an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region; a wiring layer laminated in the second photoelectric conversion section; a second wiring connecting the electrode and the first wiring in the wiring layer; and a region of a second conductivity type different from the first conductivity type surrounding a part of the second wiring.

6. The photodetector according to claim 1, further comprising: an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region; and a region of a second conductivity type different from the first conductivity type in at least one of the first photoelectric conversion unit and the second photoelectric conversion unit.

7. The photodetector element according to claim 1, further comprising: an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region; a wiring layer laminated in the second photoelectric conversion section; a second wiring connecting the electrode and the first wiring in the wiring layer; and a region of a second conductivity type different from the first conductivity type on the side surface surrounding the second wiring.

8. The photodetector according to claim 1, further comprising an electrode to which a predetermined voltage is applied in a region of a first conductivity type constituting the multiplication region, wherein the region of the first conductivity type is composed of a first region having a high concentration of the first conductivity type and a second region having a lower concentration of the first conductivity type than the first region.

9. The photodetector element according to claim 8, wherein the electrode is provided in the first region.

10. The photodetector according to claim 1, further comprising a plurality of electrodes to which a predetermined voltage is applied in the multiplication region.

11. The photodetector according to claim 3, wherein one of the first photoelectric conversion unit and the second photoelectric conversion unit converts to electrons and the other converts to holes.

12. The photodetector element according to claim 3, wherein the cathode electrode or anode electrode is connected to wiring provided on an inter-pixel separation section that separates pixels, the wiring extends outside the pixel array section and is connected to a power source that supplies a predetermined voltage in the region outside the pixel array section.

13. An electronic device comprising, in order from the light incident surface side, a photodetector element having a first photoelectric conversion unit that performs photoelectric conversion, a multiplication region that multiplies carriers by a high electric field region, and a second photoelectric conversion unit that performs photoelectric conversion, and a processing unit that processes signals from the photodetector element.

Images