Display panel and electronic device including same

Abstract

The electronic device according to the present invention includes: a pixel defining film in which first openings overlapping light emitting areas and second openings overlapping a contact area are defined; a light emitting element including a first electrode of which at least a portion is exposed by the first openings, a second electrode, and a common layer; and a border partition wall which overlaps the contact area and is disposed on the pixel defining film, wherein at least a portion, which overlaps a non-display area, of the first electrode is exposed by the second openings; and the second electrode, in the non-display area, covers the border partition wall and is connected to the first electrode exposed by the second openings.

Description

Display panel and electronic device including the same

[0001] The present invention relates to a display panel and an electronic device including the same, and more specifically, to an electronic device including a display panel with simplified manufacturing processes and improved display quality.

[0002] Generally, electronic devices that provide video to users, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions, include electronic devices for displaying video. The electronic device generates video and provides the generated video to the user through a display screen.

[0003] The electronic device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines.

[0004] Large-sized electronic devices, such as tablets and smart televisions, may experience differences in the driving voltage delivered to each pixel, requiring a design to compensate for this.

[0005] Generally, electronic devices that provide video to users, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions, include electronic devices for displaying video. The electronic device generates video and provides the generated video to the user through a display screen.

[0006] The electronic device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines.

[0007] Large-sized electronic devices, such as tablets and smart televisions, may experience differences in the driving voltage delivered to each pixel, requiring a design to compensate for this.

[0008] An electronic device according to one embodiment comprises: a processor providing image data and a display brightness value; a display panel connected to the processor; and a driving unit that receives the image data and the display brightness value and drives the display panel based on the image data and the display brightness value, wherein the display panel comprises: a base substrate including a display area including light-emitting regions and a non-light-emitting region disposed between the light-emitting regions, and a non-display area including a contact region adjacent to the display area; a pixel defining film disposed on the base substrate having first openings overlapping the light-emitting regions and second openings overlapping the contact region; and a light-emitting element comprising a common layer including a first electrode with at least one portion exposed by the first opening, a second electrode disposed on the first electrode, and a second electrode disposed between the first electrode and the second electrode. A border partition is included that overlaps with the contact area and is disposed on the pixel definition film, and at least a portion of the first electrode that overlaps with the non-display area is exposed by the second openings, and the second electrode covers the border partition in the non-display area and is connected to the first electrode exposed by the second openings.

[0009] The above border barrier may be characterized by including a first insulation pattern disposed on the pixel definition film, a second insulation pattern disposed on the first insulation pattern, a first barrier pattern disposed on the second insulation pattern, and a second barrier pattern disposed on the first barrier pattern.

[0010] The first bulkhead pattern may be characterized by including aluminum, and the second bulkhead pattern may be characterized by including titanium.

[0011] The width of the first bulkhead pattern may be smaller than the width of the second bulkhead pattern, and the thickness of the first bulkhead pattern may be larger than the thickness of the second bulkhead pattern.

[0012] The width of the second insulation pattern may be greater than the width of the second bulkhead pattern.

[0013] The width of the second insulation pattern may be greater than the width of the first insulation pattern.

[0014] It may further include a dummy pattern disposed on the second partition pattern and covered by the second electrode, wherein the dummy pattern comprises the same material as the common layer.

[0015] It may be characterized by further including a protective layer containing an inorganic material disposed between the above dummy pattern and the above second bulkhead pattern.

[0016] The second bulkhead pattern protruding from the first bulkhead pattern may be characterized by defining a downwardly protruding tip portion.

[0017] It may further include a normal barrier disposed on the pixel definition film and overlapping with the above non-luminous region, wherein the normal barrier is covered by the second electrode.

[0018] The shape of the normal bulkhead above may be characterized as being identical to the border bulkhead above.

[0019] The above normal bulkhead and the above border bulkhead may be characterized as having an integral pattern.

[0020] The thickness of the second electrode may be greater than the thickness of the first insulation pattern.

[0021] In the contact area, the second openings may be arranged along a first direction and a second direction that intersect each other, and the border bulkhead may be characterized as not overlapping with the second openings.

[0022] The above border bulkhead may be characterized by including first parts extending along the first direction and spaced apart along the second direction, and second parts disposed between adjacent first parts.

[0023] Each of the above second parts may be characterized by having a stepped shape.

[0024] Each of the above second parts may be characterized by being extended along the above second direction.

[0025] It may be characterized by including a first inorganic layer covering the light-emitting element, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer.

[0026] The display panel may further include a dam portion disposed in a non-display area and surrounding at least a portion of the contact area, and the dam portion may be characterized by including sequentially stacked organic patterns.

[0027] In the above non-display area, the boundary of the organic layer may be characterized by being defined by the dam portion.

[0028] A display panel according to one embodiment comprises: a base substrate including a display area including light-emitting regions and a non-light-emitting region disposed between the light-emitting regions, and a non-display area including a contact region adjacent to the display area; a pixel defining film disposed on the base substrate, wherein first openings overlapping the light-emitting regions and second openings overlapping the contact region are defined; a light-emitting element comprising a common layer including a first electrode with at least one portion exposed by the first opening, a second electrode disposed on the first electrode, and a second electrode disposed between the first electrode and the second electrode; and a border partition disposed on the pixel defining film that overlaps the contact region, wherein at least one portion of the first electrode overlapping the non-display area is exposed by the second openings, and the second electrode covers the border partition in the non-display area and is connected to the first electrode exposed by the second openings.

[0029] The above border barrier may be characterized by including a first insulation pattern disposed on the pixel definition film, a second insulation pattern disposed on the first insulation pattern, a first barrier pattern disposed on the second insulation pattern, and a second barrier pattern disposed on the first barrier pattern.

[0030] The first bulkhead pattern may be characterized by including aluminum, and the second bulkhead pattern may be characterized by including titanium.

[0031] The width of the first bulkhead pattern may be smaller than the width of the second bulkhead pattern, and the thickness of the first bulkhead pattern may be larger than the thickness of the second bulkhead pattern.

[0032] The width of the second insulation pattern may be greater than the width of the second bulkhead pattern.

[0033] The width of the second insulation pattern may be greater than the width of the first insulation pattern.

[0034] It may further include a dummy pattern disposed on the second partition pattern and covered by the second electrode, wherein the dummy pattern comprises the same material as the common layer.

[0035] It may be characterized by further including a protective layer containing an inorganic material disposed between the above dummy pattern and the above second bulkhead pattern.

[0036] The second bulkhead pattern protruding from the first bulkhead pattern may be characterized by defining a downwardly protruding tip portion.

[0037] It may further include a normal barrier disposed on the pixel defining film and overlapping with the above non-luminous region, wherein the normal barrier is covered by the second electrode.

[0038] According to an embodiment of the present invention, the electronic device can provide an electronic device with simplified manufacturing processes and costs as electrodes are interconnected through a partition in a non-display area. Additionally, the reliability of the display panel can be improved as the electrode covering the partition, which includes different metal layers, has the effect of reducing resistance.

[0039] FIG. 1a is a block diagram of an electronic device according to one embodiment of the present invention.

[0040] FIG. 1b is a schematic diagram of an electronic device according to various embodiments of the present invention.

[0041] FIG. 1c is a perspective view of an electronic device according to one embodiment of the present invention.

[0042] FIG. 2 is a cross-sectional view of an electronic device according to one embodiment of the present invention.

[0043] FIG. 3 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0044] FIG. 4a is a block diagram of a display module according to one embodiment of the present invention.

[0045] Figure 4b is an equivalent circuit of any one of the pixels shown in Figure 4a.

[0046] FIG. 5a is a plan view of a pixel unit according to one embodiment of the present invention.

[0047] FIG. 5b is a plan view of a pixel according to one embodiment of the present invention.

[0048] Figure 6 is a cross-sectional view taken along I-I' of Figure 5a.

[0049] Figure 7 is a cross-sectional view taken along II-II' of Figure 5a.

[0050] FIG. 8 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0051] FIG. 9a is a cross-sectional view of a contact area of ​​a display panel according to one embodiment of the present invention.

[0052] FIG. 9b is a cross-sectional view of a contact area of ​​a display panel according to one embodiment of the present invention.

[0053] Figure 10 is a cross-sectional view taken along III-III' of Figure 9a.

[0054] FIG. 11 is a cross-sectional view of a contact area of ​​a display panel according to one embodiment of the present invention.

[0055] FIG. 12 is a cross-sectional view of a contact area of ​​a display panel according to one embodiment of the present invention.

[0056] FIG. 13 is a cross-sectional view of a contact area of ​​a display panel according to one embodiment of the present invention.

[0057] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0058] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0059] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0060] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0061] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0063] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0064] FIG. 1a is a block diagram of an electronic device according to an embodiment of the present invention. Referring to FIG. 1a, an electronic device (10) according to an embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0065] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0066] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (15), a video data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output video information through a display screen.

[0067] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0068] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0069] FIG. 1b is a schematic diagram of an electronic device according to various embodiments.

[0070] Referring to FIG. 1b, various electronic devices to which a display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0071] The display device according to the embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device described above and may further include a module or device having other additional functions in addition to the display device.

[0072] FIG. 1c is a perspective view of an electronic device according to an embodiment of the present invention. The electronic device described in FIG. 1a and FIG. 1b can be applied to the electronic device (DD) described in FIG. 1c. For example, the smartphone (10_1a) described in FIG. 1b can correspond to the electronic device (DD) of FIG. 1c.

[0073] Referring to FIG. 1c, an electronic device (DD) according to an embodiment of the present invention may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). The corners of the electronic device (DD) connecting the long sides and the short sides may have a curved shape. The corners of the electronic device (DD) having a curved shape may be defined as round corners. The shape of such an electronic device (DD) may be defined as a round corner rectangle. However, this is merely one example of the shape of an electronic device (DD) and is not limited to a round corner rectangle.

[0074] Hereinafter, the direction that intersects substantially perpendicularly with the plane defined by the first direction (DR1) and the second direction (DR2) is defined as the third direction (DR3). Additionally, in this specification, the meaning of "when viewed on a plane" is defined as the state viewed from the third direction (DR3).

[0075] The front surface of the electronic device (DD) can be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (DD) can be provided to the user through the display surface (DS).

[0076] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) displays images (IM), and the non-display area (NDA) may not display images (IM). The non-display area (NDA) surrounds the display area (DA) and may define the border of an electronic device (DD) that is printed in a predetermined color.

[0077] The display area (DA) may have a rounded corner rectangle shape depending on the shape of the electronic device (DD). For example, the display area (DA) may include rectangular sides extending in a first direction (DR1) and a second direction (DR2), and rounded corners connecting the sides. Among the four sides, the sides extending in the first direction (DR1) may be defined as long sides, and among the four sides, the sides extending in the second direction (DR2) may be defined as short sides.

[0078] The electronic device (DD) can detect inputs applied from outside the electronic device (DD). For example, the electronic device (DD) can detect a first input by a touch pen (PEN) and a second input by touch (TC). The touch pen (PEN) can be defined as an input device.

[0079] The touch pen (PEN) may be an active pen that outputs a signal. The second input by touch (TC) may include various forms of external inputs, such as parts of the user's body, light, heat, or pressure.

[0080] The electronic device (DD) and the touch pen (PEN) can communicate bidirectionally. The electronic device (DD) can provide an uplink signal to the touch pen (PEN). For example, the uplink signal may include information such as panel information and protocol version, but is not specifically limited thereto.

[0081] The touch pen (PEN) can provide a downlink signal to the electronic device (DD). The downlink signal may include a synchronization signal or status information of the touch pen (PEN). For example, the downlink signal may include coordinate information of the touch pen (PEN), battery information of the touch pen (PEN), tilt information of the touch pen (PEN), and / or various information stored in the touch pen (PEN), but is not particularly limited thereto.

[0082] The electronic device (DD) can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Additionally, the electronic device (DD) can be used in small and medium-sized electronic devices such as personal computers, laptop computers, personal digital terminals, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented merely as exemplary embodiments, and the electronic device (DD) can be used in other electronic devices without departing from the concept of the invention.

[0083] FIG. 2 is a cross-sectional view of an electronic device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0084] FIG. 2 is a drawing illustrating an exemplary cross-section of the electronic device illustrated in FIG. 1c. FIG. 2 illustrates an exemplary cross-section of the electronic device (DD) viewed from a second direction (DR2). FIG. 2 omits some of the components of the electronic device (DD) described in FIG. 1c.

[0085] Referring to FIG. 2, the electronic device (DD) may include a display panel (DP), an input sensor (ISP), an anti-reflective layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2).

[0086] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0087] The input sensor (ISP) may be placed on the display panel (DP). The input sensor (ISP) may include a plurality of sensing units (not shown) for sensing external input in a capacitive manner. The input sensor (ISP) may be manufactured directly on the display panel (DP) during the manufacture of the electronic device (DD). Therefore, the input sensor (ISP) according to one embodiment may be placed directly on the display panel (DP). However, not limited thereto, the input sensor (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) by an adhesive layer.

[0088] The anti-reflective layer (RPL) can be placed on the input sensor (ISP). The anti-reflective layer (RPL) can be manufactured directly on the input sensor (ISP) during the manufacture of the electronic device (DD). However, it is not limited thereto, and the anti-reflective layer (RPL) can be manufactured as a separate panel and attached to the input sensor (ISP) by an adhesive layer.

[0089] The anti-reflective layer (RPL) can be defined as an external light anti-reflective film. The anti-reflective layer (RPL) can reduce the reflectivity of external light incident from the electronic device (DD) toward the display panel (DP). External light may not be visible to the user due to the anti-reflective layer (RPL).

[0090] When external light traveling toward the display panel (DP) is reflected from the display panel (DP) and provided back to an external user, the user may perceive the external light as if through a mirror. To prevent this phenomenon, for example, the anti-reflection layer (RPL) may include a plurality of color filters that display the same color as the pixels of the display panel (DP).

[0091] Color filters can filter external light to the same color as the pixels. In this case, external light may not be visible to the user. However, not limited thereto, the anti-reflective layer (RPL) may include a phase retarder and / or polarizer to reduce the reflectivity of external light.

[0092] The window (WIN) can be placed on the anti-reflective layer (RPL). The window (WIN) can protect the display panel (DP), input sensor (ISP), and anti-reflective layer (RPL) from external scratches and impacts.

[0093] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may protect the lower part of the display panel (DP). The panel protection film (PPF) may include a flexible plastic material such as polyethyleneterephthalate (PET).

[0094] A first adhesive layer (AL1) is placed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded together by the first adhesive layer (AL1). A second adhesive layer (AL2) is placed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded together by the second adhesive layer (AL2).

[0095] FIG. 3 is a drawing illustrating an exemplary cross-section of the display panel shown in FIG. 2. For example, FIG. 3 shows a cross-section of the display panel (DP) viewed from a second direction (DR2).

[0096] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0097] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) around the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide. A display element layer (DP-OLED) may be placed on the display area (DA).

[0098] Multiple pixels may be disposed in the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor disposed in the circuit element layer (DP-CL) and a light-emitting element (OLED) disposed in the display element layer (DP-OLED) and connected to the transistor.

[0099] A thin film encapsulation layer (TFE) can be placed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) can protect the pixels from moisture, oxygen, and external foreign substances.

[0100] A thin film encapsulation layer (TFE) can be disposed on a light-emitting device (OLED) to cover the light-emitting device (OLED). The thin film encapsulation layer (TFE) may include a first inorganic layer (LIL) disposed on pixels (PXij, see FIG. 4b), a second inorganic layer (UIL) disposed on the first inorganic layer (LIL), and an organic layer (OL) disposed between the first and second inorganic layers (LIL, UIL).

[0101] The first and second inorganic layers (LIL, UIL) contain inorganic materials and can protect the pixels from moisture / oxygen. The organic layer (OL) contains organic materials and can protect the pixels (PXij, see FIG. 4b) from foreign substances such as dust particles. The organic layer (OL) can be formed through solution processes such as spin coating, slit coating, and inkjet processes.

[0102] FIG. 4a is a block diagram of a display module according to an embodiment of the present invention. FIG. 4b is an equivalent circuit of any one of the pixels shown in FIG. 4a.

[0103] Referring to FIG. 4a, the display module (DM) may include a display panel (DP), a timing controller (TC), a scan driver (SDV), a data driver (DDV), a light emission driver (EDV), and a voltage generator (VG). The display module (DM) corresponds to the display module (11) described in FIG. 1a, and the display panel (DP) corresponds to the display panel (DP) described in FIG. 2 and FIG. 3.

[0104] The display panel (DP) may include a plurality of scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm), a plurality of light-emitting lines (EML1~EMLm), a plurality of data lines (DL1~DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0105] Pixels (PX) can be electrically connected to scanning lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm), light emission lines (EML1~EMLm), and data lines (DL1~DLn), respectively. Each pixel (PX) can be electrically connected to four corresponding scanning lines, one corresponding data line, and one corresponding light emission line.

[0106] The scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm) may include a plurality of initialization scan lines (GIL1~GILm), a plurality of compensation scan lines (GCL1~GCLm), a plurality of write scan lines (GWL1~GWLm), and a plurality of bias scan lines (GBL1~GBLm).

[0107] Each pixel (PX) can be connected to a corresponding one of the initialization scan lines (GIL1~GILm), a corresponding one of the compensation scan lines (GCL1~GCLm), a corresponding one of the write scan lines (GWL1~GWLm), and a corresponding one of the bias scan lines (GBL1~GBLm).

[0108] Scan lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm) are connected to a scanning driver (SDV) and extend in a first direction (DR1) and can be arranged in a second direction (DR2). Light emission lines (EML1~EMLm) are connected to a light emission driver (EDV) and extend in a first direction (DR1) and can be arranged in a second direction (DR2). Data lines (DL1~DLn) are connected to a data driver (DDV) and extend in a second direction (DR2) and can be arranged in a first direction (DR1).

[0109] The scanning driver (SDV), the light-emitting driver (EDV), and the data driver (DDV) can be substantially placed on the display panel (DP), and this configuration will be illustrated below in FIG. 8.

[0110] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to match the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0111] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0112] The scanning driver (SDV) can receive a scanning control signal (SCS) from the timing controller (TC). In response to the scanning control signal (SCS), the scanning driver (SDV) can output scanning signals to the scanning lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm). The scanning signals can be applied to pixels (PX) through the scanning lines (GIL1~GILm, GCL1~GCLm, GWL1~GWLm, GBL1~GBLm).

[0113] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from the timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to pixels (PX) through data lines (DL1 to DLn).

[0114] The light-emitting driver (EDV) can receive a light-emitting control signal (ECS) from the timing controller (TC). The light-emitting driver (EDV) can output light-emitting signals to the light-emitting lines (EML1 to EMLm) in response to the light-emitting control signal (ECS). The light-emitting signals can be applied to pixels (PX) through the light-emitting lines (EML1 to EMLm).

[0115] Pixels (PX) can receive data voltages corresponding to data signals provided by a data driver (DDV) in response to scanning signals. Pixels (PX) can display an image by emitting light of a brightness corresponding to the data voltages in response to light emission signals.

[0116] FIG. 4b is a diagram illustrating the equivalent circuit of any one of the pixels shown in FIG. 4a.

[0117] For example, FIG. 4b shows a pixel (PXij) connected to the j-th data line (DLj), the i-th scan lines (GWLi, GCLi, GILi, GBLi), and the i-th emission line (EMLi). i and j are natural numbers.

[0118] Referring to FIG. 4b, a pixel (PXij) may include a pixel circuit (PC) and a light-emitting element (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) can drive the light-emitting element (OLED).

[0119] The pixel circuit (PC) may include a plurality of transistors (T1 to T8) and a capacitor (CST). The transistors (T1 to T8) and the capacitor (CST) can control the amount of current flowing to the light-emitting element (OLED). The light-emitting element (OLED) can generate light having a predetermined brightness according to the amount of current provided.

[0120] The i-th write scan line (GWLi) can receive the i-th write scan signal (GWi), and the i-th compensation scan line (GCLi) can receive the i-th compensation scan signal (GCi). The i-th initialization scan line (GILi) can receive the i-th initialization scan signal (GIi), and the i-th bias scan line (GBLi) can receive the i-th bias scan signal (GBi). The i-th emission line (EMLi) can receive the i-th emission signal (EMi).

[0121] The pixel (PXij) can be connected to the j-th data line (DLj), the i-th write scan line (GWLi), the i-th compensation scan line (GCLi), the i-th initialization scan line (GILi), the i-th bias scan line (GBLi), the i-th light emission line (EMLi), the first initialization line (VIL1), the second initialization line (VIL2), the bias line (VBL), and the first and second power lines (PL1, PL2).

[0122] The first initialization line (VIL1) can receive the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The bias line (VBL) can receive the bias voltage (VBIAS). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0123] The transistors (T1 to T8) may each include a source electrode, a drain electrode, and a gate electrode. Hereinafter, for convenience in FIG. 4b, either the source electrode or the drain electrode is defined as the first electrode and the other as the second electrode. Additionally, the gate electrode is defined as the control electrode.

[0124] The transistors (T1 to T8) may include the first to eighth transistors (T1 to T8). The first, second, and fifth to eighth transistors (T1, T2, T5 to T8) may be PMOS transistors. The third and fourth transistors (T3, T4) may be NMOS transistors.

[0125] The first transistor (T1) can be defined as a driving transistor, and the second transistor (T2) can be defined as a switching transistor. The third transistor (T3) can be defined as a compensation transistor. The fourth transistor (T4) and the seventh transistor (T7) can be defined as initialization transistors. The fifth transistor (T5) and the sixth transistor (T6) can be defined as light emission control transistors. The eighth transistor (T8) can be defined as a bias transistor.

[0126] A light-emitting element (OLED) can be defined as an organic light-emitting element. The light-emitting element (OLED) may include a first electrode (AE) and a second electrode (CE). The first electrode (AE) may receive a first driving voltage (ELVDD) through the sixth, first, and fifth transistors (T6, T1, T5). The first driving voltage (ELVDD) may be applied to a pixel circuit (PC) through a first power line (PL1).

[0127] The second electrode (CE) can receive a second driving voltage (ELVSS) having a level lower than the first driving voltage (ELVDD). The second driving voltage (ELVSS) can be applied to the pixel circuit (PC) through the second power line (PL2).

[0128] The first transistor (T1) is positioned between the fifth transistor (T5) and the sixth transistor (T6) and can be connected to the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to the first power line (PL1) through the fifth transistor (T5) and to the first electrode (AE) through the sixth transistor (T6).

[0129] The first transistor (T1) may include a first electrode connected to the first power line (PL1) through the fifth transistor (T5), a second electrode connected to the first electrode (AE) through the sixth transistor (T6), and a control electrode connected to the first node (N1).

[0130] The first electrode of the first transistor (T1) can be connected to the fifth transistor (T5), and the second electrode of the first transistor (T1) can be connected to the sixth transistor (T6). The first transistor (T1) can control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the first node (N1) applied to the control electrode of the first transistor (T1).

[0131] The second transistor (T2) may be positioned between the first transistor (T1) and the j-th data line (DLj) and connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a first electrode connected to the j-th data line (DLj), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th write scan line (GWLi).

[0132] The second transistor (T2) can be turned on by the i-th write scan signal (GWi) applied through the i-th write scan line (GWLi) to electrically connect the j-th data line (DLj) and the first electrode of the first transistor (T1). The second transistor (T2) can perform a switching operation to provide the data voltage (VD) (corresponding to the aforementioned data signal) applied through the j-th data line (DLj) to the first electrode of the first transistor (T1).

[0133] The third transistor (T3) can be connected to the second electrode of the first transistor (T1) and the first node (N1). The third transistor (T3) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first node (N1), and a control electrode connected to the i-th compensation scan line (GCLi).

[0134] The third transistor (T3) can be turned on by the i-th compensation scan signal (GCi) applied through the i-th compensation scan line (GCLi) to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in the form of a diode.

[0135] The fourth transistor (T4) may be connected to the first node (N1). The fourth transistor (T4) may include a first electrode connected to the first node (N1), a second electrode connected to the first initialization line (VIL1), and a control electrode connected to the i-th initialization scan line (GILi). The fourth transistor (T4) may be turned on by the i-th initialization scan signal (GIi) applied through the i-th initialization scan line (GILi) to provide the first initialization voltage (VINT) applied through the first initialization line (VIL1) to the first node (N1).

[0136] The fifth transistor (T5) may include a first electrode connected to the first power line (PL1), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th light-emitting line (EMLi).

[0137] The sixth transistor (T6) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first electrode (AE), and a control electrode connected to the i-th light-emitting line (EMLi).

[0138] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the i-th light emission signal (EMi) applied through the i-th light emission line (EMLi). By turning on the fifth transistor (T5) and the sixth transistor (T6), a first driving voltage (ELVDD) is provided to the light-emitting element (OLED), and a driving current can flow through the light-emitting element (OLED). Thus, the light-emitting element (OLED) can emit light.

[0139] The seventh transistor (T7) may include a first electrode connected to the first electrode (AE), a second electrode connected to the second initialization line (VIL2), and a control electrode connected to the i-th bias scan line (GBLi). The seventh transistor (T7) may be turned on by the i-th bias scan signal (GBi) applied through the i-th bias scan line (GBLi) to provide the second initialization voltage (VAINT) received through the second initialization line (VIL2) to the first electrode (AE) of the light-emitting element (OLED).

[0140] In an embodiment of the present invention, the second initialization voltage (VAINT) may have a different level from the first initialization voltage (VINT), but is not limited thereto and may have the same level as the first initialization voltage (VINT).

[0141] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) can be discharged. Therefore, when black luminance is implemented, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and accordingly, the black expression capability can be improved.

[0142] The capacitor (CST) may include a first electrode connected to the first power line (PL1) and a second electrode connected to the first node (N1). When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing through the first transistor (T1) can be determined according to the voltage stored in the capacitor (CST).

[0143] The eighth transistor (T8) may include a first electrode connected to the bias line (VBL), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th bias scan line (GBLi).

[0144] The eighth transistor (T8) is turned on by the i-th bias scan signal (GBi) and can provide a bias voltage (VBIAS) applied through the bias line (VBL) to the first electrode of the first transistor (T1). However, the transistors included in the pixel (PXij) are not limited to this.

[0145] FIG. 5a is a plan view of a pixel unit according to one embodiment of the present invention. FIG. 5b is a plan view of a pixel according to one embodiment of the present invention.

[0146] Referring to FIG. 5a, in this embodiment, one pixel unit (PXU) may include the pixels described in FIG. 4a and 4b. A plurality of pixel units (PXU) may be provided and arranged along the first and second diagonal directions (CDR1, CDR2) within the display area (DA) described in FIG. 1c.

[0147] A pixel unit (PXU) according to one embodiment may include first-1 to third pixels (PXA-G1, PX-G2, PX-R, PX-B). The first-1 pixel (PX-G1) may provide green light. Light generated from the first pixel (PX-G1) may be provided to a display area (DA, see FIG. 1c) through a first-1 light-emitting region (PXA-G1). In this embodiment, the first-1 light-emitting region (PXA-G1) may be rhombus-shaped.

[0148] The first-2 pixel (PX-G2) can provide green light similar to the first-1 pixel (PX-G1). The light generated from the first-2 pixel (PX-G2) can be provided to the display area (DA, see FIG. 1c) through the first-2 light-emitting region (PXA-G2). The first-2 light-emitting region (PXA-G2) can be spaced apart from the first-1 light-emitting region (PXA-G1) along the first direction (DR1). In this embodiment, the first-2 light-emitting region (PXA-G2) may be rhombus-shaped.

[0149] The second pixel (PX-R) can provide red light. The light generated from the second pixel (PX-R) can be provided to the display area (DA, see FIG. 1c) through the second light-emitting region (PXA-R). The second light-emitting region (PXA-R) can be spaced apart from the third light-emitting region (PXA-B) along the second direction (DR2). The second light-emitting region (PXA-R) can be spaced apart from the first-1 light-emitting region (PXA-G1) along the first diagonal direction (CDR1) and spaced apart from the first-2 light-emitting region (PXA-G2) along the second diagonal direction (CDR2). In this embodiment, the second light-emitting region (PXA-R) may be rhombus-shaped.

[0150] The third pixel (PX-B) can provide blue light. The light generated from the third pixel (PX-B) can be provided to the display area (DA, see FIG. 1c) through the third light-emitting region (PXA-B). The third light-emitting region (PXA-B) may be spaced apart from the first-second light-emitting region (PXA-G2) along the first diagonal direction (CDR1) and spaced apart from the first-first light-emitting region (PXA-G1) along the first diagonal direction (CDR1). In this embodiment, the third light-emitting region (PXA-B) may be rhombus-shaped.

[0151] According to one embodiment, the area of ​​the second light-emitting region (PXA-R) may be larger than the area of ​​the first-1 and first-2 light-emitting regions (PXA-G1, PXA-G1) and smaller than the area of ​​the third light-emitting region (PXA-B).

[0152] The region between the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B) can be defined as a non-light-emitting region (NPXA).

[0153] A display panel (DP, see FIG. 3) of an electronic device (DD) according to the present invention may include a partition (WL). A portion of the partition (WL) may be placed in a non-luminous area (NPXA) within a display area (DA, see FIG. 3). Another portion of the partition (WL) may be placed in a non-display area (NDA, see FIG. 3). The partition (WL) placed in the non-display area (NDA, see FIG. 3) will be described later.

[0154] The partition (WL) placed in the non-luminous region (NPXA) may surround at least a portion of the first to third luminous regions (PXA-G1, PXA-G2, PXA-R, PXA-B). That is, the partition (WL) placed in the non-luminous region (NPXA) may surround the entire area or have a shape with a portion open, and is not limited to any one embodiment.

[0155] Referring to FIG. 5b, in this embodiment, one pixel unit (PXU-a) may include the pixels described in FIG. 4a and 4b. A plurality of pixel units (PXU-a) may be provided and arranged along the first and second directions (DR1, DR2) within the display area (DA) described in FIG. 1c.

[0156] A pixel unit (PXU-a) according to one embodiment may include first to third pixels (PX-R, PX-G, PX-B). The first pixel (PX-R) may provide red light. Light generated from the first pixel (PX-R) may be provided to a display area (DA, see FIG. 1c) through a first light-emitting region (PXA-R). In this embodiment, the first light-emitting region (PXA-R) may have a round-cornered square shape.

[0157] The second pixel (PX-B) can provide blue light. Light generated from the second pixel (PX-B) can be provided to the display area (DA, see FIG. 1c) through the second light-emitting region (PXA-B). The second light-emitting region (PXA-B) may be spaced apart from the first light-emitting region (PXA-R) along the first direction (DR1). When viewed from the second direction (DR2), the second light-emitting region (PXA-B) may overlap with the first and third light-emitting regions (PXA-R, PXA-G). The second light-emitting region (PXA-B) may be a round-cornered rectangular shape extending along the second direction (DR2).

[0158] The third pixel (PX-G) can provide green light. The light generated from the third pixel (PX-G) can be provided to the display area (DA, see FIG. 1c) through the third light-emitting region (PXA-G). The third light-emitting region (PXA-G) can be spaced apart from the first light-emitting region (PXA-R) along the second direction (DR2). The third light-emitting region (PXA-G) may have a round-cornered square shape.

[0159] According to one embodiment, the area of ​​the first light-emitting region (PXA-R) may be larger than the area of ​​the third light-emitting region (PXA-G) and smaller than the area of ​​the second light-emitting region (PXA-B).

[0160] The region between the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) can be defined as a non-light-emitting region (NPXA).

[0161] A display panel (DP, see FIG. 3) of an electronic device (DD) according to the present invention may include a partition (WL). A portion of the partition (WL) may be placed in a non-luminous area (NPXA) within a display area (DA, see FIG. 3). Another portion of the partition (WL) may be placed in a non-display area (NDA, see FIG. 3). The partition (WL) placed in the non-display area (NDA, see FIG. 3) will be described later.

[0162] FIG. 6 is a cross-sectional view taken along I-I' of FIG. 5a. FIG. 7 is a cross-sectional view taken along II-II' of FIG. 5a.

[0163] FIG. 6 illustrates a cross-sectional view of the first pixel (PX-R) in FIG. 5a. Referring to FIG. 3, 4a, 4b, and 6, a light-emitting element (OLED) according to one embodiment may include a first electrode (AE), a second electrode (CE), and a first common layer (CL). The first common layer (CL) may include a hole control layer, an electron control layer, and a light-emitting layer, etc.

[0164] A second electrode (CE) may be disposed on a first electrode (AE), and a common layer (CL) may be disposed between the first electrode (AE) and the second electrode (CE). A light-emitting element (OLED) according to one embodiment may further include a protective layer disposed on the second electrode (CE). The protective layer comprises an organic material and can prevent damage to components disposed beneath the protective layer during a subsequent process. According to one embodiment, the protective layer may be omitted.

[0165] The first, fourth, and sixth transistors (T1, T4, T6) and the light-emitting element (OLED) may be disposed on a substrate (SUB). The display area (DA) may include a second light-emitting area (PXA) corresponding to a pixel (PXij, see FIG. 4b) and a non-light-emitting area (NPXA) adjacent to the second light-emitting area (PXA).

[0166] The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE) may be disposed on the substrate (SUB). The circuit element layer (DP-CL) may be disposed on the substrate (SUB). The circuit element layer (DP-CL) may include insulating layers and conductive patterns. The display element layer (DP-OLED) may include a light-emitting element (OLED) and a pixel definition film (PDL).

[0167] A barrier layer (BRL) can be disposed on a substrate (SUB). The barrier layer (BRL) can increase the bonding strength between the semiconductor pattern included in the transistors and the substrate (SUB). The barrier layer (BRL) may include an inorganic material.

[0168] A metal layer (BML) may be disposed on the barrier layer (BRL). The metal layer (BML) may be superimposed on the first transistor (T1). According to one embodiment, the metal layer (BML) may receive a positive voltage. When a positive voltage is applied to the metal layer (BML), the threshold voltage (Vth) value of the first transistor (T1) disposed on the metal layer (BML) may be maintained without changing.

[0169] The metal layer (BML) can block light incident on the first transistor (T1) from the bottom of the metal layer (BML). The metal layer (BML) may include a reflective metal. According to one embodiment, the metal layer (BML) may be omitted.

[0170] The buffer layer (BFL) is placed on the barrier layer (BRL) and can cover the metal layer (BML). The buffer layer (BFL) may include an inorganic material.

[0171] Semiconductor layers (S1, A1, D1) of the first transistor (T1) and semiconductor layers (S6, A6, D6) of the sixth transistor (T6) may be disposed on the buffer layer (BFL). The semiconductor layers (S1, A1, D1, S6, A6, D6) may comprise polysilicon. However, not limited thereto, the semiconductor layers (S1, A1, D1, S6, A6, D6) may comprise amorphous silicon.

[0172] The semiconductor layers (S1, A1, D1, S6, A6, D6) may be doped with an N-type dopant or a P-type dopant. The semiconductor layers (S1, A1, D1, S6, A6, D6) may include a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than that of the low-doping region and may substantially serve as the source electrode and drain electrode of the first and sixth transistors (T1, T6). The low-doping region may substantially correspond to the active (or channel) of the first and sixth transistors (T1, T6).

[0173] The first source region (S1), the first channel region (A1), and the first drain region (D1) of the first transistor (T1) may be formed from semiconductor layers (S1, A1, D1). The sixth source region (S6), the sixth channel region (A6), and the sixth drain region (D6) of the sixth transistor (T6) may be formed from semiconductor layers (S6, A6, D6). The first channel region (A1) may be positioned between the first source region (S1) and the first drain region (D1). The sixth channel region (A6) may be positioned between the sixth source region (S6) and the sixth drain region (D6).

[0174] A first insulating layer (INS1) may be disposed on a buffer layer (BFL) to cover semiconductor layers (S1, A1, D1, S6, A6, D6). A first gate electrode (G1, or control electrode) of a first transistor (T1) and a sixth gate electrode (G6, or control electrode) of a sixth transistor (T6) may be disposed on the first insulating layer (INS1). When viewed in a planar view, the first gate electrode (G1) may overlap the first channel region (A1), and the sixth gate electrode (G6) may overlap the sixth channel region (A6).

[0175] Although not illustrated, the structure of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors (T2, T5, T7) may be substantially the same as that of the first and sixth transistors (T1, T6).

[0176] A second insulating layer (INS2) may be disposed on a first insulating layer (INS1) to cover the first and sixth gate electrodes (G1, G6). A dummy electrode (DME) may be disposed on the second insulating layer (INS2). The dummy electrode (DME) is disposed on the first gate electrode (G1) and may overlap the first gate electrode (G1) when viewed in a planar view. The dummy electrode (DME) may form the aforementioned capacitor together with the first gate electrode (G1).

[0177] A third insulating layer (INS3) may be disposed on a second insulating layer (INS2) to cover a dummy electrode (DME). A semiconductor layer (S4, A4, D4) of a fourth transistor (T4) may be disposed on the third insulating layer (INS3). The semiconductor layer (S4, A4, D4) may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0178] The semiconductor layer (S4, A4, D4) may include multiple regions distinguished by whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, reduced region) may have greater conductivity than the region where it is not reduced (hereinafter, non-reduced region). The reduced region may substantially serve as the source electrode or drain electrode of the fourth transistor (T4). The non-reduced region may substantially correspond to the active (or channel) of the fourth transistor (T4).

[0179] The fourth source region (S4), the fourth channel region (A4), and the fourth drain region (D4) of the fourth transistor (T4) may be formed from semiconductor layers (S4, A4, D4). The fourth channel region (A4) may be positioned between the fourth source region (S4) and the fourth drain region (D4).

[0180] A fourth insulating layer (INS4) may be disposed on a third insulating layer (INS3) to cover the semiconductor layer (S4, A4, D4). A fourth gate electrode (G4) of a fourth transistor (T4) may be disposed on the fourth insulating layer (INS4). When viewed in a planar view, the fourth gate electrode (G4) may overlap with the fourth channel region (A4).

[0181] A fifth insulating layer (INS5) may be disposed on the fourth insulating layer (INS4) to cover the fourth gate electrode (G4). Although not illustrated, the structure of the source region, channel region, drain region, and gate electrode of the third transistor (T3) may be substantially the same as that of the fourth transistor (T4).

[0182] The barrier layer (BRL), buffer layer (BFL), and first to fifth insulating layers (INS1 to INS5) may comprise inorganic materials. For example, the barrier layer (BRL), buffer layer (BFL), and first to fifth insulating layers (INS1 to INS5) may comprise either silicon oxide or silicon nitride, or one insulating layer may comprise multiple inorganic layers, and is not limited to any specific embodiment. The multiple inorganic layers may have a structure in which layers comprising silicon nitride and silicon oxide are alternately stacked.

[0183] A connecting electrode (CNE) may be disposed between the sixth transistor (T6) and the light-emitting element (OLED). The connecting electrode (CNE) may electrically connect the sixth transistor (T6) and the light-emitting element (OLED). The connecting electrode (CNE) may include a first connecting electrode (CNE1) and a second connecting electrode (CNE2) disposed on the first connecting electrode (CNE1).

[0184] A first connecting electrode (CNE1) is disposed on a fifth insulating layer (INS5) and can be connected to a sixth drain region (D6) through a first contact hole (CH1) defined in the first to fifth insulating layers (INS1~INS5). A sixth insulating layer (INS6) can be disposed on the fifth insulating layer (INS5) to cover the first connecting electrode (CNE1).

[0185] The second connecting electrode (CNE2) may be disposed on the sixth insulating layer (INS6). The second connecting electrode (CNE2) may be connected to the first connecting electrode (CNE1) through a second contact hole (CH2) defined in the sixth insulating layer (INS6).

[0186] A seventh insulating layer (INS7) may be disposed on a sixth insulating layer (INS6) to cover the second connecting electrode (CNE2) and the first power line (ES). The sixth and seventh insulating layers (INS6, INS7) may include an organic material.

[0187] A pixel defining film (PDL) may be disposed on a seventh insulating layer (INS7, the insulating layer between claims). A first opening (PDL-OP1) that exposes at least a portion of the first electrode (AE) may be defined in the pixel defining film (PDL). In this embodiment, the pixel defining film (PDL) may include an organic material. Additionally, the pixel defining film (PDL) may have a predetermined color and is not limited to any one embodiment.

[0188] A common layer (CL) and a second electrode (CE) included in the light-emitting element (OLED) can be disposed on the pixel definition film (PDL).

[0189] A thin film encapsulation layer (TFE) can be disposed on a light-emitting element (OLED) to cover the light-emitting element (OLED). The thin film encapsulation layer (TFE) can be disposed over the entire area of ​​a display area (DA). It may include inorganic films and an organic film disposed between the inorganic films, and is not limited to any one embodiment.

[0190] FIG. 7 shows a cross-sectional view of a normal barrier (WA-N) placed in a non-luminous region (NPXA). The barrier (WL) described in FIG. 5a may include a normal barrier (WA-N) and a border barrier (WA-C, see FIG. 8). The normal barrier (WA-N) is placed in the non-luminous region (NPXA) of the display region (DA), and the border barrier (WA-C, see FIG. 8) may be placed in the contact region (CA, see FIG. 8) of the non-display region (NDA, see FIG. 8).

[0191] Referring to FIG. 7, a normal barrier (WA-N) may be placed in a non-luminous region (NPXA) of a display area (DA). The normal barrier (WA-N) may include a first insulation pattern (IN1), a second insulation pattern (IN2), a first barrier pattern (W1), and a second barrier pattern (W2).

[0192] A first insulating pattern (IN1) may be disposed on a pixel defining film (PDL). The first insulating pattern (IN1) may include an inorganic material. A second insulating pattern (IN2) may be disposed on the first insulating pattern (IN1). The second insulating pattern (IN2) may include an inorganic material different from that of the first insulating pattern (IN1).

[0193] For example, the first insulation pattern (IN1) may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and the second insulation pattern (IN2) may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0194] In this embodiment, the first insulation pattern (IN1) may be configured to disconnect the P-type hole injection layer among the layers included in the common layer (CL-G1). Accordingly, the thickness of the first insulation pattern (IN1) may be thicker than the thickness of the P-type hole injection layer among the layers included in the common layer (CL-G1).

[0195] According to one embodiment, the width of the second insulating pattern (IN2) in cross-section may be greater than the width of the first insulating pattern (IN1). The difference in width may be formed due to the difference in etching rates with respect to the etching solution between the first insulating pattern (IN1) and the second insulating pattern (IN2).

[0196] According to one embodiment, a step difference may be formed between the portion of the second insulation pattern (IN2) that overlaps with the first partition pattern (W1) and the portion of the second insulation pattern (IN2) that does not overlap with the first partition pattern (W1). Accordingly, the thickness of the portion of the second insulation pattern (IN2) that overlaps with the first partition pattern (W1) may be greater than the thickness of the portion of the second insulation pattern (IN2) that does not overlap with the first partition pattern (W1).

[0197] Common layers (CL-G1, CL-B) included in different pixels (PXij, see FIG. 4B) are disconnected from each other with a partition (WL) in between by a first insulation pattern (IN1) and a second insulation pattern (IN2), and the disconnected common layers (CL-G1, CL-B) may come into contact with the sides of the first insulation pattern (IN1) and the second insulation pattern (IN2). However, this is not limited thereto, and the disconnected common layers (CL-G1, CL-B) may come into contact with the side (N1-S) of the first partition pattern (W1), and is not limited to any one embodiment.

[0198] A first barrier pattern (W1) is placed on a second insulation pattern (IN2). The first barrier pattern (W1) may include a metal. For example, the first barrier pattern (W1) may include aluminum. As the first barrier pattern (W1) includes aluminum, the side (N1-S) of the first barrier pattern (W1) may be oxidized and not conductive. Therefore, the side (N1-S) of the first barrier pattern (W1) may include an insulating region (N1-O).

[0199] A second bulkhead pattern (W2) may be placed on a first bulkhead pattern (W1). The second bulkhead pattern (W2) may include a metal different from that of the first bulkhead pattern (W1). For example, the second bulkhead pattern (W2) may include titanium.

[0200] According to the present embodiment, the thickness of the first partition pattern (W1) may be greater than the thickness of the second partition pattern (W2), and the width of the first partition pattern (W1) may be smaller than the width of the second partition pattern (W2). According to one embodiment, a portion of the second partition pattern (W2) may protrude from the first partition pattern (W1) and be exposed from the first partition pattern (W1).

[0201] Accordingly, the lower surface (N2-B) of the second barrier pattern (W2) may be exposed from the first barrier pattern (W1). This may be formed due to the difference in etching rates with respect to the etching solution between the first barrier pattern (W1) and the second barrier pattern (W2). The first barrier pattern (W1) and the second barrier pattern (W2) may be defined as having a tip structure.

[0202] According to one embodiment, the width of the second insulation pattern (IN2) may be equal to or greater than the width of the second partition pattern (W2), and is not limited to any one embodiment.

[0203] The second electrode (CE) can extend from the second light-emitting region (PXA-R) shown in FIG. 6 to the non-light-emitting region (NPXA) to cover the normal barrier (WA-N). The second electrode (CE) overlapping with the normal barrier (WA-N) can come into contact with the side (N1-S) of the first barrier pattern (W1), the lower surface (N2-B) of the second barrier pattern (W2) exposed from the first barrier pattern (W1), and the side (N2-S) of the second barrier pattern (W2).

[0204] According to one embodiment, the second electrode (CE) may include indium zinc oxide. The second electrode (CE) may be formed through a sputtering process.

[0205] As described above, since the side (N1-S) of the first bulkhead pattern (W1) includes an oxidized non-conductive region (N1-O), a portion of the second electrode (CE) covering the normal bulkhead (WA-N) can be connected to another portion of the second electrode (CE) through the lower surface (N2-B) of the second bulkhead pattern (W2) exposed from the first bulkhead pattern (W1) and the inner portion of the first bulkhead pattern (W1). The same description can be applied to the border bulkhead (WA-C).

[0206] According to one embodiment, the first thickness (TH1) of the second electrode (CE) disposed on the common layer (CL-G1, CL-B) may be greater than the second thickness (TH2) of the second electrode (CE) surrounding the normal partition (WA-N). The second thickness (TH2) may have a thickness of 20% to 25% relative to the first thickness (TH1).

[0207] A dummy pattern (CL-P) may be placed on the second partition pattern (W2). The dummy pattern (CL-P) may be covered by the second electrode (CE). For example, the dummy pattern (CL-P) may be entirely covered by the second electrode (CE). The dummy pattern (CL-P) is formed by the same process as the common layer (CL-G1, CL-B) and may contain the same material as the common layer (CL-G1, CL-B). The common layer (CL-G1, CL-B) may be disconnected on the second partition pattern (W2) by the tip structure of the partition (WL), and the disconnected portion of the common layer (CL-G1, CL-B) may be defined as the common layer (CL-G1, CL-B).

[0208] According to the present invention, by bringing a normal partition (WA-N) comprising different metal layers within a display area (DA) into contact with a second electrode (CE), the resistance of the second electrode (CE) can be reduced.

[0209] FIG. 8 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 8 is a cross-sectional view of a portion of the display panel (DP) that overlaps with a non-display area (NDA). Among the configurations described in FIG. 6, the barrier layer (BRL) disposed on the base substrate (SUB) to the fifth insulating layer (INS5) is briefly illustrated as an "insulating layer (INS)." At least one of the barrier layer (BRL) to the fifth insulating layer (INS5) may be omitted from the insulating layer (INS), and the embodiment is not limited to any one of the embodiments.

[0210] The display panel (DP) may include first and second dam sections (DMP-1, DMP-2) positioned at the outer edge of the non-display area (NDA). The first dam section (DMP-1) may be positioned adjacent to the display area (DA, see FIG. 6) relative to the second dam section (DMP-2). The first dam section (DMP-1) and the second dam section (DMP-2) may be positioned in the non-display area (NDA) to surround at least a portion of the contact area (CA).

[0211] Each of the first dam section (DMP-1) and the second dam section (DMP-2) may include dam patterns in which organic layers are stacked. Each of the dam patterns may include the same material as the layer containing organic material among the insulating layers described in FIG. 6.

[0212] The first dam portion (DMP-1) may include first to third dam patterns (D-1, D-2, D-3) sequentially stacked on an insulating layer (INS). The second dam portion (DMP-2) may include first to fourth dam patterns (D-1, D-2, D-3, D-4) sequentially stacked on an insulating layer (INS). The first to third dam patterns (D-1, D-2, D-3) may include the same material as the sixth insulating layer (INS6), the seventh insulating layer (INS7), and the pixel defining film (PDL). The fourth dam pattern (D-4) may include a material corresponding to a spacer that is placed on the pixel defining film (PDL) and serves as a support during the deposition process.

[0213] At least one of the first dam portion (DMP-1) and the second dam portion (DMP-2) can define the boundary of the organic layer (OL) in the non-display area (NDA). During the process of forming the organic layer (OL) through a solution process such as spin coating, slit coating, or inkjet process, the height of the first dam portion (DMP-1) can prevent the solution from overflowing.

[0214] According to the present invention, a non-display area (NDA) of a display panel (DP) may include a contact area (CA). The contact area (CA) may be defined as an area where a second electrode (CE) and a first electrode (AE), which are commonly disposed on a light-emitting element (OLED), come into contact.

[0215] A barrier (WL) may be disposed in the contact area (CA). More specifically, a border barrier (WA-C) included in the barrier (WL) may be disposed. The barrier (WL) may be disposed on the pixel defining film (PDL). In the contact area (CA), the pixel defining film (PDL) may have a second opening (PDL-OP2) that exposes at least a portion of the first electrode (AE). That is, the pixel defining film (PDL) may have first openings (PDL-OP1, see FIG. 6) that overlap with the first electrode (AE) included in each light-emitting element (OLED), and second openings (PDL-OP2) that expose portions of the first electrode (AE) disposed in a pattern in the non-display area (NDA).

[0216] FIG. 9a is a cross-sectional view of a contact area of ​​a display panel according to an embodiment of the present invention. FIG. 9b is a cross-sectional view of a contact area of ​​a display panel according to an embodiment of the present invention. FIG. 9a and FIG. 9b illustrate a shape in which border partitions (WA-C, WA-Ca) are arranged in a planar configuration.

[0217] Referring to FIG. 9a, the border partition (WA-C) may include first portions (WU) and second portions (WS). The first portions (WU) and second portions (WS) may be placed on the pixel definition film (PDL) and spaced apart from the second opening (PDL-OP2). The first portions (WU) and second portions (WS) are substantially one pattern, but for convenience of explanation, they will be described separately.

[0218] Each of the first parts (WU) may extend along the second direction (DR2) and be spaced apart along the first direction (DR1). Second parts (WS) may be placed between the first parts (WU). The first part (WU) closest to the display area (DA, see FIG. 6) among the first parts (WU) may be connected to a normal bulkhead (WA-N, see FIG. 7) extending from the display area (DA, see FIG. 6). Thus, the normal bulkhead (WA-N, see FIG. 7) may be in a pattern that is integral with the border bulkhead (WA-C).

[0219] According to the present embodiment, each of the second parts (WS) may have a stepped shape. The second parts (WS) may be spaced apart along the second direction (DR2) between two adjacent first parts (WU) along the first direction (DR1).

[0220] Referring to FIG. 9b, the border partition (WA-Ca) may include first portions (WU) and second portions (WS). The first portions (WU) and second portions (WS) may be placed on the pixel definition film (PDL) and spaced apart from the second opening (PDL-OP2). The first portions (WU) and second portions (WS) are substantially one pattern, but for convenience of explanation, they will be described separately.

[0221] Each of the first parts (WU) may extend along the second direction (DR2) and be spaced apart along the first direction (DR1). The second parts (WS) may be positioned between the first parts (WU).

[0222] According to the present embodiment, each of the second parts (WS) extends along the first direction (DR1) and can be spaced apart along the second direction (DR2) between two adjacent first parts (WU) along the first direction (DR1).

[0223] Figure 10 is a cross-sectional view taken along III-III' of Figure 9a.

[0224] Referring to FIG. 10, a border barrier (WA-C) may be disposed on a pixel defining film (PLD) in a contact area (CA). The border barrier (WA-C) may include the same layer structure as the normal barrier (WA-N) described in FIG. 7. The border barrier (WA-C) may include a first insulation pattern (IN1), a second insulation pattern (IN2), a first barrier pattern (W1), and a second barrier pattern (W2).

[0225] A first insulating pattern (IN1) may be disposed on a pixel defining film (PDL). The first insulating pattern (IN1) may include an inorganic material. A second insulating pattern (IN2) may be disposed on the first insulating pattern (IN1). The second insulating pattern (IN2) may include an inorganic material different from that of the first insulating pattern (IN1).

[0226] For example, the first insulation pattern (IN1) may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and the second insulation pattern (IN2) may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0227] In this embodiment, the first insulation pattern (IN1) may be configured to disconnect the P-type hole injection layer among the layers included in the common layer (CL-G1). Accordingly, the thickness of the first insulation pattern (IN1) may be thicker than the thickness of the P-type hole injection layer among the layers included in the common layer (CL-G1).

[0228] According to one embodiment, the width of the second insulating pattern (IN2) in cross-section may be greater than the width of the first insulating pattern (IN1). The difference in width may be formed due to the difference in etching rates with respect to the etching solution between the first insulating pattern (IN1) and the second insulating pattern (IN2).

[0229] According to one embodiment, the thickness of the second electrode (CE) may be greater than the thickness of the first insulation pattern (IN1). Therefore, even if the second electrode (CE) covers the border partition (WA-C), it may not be disconnected by the first insulation pattern (IN1).

[0230] According to one embodiment, a step difference may be formed in the portion of the second insulation pattern (IN2) that overlaps with the first partition pattern (W1) and in the portion of the second insulation pattern (IN2) that does not overlap with the first partition pattern (W1).

[0231] A first barrier pattern (W1) is placed on a second insulation pattern (IN2). The first barrier pattern (W1) may include a metal. For example, the first barrier pattern (W1) may include aluminum. As the first barrier pattern (W1) includes aluminum, the side (C1-S) of the first barrier pattern (W1) may be oxidized and not conductive. Therefore, the side (C1-S) of the first barrier pattern (W1) may include an insulating region (C1-O).

[0232] A second bulkhead pattern (W2) may be placed on a first bulkhead pattern (W1). The second bulkhead pattern (W2) may include a metal different from that of the first bulkhead pattern (W1). For example, the second bulkhead pattern (W2) may include titanium.

[0233] According to the present embodiment, the thickness of the first partition pattern (W1) may be greater than the thickness of the second partition pattern (W2), and the width of the first partition pattern (W1) may be smaller than the width of the second partition pattern (W2). According to one embodiment, a portion of the second partition pattern (W2) may protrude from the first partition pattern (W1) and be exposed from the first partition pattern (W1).

[0234] Accordingly, the lower surface (N2-B) of the second barrier pattern (W2) may be exposed from the first barrier pattern (W1). This may be formed due to the difference in etching rates with respect to the etching solution between the first barrier pattern (W1) and the second barrier pattern (W2). The first barrier pattern (W1) and the second barrier pattern (W2) may be defined as having a tip structure.

[0235] According to one embodiment, the width of the second insulation pattern (IN2) may be equal to or greater than the width of the second partition pattern (W2), and is not limited to any one embodiment.

[0236] A dummy pattern (CL-P) may be placed on the second partition pattern (W2). The dummy pattern (CL-P) may be covered by the second electrode (CE). For example, the dummy pattern (CL-P) may be entirely covered by the second electrode (CE). The dummy pattern (CL-P) is formed by the same process as the common layer (CL-G1, CL-B, see FIG. 7) and may contain the same material as the common layer (CL-G1, CL-B, see FIG. 7).

[0237] The insulation patterns and bulkhead patterns included in the normal bulkhead (WA-N) include the same material as the insulation patterns and bulkhead patterns included in the border bulkhead (WA-C) and can be patterned and formed by the same process.

[0238] The second electrode (CE) can be connected to the first electrode (AE) in the contact area (CA) of the non-display area (NDA). The second electrode (CE) is commonly placed in the light-emitting elements (OLED) described in FIG. 6 and can extend from the display area (DA) to the non-display area (NDA).

[0239] A second opening (PDL-OP2) that exposes a portion of the first electrode (AE) may be defined in the pixel defining film (PDL) overlapping with the contact area (CA). A second electrode (CE) extending into the non-display area (NDA) may cover the pixel defining film (PDL) and be connected to the first electrode (AE). A portion of the second electrode (CE) may cover a border barrier (WA-C) disposed on the pixel defining film (PDL).

[0240] In the contact region (CA), the second electrode (CE) can reduce the resistance of the second electrode (CE) by covering the border barrier (WA-C) which includes different metal layers.

[0241] According to the present invention, within the non-display area (NDA), the second electrode (CE) can be contacted with the first electrode (AE) through the border barrier (WA-C) with reduced resistance. Thus, a separate mask process for connecting the second electrode (CE) and the second power line (PL2, see FIG. 4b) through the normal barrier (WA-N) within the display area (DA) can be omitted. Thus, an electronic device (DD) with simplified manufacturing processes and costs can be provided.

[0242] FIG. 11 is a cross-sectional view of a contact area of ​​a display panel according to an embodiment of the present invention. FIG. 12 is a cross-sectional view of a contact area of ​​a display panel according to an embodiment of the present invention. FIG. 13 is a cross-sectional view of a contact area of ​​a display panel according to an embodiment of the present invention. Identical or similar reference numerals are used for configurations identical or similar to those described in FIG. 10, and redundant descriptions are omitted.

[0243] Referring to FIG. 11, a display panel (DP-1) according to one embodiment may include a border barrier (WA-C1) disposed in a contact area (CA) of a non-display area (NDA). The border barrier (WA-C1) may be disposed on a pixel defining film (PDL). The border barrier (WA-C1) may include a first insulating pattern (IN1) disposed on the pixel defining film (PDL), a second insulating pattern (IN2) disposed on the first insulating pattern (IN1), a first barrier pattern (W1) disposed on the second insulating pattern (IN2), and a second barrier pattern (W2) disposed on the first barrier pattern (W1).

[0244] According to the present embodiment, the first width (WD1) of the second insulation pattern (IN2) may be larger than the second width (WD2) of the second barrier pattern (W2). Accordingly, the side (I2-S) of the second insulation pattern (IN2) may protrude outward from the border barrier (WA-C) more than the side (C2-S) of the second barrier pattern (W2). The shape of the normal barrier (WA-N, see FIG. 7) may be the same as the shape of the border barrier (WA-C). Accordingly, when forming the common layer (CL-G1, CL-B, see FIG. 7), the thickness of the light-emitting layer included in the common layer (CL-G1, CL-B, see FIG. 7) can be secured, and the P-type hole injection layer included in the common layer (CL-G1, CL-B, see FIG. 7) can be easily disconnected.

[0245] Referring to FIG. 12, a display panel (DP-2) according to one embodiment may include a border barrier (WA-C2) disposed in a contact area (CA) of a non-display area (NDA). The border barrier (WA-C2) may be disposed on a pixel defining film (PDL). The border barrier (WA-C2) may include a first insulating pattern (IN1) disposed on the pixel defining film (PDL), a second insulating pattern (IN2) disposed on the first insulating pattern (IN1), a first barrier pattern (W1) disposed on the second insulating pattern (IN2), and a second barrier pattern (W2) disposed on the first barrier pattern (W1).

[0246] The border bulkhead (WA-C2) according to the present embodiment may further include a protective layer (PL). The protective layer (PL) may be placed on the second bulkhead pattern (W2) and covered by a dummy pattern (CL-P). The protective layer (PL) may be placed on the upper surface of the second bulkhead pattern (W2). The protective layer (PL) may be placed on the second bulkhead pattern (W2) to prevent the second bulkhead pattern (W2) from being damaged in a subsequent process.

[0247] The protective layer (PL) may include an inorganic material. For example, the protective layer (PL) may include at least one of silicon nitride and silicon oxide.

[0248] According to the present embodiment, a border bulkhead (WL-C2) having a robust tip structure can be provided as a protective layer (PL) is disposed on the second bulkhead pattern (W2). The normal bulkhead (WA-N) described in FIG. 7 may further include a protective layer (PL) as the border bulkhead (WL-C2).

[0249] Referring to FIG. 13, a display panel (DP-3) according to one embodiment may include a border barrier (WA-C3) disposed in a contact area (CA) of a non-display area (NDA). The border barrier (WA-C3) may be disposed on a pixel defining film (PDL). The border barrier (WA-C3) may include a first insulating pattern (IN1) disposed on the pixel defining film (PDL), a second insulating pattern (IN2) disposed on the first insulating pattern (IN1), a first barrier pattern (W1) disposed on the second insulating pattern (IN2), and a second barrier pattern (W2) disposed on the first barrier pattern (W1).

[0250] In this embodiment, a portion of the second bulkhead pattern (W2) exposed from the first bulkhead pattern (W1) may include a tip portion (TIP) bent downward. The normal bulkhead (WA-N) described in FIG. 7 may include the same tip portion (TIP) as the border bulkhead (WL-C2). Accordingly, according to this embodiment, as the second bulkhead pattern (W2) includes a tip portion (TIP), the common layer (CL-G1, CL-B, see FIG. 7) can be more easily disconnected at the border bulkhead (WA-C3).

[0251] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0252] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0253] The electronic device according to the present invention can provide an electronic device with simplified manufacturing processes and costs as electrodes are interconnected through a partition in a non-display area, and the electrode covering the partition, which includes different metal layers, has the effect of reducing resistance, thus having high industrial applicability.

Claims

1. A processor that provides video data and display brightness values; A display panel connected to the above processor; and It includes a driving unit that receives the image data and the display brightness value, and drives the display panel based on the image data and the display brightness value. The above display panel is, A base substrate comprising a display area including light-emitting regions and a non-light-emitting region disposed between the light-emitting regions, and a non-display area adjacent to the display area and including a contact region; A pixel defining film disposed on the base substrate, wherein first openings overlapping with the light-emitting regions and second openings overlapping with the contact regions are defined in a third direction perpendicular to the first direction and the second direction and parallel to the upper surface of the base substrate; A light-emitting element comprising a common layer including a first electrode with at least one portion exposed by the first opening, a second electrode disposed on the first electrode, and a second electrode disposed between the first electrode and the second electrode; It includes a border barrier disposed on the pixel defining film, which overlaps at least a portion with the contact area in the third direction, and At least one portion of the first electrode overlapping with the above-mentioned non-display area is exposed by the second openings, and The second electrode is an electronic device that covers the border partition in the non-display area and is connected to the first electrode exposed by the second openings.

2. In Paragraph 1, The above border bulkhead is, An electronic device comprising a first insulating pattern disposed on the pixel defining film, a second insulating pattern disposed on the first insulating pattern, a first barrier pattern disposed on the second insulating pattern, and a second barrier pattern disposed on the first barrier pattern.

3. In Paragraph 2, The above first bulkhead pattern includes aluminum, and The above second partition pattern is an electronic device containing titanium.

4. In Paragraph 3, The width of the first bulkhead pattern is smaller than the width of the second bulkhead pattern, and An electronic device in which the thickness of the first partition pattern is greater than the thickness of the second partition pattern.

5. In Paragraph 2, An electronic device in which the width of the second insulation pattern is greater than the width of the second partition pattern.

6. In Paragraph 2, An electronic device in which the width of the second insulation pattern is greater than the width of the first insulation pattern.

7. In Paragraph 2, An electronic device further comprising a dummy pattern disposed on the second partition pattern and covered by the second electrode, wherein the dummy pattern comprises the same material as the common layer.

8. In Paragraph 2, An electronic device further comprising a protective layer containing an inorganic material disposed between the above dummy pattern and the above second partition pattern.

9. In Paragraph 2, An electronic device in which a second partition pattern protruding from the first partition pattern defines a downwardly protruding tip portion.

10. In Paragraph 2, It further includes a normal partition that overlaps with the above-mentioned non-luminous region and is disposed on the above-mentioned pixel definition film, and The above normal partition is an electronic device covered by the above second electrode.

11. In Paragraph 10, The shape of the above normal bulkhead is the same as the above border bulkhead, an electronic device.

12. In Paragraph 10, The above normal bulkhead and the above border bulkhead are an electronic device that forms an integral pattern.

13. In Paragraph 2, An electronic device in which the thickness of the second electrode is greater than the thickness of the first insulation pattern.

14. In Paragraph 1, In the above contact area, the second openings are arranged along a first direction and a second direction that intersect each other, and The above border bulkhead is an electronic device that does not overlap with the above second openings.

15. In Paragraph 14, The above border bulkhead is, An electronic device comprising first parts extending along the first direction and spaced apart along the second direction, and second parts disposed between adjacent first parts.

16. In Paragraph 15, Each of the above second parts is an electronic device having a stepped shape.

17. In Paragraph 15, Each of the above second parts is an electronic device extended along the above second direction.

18. In Paragraph 1, An electronic device comprising a first inorganic layer covering the light-emitting element, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer.

19. In Paragraph 18, The above display panel further includes a dam portion disposed in a non-display area and surrounding at least a portion of the contact area, and The above dam part is an electronic device comprising sequentially stacked organic patterns.

20. In Paragraph 19, The boundary of the organic layer in the above non-display area is an electronic device defined by the dam portion.

21. A base substrate comprising a display area including light-emitting regions and a non-light-emitting region disposed between the light-emitting regions, and a non-display area adjacent to the display area and including a contact region; A pixel defining film disposed on the base substrate, wherein first openings overlapping with the light-emitting regions and second openings overlapping with the contact regions are defined in a third direction perpendicular to the first direction and the second direction and parallel to the upper surface of the base substrate; A light-emitting element comprising a common layer including a first electrode with at least one portion exposed by the first opening, a second electrode disposed on the first electrode, and a second electrode disposed between the first electrode and the second electrode; In the above third direction, at least a portion overlaps with the contact area and includes a border barrier disposed on the pixel defining film, At least one portion of the first electrode overlapping with the above-mentioned non-display area is exposed by the second openings, and The second electrode covers the border partition in the non-display area and is connected to the first electrode exposed by the second openings in the display panel.

22. In Article 21, The above border bulkhead is, A display panel comprising a first insulating pattern disposed on the pixel defining film, a second insulating pattern disposed on the first insulating pattern, a first partition pattern disposed on the second insulating pattern, and a second partition pattern disposed on the first partition pattern.

23. In Paragraph 22, The above first bulkhead pattern includes aluminum, and The above second partition pattern is a display panel containing titanium.

24. In Paragraph 23, The width of the first bulkhead pattern is smaller than the width of the second bulkhead pattern, and A display panel in which the thickness of the first bulkhead pattern is greater than the thickness of the second bulkhead pattern.

25. In Paragraph 23, A display panel in which the width of the second insulation pattern is larger than the width of the second partition pattern.

26. In Paragraph 22, A display panel in which the width of the second insulation pattern is larger than the width of the first insulation pattern.

27. In Paragraph 22, A display panel further comprising a dummy pattern disposed on the second partition pattern and covered by the second electrode, wherein the dummy pattern comprises the same material as the common layer.

28. In Paragraph 22, A display panel further comprising a protective layer containing an inorganic material disposed between the above dummy pattern and the above second partition pattern.

29. In Paragraph 22, A second partition pattern protruding from the first partition pattern is a display panel defining a downwardly protruding tip portion.

30. In Paragraph 21, It further includes a normal partition that overlaps with the above-mentioned non-luminous region and is disposed on the above-mentioned pixel definition film, and The above normal partition is a display panel covered by the above second electrode.

Images