Configurable associative conversion memory and operating method thereof

Abstract

The invention relates to computing, and more particularly to (sub)processors in an associative, synchronous, FIFO register, conversion memory. The technical results consist in an increase in reliable diagnostic capability in SIMD mode, and conflict-free multi-stream processing of instructions and data in MIMD mode. A configurable associative, FIFO register, conversion memory is configured in the form of a computing surface comprised of operating bits and permits the formation of a part or the whole of a connected orientable computing surface of genus 0 or more. The claimed method comprises (micro)programmably configuring or reconfiguring a computing surface by a part or the whole of a connected orientable surface of genus 0 or more, carrying out testing in SIMD mode, excluding operating bits that fail information transfer and / or conversion process tests, (micro)programmably changing the genus of the connected orientable computing surface, and using said surface in information processes.

Description

[0001] Configurable transformative associative memory and its operating method Field of technology

[0002] The inventions relate to computing technology, in particular to computing complexes, fine-grained structural-functional reconfigurable (sub)processors in converting, synchronous, PPPO-register, associative memory.

[0003] The abbreviation PPPO stands for “first come, first served”, similar to “first in, first out” (FIFO).

[0004] State of the art

[0005] Similar in technical essence is the “Module of a homogeneous computing structure” according to the USSR Author’s Certificate for Invention No. 1359782, which was published on 15.12.1987, according to IPC G06F 15 / 00, including an arithmetic logic unit, a command register, delay elements, input switching units, output switching units, a transit control unit, and a transit expansion unit.

[0006] Similar in technical essence is a device implemented, according to the information from the source “Software synthesis of arrays of processor elements”, US patent for invention No. 6507947, which was published on 01 / 14 / 2003, according to IPC G06F 9 / 45, including a generated array of processors with arithmetic logic units, command registers, delay elements, input switching units, output switching units, and a transit control unit.

[0007] Similar in technical essence is the “Array of reconfigurable processors with a zero-buffer pipeline” according to the Chinese patent application No. 112506853, which was published on March 16, 2021, under IPC G06F 15 / 78, including reconfigurable processor units, local registers, global registers, and buses.

[0008] The disadvantages of the above-mentioned devices include insufficient reliable diagnostic suitability and low conflict-free multi-threaded processing of instructions and data.

[0009] The closest in technical essence is the “Cell of a homogeneous computing environment” according to the USSR Author’s Certificate for Invention No. 691846, which was published on October 15, 1979, according to IPC G06F 7 / 00, including an arithmetic logic element, a command register, delay elements, input switches, output switches, a transit circuit, and a transit expansion unit.

[0010] The disadvantages of the above-mentioned device include insufficiently high reliable diagnostic suitability and low conflict-free multi-threaded processing of instructions and data.

[0011] Disclosure of inventions

[0012] The increased packaging density of electronic components is currently achieved by reducing the component size—using VLSI manufacturing technologies with components smaller than 10 nm. This allows for increased VLSI performance and reduced power consumption. However, reducing component size can lead to malfunctions in some VLSI components. To improve VLSI reliability, it is important to perform component diagnostics during operation, eliminating malfunctioning VLSI components from use.

[0013] The objectives of the invention are to improve reliable diagnostics and create conflict-free multi-threaded processing of instructions and data.

[0014] The technical results of the inventions are an increase in reliable diagnostic suitability in the OKMD mode and the creation of conflict-free multi-threaded processing of instructions (commands) and data in the MKMD mode.

[0015] 1

[0016] SUBSTITUTE SHEET (RULE 26) The abbreviation OKMD stands for "single instruction stream and multiple data stream," analogous to "Single instruction stream / Multiple Data stream" (SIMD) in M. Flynn's taxonomy. The abbreviation MKMD stands for "multiple instruction stream and multiple data stream," analogous to "Multiple Instruction stream / Multiple Data stream" (MIMD) in M. Flynn's taxonomy.

[0017] The technical results are achieved by the fact that the configurable converting PPPO-register associative memory is implemented in the form of a computing surface of operational bits (OB), synchronously operating and united by a single PPPO-register channel for input and storage of configuring bit instructions, switched with the memory configuration control controller and the programmer via a system bus, intended for computer applications of (multi)stream information processing and included in (sub)processor paths in the form of pre-, co- and postprocessors interacting with each other via a (micro)software-reconfigurable loop-bus, ensuring the formation of computing: parts of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher.

[0018] Technical results are also achieved by the fact that in the configurable converting PPPO-register associative memory, operational bits can be combined in hardware and time with the computing functionalities of storage, transfer and conversion, and the content of the stored, transferred and converted information can be used for the dynamic (re)configuration of the structure of the computing surface.

[0019] Technical results are also achieved by the fact that in the computing surface, operational bits can be connected by bidirectional galvanic connections with their nearest orthogonal neighbors.

[0020] The technical results are also achieved by the fact that the computing surface can include input and output interfaces for physical coupling with external devices, including an interface for bidirectional information exchange with a memory configuration controller, flash memory for firmware for application functionality and diagnostics, storing input and output signatures of diagnostic data, with the ability to be configured in a circuit and (micro)software-based manner in a time-sharing mode with information processing with virtualization of its address space by segmentation at the stage of memory configuration of arbitrary volumes and, at the stage of normal operation, to be reconfigured in real time (micro)software-based and / or by the contents of converted data streams.

[0021] The technical results are also achieved by the fact that the operational bits can include a converting complementary static D-trigger, which is part of a VLSI equidistant delay 1111110-register structure, the (^-outputs of which set and fix for a certain period of time the Config / Processing memory segments operating mode synchronously and in-phase across all operational bits of the segment, a configuration register of complementary static converting D-triggers, which is part of the input and storage channel of user-defined memory segment configurations, a distributed decoder that converts the contents of the register into control signals for (micro)command-controlled volatile electronic keys, an input and output switching field of volatile electronic keys for addressless data exchange with the nearest orthogonal operational bits,a two-layer operating device made of clusters of converting complementary static D-triggers, the configuration of connections between which is determined by the switching field of energy-dependent electronic keys, ensuring unaddressed data exchange.

[0022] 2

[0023] SUBSTITUTE SHEET (RULE 26) Technical results are also achieved by the fact that a non-volatile switch can be included in the complementary static D-triggers, which ensures the distribution of complementary signals along two transmission channels formed by two D-triggers of the TT type and a non-volatile switch, ensuring the distribution of signals between four D-triggers of the T type and an output non-volatile switch, which ensures the distribution of complementary signals to the outputs (w !+ i,-,w !+i) And Qi, from which complementary signals to the outputs (щ+1, -,щ+1) are used to form 1111110- registers of arbitrary bit width, and Qi is used to fix the state of each bit of the configuration register, which determines the state of the energy-dependent keys in the corresponding components of the operational bits.

[0024] The technical results are achieved by the fact that in the method of operation of the configurable converting PPPO-register associative memory, the computing surface is (micro)programmatically configured or reconfigured with a part of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher, tested in the OKMD mode, operational bits that have not passed the tests are excluded from the processes of transmission and / or transformation of information, the type of the connected orientable computing surface is (micro)programmatically changed and used in the processes of storage, transmission and / or transformation of information.

[0025] Technical results are also achieved by changing the type of connected orientable computational surface by increasing.

[0026] Technical results are also achieved by changing the genus of a connected orientable computational surface by lowering it.

[0027] Technical results are also achieved by (micro)programmatically changing the type of connected orientable computing surface by puncturing areas of operational bits that have not passed tests.

[0028] The term "puncture" (or "puncture") (topologically) should be understood as a portion of a connected orientable computational surface containing at least one operational bit, excluded from the connected orientable computational surface (matrix of operational bits). The remaining portion of the connected orientable computational surface (matrix of operational bits) constitutes the "neighborhood of the puncture" (the punctured set of operational bits). It is also acceptable to use the phrases "punctured neighborhood of the computational surface" or "punctured neighborhood of the computational surface" for this entity.

[0029] A pair of neighborhoods of punctures of a connected orientable computational surface, connected to each other along the boundaries of the corresponding punctures, is understood as a “computational surface with a topological hole”.

[0030] In addition to a structurally organized (physically) connected orientable computational surface (of genus 1 - with one "topological hole", of genus 2 - with two "topological holes", and so on), it is appropriate to use the term "hardware hole", which topologically increases the genus of a connected orientable computational surface. Galvanic connection of a pair of puncture neighborhoods in a connected orientable computational surface actually forms a hardware hole in it and, accordingly, increases the topological genus of the connected orientable computational surface by one. In a terminological sense, disconnected puncture neighborhoods can be designated by an additional negative genus of a connected orientable computational surface, for example, a single puncture in a connected orientable computational surface of genus 0 transforms it into a connected orientable computational surface of genus -1 / 0 (such as "circle", "square"), where "O" after the sign

[0031] 3

[0032] SUBSTITUTE SHEET (RULE 26) " / " denotes the topological genus of the transformed computational surface, additional disconnected neighborhoods of two punctures in a connected orientable computational surface of genus 0 - in a connected orientable computational surface of genus -2 / 0 (of the "flat ring", "cylinder" type), three neighborhoods of punctures, two of which are connected, - in a connected orientable computational surface of genus -1 / 1 (in this case, a pair of connected neighborhoods of punctures lead to the formation of a topological hole in the computational surface, i.e. to an increase in its topological genus to 1).

[0033] Implementation of inventions

[0034] Fig. 1 shows the structure of a configurable transforming 1111110-register associative memory.

[0035] Fig. 2 shows the structural diagram of the operational bit with the designations Config / Processing - operating mode; UstConfig (in) - stream (array) of input codes of operational bit configurations; UstConfig (out) - stream (array) of output codes of operational bit configurations.

[0036] Fig. 3 shows the structure of the operational bit matrix with the following designations: Config / Processing — operating mode; UstConfig (in) — stream (array) of input operational bit configuration codes; UstConfig (out) — stream (array) of output operational bit configuration codes; I (in / out) — stream of input / output data, 2(M*A).

[0037] Fig. 4 shows a simplified diagram of an operational bit.

[0038] Fig. 5 shows the symbols for open and closed keys.

[0039] Fig. 6 shows the structural diagram of a converting complementary static D-trigger.

[0040] Fig. 7 shows the structural diagram of channels (clusters) of pipeline arithmetic-logical processing and transit data transmission.

[0041] Fig. 8 shows the connection diagram of the elements of the addressless PPPO-register structure.

[0042] Fig. 9 shows a diagram of methods for configuring computational surfaces using thermal operation bits for a cylinder-type computational surface.

[0043] Fig. 10 shows a diagram of methods for configuring computational surfaces using thermal operational bits for a connected surface of genus 0 (such as “ball”, “cube”).

[0044] Fig. 11 shows a diagram of methods for configuring computational surfaces using thermal operation bits for a connected surface of genus 1 (torus type).

[0045] Fig. 12 shows the structure of controlled physical transitions (connections) of terminal operational bits based on D-triggers (simplified).

[0046] Fig. 13 shows examples of activation of operational bit connections.

[0047] Fig. 14 shows the configuration of a Y-cylinder computing surface using double-sided VLSI mounting on a board.

[0048] Fig. 15 shows the configuration of a cube / ball type computing surface using double-sided mounting of the integrated circuit on the board.

[0049] Fig. 16 shows the configuration of a torus-type computing surface using double-sided mounting of the integrated circuit on a board.

[0050] Fig. 17 shows the schematic diagram of a digital pipeline adder.

[0051] Fig. 18 shows the conventional designations of the OB configured to implement one of the possible bit instructions and commutation with the nearest orthogonal neighbors.

[0052] 4

[0053] SUBSTITUTE SHEET (RULE 26) Fig. 19 shows the structure of a PD-associative multiplier on operational bits.

[0054] Fig. 20 shows the signature of a PD-associative multiplier on the operational bits (least significant bit on the left).

[0055] Fig. 21 shows the functional diagram of the parallel-serial code input interface (least significant digit on the left).

[0056] Fig. 22 shows the topology of a functioning loop bus.

[0057] Fig. 23 shows the topology of a faulty loop bus.

[0058] Fig. 24 shows the structure of the horizontal connection test of operational bits in the absence of functional deficiencies.

[0059] Fig. 25 shows the signature of the horizontal communication test of operational bits in the absence of functional deficiencies.

[0060] Fig. 26 shows the structure of the horizontal connection test of operational bits in the presence of functional deficiencies.

[0061] Fig. 27 shows the signature of the horizontal communication test of operational bits in the presence of functional deficiencies.

[0062] Fig. 28 shows the structure of the test of the top row of operating channels.

[0063] Fig. 29 shows the signature of the test of the top row of operating channels. Fig. 30 shows the structure of the test of the middle row of operating channels. Fig. 31 shows the signature of the test of the middle row of operating channels. Fig. 32 shows the terms of the test of commutability (horizontal connections) of operating bits.

[0064] Fig. 33 shows examples of terms that ensure complete functional control (executability) of the AND bit instruction of operational bits.

[0065] The configurable converting NNNO-register associative memory is made in the form of a computing surface 1 of operational bits 2, synchronously operating and united by a single NNNO-register channel for input and storage of configuring bit instructions, switched with a memory configuration control controller 3 and a programmer 4 via a system bus 5, intended for computer applications of (multi)stream information processing and included in (sub)processor paths in the form of pre-, co- and postprocessors interacting with each other via a (micro)software-reconfigurable loop-bus 6, ensuring the formation of the computing part of a connected orientable surface 1 of genus 0 or a connected orientable surface 1 of genus 0 and higher.

[0066] In the configurable transforming 1111110-register associative memory, the operational bits 2 can be combined in hardware and time with the computing functionalities of storage, transfer and transformation, and the content of the stored, transferred and transformed information can be used for the dynamic (re)configuration of the structure of the computing surface 1.

[0067] In the computational surface 1, the operational bits 2 can be connected by bidirectional galvanic connections 7 with their nearest orthogonal neighbors.

[0068] The computing surface 1 may include input 8 and output 9 interfaces for physical coupling with external devices, including an interface 10 for bidirectional information exchange with the memory configuration controller 3, flash memory for the firmware of the application functionalities 11 and diagnostics 12, storing the input and output signatures of the diagnostic data, with the ability to be configured by circuitry and (micro)software in a time-sharing mode with the processing of information with the virtualization of its address space by segmentation at the stage of memory configuration of arbitrary volumes and at the stage of normal operation to be reconfigured in real time (micro)software and / or the contents of the converted data streams.

[0069] 5

[0070] SUBSTITUTE SHEET (RULE 26) Operational bits 2 may include a converting complementary static D-flip-flop 13, which is part of the VLSI equidistant time delay 1111110-register structure, the (^-outputs of which set and fix for a certain period of time the Config / Processing memory segments operating mode synchronously and in-phase across all operational bits of the segment, a configuration register 14 of complementary static converting D-flip-flops, which is part of the input and storage channel for user-defined memory segment configurations, a distributed decoder 15, converting the contents of register 14 into control signals for (micro)command-controlled volatile electronic keys, an input 16 and output 17 switching field of volatile electronic keys for unaddressed data exchange with the nearest orthogonal operational bits 2, a two-layer operating device 18,19 of the clusters of converting complementary static D-triggers, the configuration of connections between which is determined by the switching field of 20 energy-dependent electronic keys, ensuring unaddressed data exchange.

[0071] A non-volatile switch 21 can be included in the complementary static D-triggers 13, which ensures the distribution of complementary signals (and г -,-,And г ) via two transmission channels formed by two D-triggers of the TT type and a non-volatile switch 22, ensuring the distribution of signals between four D-triggers 23, 24 of the T type and an output non-volatile switch 25, which ensures the distribution of complementary signals to the outputs (w !+ i,-,w !+ i) And Qi, from which complementary signals to the outputs (w !+ i,-,w !+i) are used to form 1111110-registers of arbitrary bit width, and Qi is used to fix the state of each bit of the configuration register, which determines the state of the volatile keys in the corresponding components of the operational bits 2.

[0072] Each operational bit (Fig. 4), at the discretion of the VLSI user, can contain several channels (clusters) (see Fig. 7) of pipeline arithmetic-logical processing and transit transmission in four independently addressed directions of data reception / transfer, each of which includes:

[0073] - input 26 and output 27 energy-dependent switches, the states of which are set and recorded by the outputs Qi of the converting D-triggers, belonging respectively to the Bx and Bx fields of the configuration register 14;

[0074] - two layers 28 and 29 of converting D-triggers of type T and a energy-dependent switch 30, the state of which is set and fixed by the outputs Qi of the converting D-triggers belonging to the operation code field (OCF) of the configuration register 14.

[0075] The difference between the converting D-triggers used in blocks 13, 14 and blocks 18, 19 is that the configuration of the former is set by non-volatile keys that retain their state over long periods of time T, while in the latter, by volatile keys that can change their state at each memory clock cycle.

[0076] Each segment of the volatile key configuration codes, loaded once into the registers 14 of the operational bit configurations of the single-level physically user-configurable converting 1111110-register associative memory, includes fragments of addressless 1111110-register structures of arbitrary size and the following functional purpose (Fig. 8):

[0077] - independently addressable logical input interfaces 31, providing for the conversion of input data streams from parallel code to serial code;

[0078] - independently addressable logical output interfaces 32, providing conversion of input data streams from serial code to parallel code;

[0079] 6

[0080] SUBSTITUTE SHEET (RULE 26) - algorithmically oriented arithmetic-logical devices of the graph-flow of applied functionality 33;

[0081] - controller for cyclic control of parameters and structure of the flow graph of application functionality 34;

[0082] - vector address coprocessor for controlling interaction with external RAM 35;

[0083] - diagnostic controller for real-time detection of failures and malfunctions (structural and functional deficiencies) of operational bits 36;

[0084] - generator of input 37 and output 38 signatures;

[0085] - a loop-bus 6 for conflict-free data exchange along the graph-flow of application functionality and reconfiguration of computing surfaces of a tolerant algorithmically-oriented structure of associative memory and the current topology of cells with structural and functional insufficiency.

[0086] Methods for configuring computing surfaces 1 using thermal operational bits for computing surfaces are shown in Figs. 9 - 11. Array of software-reconfigurable input / output galvanic connections 7, conditional Y-axis of “rotation” 39 of computing surface 1, conditional X-axis of “rotation” 40 of computing surface 1.

[0087] In Fig. 12 and Fig. 13, the conductor (metal) 41 can be in passive connection (indicated by the dotted line) and in activated connection 42.

[0088] In Fig. 14 - 15 SBIS 43, front side of board 44 and back side of board 45, in Fig. 16 front side of first board 46, back side of first board 47, front side of second board 48, back side of second board 49.

[0089] In Fig. 20 there is a converting register-receiver 50, an equidistant splitter “1^-16” 51, a cyclic strobe generator “C_1_16” 52.

[0090] In Fig. 22, faulty operational bit 53 (operational bit with functional insufficiency).

[0091] In Fig. 31 the main term 54, the thermal structure 55 of bypassing the failed (functionally insufficient) operational bit

[0092] In Fig. 32 the testing term of the top row is 56, the testing term of the middle row is 57, the testing term of the bottom row is 58.

[0093] The condition for the correct operation of the converting NNNO-register associative memory in the volatile control mode is the complementarity (mutual complementarity) of the converted information flows, which is ensured due to the fact that in CMOS technologies, the volatile closure of galvanic connections 7 corresponds to the Boolean function (BF) "mounting OR" only in the case when, on the closed contact of the volatile type, the sum (additive superposition) of the currents E / does not violate the rules for assigning values ​​of logical variables ("0" or "1") to physical parameters and does not lead to the destruction of the semiconductor heterostructure, i.e. the following restrictions are met:

[0094] E / ,° < / ' и ЕЛ / лрДля i=\^n. (1)

[0095] Here: 7° and I 1 (Z° << 7 1 ) the values ​​of currents identified, respectively, as “logical zero” and “logical one”, 1 пр- the breakdown current of the D-input of the trigger, and the number of inputs of the “mounting OR” is within the range of and=2t4.

[0096] Compliance with restrictions (1) guarantees:

[0097] - implementation of the switching standard for coding logical variables f l г e{«0», «1»} their physical representatives / 'и / 1 ;

[0098] - the correctness of the transition from the linear superposition of analog disturbances to the digital “assembly OR”, since galvanic switching is essentially an analog circuit implementing the EL transformation, which at the §(f) « Q( ) outputs of the D-trigger is transformed, respectively, into complementary BFs F(x2, xi) = T2VT1 and F(%2, Xl) = -I(%2VX1).

[0099] 7

[0100] SUBSTITUTE SHEET (RULE 26) The virtual address space of the circuit- and (micro)software-configurable converting 1111110-register associative memory uses a hierarchy of algorithmically oriented objects of varying functional complexity, located in a single-level physical PPPO-register associative memory:

[0101] - all objects of the “zero” level of the hierarchy are homogeneous and provide a tabulated (normalized) nature of analog physical interactions for any configuration of galvanic connections 7 in the basic structure of converting D-triggers (Fig. 6, 7);

[0102] - objects of the “first” level of the hierarchy ensure the implementation of elementary BFs of two to four input variables and their corresponding continuous analogues;

[0103] - operational objects of the “second” level of the hierarchy ensure the implementation of individual arithmetic-logical functions defined over “infinite” data flows;

[0104] - operational objects of the “third” level of the hierarchy (operational bits) ensure the implementation of all bit instructions and all options for switching operational bits in the transformative associative memory;

[0105] - “thermal” objects of the “fourth” level of the hierarchy simplify the instructed synthesis of “assembler” structures according to a given computational function, within the framework of which algorithmically oriented structures of operational bits are used, defined over an “infinite” data flow;

[0106] - “assembler” objects of the “fifth” level of the hierarchy ensure the implementation of computational functionalities defined over “infinite” streams of “-bit operands;

[0107] - flow-operator objects of the “sixth” level of the hierarchy provide the implementation of computational functionalities defined over flows of N “-bit operands.

[0108] In the initial unconfigured state, each cell of the converting P1P10-register associative memory represents two sites with approximately an equal number of converting D-triggers (Figs. 6 and 7) in each.

[0109] The non-volatile configuration of the converting PPPO-register associative memory is carried out using the controller 3, the programmer 4 and the flash memory 11 and 12 and is completed by converting the homogeneous two-site field of converting D-triggers (Figs. 6 and 7) into a microcommand-controlled matrix of object-oriented OB that meet the structural and functional requirements (Figs. 2, 3, 7) and the parameters of the user functionality (Fig. 8) according to: the structure of the equidistant bus 13 Config / Processing the bit depth of the configuration registers 14, the configuration of the bus UstConfig structure and the parameters of the distributed decoder 15.

[0110] Dynamic energy-dependent configuration of the converting 1111110-register associative memory is carried out in the time-sharing mode with processing using the controller 3, programmer 4 and flash memory 11 and 12. It is completed by loading the bit-instruction codes into the configuration registers 14 of each operational bit, corresponding to the requirements of the active flow-operator (Fig. 8).

[0111] Dynamic energy-dependent control of the converting PPPO-register associative memory is carried out due to the dependence of the structural-functional clusters of the operational bit (Fig. 7) not only on the contents of register 14, but also on the contents of the converted data streams, which is shown using the example of a pipeline adder.

[0112] Example 1. The pipeline adder (Fig. 17) operates according to the rule:

[0113] 8

[0114] SUBSTITUTE SHEET (RULE 26) where the content of the control variable e(t— 1) is formed according to the rules of the “transfer unit” BF and can change at each operation cycle depending on the content of the input streams X1 (t) and X1 (t).

[0115] Dynamic synthesis and energy-dependent configuration of the converting 1111110-register associative memory, carried out in the time-sharing mode with processing, make it possible to use a special class of associative arithmetic logic units, the structure of which depends on the content of one of the converted operands, which is shown in the example of the PD-associative multiplier.

[0116] Example 2. PD-associative multiplier

[0117] The PD-associative multiplier (Fig. 19, 20 and Table 1 in the legend of Fig. 18) implements the following transformation: which corresponds to its full functionality, = 0, which corresponds to the “storage” functional

[0118] As», D which corresponds to the functionality

[0119] "multiplying the flow (A") by the constant Az", 0 f which corresponds to the functionality

[0120] "addition of the flux (F) with the constant Az".

[0121] Table 1 - Decimal protocol of operation of the PD-associative multiplier on the OB

[0122] (least significant bit on the left)

[0123] The functionality of the PD-associative computing structure of Fig. 19: a) depends on the content of the operands being converted:

[0124] - with a “single” excitation X = 1 and V = 0, the PD-associative multiplier is used as a “macro-operational bit” of memory, which reproduces the binary sequence 11001000, interpreted as the decimal number P = 19;

[0125] - with “non-unit” excitation X > 1 and V = 0, the PD-associative multiplier is used in its natural mode of multiplication by the constant C = 19: P = 19*X;

[0126] - with “non-unit” excitation X > 1 and V > 0, the PD-associative multiplier produces a result with a bias specific to each cycle: F = 19*X + Y 7 ;

[0127] - with a “single” excitation X = 1 and V >0, the PD-associative multiplier degenerates into an adder with a bias: F = Y 7 +19;

[0128] 9

[0129] SUBSTITUTE SHEET (RULE 26) b) can be changed in real time depending on the contents of streams X ) and (Y ) and reconfigured by firmware when the contents of A change.

[0130] The specified fault tolerance of converting D-triggers in the channel for forwarding and storing bit instructions of operational bit configurations is achieved by increasing the number of “bypass” options for functionally insufficient components supporting the “forwarding / storing” functionality, and by increasing their bit depth in relation to the bit depth of the operational bit operands.

[0131] Example 3. Ensuring the specified fault tolerance of converting D-triggers and a bus

[0132] Ensuring the specified fault tolerance of converting D-triggers in the channel for forwarding and storing bit-instructions of operational bit configurations is achieved by increasing the number of “bypass” options for functionally insufficient components supporting the “forwarding / storing” functionality, which exceeds the reserve factor.

[0133] Thus, with a double reserve of converting D-triggers (Figs. 6 and 7), there are eight options for compensating not only their functional failure (control object), but also the functional failure of non-volatile and volatile keys (control means): a) without “pre-distortion” of the contents of the z-th Ui=m:

[0134] Qi-= Q 2 I(:=Q 1 I); Q .= Q^-Q^y Qr.= Q -=QQ = Q^-Q^

[0135] Ql = ^ e 2 1(:= ^ ei1); Ql .= ^Q2 1(:= ^QI 2) .QI ._ Q 2 2y=^Q\y Qi .= ^Q2 2(:= ^ Q I 2) . b) due to the “pre-distortion” of the contents of the z-th Ui= —iUi

[0136] Ensuring the specified fault tolerance of computing structures from converting D-triggers due to the redundancy of operational bits included in these structures, as is the case in input interfaces 31, is achieved by doubling their bit capacity in relation to the bit capacity of n operands transmitted and converted from parallel code to serial code (Fig. 21). For this purpose, it is sufficient to exclude, using energy-dependent firmware, from the gating of the converting register of the receiver of an operational bit with a functional deficiency, which distorts the content of the corresponding bit of the operand in a serial code of lower bit capacity. As a result, double redundancy of the input register-receiver ensures the parity of not two, but n failures (functional deficiencies in the OBs used).

[0137] Here C_1_16 is a cyclic constant of the form

[0138] С_1_16=1000.0000.0000.0000.1000.0000.0000.0000, . . .

[0139] Similarly, ensuring the specified fault tolerance of computing structures is achieved in the loop bus (6) for conflict-free data exchange (Fig. 22, 23).

[0140] Ensuring the specified depth and reliability of diagnostics of the converting 1111110-register associative memory, with the specified accuracy (up to the coordinates of the OB and the type of their failure, malfunction (functional insufficiency)) and carried out at a rate close to real time, is achieved due to:

[0141] - dynamic synthesis of test structures adapted to the detected topology of the OB with a certain functional deficiency;

[0142] - a testing strategy built on a hierarchy of test functionalities: “controllability”, “commutability” and “executability” of operational bits, in which operational bits that have not passed the test for the ability to execute the previous functionality are excluded from each subsequent functionality;

[0143] 10

[0144] SUBSTITUTE SHEET (RULE 26) - a testing methodology based on the analysis of “responses” to each test combination of input disturbances from the operational bit, implementing the same function being tested (corresponds to the OKMD testing mode).

[0145] The possibilities of dynamic synthesis of test structures, providing a given fault tolerance of operational bits of a configurable transformative associative memory, are illustrated by Example 4.

[0146] Example 4. Ensuring a specified fault tolerance of operational bits of a configurable transformative associative memory by dynamically synthesizing test structures

[0147] When testing the “commutability” of horizontal connections of operational bits of a configurable transformative associative memory (Fig. 23), the test signal is a single “probing” pulse, which, propagating through transit channels, forms a multiple response at the output in the form of a meander if all operational bits being tested are operational (Fig. 25).

[0148] In the event of a malfunction (failure, functional failure), the meander structure is disrupted by the appearance of either an additional “single” pulse or an additional “pause”, the location of which identifies the coordinates of the failed operational bit with an accuracy of two equidistant from the response return point.

[0149] To continue the testing procedure, it is necessary to exclude from the test structure the operational bit with a failure (functional insufficiency) (Fig. 26) and obtain the “correct” response from the entire structure (Fig. 27), which does not disrupt the meander, but only lengthens it.

[0150] When checking the “executability” of the functions of operational bits, the need to modify the test structure arises from the requirements for its completeness, since only one line of operational bits is tested, and the other two are terminal and provide switching of two excitations and one response (Fig. 28-31).

[0151] The dynamic synthesis of test structures is provided by means of thermal objects of the fourth level of the organization of the work of the transforming PPPO-register associative memory, which simplifies and accelerates the synthesis of not only tests, but also objects of the assembler level included in the structures of the flow operators of Fig. 8 according to the principle of “one instruction - one operating device”.

[0152] Example 5. Ensuring a given completeness of diagnostics of operational bits of a configurable transformative associative memory using fourth-level thermal objects

[0153] To generate test structures at a rate close to real time, it is sufficient to use several types of terms for each of the functionalities - “commutability” (Fig. 32) and “executability” (Fig. 33), which makes the operation of the diagnostic system similar to the silicon compilation system, with the difference that the former operates in quasi-real time.

[0154] A similar technology of thermal synthesis and failure coping is also used for computing functions: “forwarding”, “storage” and “conversion”, the operability of which is also restored in quasi-real time and with a non-multiple hardware reserve.

[0155] Fig. 32 shows examples of terms that ensure complete control of horizontal connections (commutability) of matrix 1 of operational bits, where (54) is the main one, and the rest (55) provide parrying (bypass) of the operational bit with a functional deficiency to continue testing the subsequent operational bits 53 (designated by the symbol “X”). The serial connection of these terms forms a channel for distributing the test sequence.

[0156] 11

[0157] SUBSTITUTE SHEET (RULE 26) from left to right and the responses of each operational bit from right to left, and the violation of the regularity of the response sequence, caused by the regularity of the test structure, is used to identify the coordinate of the failed operational bit.

[0158] Fig. 33 shows examples of terms that ensure complete functional control (executability) of the AND bit instruction of the operational bit independently across the top (56), middle (57), and bottom (58) rows. Here, the test data is distributed from left to right across two rows of the operational bit, and the response is distributed across the third row from right to left. For other bit instructions, the structure of the data input / output channel is preserved, which creates the effect of the SIMD mode of their control throughout the converting PPPO-register associative memory.

[0159] The segments of the configuration codes of volatile keys, covering all functionalities (Fig. 8) loaded once into the registers of 14 operational bit configurations, are structurally limited by the sizes of I P *J P converting 1111110-register associative memory, located on the board, which includes not only the actively used working field, but also a hot reserve (about 30% of the working field).

[0160] The means of centralized use of the physical volume of all boards of the converting PPPO-register associative memory are the bus-strip 6, the components of which, according to Fig. 8, are attributes of each board and allow, without changing the design, to include them in reconfigurable computing surfaces of a certain type, including surfaces of topological genus 0 (such as “ball”, “cube”), genus 1 (such as “torus”) and their combinations (Figs. 9-11).

[0161] Operational bits that fail testing, i.e., contain failures or malfunctions (structural and functional deficiencies), are interpreted as punctures (in the topological sense) in the computational surfaces formed using the busbars. The types of failures and malfunctions (structural and functional deficiencies) localized during testing and diagnostics are recorded in the config / r files of the operational bit matrix.

[0162] Thus, the cylindrical surface (Fig. 9) allows centralized variation of only one of the parameters 1 Р or J p , fc-fold laying out on it in the form of a spiral each matrix I P *J P along the y-axis. In the three-dimensional volume of a cube, both parameters of the matrix 1 can be increased by a factor of ^ Р and J p , and this multiplicity also applies to the size of the hot reserve.

[0163] The features of the 6-lane bus are that it:

[0164] - the transfer of information via activated connections between boards occurs due to D-triggers of peripheral operational bits (terminal bits) and is carried out with a normalized delay of one clock cycle (Fig. 12);

[0165] - with double-sided mounting of the integrated circuit on the board, all galvanic connections 7, which form the computing surface in the form of X or Y-cylinders, cubes and equidistant tori (Fig. 9, 10), are realized due to metallized holes in the boards and / or electrically conductive connections of equal length;

[0166] - the movement of the rectangular working field of the microprogram segments, meeting the requirements of Fig. 8, along the cylindrical surface is carried out by shifting it due to the inclusion (exclusion) of the inserts of terminal D-triggers, providing transit data transfer from the peripheral operational bits to the working field, the dimensions of which are determined by the parameters of the input 31 and output 32 logical interfaces and algorithmically oriented arithmetic-logical devices of the graph-flow of the application functionality 33.

[0167] According to the data provided:

[0168] 12

[0169] SUBSTITUTE SHEET (RULE 26) a) the process of (re)configuring the structure of the transforming 1111110-register associative memory to meet the requirements of the flow operators of Fig. 8 is reduced to editing the texts of their microprograms loaded into the physical transforming PPPO-register associative memory from flash memory 11 and 12, the "words" of which are displayed in the structures of operational bits. b) the initial data for editing are:

[0170] - texts of library microprogram files (yg / yl-files), which in object codes are stored in flash memory 11 (user microprograms) and flash memory 12 (system microprograms) and which reflect the content of the bit-instructions of the OB on the matrix without linking it to the physical address in the converting PPPO-register associative memory;

[0171] - texts of files that reflect the actual structural and functional capabilities of the OB matrix of the transforming PPPO-register associative memory (config / g-files), which are stored in flash memory 11 (system microprograms) and are common to all flow operators;

[0172] - file texts that reflect the composition of terms used in the creation of yg / yl files and their adaptation to the used computational surface and the failure map operating in it; c) the result of editing is reflected in the download file (zag file), which:

[0173] - is formed by controller 3 of flash memory 11 and 12 from the edited intermediate yg / yl file;

[0174] - is linked to the physical addresses of the PPPO-register associative memory matrix, the computing surface operating in it, and the physical structure of the single PPPO-register control channel 14 for input and storage of bit instructions. d) the process of editing the texts of test microprograms can be carried out at a pace close to real time due to direct access to their object code, and with an accuracy of up to the coordinate of the failed operational bit and the bit instructions and configurable links not executed by them.

[0175] The configurable transforming PPPO-register associative memory operates using elements 1-38: (micro)software-based configuration or reconfiguration of computational surface 1 with a portion of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher, testing in the OKMD mode, excluding operational bits 2 that failed the tests from the processes of data transmission and / or data conversion, (micro)software-based changing the genus of the connected orientable computational surface and using them in the processes of data storage, transmission, and / or data conversion. The genus of connected orientable computational surface 1 can be changed by increasing. The genus of connected orientable computational surface 1 can be changed by decreasing. The genus of connected orientable computational surface 1 can also be (micro)software-based changing by puncturing the regions of operational bits that failed the tests.

[0176] 13

[0177] SUBSTITUTE SHEET (RULE 26)

Claims

1.

1. A configurable converting 11111 U-register associative memory in the form of a computing surface of operational bits, synchronously operating and united by a single U-register channel for input and storage of configuring bit instructions, switched with a memory configuration control controller and a programmer via a system bus, intended for computer applications of (multi)stream information processing and included in (sub)processor paths in the form of pre-, co- and post-processors interacting with each other via a (micro)software-reconfigurable loop bus, ensuring the formation of computing: parts of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher.

2. Memory according to paragraph 1, characterized in that the operational bits combine the computing functionalities of storage, transfer and conversion in terms of hardware and time, and the content of the stored, transferred and converted information is used for the dynamic (re)configuration of the structure of the computing surface.

3. Memory according to claim 1, characterized in that in the computing surface the operational bits are connected by bidirectional galvanic connections with the nearest orthogonal neighbors.

4. Memory according to claim 1, characterized in that the computing surface includes input and output interfaces for physical coupling with external devices, including an interface for bidirectional information exchange with a memory configuration controller, flash memory of firmware for application functionality and diagnostics, storing input and output signatures of diagnostic data, with the ability to be configured by circuitry and (micro)software in a time-sharing mode with information processing with virtualization of its address space by segmentation at the stage of memory configuration of arbitrary volumes and at the stage of normal operation to be reconfigured in real time (micro)software and / or the contents of converted data streams.

5. The memory according to claim 1, characterized in that the operational bits include a converting complementary static D-flip-flop, which is part of a distributed over the VLSI equidistant in time delay PPPO-register structure, the ^-outputs of which set and fix for a certain period of time the Config / Processing memory segments operating mode synchronously and in-phase across all operational bits of the segment, a configuration register of complementary static converting D-flip-flops, which is part of the input and storage channel of user-defined configurations of memory segments, a distributed decoder converting the contents of the register into control signals for (micro)command-controlled volatile electronic keys, an input and output switching field of volatile electronic keys for addressless data exchange with the nearest orthogonal operational bits, a two-layer operational device of clusters of converting complementary static D-flip-flops,the configuration of connections between which is determined by the switching field of energy-dependent electronic keys, ensuring unaddressed data exchange.

6. Memory according to claim 5, characterized in that a non-volatile switch is included in the complementary static D-triggers, which ensures the distribution of complementary signals (in, -, Ui) along two transmission channels formed by two D-triggers of the TT type and a non-volatile switch, ensuring the distribution of signals between four D-triggers of the T type and an output non-volatile switch, which ensures the distribution of complementary signals to the outputs (щ + 1,-,m 1+ 1) and Qi, from which complementary signals to the outputs (and (+ 1,-,m 1+1) are used to form 1111110-registers of arbitrary bit width, and Qi is used to fix the state of each bit of the configuration register, which determines the state of the volatile keys in the corresponding components of the operational bits.

7. A method of operating a configurable transforming PPPO-register associative memory, in which the computing surface is (micro)programmatically configured or reconfigured as a part of a connected orientable surface of genus 0 or a connected orientable surface of genus 0 and higher, tested in the OKMD mode, operational bits that have not passed the tests are excluded from the processes of transmitting and / or converting information, the type of connected orientable is (micro)programmatically changed computing surface and are used in the processes of storing, transmitting and / or converting information.

8. The method according to claim 7, characterized in that the type of the connected orientable computational surface is changed by increasing.

9. The method according to claim 7, characterized in that the type of the connected orientable computational surface is changed by decreasing.

10. The method according to claim 7, characterized in that the type of connected orientable computing surface is changed (micro)programmatically by puncturing areas of operational bits that have not passed the tests.

Images