Writing renewal configuration data to print component

Abstract

An apparatus can include a set of electrical contacts to interface with a print component, a processor, a non-transitory, computer-readable medium including instructions which, when executed by the processor, cause the processor to transmit, using the set of electrical contacts, a renewal passcode to the print component, write, using the set of electrical contacts, a renewal status bit of the print component after transmitting the renewal passcode to the print component, and write, using the set of electrical contacts, renewal configuration data to the print component.

Description

Atty. Dkt. No.: 86349012WRITING RENEWAL CONFIGURATION DATA TO PRINT COMPONENT BACKGROUND

[0001] Fluid ejection devices deposit print fluid (e.g., ink, resin, biological materials, or other substances, etc.) onto a substrate (e.g., paper, powder, support structures, etc.) to print in two or three dimensions. The fluid ejection devices may be part of a replaceable component such as a fluid ejection cartridge, or part of a host device such as a printer. A fluid ejection die in the device may dispense the print fluid for printing based on logic of its integrated circuitry. The integrated circuitry may be part of the die. In certain instances, integrated circuitry can be provided separate from the die, attached to the fluid ejection device. The logic may use non-volatile memory cells which store an ID and / or parameters of the fluid ejection die for dispensing the print fluid.

[0002] An interconnect circuit may interface with a printer control interface and the print die to receive signals from and transmit signals to the printer control interface and the fluid ejection die. The interconnect circuit may comprise a thin (e.g., flexible) circuit including routing between the die and contacts that connect to the host. A fluid ejection cartridge may further include a reservoir to store print fluid. The fluid ejection die is to dispense the print fluid from the reservoir according to the logic based on signals received via the integrated circuit. The host controller may use the ID and parameters of the fluid ejection die to operate the fluid ejection device.

[0003] Toner cartridges may include similar integrated circuits including dispensing logic for dispensing toner. A toner cartridge can include a reservoir to store toner, where the dispensing logic determines how and / or when the toner cartridge dispenses toner. The integrated circuit of the toner cartridge can store, in memory cells, information such as how much toner is in the toner cartridge. In this way, print cartridges (e.g., fluid ejection cartridges, tonerAtty. Dkt. No.: 86349012 cartridges, etc.) can include integrated circuits that store information in memory cells and logic for dispensing fluids (e.g., print fluid, toner, etc.).BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. l is a block diagram of an example print component.

[0005] FIG. 2 is a block diagram of an example print component.

[0006] FIG. 3 is a block diagram of an example print component.

[0007] FIG. 4 is a block diagram of an example print component.

[0008] FIG. 5 illustrates a perspective view of an example fluid ejection cartridge.

[0009] FIG. 6 illustrates an example integrated circuit prior to singulation.

[0010] FIG. 7A is a block diagram of an example integrated circuit.

[0011] FIG. 7B is a block diagram of the integrated circuit of FIG. 7A with multiple memory cells written.

[0012] FIG. 8 is a block diagram of an example integrated circuit.

[0013] FIG. 9 is a block diagram of an example integrated circuit.

[0014] FIG. 10A illustrates an example set of signals for providing a passcode to an integrated circuit.

[0015] FIG. 10B illustrates a continuation of the set of signals of FIG. 10A for providing a response from the integrated circuit.

[0016] FIG. 11 is a flowchart of an example memory access protocol.

[0017] FIG. 12 is a block diagram of an example print component renewal apparatus.

[0018] FIG. 13 is a flow diagram illustrating operations of an example method for adding updated configuration data to a print component.Atty. Dkt. No.: 86349012

[0019] FIG. 14 is a block diagram of an example printer.

[0020] FIG. 15 is a flow diagram illustrating operations of an example method for adding renewal configuration data to a print component.

[0021] FIG. 16 is a flow diagram illustrating details of operations of the method of FIG. 15.

[0022] FIG. 17 is a flow diagram illustrating operations of an example method for using renewal configuration data of a print component.

[0023] The foregoing and other features of the present disclosure will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict several examples in accordance with the disclosure and are therefore, not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings.DETAILED DESCRIPTION

[0024] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative examples described in the detailed description, drawings, and claims are not meant to be limiting. Other implementations may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and made part of this disclosure.

[0025] This disclosure relates to print components, renewal apparatuses, and printers. Print components may include fluid ejection devices. Print components may include reservoirs to provide ink to a printhead. Print components may be print cartridges, or print cartridgeAtty. Dkt. No.: 86349012 components such as printheads or components comprising integrated circuitry to communicated with the host printer and / or printhead. Print components may be part of a host printer, to be permanently or temporarily fixed inside. Print components may include contacts and interconnect circuits to communicate with the host printer. The interconnect circuit may comprise thin, flexible circuitry with contacts and flexible routing, and / or a thin PCB. Integrated circuitry may be provided comprising memory elements and read / write logic. The integrated circuits may be part of the printhead or may be separate from the printhead. The printhead may include at least one fluid ejection die. The print component may be used in any field of high precision dispensing, including but not limited to the fields of 2D and 3D printing, digital titration, microfluidics, and other fields.A print component may be any component of print systems, such as an exchangeable print cartridge, or a component of a cartridge such as a fluid ejection device (e.g., printhead) or another integrated circuit associated with a cartridge. A print component may include a fluid ejection component for dispensing print fluid and a reservoir for storing the print fluid. The print fluid may include any 2D or 3D print agent including ink for printing on a medium such as paper (2D) or (e.g., powdered) build material (3D). The print fluid may include dispensable fluid to be dispensed at relatively high precision (as to volume and / or location) for fields of implementation other than 2D or 3D imaging, including but not limited to forensic, laboratory or pharmaceutical applications. While certain embodiments described in this application refer to cartridges and fluid ejection dies, certain aspects can be applied to any print component and any piece of integrated circuitry associated with the fluid ejection die.Renewal apparatuses may be used to update information stored on print components, (e.g., usage information, region information, etc.). The renewal apparatuses can be used to update the information stored on print components to reflect a current status of the print components e.g., refilled, refurbished, etc.). The renewal apparatuses may communicate with a server overAtty. Dkt. No.: 86349012 a network to receive the updated information, also referred to as renewal information. The renewal apparatuses may include authentication information such as a digital signature in the updated information. Printers may read the updated information stored on the print components to generate print commands for the print components and authenticate the updated information In this way, the renewal apparatuses may update the information stored on the print components such that the printers can authenticate the renewed print components without network connectivity.

[0026] In one example of this disclosure, a fluid ejection cartridge includes structures that record a renewal status of the fluid ejection cartridge. The fluid ejection cartridge can be renewed by refilling the fluid ejection cartridge and writing renewal configuration information to the fluid ejection cartridge. To indicate that the fluid ejection cartridge was properly renewed, a renewal status memory cell of the fluid ejection cartridge can be written. The fluid ejection cartridge can include passcode memory cells and passcode authentication logic to prevent unauthorized writes to the renewal status memory cell. In this way, the renewal status memory cell can be passcode protected, preventing improper or unauthorized writes to the renewal status memory cell.

[0027] The passcode memory cells can be used to compare a passcode received by a host device (e.g., printer) to a passcode stored in the passcode memory cells. The received passcode can be compared against the stored passcode bit by bit to ensure that the received passcode matches the stored passcode. Based on the received passcode matching the stored passcode, among other verifications performed by the fluid ejection cartridge, the fluid ejection cartridge can allow write access to the renewal status memory cell. A renewal apparatus or renewal system corresponding to a remanufacturing apparatus or remanufacturing system can write to the renewal status memory cell to indicate that the correct passcode was used in writing the renewal configuration data. By writing to the renewalAtty. Dkt. No.: 86349012 status memory cell, the renewal apparatus creates a record of the renewal of the fluid ejection cartridge within the fluid ejection cartridge itself. Thus, a host device, such as a printer, is not required to query a database, look up an identifier of the fluid ejection cartridge, or otherwise connect to a network in order to verify that the fluid ejection cartridge was properly renewed. The host device can read the renewal status memory cell to determine whether the fluid ejection cartridge was properly renewed, as the renewal status memory cell was written using the correct passcode.

[0028] This specification also recognizes that memory and / or functions of the fluid ejection die can be realized through separate integrated circuits, that communicate to the host device, and potentially to the fluid ejection die. These integrated circuits can comprise their own replacement memory cells, thin (interconnect) circuits including contacts, and routing that are to communicate with the host. These separate integrated circuits can be attached to a cartridge component (e.g., connected to the memory cells of the cartridge) to indicate a region, an ID, a fluid volume, a fluid level, nozzle addressing scheme, etc. of the print component, which may be different from the original data of the associated fluid ejection die. These integrated circuits may also be considered embodiments of print components of this disclosure, comprising the same logic, memory cells and functions as the fluid ejection die, except for the fluid ejection circuitry itself. Where the fluid ejection die includes logic and memory cells to inhibit data corruption, the integrated circuit that is not on the die but attached to the cartridge may be used to adapt, repurpose, re-regionalize, reset configuration bits, or reset certain other data (e.g., an address scheme) for the printer to accept the adapted cartridge.

[0029] FIG. 1 is a block diagram of an example integrated circuit 110. The integrated circuit 110 may be associated with a print component 100. In some implementations, the integrated circuit 110 is part of the print component 100. In some implementations, the integrated circuit 110 is attached to, or placed upon, the print component 100. The print component 100 mayAtty. Dkt. No.: 86349012 include a plurality of fluid ejection nozzles. In some implementations, the print component 100 is a fluid ejection die including a plurality of fluid ejection nozzles. The integrated circuit 110 can be part of the fluid ejection die or part of a same packaging as the fluid ejection die. In an example, the integrated circuit 110 is attached to a print cartridge including the fluid ejection die. In some implementations, the integrated circuit 110 includes a first contact to interface with a print component contact of the print component 100 and a second contact to interface with a printer contact. In an example, the integrated circuit 110 is a man-in-the- middle circuit that interfaces with the print component 100 and the printer in order to modify signals between the print component 100 and the printer.

[0030] The integrated circuit 110 includes a read and write circuit 111 and an authentication circuit 114 include passcode authentication logic 115. The read and write circuit 111 may be to receive a memory access protocol including an indication of an authentication mode. The memory access protocol may include a series of electrical signals. An example of the memory access protocol is illustrated in FIG. 11. The indication of the authentication may include one or more signals and / or the writing of one or more memory cells during the memory access protocol. The authentication mode may be to authenticate the integrated circuit 110 or print component 100, authenticate a status of the integrated circuit 110 or print component 100, and / or authenticate a host device (e.g., printer) of the print component 100.

[0031] The read and write circuit 111 may receive a passcode and, in response to the indication of the authentication mode, provide the received passcode to the passcode authentication logic of the authentication circuit 114. The passcode authentication logic 115 may determine whether or not the received passcode is correct. The authentication circuit 114 may make additional determinations as to whether additional authentication signals were received with the passcode and, in response to the passcode being correct, and the additional authentication signals being received, indicate to the read and write circuit 111 that theAtty. Dkt. No.: 86349012 passcode is correct. The additional authentication signals may include a logic high signal on a voltage line required to write to memory cells of the authentication circuit 114, a write to a memory cell of the authentication signal, and / or signals complementary to the passcode. In some implementations, the authentication circuit 114 includes a state machine to track signals received by the authentication circuit 114 and to perform logic checks based on the signals received by the authentication circuit 114.

[0032] The authentication circuit 114 can include a plurality of passcode memory cells containing a passcode. The passcode authentication logic 115 can use the passcode memory cells in determining whether or not the received passcode is correct. The passcode authentication logic 115 can compare the received passcode to the passcode stored in the plurality of memory cells to determine whether the received passcode is correct. In some implementations, the authentication circuit 114 includes one or more attempt memory cells. The attempt memory cells may track passcode verification attempts received by the authentication circuit 114. The authentication circuit 114 may determine whether to accept a passcode based on the status of the one or more attempt memory cells. In this way, only a finite number of attempts (e.g., three attempts for three attempt memory cells) are allowed when providing the passcode to the passcode authentication logic 115.

[0033] In some implementations, the authentication circuit 114 writes to one of the one or more attempt memory cells before comparing the received passcode to the passcode stored in the plurality of passcode memory cells. In this way, the authentication circuit 114 can prevent an attacker from guessing the passcode and then cutting power to the integrated circuit 110 to prevent a write to the one or more attempt memory cells. The authentication circuit 114 can read the attempt memory cell to determine that the attempt memory cell is unwritten, write to the attempt memory cell, and again read the attempt memory cell to determine that the write was successful, or that the attempt memory cell is written, prior to authenticatingAtty. Dkt. No.: 86349012 the received passcode.

[0034] In some implementations, the authentication circuit 114 can provide a response code to the read and write circuit 111. In some implementations, the authentication circuit 114 determines that the one of the one or more attempt memory cells is written before providing the response code to the read and write circuit 111. As noted above, the authentication circuit 114 can read, write, and then again read the attempt memory cell to ensure that the attempt memory cell is written. In some implementations, the authentication circuit 114, in response to the received passcode being incorrect, provides an incorrect response code to the read and write circuit 112. In other words, if the authentication circuit 114 determines that the received passcode is incorrect, the response code the authentication circuit 114 returns to the read and write circuit 111 is an incorrect response code. The incorrect response code can be a default incorrect response code. In an example, upon determining that the received passcode is incorrect, the authentication circuit 114 returns a response code of “11111” to the read and write circuit 111.

[0035] In some implementations, the authentication circuit 114 includes one or more renewal status memory cells. The authentication circuit 114 can, in response to the received passcode being correct, allow write access to the one or more renewal status memory cells. As the one or more renewal status memory cells are write-protected by the passcode, writing to the one or more renewal status memory cells can indicate that the print component 100 was renewed (e.g., refilled, reconfigured, etc.) by an authorized party who had access to the passcode. In some implementations, the authentication circuit 114 determines that one of the one or more attempt memory cells of the authentication circuit 114 is written before allowing write access to the one or more renewal status memory cells. As noted above, the authentication circuit 114 can read, write, and then again read the attempt memory cell to ensure that the attempt memory cell is written.Atty. Dkt. No.: 86349012

[0036] In some implementations, the authentication circuit 114 writes to one of the one or more attempt memory cells upon determining that the received passcode is not correct. The authentication circuit 114 may receive, with the received passcode, a complement code containing bits that are complementary to the bits of the received passcode. In an example, the complement code includes bits that are the opposite of the bits of the received passcode. In an example, the received passcode is “001010” and the complement code is “110101.” The authentication circuit 114 may compare the received passcode to the complement code to determine whether the bits of the complement code complement bits of the received passcode. Comparing the received passcode to the complement code can aid in identifying errors in the entry of the received passcode, as opposed to errors in the received passcode itself. The authentication circuit 114 can determine that the received passcode is incorrect, and write to the attempt memory cell in response to determining that the received passcode is not correct and determining that the bits of the complement code complement bits of the received passcode. In this way, the complement bits serve to ensure that the attempt memory cell is only written when an incorrect passcode is entered, as opposed to a correct passcode being entered, but not properly received. The authentication circuit 114 may unlock one or more nozzles of the print component 100 upon determining that the received passcode is correct and determining that the bits of the complement code complement bits of the received passcode. Requiring the bits of the complement code to complement the bits of the received passcode ensures that an incorrect passcode was not improperly received as the correct passcode.

[0037] In some implementations, the authentication circuit 114 unlocks one or more nozzles of the print component 100 upon determining that the received passcode is correct. In some implementations, the authentication circuit 114 unlocks the one or more nozzles of the print component 100 upon determining that the received passcode is correct and determining thatAtty. Dkt. No.: 86349012 the bits of the complement code complement bits of the received passcode. In this way, the passcode serves to active, or fully unlock the print component 100 upon verification of the passcode. In an example, half of the nozzles of the print component 100 are locked until successful authentication of the passcode. In this example, unlocking the half of the nozzles of the print component 100 allows fluid ejection commands to be sent to all of the nozzles of the print component 100 to cause them to eject print fluid. In some implementations, the nozzles of the print component 100 are unlocked as long as the print component 100 receives power. In an example, each time a printer powers up, the passcode must be authenticated to unlock the nozzles of the print component 100 coupled to the printer. In some implementations, the nozzles of the print component 100 are unlocked for a predetermined amount of time after authentication of the passcode, after which the nozzles are once again locked until the passcode is once again authenticated. In some implementations, the authentication circuit 114 includes a plurality of passwords, or a dynamic password, such that each authentication of the received passcode includes comparing the received passcode to a new passcode, or a passcode that is different from a previous passcode.

[0038] In some implementations, the authentication circuit 114 includes a lock memory cell. The authentication circuit 114 can use a status of the lock memory cell in determining whether the received passcode is correct. The lock memory cell can be in a proximity of at least one of the plurality of passcode memory cells containing the passcode and one or more attempt memory cells of the authentication circuit 114. In some implementations, the authentication circuit 114 includes a plurality of lock memory cells located adjacent various other bits, such as the passcode memory cells, the one or more attempt memory cells, and other bits. The lock memory cell can prevent a wipe of the memory cells of the integrated circuit 110. The authentication circuit 114 may require the lock memory cell to be written in order to authenticate the received passcode. As discussed herein, the lock memory cell may be write-Atty. Dkt. No.: 86349012 protected by a temporary electrical contact or electrical pad such that if the bits of the integrated circuit 110 are wiped in order to change the bits of the integrated circuit 110, the lock memory cell cannot be written and thus cannot be used to authenticate the received passcode. By being located in the proximity of the passcode memory cells or the one or more attempt memory cells, the lock memory cell can prevent wiping and re-writing of the passcode memory cells or the one or more attempt memory cells, as a wipe of those memory cells would wipe the lock memory cell within the proximity.

[0039] In some implementations, the authentication circuit 114 includes a voltage verification circuit to determine whether a voltage received by the integrated circuit 110 is above a predetermined threshold. In an example, the integrated circuit 110 receives power from a host device, such as a printer, for writing to memory cells of the integrated circuit 110. In this example, if a voltage received from the host device is not above the predetermined threshold, the integrated circuit 110 is unable to write to the memory cells of the integrated circuit 110, and so the authentication circuit 114 cannot write to the attempt memory cells. To prevent an attacker from guessing the passcode and then not allowing for a write to the attempt memory cells by using a reduced voltage or cutting power, the voltage verification circuit determines whether the voltage is above the predetermined threshold to inform the authentication circuit 114 as to whether to authenticate the passcode.

[0040] In some implementations, the authentication circuit 114 includes a clock verification circuit to determine whether a clock speed of the passcode is below a predetermined threshold. The clock verification circuit can determine whether a clock speed of any signals received or transmitted by the integrated circuit 110 is below the predetermined threshold. The predetermined threshold may represent normal clock operating speeds of the integrated circuit 110. By verifying the clock speed, the clock verification circuit can prevent an attacker from guessing the passcode at a high clock speed. In an example, an attempt memory cellAtty. Dkt. No.: 86349012 requires a predetermined amount of voltage for a predetermined amount of time to be written, such that a sufficiently high clock speed could cause a write to the attempt memory cell from being successful. To prevent this workaround, and to ensure that the passcode is properly entered and verified(and other signals), the clock verification circuit measures the clock speed to inform the authentication circuit 114 as to whether to authenticate the passcode.

[0041] In some implementations, the integrated circuit 110 includes a trace that extends to an edge of the integrated circuit 110. The authentication circuit 114 may require a logic high voltage on the trace to allow a write to and / or read the plurality of passcode memory cells, the lock memory cell, and / or other memory cells of the integrated circuit 110. The trace may be connected to a temporary electrical contact that is present during a first phase of manufacturing the integrated circuit 110 and then removed during a second phase of manufacturing the integrated circuit 110 such that the passcode memory cells, the lock memory cell, and / or other memory cells cannot be read and / or written after the first phase of manufacturing the integrated circuit 110. In this way, the passcode memory cells, the lock memory cell, and / or other memory cells are read and / or write protected after the first phase of manufacturing the integrated circuit 110.

[0042] FIG. 2 is a block diagram of an example integrated circuit 210. The integrated circuit 210 may be associated with a print component 200. In some implementations, the integrated circuit 210 is part of the print component 200. In some implementations, the integrated circuit 210 is attached to, or placed upon, the print component 200. The print component 200 may include a plurality of fluid ejection nozzles. In some implementations, the print component 200 is a fluid ejection die including a plurality of fluid ejection nozzles. The integrated circuit 210 can be part of the fluid ejection die or part of a same packaging as the fluid ejection die. In an example, the integrated circuit 210 is attached to a print cartridge including the fluid ejection die. In some implementations, the integrated circuit 210 includes a first contact toAtty. Dkt. No.: 86349012 interface with a print component contact of the print component 200 and a second contact to interface with a printer contact. In an example, the integrated circuit 210 is a man-in-the- middle circuit that interfaces with the print component 200 and the printer in order to modify signals between the print component 200 and the printer.

[0043] The integrated circuit 210 includes passcode authentication logic 215 and a renew status memory cell 216. The integrated circuit 210 may receive a memory access protocol including an indication of a renewal authentication mode. The renewal authentication mode may function to write to the renew status memory cell 216 to authenticate a renewal status of the print component 210. In an example, the print component 200 is refilled and the integrated circuit 210 is programmed with renewal configuration data, which is used by a printer to ensure proper functioning of the refilled print component 200. In this example, the renewal authentication mode may be triggered by the system that programs the integrated circuit 210 with the renewal configuration data in order to write to the renew status memory cell 216 which will indicate to a printer in which the print component 200 is installed that the renewal configuration data is authentic. The integrated circuit 210 may receive a passcode, and in response to the indication of the renewal authentication mode, determine, using the passcode authentication logic 215, whether or not the received passcode is correct. In response to the received passcode being correct, the integrated circuit 210 allows write access to the renew status memory cell 216.

[0044] In some implementations, the integrated circuit 210 includes a plurality of passcode memory cells containing a passcode. The passcode authentication logic 215 can determine whether the received passcode is correct by comparing the received passcode to the passcode stored in the plurality of passcode memory cells. The integrated circuit 210 can include one or more attempt memory cells. The attempt memory cells can track a number of passcode attempts. In some implementations, the integrated circuit 210 writes to one of the one or moreAtty. Dkt. No.: 86349012 attempt memory cells before comparing the received passcode to the passcode stored in the plurality of passcode memory cells. The integrated circuit 210 can determine that the attempt memory cell is written before allowing write access to the renewal status memory cell. As discussed herein, this can prevent an attacker from guessing the passcode and then cutting power to the integrated circuit 210 before the attempt memory cell can be written. In an example, the integrated circuit 210 reads the attempt memory cell to verify that it is unwritten, writes to the attempt memory cell, reads the attempt memory cell to verify that it is now written, and then authenticates the received passcode. In this way, each time a passcode is received by the integrated circuit 210, an attempt memory cell is written, whether or not the passcode is correct.

[0045] Similar to the integrated circuit 110 of FIG. 1, the integrated circuit 210 can include a lock memory cell. The integrated circuit 210 can allow write access to the renew status memory cell based on the lock memory cell being written. Similar to the integrated circuit 110 of FIG. 1, the lock memory cell can be located in a proximity of the plurality of passcode memory cells and / or the one or more attempt memory cells to prevent wiping and re-writing of those memory cells. Similar to the integrated circuit 110, the integrated circuit 210 can include a clock verification circuit to determine whether a clock speed of signals received by and transmitted by the integrated circuit 210 is below a predetermined threshold. Similar to the integrated circuit 110 of FIG. 1, the integrated circuit 210 can include a trace that extends to an edge of the integrated circuit 210, where the integrated circuit 210 requires a logic high voltage on the trace to allow a write to the plurality of passcode memory cells. The lock memory cell, the clock verification circuit, and the trace can be the same and / or function similar to the lock memory cell, the clock verification circuit, and the trace of the integrated circuit 110 of FIG. 1.

[0046] FIG. 3 is a block diagram of an example integrated circuit 310. The integrated circuitAtty. Dkt. No.: 86349012310 may be associated with a print component 300. In some implementations, the integrated circuit 310 is part of the print component 300. In some implementations, the integrated circuit 310 is attached to, or placed upon, the print component 300. The print component 300 may include a plurality of fluid ejection nozzles. In some implementations, the print component 300 is a fluid ejection die including a plurality of fluid ejection nozzles. The integrated circuit 310 can be part of the fluid ejection die or part of a same packaging as the fluid ejection die. In an example, the integrated circuit 310 is attached to a print cartridge including the fluid ejection die. In some implementations, the integrated circuit 310 includes a first contact to interface with a print component contact of the print component 300 and a second contact to interface with a printer contact. In an example, the integrated circuit 310 is a man-in-the- middle circuit that interfaces with the print component 300 and the printer in order to modify signals between the print component 300 and the printer.

[0047] The integrated circuit 310 includes passcode authentication logic 315 and a plurality of response memory cells 316 containing a response. The response may be used by a printer or by another system to authenticate the print component 300 based on the response matching an expected response. The integrated circuit 310 may receive a memory access protocol including an indication of a response authentication mode. The integrated circuit 310 receives a passcode and, in response to the indication of the response authentication mode, determines, using the passcode authentication logic 315, whether the received passcode is correct. In response to the received passcode being correct, the integrated circuit 310 provides the response stored in the plurality of response memory cells. In an example, a printer provides the passcode to the integrated circuit 310, the integrated circuit 310 authenticates the passcode and returns the response to the printer, and the printer compares the response to an expected response to authenticate the print component 300.

[0048] In some implementations, the integrated circuit 310 includes a plurality of passcodeAtty. Dkt. No.: 86349012 memory cells containing a passcode. The passcode authentication logic 315 can determine whether the received passcode is correct by comparing the received passcode to the passcode stored in the plurality of passcode memory cells. The integrated circuit 310 can include one or more attempt memory cells. The attempt memory cells can track a number of passcode attempts. In some implementations, the integrated circuit 310 writes to one of the one or more attempt memory cells before comparing the received passcode to the passcode stored in the plurality of passcode memory cells. The integrated circuit 310 can determine that the attempt memory cell is written before allowing write access to the renewal status memory cell. As discussed herein, this can prevent an attacker from guessing the passcode and then cutting power to the integrated circuit 310 before the attempt memory cell can be written. In an example, the integrated circuit 310 reads the attempt memory cell to verify that it is unwritten, writes to the attempt memory cell, reads the attempt memory cell to verify that it is now written, and then authenticates the received passcode. In this way, each time a passcode is received by the integrated circuit 310, an attempt memory cell is written, whether or not the passcode is correct.

[0049] In some implementations, the integrated circuit 310 includes a renew status memory cell similar to the renew status memory cell 216 of FIG. 2. The integrated circuit 310 can use the same passcode stored in the plurality of memory cells to authenticate the received passcode to allow write access to the renew status memory cell and to provide the response. The passcode authentication logic 315 can authenticate the same received passcode to allow write access to the renew status memory cell or to provide the response based on the memory access protocol indicating the renewal authentication mode or the response authentication mode, respectively.

[0050] Similar to the integrated circuit 110 of FIG. 1, the integrated circuit 310 can include a lock memory cell. The integrated circuit 310 can provide the response based on the lockAtty. Dkt. No.: 86349012 memory cell being written. Similar to the integrated circuit 110 of FIG. 1, the lock memory cell can be located in a proximity of the plurality of passcode memory cells and / or the one or more attempt memory cells to prevent wiping and re-writing of those memory cells. Similar to the integrated circuit 110, the integrated circuit 310 can include a clock verification circuit to determine whether a clock speed of signals received by and transmitted by the integrated circuit 310 is below a predetermined threshold. Similar to the integrated circuit 110 of FIG. 1, the integrated circuit 310 can include a trace that extends to an edge of the integrated circuit 310, where the integrated circuit 310 requires a logic high voltage on the trace to allow a write to the plurality of passcode memory cells. The lock memory cell, the clock verification circuit, and the trace can be the same and / or function similar to the lock memory cell, the clock verification circuit, and the trace of the integrated circuit 110 of FIG. 1.

[0051] FIG. 4 is a block diagram of an example integrated circuit 410. The integrated circuit 410 may be associated with a print component 400. In some implementations, the integrated circuit 410 is part of the print component 400. In some implementations, the integrated circuit 410 is attached to, or placed upon, the print component 400. The print component 400 may include a plurality of fluid ejection nozzles. In some implementations, the print component 400 is a fluid ejection die including a plurality of fluid ejection nozzles 420. The integrated circuit 410 can be part of the fluid ejection die or part of a same packaging as the fluid ejection die. In an example, the integrated circuit 410 is attached to a print cartridge including the fluid ejection die. In some implementations, the integrated circuit 410 includes a first contact to interface with a print component contact of the print component 400 and a second contact to interface with a printer contact. In an example, the integrated circuit 410 is a man-in-the- middle circuit that interfaces with the print component 400 and the printer in order to modify signals between the print component 400 and the printer.

[0052] The integrated circuit 410 includes passcode authentication logic 415. The passcodeAtty. Dkt. No.: 86349012 authentication logic 415 can activate or unlock the plurality of fluid ejection nozzles 420 of the print component 420. The integrated circuit 410 may receive a memory access protocol including an indication of an activation authentication mode. The integrated circuit 410 receives a passcode and, in response to the indication of the activation authentication mode, determines, using the passcode authentication logic 415, whether the received passcode is correct. In response to the received passcode being correct, the integrated circuit 410 generates one or more signals to activate at least a portion of the plurality of fluid ejection nozzles 420. In an example, a printer provides the passcode to the integrated circuit 410, the integrated circuit 410 authenticates the passcode and activates half of the plurality of fluid ejection nozzles 420 (the other half already activated), and the printer transmits print commands to cause the print component 400 to eject print fluid from the plurality of fluid ejection nozzles 420.

[0053] In some implementations, the integrated circuit 410 includes a plurality of passcode memory cells containing a passcode. The passcode authentication logic 415 can determine whether the received passcode is correct by comparing the received passcode to the passcode stored in the plurality of passcode memory cells. The integrated circuit 410 can include one or more attempt memory cells. The attempt memory cells can track a number of incorrect passcode attempts. In some implementations, the integrated circuit 410 writes to one of the one or more attempt memory cells upon determining that the received passcode is not correct. In this way, the attempt memory cells restrict a number of guesses an attacker has to guess the passcode, without restricting a number of times the plurality of fluid ejection nozzles 420 can be activated or unlocked. In some implementations, the plurality of fluid ejection nozzles 420 are unlocked each time the print component 400 is used, each time a host device (e.g., printer) is powered on, or at predetermined intervals. In some implementations, the integrated circuit 410 requires periodic passcode authentications to maintain the plurality of fluidAtty. Dkt. No.: 86349012 ejection nozzles 420 unlocked. As discussed herein, the integrated circuit 410 can include a plurality of stored passcodes and / or a dynamic passcode generator such that the received passcode must be updated in order to unlock the plurality of fluid ejection nozzles 420 in subsequent authentication attempts.

[0054] The integrated circuit 410 can receive, with the received passcode, a complement code. The complement code can include bits that complement (e.g., are the opposite of) the bits of the received passcode. In an example, the received passcode is “00100” and the complement code is “11011.” The integrated circuit 410 can compare the complement code to the received passcode to determine whether the bits of the complement code complement the bits of the received passcode. The integrated circuit 410 can determine that the received passcode is incorrect based on the passcode being incorrect and the complement code complementing the received passcode 410. The integrated circuit 410 can determine that the received passcode is correct based on the passcode being correct and the complement code complementing the received passcode 410. The integrated circuit 410 can determine that the received passcode was incorrectly received based the complement code not complementing the received passcode 410. The integrated circuit 410 can activate or unlock the plurality of fluid ejection nozzles 420 based on the received passcode being correct and the complement code complementing the received passcode and write to the attempt memory cell in response based on the received passcode not being correct and the complement code complementing the received passcode. In this way, the integrated circuit 410 reduces the chance of an incorrectly entered passcode (e.g., one bit is mis-transmitted) resulting in a write to the attempt bit.

[0055] In some implementations, the integrated circuit 410 includes an activation bit. The activation bit may indicate that the plurality of fluid ejection nozzles 420 are locked and that a passcode must be authenticated to unlock the plurality of fluid ejection nozzles 420. TheAtty. Dkt. No.: 86349012 activation bit may be written to the integrated circuit 410 during manufacturing of the integrated circuit 410. The activation bit may be written to the integrated circuit 410 after testing of the print component 400 to ensure proper functioning of the plurality of fluid ejection nozzles 420. The integrated circuit 410 may authenticate the received passcode and / or compare the received passcode to the passcode stored in the plurality of memory cells based on the activation bit being written. As discussed herein, the activation bit may be read and write protected by a temporary electrical contact.

[0056] In some implementations, the integrated circuit 410 includes a renew status memory cell similar to the renew status memory cell 216 of FIG. 2 and / or a plurality of response memory cells similar to the plurality of response memory cells 316 of FIG. 3. The integrated circuit 410 can use the same passcode stored in the plurality of memory cells to authenticate the received passcode to allow write access to the renew status memory cell and to provide the response. The passcode authentication logic 415 can determine how to authenticate the received password (e.g., which stored passcode to compare the received passcode to) based on the memory access protocol indicating the renewal authentication mode, the response authentication mode, or the activation authentication mode.

[0057] Similar to the integrated circuit 110 of FIG. 1, the integrated circuit 410 can include a lock memory cell. The integrated circuit 410 can provide the response based on the lock memory cell being written. Similar to the integrated circuit 110 of FIG. 1, the lock memory cell can be located in a proximity of the plurality of passcode memory cells, the one or more attempt memory cells, and / or the activation bit to prevent wiping and re-writing of those memory cells. Similar to the integrated circuit 110, the integrated circuit 410 can include a clock verification circuit to determine whether a clock speed of signals received by and transmitted by the integrated circuit 410 is below a predetermined threshold. Similar to the integrated circuit 110 of FIG. 1, the integrated circuit 410 can include a trace that extends toAtty. Dkt. No.: 86349012 an edge of the integrated circuit 410, where the integrated circuit 410 requires a logic high voltage on the trace to allow a write to the plurality of passcode memory cells. Similar to the integrated circuit 110 of FIG. 1, the integrated circuit 410 can include a voltage verification circuit to determine whether a voltage received by the integrated circuit 410 is above a predetermined threshold to prevent a low voltage from preventing writes to the attempt memory cell. The lock memory cell, the clock verification circuit, the trace, and the voltage verification circuit can be the same and / or function similar to the lock memory cell, the clock verification circuit, the trace, and the voltage verification circuit of the integrated circuit 110 of FIG. 1.

[0058] FIG. 5 illustrates a perspective view of an example fluid ejection cartridge 500. The fluid ejection cartridge includes a molded body 505. The molded body 505 may include a reservoir for holding print fluid. The fluid ejection cartridge 500 includes a fluidic structure 515 that includes an integrated circuit 520. In some implementations, the integrated circuit 520 is a fluid ejection die. The fluidic structure 515 is configured to receive the print fluid from the reservoir of the molded body 505 and provide the print fluid to the integrated circuit 520 for dispensing the print fluid. The integrated circuit 520 is electrically connected to a set of contacts 510 of interconnect circuitry, to receive signals from a host device (e.g., printer) for directing fluid ejection by the integrated circuit 520. The set of contacts 510 may be disposed along a surface of the molded body 505 such that a set of host device contacts can connect with the set of contacts 510 while the integrated circuit 520 dispenses print fluid. The set of contacts 510 may be electrically connected to the integrated circuit 520 via an interconnect circuit such as a thin and / or flexible circuit. The set of contacts 510 may be electrical pads configured to transmit electrical signals. In another embodiment, a similar circuit and / or set of contacts may be provided on a separate integrated circuit which includes the first and second plurality of memory cells, which integrated circuit is attachable orAtty. Dkt. No.: 86349012 attached to a fluid ejection device.

[0059] FIG. 5 illustrates an example fluidic structure assembly including a fluidic structure 515, an integrated circuit 520, and a set of contacts 510 connected to the integrated circuit 520 via an interconnect circuit. In some implementations, the integrated circuit 520 is, or is part of, a fluid ejection die. The set of contacts 510 may correspond to contacts on the integrated circuit 520. Bond wires 525 may electrically connect the set of contacts 510 to the corresponding contacts on the integrated circuit 520. As discussed herein, a write-enable contact, also referred to as a memory-protect contact, of the integrated circuit 520 may not be connected to the set of contacts 510 such that the host device, interfacing with the set of contacts 510, is unable to access the write-enable contact to write to write-protected memory cells.

[0060] FIG. 6 illustrates an example integrated circuit 620 prior to singulation. In some implementations, the integrated circuit 620 is, or is part of, a fluid ejection die. The integrated circuit 620 is formed on a substrate 602, such as silicon. A termination ring 601 on the substrate 602 defines a boundary of the integrated circuit 620. The integrated circuit 620 may be singulated (i.e., removed) from the substrate 602 at the termination ring 601. The substrate 602 may be scored, etched, and / or cut at or adjacent the termination ring 601 to singulate the integrated circuit 620. The integrated circuit 620 includes a plurality of nozzles 610 for ejecting print fluid. The plurality of nozzles 610 may eject print fluid in response to signals received via die contacts 621. The die contacts 621, when the integrated circuit 620 is singulated, may be electrically connected (e.g., using bond wires) to host-device-facing contacts of a fluid ejection cartridge, such as the contacts 510 of FIG. 5. The signals from the host device may include host device commands which are translated by die logic 622 into fluid ejector commands for the plurality of nozzles 610. The die logic 622 includes read and write logic as well as printing logic. The die logic 622 may use memory cells of the integratedAtty. Dkt. No.: 86349012 circuit 620 to translate the host device commands from the host device into fluid ejector commands for the plurality of nozzles 610. The die logic 622 may include circuitry (e.g., printing logic) configured to translate the host device commands from the host device into the fluid ejector commands for the plurality of nozzles 610. The die logic 622 may include circuitry (e.g., read and write logic) configured to enforce read and write access to the memory cells of the integrated circuit 620.

[0061] The integrated circuit 620 includes an authentication circuit 624. The authentication circuit 624 may include authentication information, such as a stored passcode. To prevent reads of and writes to the authentication information of the authentication circuit 624, a temporary contact 628 is applied to the substrate 602 outside of the termination ring 601 of the integrated circuit 620. The temporary contact 628 can provide a signal to the die logic 622 via a routing 627 to allow writes to the authentication information of the authentication circuit 624. The die logic 622 requires a logic high signal (e.g., a voltage) on the routing 627 to allow writes to the authentication information of the authentication circuit 624. In some implementations, the integrated circuit 620 includes a state machine to track signals received by the integrated circuit 620 and to perform logic checks based on the signals received by the integrated circuit 620.

[0062] The die logic 622 may require a set of signals (e.g., a memory access protocol) on the die contacts 621 as well as the logic high on the temporary contact 628 to read and write to the authentication information of the authentication circuit 624. As discussed in conjunction with FIG. 11, different contacts of the contacts of the die contacts 621 can be used for transmitting signals for writing to and reading memory cells. In an example, a first contact of the die contacts 621 (e.g., a sense contact) can be used to read the authentication information of the authentication circuit 624, and a second contact of the die contacts 621 (e.g., a fire contact or a data contact) can be used to write to the authentication information of theAtty. Dkt. No.: 86349012 authentication circuit 624, but only if the additional signal of the logic high on the temporary contact 628 is received. Thus, the die logic 622 requires a first write-enable signal, or set of signals (e.g., the memory access protocol) as well as the logic high on the temporary contact 628 to allow reads and writes to the authentication information of the authentication circuit 624.

[0063] In this way, the authentication information of the authentication circuit 624 is protected, as the die logic 622 requires a logic high on the temporary contact 628 to write to the authentication information of the authentication circuit 624. As the temporary contact 628 is outside the termination ring 601 of the integrated circuit 620, the temporary contact 628 will be separated from the integrated circuit 620 when the integrated circuit 620 is singulated, preventing reads of and writes to the authentication information of the authentication circuit 624 after the die is singulated.

[0064] The routing 627 and the temporary contact 628 may be a same material, and may be a same material as the die contacts 621. The die contacts 621 may be connected via die contact routings (not shown) between the die contacts 621 and the die logic 622. The die logic 622 may be connected via other routings (not shown) to the authentication circuit 624 and the plurality of nozzles 610. The routing 627, the temporary contact 628, the die contacts 621, the die contact routings, and the other routings may in a same plane of the integrated circuit 620. The routing 627, the temporary contact 628, the die contacts 621, the die contact routings, and the other routings may be a same material deposited on the substrate 602 at a same time. The routing 627, the temporary contact 628, the die contacts 621, the die contact routings, and the other routings may be separate routings which are physically and electrically separate from each other. The routing 627 is not connected to any of the die contacts 621. In this way, the host device commands, which are received via the die contacts 621 are unable to drive a logic high signal on the routing 627.Atty. Dkt. No.: 86349012

[0065] The authentication information of the authentication circuit 624 (e.g., passcode in a set of memory cells of the authentication circuit 624) may be written to prior to singulation of the integrated circuit 620. In this way, the authentication information of the authentication circuit 624 may be written to while the temporary contact 628 is connected to the die logic 622, allowing for writes to the authentication information of the authentication circuit 624. Testing of the integrated circuit 620 may be performed prior to singulation, when the temporary contact 628 is connected to the die logic 622. In this way, various memory cells, functionality, and / or modes of operation of the integrated circuit 620 may be restricted to access and / or use based on the presence of the temporary contact 628.

[0066] Applying the logic high signal to the temporary contact 628 to write to the authentication information of the authentication circuit 624 and / or to test the integrated circuit 620 may be part of a first phase of manufacturing the integrated circuit 620. The first phase of manufacturing the integrated circuit 620 may include wafer-level testing using the temporary contact 628 and / or programming configuration bits in the authentication information of the authentication circuit 624. Singulating the integrated circuit 620 from the substrate 602 may be part of a second phase of manufacturing the integrated circuit 620 after the first phase of manufacturing the integrated circuit 620.

[0067] FIG. 7A is a block diagram of an example integrated circuit 720. The integrated circuit 720 may be similar to the integrated circuit 210 of FIG. 2, allowing write access to a renewal status bit in response to authentication of a received passcode. The integrated circuit 720 includes an authentication circuit 724, a plurality of electrical contacts 721, and read / write logic 726. In some implementations, the integrated circuit 720 includes a state machine 728.

[0068] The plurality of electrical contacts 721 can be similar to the die contacts 621 of FIG. 6. The plurality of electrical contacts 721 include a sense contact 721a, a data contact 721b, and a clock contact 721c. While three contacts are shown, the plurality of electrical contactsAtty. Dkt. No.: 86349012721 can include additional contacts. The data contact 721b can receive data signals from a host device, such as a printer or renewal system. The clock contact 721c can receive a clock signal from the host device. The data signals received via the data contact 721b can be synchronized with the clock signal from the clock contact 721c in order to transmit data (e.g., information, passcodes, commands) from the host device to the integrated circuit 720. The data signals can include a memory access protocol to read and / or write to memory cells of the integrated circuit 720.

[0069] The read / write logic 726 can receive the data signals and the clock signals from the data contact 721b and the clock contact 721c, respectively. The read / write logic 726 can be part of die logic, such as the die logic 622 of FIG. 6, including read / write logic and printing logic. The read / write logic 726 can receive the memory access protocol via the plurality of electrical contacts 721 and determine whether to allow a read or write to memory cells identified in the memory access protocol. The memory access protocol can include an indications of an authentication mode, as discussed herein. In some implementations, the indication of the authentication mode can include writing to one or more memory cells of the integrated circuit 720. In an example, the integrated circuit 720 includes two memory cells that can each be represented by a “0” for unwritten and a “1” for written for identifying different authentication modes. In this example, a status of “01” of the two memory cells indicates a response authentication mode, a status of “10” indicates an activation authentication mode, and a status of “11” indicates a renewal authentication mode.

[0070] The read / write logic 726 can, in response to a successful memory access protocol, pass signals to the authentication circuit 724. The signals can include a passcode to be authenticated by the authentication circuit 724. In some implementations, the read / write logic 726 passes the signals to the authentication circuit 724 via the state machine 728. In some implementations, the state machine 728 tracks what authentication mode is being used andAtty. Dkt. No.: 86349012 what passcode bits have been provided to the authentication circuit 724.

[0071] The authentication circuit 724 includes a plurality of passcode memory cells 710. The plurality of passcode memory cells 710 can include a first passcode memory cell 710a, a second passcode memory cell 710b, a third passcode memory cell 710c, a fourth passcode memory cell 710d, a fifth passcode memory cell 710e, and a sixth passcode memory cell 71 Of. While the plurality of passcode memory cells 710 is illustrated as including six memory cells, more or fewer memory cells can be included in the plurality of passcode memory cells 710. The plurality of passcode memory cells 710 can store a passcode, where each memory cell of the plurality of passcode memory cells stores a single bit (e.g., 0 or 1) of the passcode.

[0072] When the passcode is being written (e.g., during manufacturing of the integrated circuit 720), the authentication circuit 724 can receive the passcode from the read / write logic 726 and cause the passcode to be written to the plurality of passcode memory cells 710. As discussed herein, the plurality of passcode memory cells 710 can be read / write protected by a temporary electrical contact. When the passcode is being authenticated, (e.g., during renewal of a print component associated with the integrated circuit 720), the authentication circuit 724 receives a passcode from the read / write logic 726 that was received from a host device. The authentication circuit 724 compares the received passcode to the passcode stored in the plurality of passcode memory cells 710. In some implementations, the received passcode is received one bit at a time and the authentication circuit 724 (e.g., passcode authentication logic of the authentication circuit 724) compares each received bit to a bit in a corresponding passcode memory cell of the plurality of passcode memory cells 710. The authentication circuit 724 can determine whether the received passcode is correct based on comparing the received passcode to the passcode stored in the plurality of passcode memory cells. In some implementations, the authentication circuit 724 indicates to the read / write logic 726 that the received passcode is correct and / or transmits a signal to the host device via theAtty. Dkt. No.: 86349012 sense contact 721a that the received passcode is correct.

[0073] The authentication circuit 724 includes a plurality of attempt memory cells 712. The plurality of attempt memory cells includes a first attempt memory cell 712a, a second attempt memory cell 712b, and a third attempt memory cell 712c. While the plurality of attempt memory cells 712 is illustrated as including three attempt memory cells, the plurality of attempt memory cells 712 can include any number of attempt memory cells. The plurality of attempt memory cells 712 can be renewal attempt memory cells indicating a number of times a passcode was provided to the authentication circuit 724 for authentication. The number of the plurality of attempt memory cells 712 can correspond to a number of times a print component associated with the integrated circuit 720 can be renewed, or refilled and programmed with renewal configuration data.

[0074] The authentication circuit 724 can require that one of the plurality of attempt memory cells 712 be written each time a passcode is provided to the authentication circuit 724 for authentication. In some implementations, the authentication circuit 724 reads an attempt memory cell, writes to the attempt memory cell, and then reads the attempt memory cell once more to verify that the attempt memory cell was unwritten prior to the write and was successfully written during the write. After the authentication circuit 724 verifies that the attempt memory cell was written, the authentication circuit 724 authenticates the received passcode. However, if there are no unwritten attempt memory cells in the plurality of attempt memory cells 712, the authentication circuit 724 does not authenticate the received passcode. In this way, a number of attempts to authenticate a passcode is limited by the number of the plurality of attempt memory cells 712. Similarly, a number of times the print component associated with the integrated circuit 720 can be renewed is limited by the number of the plurality of attempt memory cells 712.

[0075] The authentication circuit 724 includes a plurality of status memory cells 714. TheAtty. Dkt. No.: 86349012 plurality of status memory cells 714 include a first status memory cell 714a, a second status memory cell 714b, and a third status memory cell 714c. While the plurality of status memory cells 714 is illustrated as including three status memory cells, the plurality of status memory cells 714 can include any number of status memory cells. A number of the plurality of status memory cells 714 can be equal to the number of the plurality of attempt memory cells 712. Each of the plurality of status memory cells 714 can correspond to an attempt memory cell of the plurality of attempt memory cells 712. In this way, an attempt to authenticate a passcode and write to a stats cell of the plurality of status memory cells 714 can be correlated with an attempt memory cell of the plurality of attempt memory cells 712 and a status memory cell of the plurality of status memory cells 714.

[0076] In response to the received passcode being correct, as well as an attempt memory cell of the plurality of attempt memory cells 712 being successfully written, the authentication circuit 724 allows for (e.g., grants write access to) one of the plurality of status memory cells 714 to be written. In some implementations, the authentication circuit 724 includes a pulldown, where the authentication circuit 724 uses the pulldown to allow a write signal to reach the plurality of status memory cells 714. A written status memory cell of the plurality of status memory cells 714 can indicate that a print component associated with the integrated circuit 720 has been renewed and that renewal configuration data can be used in generating print commands. The plurality of attempt memory cells 712 and the plurality of status memory cells 714 can provide a record of renewal attempts. In an example, the first attempt memory cell 712a is written, the second attempt memory cell 712b is unwritten, the third attempt memory cell 712c is unwritten, the first status memory cell 714a is written, the second status memory cell 714b is unwritten, and the third status memory cell 714c is unwritten (as illustrated in FIG. 7B), indicating that a single successful renewal attempt was performed, where the authentication circuit 724 authenticated the received passcode and allowed writeAtty. Dkt. No.: 86349012 access to the first status memory cell 714a. In an example, the first attempt memory cell 712a is written, the second attempt memory cell 712b is written, the third attempt memory cell 712c is unwritten, the first status memory cell 714a is unwritten, the second status memory cell 714b is written, and the third status memory cell 714c is unwritten, indicating that a single unsuccessful renewal attempt was performed followed by a successful renewal attempt, where the authentication circuit 724 authenticated the received passcode and allowed write access to the second status memory cell 714b.

[0077] The authentication circuit 724 can include lock memory cells 716. The lock memory cells 716 can include a first lock memory cell 716a in a proximity of the plurality of passcode memory cells 710. The lock memory cells can include a second lock memory cell 716b in a proximity of the plurality of attempt memory cells 712. The lock memory cells 716 can include more or fewer lock memory cells than shown. The lock memory cells 716 can prevent wiping and rewriting of memory cells of the authentication circuit 724. As discussed herein, the lock memory cells 716 can be write protected using a temporary electrical contact such that the lock memory cells 716 cannot be written to after the temporary electrical contact is removed. Thus, if memory cells of the authentication circuit 724 are wiped and then rewritten, the lock memory cells 716 will indicate that the memory cells were wiped. In an example, an attacker wipes the plurality of passcode memory cells 710 to write a new passcode, and the first lock bit 716a, in the proximity of the plurality of passcode memory cells 710, is wiped as well due to its physical proximity. In some implementations, the plurality of passcode memory cells 710 are also read and write protected using the temporary electrical contact. In an example, an attacker wipes the plurality of attempt memory cells 712 to gain new authentication attempts, and the second lock bit 716b, in the proximity of the plurality of attempt memory cells 712, is wiped as well due to its physical proximity.

[0078] The authentication circuit 724 can include a clock verification circuit 718. The clockAtty. Dkt. No.: 86349012 verification circuit 718 can monitor a clock speed of the clock signal received via the clock contact 721a to determine whether the clock speed is within an acceptable range. In some implementations, the clock verification circuit 718 determines whether the clock speed is below a predetermined threshold. An overly high clock speed could be used to prevent writes to the plurality of attempt memory cells 712, as a predetermined amount of time is required to write to the plurality of attempt memory cells 712. The authentication circuit 724 can, based on the clock verification circuit 718 determining that the clock speed is too fast, not authenticate the received passcode.

[0079] The memory cells of the authentication circuit 724 (i.e., the plurality of passcode memory cells 710, the plurality of attempt memory cells 712, the plurality of status memory cells 714) can be non-volatile memory cells, such as floating-gate memory cells (e.g., floating-gate MOSFETs).

[0080] FIG. 7B is a block diagram of the integrated circuit of FIG. 7A with multiple memory cells written. The first attempt memory cell 712a and the first status memory cell 714a are written, indicating that one successful renewal attempt was performed, where the authentication circuit 724 determined that the received passcode was correct and allowed write access to the first status memory cell 714a. A host device, such as a printer, can read the first attempt memory cell 712a and the first status memory cell 714a to determine that the one successful renewal attempt was performed. The host device can use corresponding renewal configuration data in generating print commands based on determining that the one successful renewal attempt was performed. As discussed herein, different combinations of written memory cells of the plurality of attempt memory cells 712 and the plurality of status memory cells 714 can be used by the host device to determine an attempt history and renewal status of the print component associated with the integrated circuit 720.

[0081] FIG. 8 is a block diagram of an example integrated circuit 820. The integrated circuitAtty. Dkt. No.: 86349012820 can be similar to the integrated circuit 720, except that an authentication circuit 824 of the integrated circuit 820 includes a plurality of response memory cells 811 and a response attempt memory cell 813. The integrated circuit 820 includes a plurality of electrical contacts821 including a sense contact 821a, a data contact 821b, and a clock contact 821c similar to the plurality of electrical contacts 721 of FIG. 7 A, read / write logic 826 similar to the read / write logic 726 of FIG. 7, and can, in some implementations, include a state machine 828 similar to the state machine 728 of FIG. 7A. The authentication circuit 824 is similar to the authentication circuit 724 of FIG. 7A, except that the authentication circuit 824 includes the plurality of response memory cells 811 and the response attempt memory cell 813. The authentication circuit 824 includes a plurality of passcode memory cells 810 including a first passcode memory cell 810a, a second passcode memory cell 810b, a third passcode memory cell 810c, a fourth passcode memory cell 810d, a fifth passcode memory cell 810e, and a sixth passcode memory cell 81 Of. In some implementations, the authentication circuit 824 includes a plurality of attempt memory cells 812 including a first attempt memory cell 812a, a second attempt memory cell 812b, and a third attempt memory cell 812c similar to the plurality of attempt memory cells 712 of FIG. 7A and a plurality of status memory cells 814 including a first status memory cell 814a, a second status memory cell 814b, and a third status memory cell 814c similar to the plurality of status memory cells 714 of FIG. 7A. The authentication circuit 824 includes lock memory cells 816 including a first lock memory cell 816a and a second lock memory cell 816b similar to the lock memory cells 716 of FIG. 7A and a clock verification circuit 818 similar to the clock verification circuit 718 of FIG. 7 A.

[0082] The plurality of response memory cells 811 include a first response memory cell 811a, a second response memory cell 811b, a third response memory cell 811c, a fourth response memory cell 81 Id, a fifth response memory cell 81 le, and a sixth response memory cell 81 If. While the plurality of response memory cells 811 is illustrated including six response memoryAtty. Dkt. No.: 86349012 cells, the plurality of response memory cells 811 can include any number of response memory cells. The plurality of response memory cells 811 can store a response (e.g., response code), where each memory cell of the plurality of response memory cells 811 stores a single bit (e.g., 0 or 1) of the response. The plurality of response memory cells 811 can be similar to the plurality of response memory cells 316 of FIG. 3.

[0083] The response can be used to authenticate the integrated circuit 820, or a print component associated with the integrated circuit 820. In some implementations, the response is associated with an identifier of the print component. In an example, a host device reads the identifier of the print component, receives the response from the integrated circuit 820, and compares the response to an expected response based on the identifier to authenticate the print component. The authentication circuit 824 can receive a passcode as part of a response authentication mode. The authentication circuit 824 can compare the received passcode to the passcode stored in the plurality of passcode memory cells 810 to determine whether the passcode is correct. In response the response authentication mode, the authentication circuit 824 can provide the response stored in the plurality of response memory cells 811 to the host device. In an example, the authentication circuit 824 can provide the response to the host device via the sense contact 821a.

[0084] The authentication circuit 824 can write to the response attempt memory cell 813 each time the response authentication mode is used to attempt to authenticate the passcode to cause the response to be delivered to the host device. While the authentication circuit 824 is illustrated as including one response attempt memory cell 813, the authentication circuit 824 can include any number of response attempt memory cells. The authentication circuit 824 can write to the response attempt memory cell 813 during the response authentication mode similar to how the authentication circuit 824 writes to the plurality of attempt memory cells 812 during the renewal authentication mode, or similar to how the authentication circuit 724Atty. Dkt. No.: 86349012 of FIG. 7A writes to the plurality of attempt memory cells 712 of FIG. 7A during the renewal authentication mode. For example, the authentication circuit 824 can read the response attempt memory cell 813 to determine that the response attempt memory cell 813 is unwritten, write to the response attempt memory cell 813, read the response attempt memory cell 813 once again to ensure that the response attempt memory cell 813 is written and that the write was successful, and then authenticate the received passcode.

[0085] The authentication circuit 824 can use the same passcode stored in the plurality of passcode memory cells 810 to authenticate a received passcode in the response authentication mode and to authenticate a received passcode in the renewal authentication mode. The authentication circuit 824 can determine, based on the response authentication mode or the renewal authentication mode whether to return the response or allow write access to the plurality of status memory cells 814, respectively. In some implementations, the authentication circuit 824 includes a second plurality of passcode memory cells and the authentication circuit 824 uses the second plurality of passcode memory cells to authenticate a received passcode in the renewal authentication mode.

[0086] In some implementations, the authentication circuit 824 does not include the plurality of attempt memory cells 812 and the plurality of status memory cells 814. In this way, the authentication circuit 824 can provide the response authentication functionality of the response authentication mode described herein, but not the renewal authentication functionality of the renewal authentication mode described herein. If, as illustrated, the authentication circuit 824 includes the plurality of attempt memory cells 812 and the plurality of status memory cells 814, the authentication circuit 824 can provide the response authentication functionality of the response authentication mode described herein and the renewal authentication functionality of the renewal authentication mode described herein.

[0087] FIG. 9 is a block diagram of an example integrated circuit 910. The integrated circuitAtty. Dkt. No.: 86349012920 can be similar to the integrated circuit 720, except that an authentication circuit 924 of the integrated circuit 820 includes an activation cell 914, a voltage verification circuit 919, and a plurality of attempt memory cells 912 corresponding to unlock / activation passcode authentication attempts unlike the plurality of attempt memory cells 712 of FIG. 7A corresponding to renewal passcode authentication attempts, and does not include a plurality of status memory cells such as the plurality of status memory cells 714 of FIG. 7A. The integrated circuit 920 includes a plurality of electrical contacts 921 including a sense contact 921a, a data contact 921b, and a clock contact 921c similar to the plurality of electrical contacts 721 of FIG. 7 A, read / write logic 926 similar to the read / write logic 726 of FIG. 7, and can, in some implementations, include a state machine 928 similar to the state machine 728 of FIG. 7A. The authentication circuit 924 is similar to the authentication circuit 724 of FIG. 7 A, except that the authentication circuit 924 includes an activation cell 914, a voltage verification circuit 919, and a plurality of attempt memory cells 912 corresponding to unlock / activation passcode authentication attempts unlike the plurality of attempt memory cells 712 of FIG. 7A corresponding to renewal passcode authentication attempts. The authentication circuit 924 includes a plurality of passcode memory cells 910 including a first passcode memory cell 910a, a second passcode memory cell 910b, a third passcode memory cell 910c, a fourth passcode memory cell 910d, a fifth passcode memory cell 910e, and a sixth passcode memory cell 910f. The authentication circuit 924 includes lock memory cells 816 including a first lock memory cell 916a, a second lock memory cell 916b, and a third lock memory cell 916c similar to the lock memory cells 716 of FIG. 7A and a clock verification circuit 918 similar to the clock verification circuit 718 of FIG. 7 A.

[0088] The authentication circuit 924 can receive a passcode in an activation authentication mode, the activation authentication mode indicated by one or more bits in the memory access protocol received by the read / write logic 926. The authentication circuit 924 can determineAtty. Dkt. No.: 86349012 whether the received passcode is correct by comparing the received passcode to a passcode stored in the plurality of passcode memory cells 910. The authentication circuit 924 can receive a complement code including complement bits that complement bits of the received passcode. The authentication circuit 924 can compare the received passcode to the complement passcode to determine whether the complement code complements the received passcode. Upon determining that the complement code does not complement the received passcode, the authentication circuit 824 determines that at least one bit was incorrectly received or transmitted and does not write to one of the plurality of attempt memory cells 912. Upon determining that the complement code complements the received passcode and the received passcode is incorrect, the authentication circuit 924 writes to one of the plurality of attempt memory cells 912. In this way, the plurality of attempt memory cells 912 store a history of incorrect passcodes received by the authentication circuit 924 in the activation authentication mode, where the incorrect passcodes were verified as accurately transmitted using the corresponding complement codes.

[0089] Upon determining that the complement code complements the received passcode and the received passcode is correct, the authentication circuit 924 unlocks or activates fluid ejection nozzles of a print component associated with the integrated circuit 920. In some implementations, the authentication circuit 924 generates one or more signals to unlock or activate the fluid ejection nozzles of the print component. Unlocking or activating the fluid ejection nozzles of the print component allows the fluid ejection nozzles to eject print fluid in response to print commands, such as print commands received from a host device (e.g., printer).

[0090] The activation cell 914 indicates, when written, that fluid ejection nozzles of the print component are locked and that the activation authentication mode must be used to unlock the fluid ejection nozzles. The activation cell 914 may be written during manufacture of theAtty. Dkt. No.: 86349012 integrated circuit 920, or during manufacture of the print component to allow for testing of the print component before the activation cell 914 is written. The activation cell 914 may be read and / or write protected by a temporary electrical contact, as described herein. The activation cell 914, when written, may cause the authentication circuit 924 to lock a portion of the fluid ejection nozzles. The activation cell 914 may be protected by the third lock memory cell 916c in a proximity of the activation cell 914.

[0091] The voltage verification circuit 919 may monitor a voltage received from the host device during the activation authentication mode to determine whether the received voltage is above a predetermined threshold. The plurality of attempt memory cells 912 may require a predetermined amount of voltage to be written, allowing an attacker to provide less voltage to avoid a write to the plurality of attempt memory cells 912. To ensure that the plurality of attempt memory cells 912 can be written to if needed, the voltage verification circuit 919 monitors the received voltage to determine whether the received voltage is above the predetermined threshold. The authentication circuit 924 may not authenticate a correct received passcode in response to a determination by the voltage verification circuit 919 that the received voltage is too low.

[0092] In some implementations, the authentication circuit 924 includes a plurality of attempt memory cells, a plurality of status memory cell, and a plurality of response memory cells, similar to the authentication circuit 824 of FIG. 8. In this way, the authentication circuit 924 can provide the activation authentication functionality of the activation authentication mode described herein, the response authentication functionality of the response authentication mode described herein, the renewal authentication functionality of the renewal authentication mode described herein, or any combination of the three.

[0093] FIG. 10A illustrates an example set of signals 1000 for providing a passcode to an integrated circuit. The set of signals 1000 may be used to provide a passcode to any of theAtty. Dkt. No.: 86349012 integrated circuits described herein. The set of signals 1000 may be generated by a host device, such as a printer. The host device may provide the set of signals 1000 using a set of electrical contacts that interface with a set of electrical contacts of an integrated circuit such as the die contacts 621 of FIG. 6 or the plurality of electrical contacts 721 of FIG. 7 A. The set of electrical contacts can include a voltage / power contact, a clock contact, and a data contact, as well as other electrical contacts. The set of signals 1000 may be provided by the host device during the renewal authentication mode, the response authentication mode, and the activation authentication mode, as described herein. The set of signals 1000 may be provided after a successful memory access protocol indicating one of the renewal authentication mode, the response authentication mode, and the activation authentication mode.

[0094] The set of signals 1000 can include a voltage signal 1010, also referred to as a power signal. The voltage signal 1010 is high during the set of signals 1000. As discussed herein, the voltage signal 1010 may be used to provide power the integrated circuit to write to memory cells of the integrated circuit and may be monitored by a voltage verification circuit to ensure that the voltage signal 1010 is above a predetermined threshold.

[0095] The set of signals 1000 includes a clock signal 1020. The clock signal 1020 can be used to identify different bits within the set of signals 1000 and to synchronize the set of signals 1000. The clock signal 1020 can be monitored by a clock verification circuit to ensure that the clock signal 1020 has a clock speed below a predetermined threshold, as discussed herein. The clock signal 1020 can have a rising and falling voltage with a predetermined frequency.

[0096] The set of signals 1000 can include a renewal authentication data signal 1040a, a response authentication data signal 1040b, or an activation authentication data signal 1040c, collectively referred to as a data signal 1040. The data signal 1040 can be received via a dataAtty. Dkt. No.: 86349012 contact and can be either the renewal authentication data signal 1040a, the response authentication data signal 1040b, or the activation authentication data signal 1040c based on the renewal authentication mode, the response authentication mode, or the activation authentication mode, respectively.

[0097] A state signal 1030 may be included in the set of signals 1000 or may be interpretations / abstractions of the set of signals 1000 by the integrated circuit and / or by a state machine of the integrated circuit. The state signal 1030 can be based on the clock signal 1020 and can include labels for each count in the clock signal 1020. In an example, the state signal 1030 can include sixteen counts, where a rising voltage in the clock signal 1020 indicates a new count. In this example, the state signal 1030 includes sixteen labels corresponding to the sixteen counts of the state signal 1030.

[0098] The set of signals 1000 includes an attempt bit verification protocol 1001. The attempt bit verification protocol 1001 can include a read of an attempt memory cell followed by a write to the attempt memory cell followed by another read of the attempt memory cell. The attempt bit verification protocol 1001 can be used, as discussed herein, to verify that an attempt bit is unwritten prior to a write and to verify that the attempt bit is written after the write. The attempt bit verification protocol 1001 can be used, as discussed herein, during the renewal authentication mode and the response authentication mode, where attempt bits are written prior to passcode authentication. In some implementations, the attempt bit verification protocol 1001 is not used during activation authentication mode where attempt bits are written only for unsuccessful activation attempts.

[0099] The set of signals 1000 includes a passcode sequence 1002 during which bits of a passcode are received. During the activation authentication mode, the passcode sequence 1002 includes receiving the complement code with the passcode. While the passcode sequence 1002 is illustrated as including five passcode bits, the passcode can include anyAtty. Dkt. No.: 86349012 number of bits.

[0100] As discussed herein, only the activation authentication mode compares the complement code to the received passcode, so only the activation authentication data signal 1040c includes the bits of the complement code. The complement code complements the received passcode. In an example, if the zero passcode bit is “0,” the zero complement bit is “1,” and if the zero passcode bit is “1,” the zero complement bit is “0.”

[0101] The set of signals 1000 can include a turnaround bit in the state signal 1030. The turnaround bit signals the end of the passcode. The turnaround bit signals to the integrated circuit to return the response code in the response authentication mode.

[0102] FIG. 10B illustrates a continuation of the set of signals 1000 of FIG. 10A for providing a response from the integrated circuit. The continuation of the set of signals 1000 may be used in the response authorization mode for the integrated circuit to deliver the response to the host device. The set of signals 1000 can include a response sequence 1003 during which the integrated circuit returns a response to the host device in response to the passcode. The response authentication data signal 1040b is transmitted via a same channel (e.g., same trace, same electrical contacts) in FIGS. 10A and 10B, but with the host device driving the response authentication data signal 1040b in FIG. 10A and the integrated circuit driving the response authentication data signal 1040b in FIG. 10B. The response can include any number of bits.

[0103] In some implementations, the set of signals 1000 includes a read of a response delivered bit of the integrated circuit to verify that the response delivered bit is unwritten. In some implementations, the set of signals 1000 includes a write of the response delivered bit indicating that the response was delivered to the host device.

[0104] FIG. 11 is a flowchart of an example memory access protocol 1100. The memory access protocol 1100 may include more, fewer, or different operations than shown. TheAtty. Dkt. No.: 86349012 operations may be performed in the order shown, in a different order, or concurrently. While specific bits, signals, and circuit components such as registers are named, these specific elements are merely examples of more general components and elements that may also have the same results. The memory access protocol 1100 includes signals received at contacts of a fluid ejection cartridge.

[0105] At 1102, a non-volatile memory (NVM) enable bit is written in a configuration register of an integrated circuit (e.g., fluid ejection die). As used herein, the NVM-enable bit may refer to a bit to enable a floating gate avalanche metal oxide semiconductor (FAMOS) element that may act as a memory element. Other memory elements capable of storing and switching between at least two states of a bit of information may also be used. The writing of the NVM-enable bit to a configuration register may also refer to other examples of other storage elements other than registers. The configuration register may be replaced by other circuitry or data organization methods capable of receiving and storing information such as the NVM-enable bit for a configuration circuit within the integrated circuit.

[0106] At 1104, nozzle data is loaded to the integrated circuit. The nozzle data may include information for setting the NVM-enable bit in the data stream as well as the information for selecting a nonvolatile memory (NVM) bit to access using a specific address for a nozzle.

[0107] The nozzle data may indicate a selection of which nozzle circuits are to be fired in response to an upcoming fire signal. The selection of which nozzle circuits are to be fired next can be stored in nozzle memory bits (e.g., flops or latches) corresponding to the nozzle circuits. In an example, the selection data includes a corresponding NVM-enable bit in the nozzle selection data. In an example, the NVM-enable bit may be transmitted in a header or footer of the nozzle selection data. In some implementations, the selection data includes bankselect bits, indicating in which memory bank the selected bits are located in the integrated circuit.Atty. Dkt. No.: 86349012

[0108] As noted above, 1102 and 1104 may be done in either order. The result of these two steps is that the NVM-enable bit is written into the configuration register and the NVM-enable bit is set.

[0109] At 1106, a fire signal is driven to signal high then low. The fire signal may be received at a fire contact of the contacts of the fluid ejection cartridge. The fire signal may be a signal that is sent to each nozzle circuit of the integrated circuit. The bits of the registers may be electrically connected to the nozzle circuits and the fire contact which results in actions being taken at the configuration register when signals are sent using the fire contact. A signal being driven high then low may refer to an amplitude of the signal roughly corresponding to the intensity of the signal whether it is a current or voltage. In an example, driving a fire signal high can be interpreted as a value of 1, while a fire signal driving low or not at all can be interpreted as having a value of 0. These high and low values may be referred to as “logic high” and “logic low,” respectively. In an example, the fire signal drives from 0 to 1 to 0. The variation in the signaling can indicate when an action, such as firing nozzles, or activating memory bits (in a memory access mode), should take place. The driving of the fire contact from high to low may clear the NVM-enable bit of the configuration register. The driving of the fire contact from high to low may set a latch within the integrated circuit. This internal latch combined with future signaling may enable a memory bit access.

[0110] At 1108, an NVM-enable bit is written in a configuration register. This is the same action as at 1102, but at 1108, the internal latch has been set and the NVM-enable bit was cleared in the configuration register. Writing the NVM-enable bit again into the configuration register, while the NVM-enable bit is being transmitted using a data contact of the contacts of the fluid ejection cartridge enables access to a memory access bit in a memory configuration register.[OHl] At 1110, the memory access bit is written in the memory configuration register. TheAtty. Dkt. No.: 86349012 memory configuration register can be another storage element separate from the configuration register. In some examples there are fewer bits in the memory configuration register than the configuration register. Once the memory access bit is written into the memory configuration register, the memory of the integrated circuit may be accessed. The enabled bits of the memory configuration register can act as control signals that enable the NVM or FAMOS memory elements to be accessed.

[0112] In some embodiments, operation 1110 includes writing authentication mode bits in the memory configuration register to indicate an authentication mode such as the renewal authentication mode, the response authentication mode, and the activation authentication mode, as described herein.

[0113] At decision 1112, a determination is made based on the control signals indicated by the bits of the memory configuration register, as written at 1110. If the bits of the memory configuration register indicate a memory write, the memory access protocol 1100 proceeds to 1114. If the bits of the memory configuration register do not indicate a memory write, the memory access protocol 1100 proceeds to 1116.

[0114] At 1114, the fire contact is driven high for a desired write time, then low. In an example, the driving of the fire contact can include providing a 0 signal, then a 1 signal, then a 0 signal. The value of the signal can correspond to a current or voltage on the fire contact. During the duration of the write time, the memory element, such as a FAMOS, may be accessed. Accessing the FAMOS or other memory element can include writing information into the FAMOS or memory element.

[0115] At 1116, the fire contact may be driven high and a voltage or current forced on a sense contact of the contacts of the fluid ejection cartridge for measurement, then returning the fire contact to a low signal. During the duration of the read time, the memory element (e.g.,Atty. Dkt. No.: 86349012FAMOS), may be accessed. A current or voltage response on the sense contact may indicate a value (e.g. programming level) of the memory element. Whether proceeding through 1114 or 1116, the falling edge of the fire signal clears the memory configuration register and clears the NVM-enable bit of the configuration register.

[0116] FIG. 12 is a block diagram of an example print component renewal apparatus 1200. The example print component renewal apparatus 1200 includes a set of electrical contacts 1210, a processor 1220, and a memory 1230.

[0117] The set of electrical contacts 1210 are to interface with a print component 1240. The set of electrical contacts 1210 can include electrical contacts corresponding to electrical contacts of the print component 1240. The set of electrical contacts 1210 can send electrical signals to the print component 1240 and receive electrical signals from the print component 1240. The electrical signals can be used to read data from memory cells of the print component 1240 and / or to write data to the memory cells of the print component 1240. The electrical signals can provide power to the print component 1240 for performing calculations, writing to memory cells, and other operations.

[0118] The memory 1230 can include a non-transitory, computer-readable medium. The memory 1230 can store instructions that cause the processor 1220 to generate electrical signals to be transmitted to the print component 1240 using the set of electrical contacts 1210. The processor 1220 can transmit, using the set of electrical contacts 1210, a renewal passcode to the print component 1240. The renewal passcode can be authenticated by the print component 1240. The renewal passcode can be stored in a plurality of passcode memory cells of the print component 1240. The print component 1240 can authenticate the renewal passcode by comparing the renewal passcode received from the print component renewal apparatus 1200 to the renewal passcode stored in the plurality of passcode memory cells.Atty. Dkt. No.: 86349012

[0119] In response to authenticating the renewal passcode, the print component 1240 allows write access to a renewal status memory cell of the print component 1240. The processor 1220 can write, using the set of electrical contacts 1210, a renewal status bit to the renewal status memory cell of the print component 1240. In this way, the print component renewal apparatus 1200 is able to write the renewal status bit to the password protected renewal status memory cell to indicate that the print component 1240 was properly renewed.

[0120] The processor writes, using the set of electrical contacts 1210, renewal configuration data to the print component 1240. The renewal configuration data may include a fill level (e.g., amount of print fluid) of the print component 1240, an expected lifetime of the print component 1240, and / or a region identifier of the print component 1240. The renewal configuration data can be written to memory cells of the print component 1240 that are not protected by a passcode, but which are associated with the renewal status memory cell of the print component 1240 to indicate that the renewal configuration data was written using the passcode.

[0121] In some implementations, the processor 1220, using the set of electrical contacts 1210, reads a print component identifier of the print component 1240. The print component identifier may be a unique identifier of the print component 1240. The processor 1220 transmits a renewal request including the print component identifier to a server. The server can store print component identifiers and corresponding renewal passcodes. The server can be associated with a manufacturer of the print component 1240. The server, in response to the renewal request including the print component identifier of the print component 1240, transmits the renewal passcode to the print component renewal apparatus 1200. The processor 1220 receives, from the server, in response to the renewal request, the renewal passcode.

[0122] The server can determine, based on the renewal request and / or an identity of the print component renewal apparatus 1200, whether to send the renewal passcode. In this way, theAtty. Dkt. No.: 86349012 server can transmit the renewal passcode based on the print component renewal apparatus 1200 being authorized to renew the print component 1240 and / or the renewal request including credentials, a token, or password indicating authorization to renew the print component 1240. The print component renewal apparatus 1200 can include a data interface to send and receive data from the server. The print component renewal apparatus 1200 can use the data interface to communicate with the server via a network, such as the Internet.

[0123] In some implementations, the print component renewal apparatus 1200 authenticates itself to the server by signing data (e.g., a nonce) provided by the server using a private key (e.g., string of characters) for which the server has the corresponding public key. The print component renewal apparatus 1200 can transmit the signed data to the server so the server can authenticate the print component renewal apparatus 1200 (e.g., authenticate the renewal request) based on the print component renewal apparatus 1200 having the private key. In some implementations, the print component renewal apparatus 1200 authenticates itself to the server by providing an identifier of the print component renewal apparatus 1200 to the server. The server can identify the identifier in a list of authorized renewal systems to authenticate the print component renewal apparatus 1200.

[0124] In some implementations, the processor 1220 transmits a renewal request including information corresponding to the renewal configuration data (e.g., a target configuration) to a server. The processor 1220 receives, from the server, in response to the renewal request, the renewal configuration data. The information corresponding to the renewal configuration data can describe a target configuration for the print component 1240, while the renewal configuration data can encode the target configuration in a form compatible with a host device, such as a printer. In an example, the information corresponding to the renewal configuration data includes a description of a fill level and the renewal configuration data received from the server includes addresses of memory cells of the print component 1240 toAtty. Dkt. No.: 86349012 be programmed (i.e., written to) to encode the fill level as renewal configuration data in the memory cells of the print component 1240. In this way, the print component renewal apparatus 1200 can, using the server, translate the information corresponding to the renewal configuration data into the renewal configuration data.

[0125] In some implementations, the server transmits, to the print component renewal apparatus 1200, in response to the renewal request, the renewal configuration data, the renewal passcode, and instructions to: transmit the renewal passcode to the print component 1240, write the renewal status bit to the print component 1240, write the renewal configuration data to the print component 1240, and write the renewal data bit to the print component 1240. The instructions can include a set of signals to be transmitted to the print component 1240 to transmit the renewal passcode, write the renewal status bit, write the renewal configuration data, and / or write the renewal data bit. In this way, the server can provide to the print component renewal apparatus all the data for the print component renewal apparatus 1200 to transmit the renewal passcode to the print component 1240, write the renewal status bit to the print component 1240, write the renewal configuration data to the print component 1240, and write the renewal data bit to the print component 1240.

[0126] In some implementations, the renewal configuration data includes a digital signature based on the print component identifier of the print component 1240. The digital signature can be computed over data using a secret key. The data over which the digital signature is computed can include portions of the renewal configuration data such as the fill level, the region, and the identifier of the print component 1240. In some implementations, the renewal configuration data includes functional renewal configuration data (i.e., fill level, region, identifier, etc.) and the signature, where the signature is computed over the functional renewal configuration data. The digital signature can be written to the memory cells of the print component 1240 as part of the renewal configuration data. A host device can verify theAtty. Dkt. No.: 86349012 renewal configuration data using the digital signature.

[0127] Computing the digital signature can include using a secret key. A host device can use the same key (if a symmetric digital signature algorithm is used) or a different key (if an asymmetric digital signature algorithm is used ) to validate the digital signature. In an example where a symmetric digital signature algorithm is used, the host device reads the print component identifier of the print component 1240 and uses the functional renewal configuration data (including the print component identifier) and the secret key to generate a digital signature to verify that the received digital signature corresponds to (e.g., matches) the generated digital signature. In this way, the renewal configuration data can be verified in multiple ways: using the passcode protected renewal status memory cell, and using the digital signature based on the print component identifier.

[0128] In some implementations, the processor 1220 writes, using the set of electrical contacts 1210, a renewal data bit to the print component 1240, the renewal data bit indicating that the print component 1240 includes the renewal configuration data. The renewal data bit can be written to a renewal data memory cell of the print component 1240. The renewal data memory cell can be part of original configuration data of the print component 1240. In this way, a host device, such as a printer, can read the original configuration data and identify that the print component 1240 includes the renewal configuration data based on the renewal data bit being written to the renewal data memory cell.

[0129] FIG. 13 is a flow diagram illustrating operations of an example method 1300 for adding updated configuration data to a print component. The updated configuration data can also be referred to as “renewal configuration data.” The method 1300 may be performed by the print component renewal apparatus 1200 of FIG. 12. The method 1300 may be performed by a processor. The processor can execute instructions stored in a non-transitory, computer- readable medium to perform the method 1300. The method 1300 may include more, fewer,Atty. Dkt. No.: 86349012 or different operations than illustrated. The operations may be performed in the order shown, in a different order, or concurrently.

[0130] At operation 1310, a set of signals including an update passcode are transmitted to a print component using a set of electrical contacts to interface with electrical contacts of the print component. The update passcode can correspond to the renewal or received passcode described herein. The update passcode can be authenticated by the print component to allow write access to an update memory cell of the print component. The update passcode can be authenticated by the print component by comparing the update passcode as stored in memory cells of the print component to the transmitted update passcode. In response to authenticating the update passcode, the print component can allow write access to an update memory cell of the print component.

[0131] At operation 1320, an update status bit is written to the print component using the set of electrical contacts after the renewal update passcode is transmitted to the print component. The update status bit can be written to the update memory cell of the print component. The update memory cell can be written by applying voltage to the update memory cell in order to write the update status bit to the update memory cell. The update status bit can indicate that the update passcode was authenticated by the print component and can correspond to an update of configuration data of the print component. A host device, such as a printer, can read the update status bit (e.g., read that the update memory cell is written or programmed) of the print component to verify that updated configuration data of the print component is valid, or was written by an authorized update system.

[0132] At operation 1330, updated configuration data is written to the print component using the set of electrical contacts. The updated configuration data can be written to memory cells of the print component. The updated configuration data can be the same or different from original configuration data of the print component. The updated configuration data can be theAtty. Dkt. No.: 86349012 same as the original configuration data, but with an updated fill status (e.g., indication of how much print fluid is in the print component). The fill status can be indicated using memory bits written to memory cells that are written as print fluid is dispensed from the print component. In this way, the fill status is similar to a gas gauge in that it indicates how much print fluid is left relative to a total fill level of the print component. In an example, the original configuration data of the print component indicates a high fill level, a North American region, and an empty status of the print component, while the updated configuration data indicates the high fill level, the North American region, and a full status of the print component. In an example, the original configuration data indicates a low fill level, a European region, and an empty status of the print component, while the updated configuration data indicates a high fill level, a North American region, and a full status of the print component.

[0133] In some implementations, the method 1300 includes reading, using the set of electrical contacts, an identifier of the print component, transmitting an update request including the identifier to a server, and receiving, from the server, in response to the update request, the update passcode. The identifier of the print component can be a unique identifier of the print component and can be associated with the update passcode in a database or server system. The server can query the database or otherwise use the association between the identifier of the print component and the update passcode to return the update passcode in response to the update request including the identifier. The server can verify that the update request is authorized based on a content of the update request, an identity of a system transmitting the update request, and / or a digital signature included in the update request. In this way, the server can return the update passcode in response to authorized requests. The identity of the system transmitting the update request can be determined based on an identifier of the system included in the update request. In some implementations, the updated configuration data includes the identifier of the system. A host device reading or using the updated configurationAtty. Dkt. No.: 86349012 data can display the identifier of the system.

[0134] In some implementations, the method 1300 includes transmitting a renewal request including a target update status to the server and receiving, from the server, in response to the renewal request, the renewal configuration data. The target update status can be a target configuration and can describe a target status of the print component upon completion of the update to the configuration data of the print component. The server can translate the target update status into the renewal configuration data for writing to the print component. In this way, the server can translate the target update status into bits to be written to memory cells of the print component.

[0135] In some implementations, the updated configuration data includes a digital signature based on an identifier of the print component and / or other data of the updated configuration data. The digital signature can be computed over data using a secret key. The data over which the digital signature is computed can include portions of the renewal configuration data such as the fill level, the region, and the identifier of the print component 1240. In some implementations, the renewal configuration data includes functional renewal configuration data (i.e., fill level, region, identifier, etc.) and the signature, where the signature is computed over the functional renewal configuration data. The digital signature can be included in the updated configuration data that is written to the print component.

[0136] The host device can verify the updated configuration data using the digital signature. In an example, a secure microcontroller of the host device uses the print component identifier, the functional updated configuration data, and the secret key to generate a digital signature to determine whether the generated digital signature corresponds to (e.g., matches) the received digital signature. In this way, the host device can verify the updated configuration data in multiple ways: using the passcode protected update status bit, and using the digital signature.Atty. Dkt. No.: 86349012

[0137] In some implementations, the method 1300 includes writing, using the set of electrical contacts, an update data bit to the print component, the update data bit indicating that the print component includes the updated configuration data. The update data bit can be written to an update data memory cell of the print component that is part of, or associated with, original configuration memory cells or original configuration memory data of the print component. In this way, the host device can read the original configuration data including the update data bit to identify that the print component includes the renewal configuration data, or that the print component has been updated.

[0138] FIG. 14 is a block diagram of an example printer 1400. The printer 1400 includes a secure microcontroller 1410, a processor 1420, and a memory 1430. The printer 1400 can interface with a print component 1440. The printer 1400 can be a host device of the print component 1440 where the printer 1400 generates print commands for the print component 1440. The printer 1400 can generate print commands for the print component 1440 based on original configuration data and / or updated configuration data of the print component 1440.

[0139] The memory 1430 can include a non-transitory, computer-readable medium. The memory 1430 can store instructions that cause the processor 1420 to generate electrical signals to be transmitted to the print component 1440 and receive electrical signals from the print component 1440 using a set of electrical contacts of the printer 1400. The set of electrical contacts of the printer 1400 can interface with electrical contacts of the print component 1440.

[0140] The processor 1420 reads original configuration data of the print component 1440. The original configuration data can include a region, a fill level, an expected lifetime, and / or a fill status. The original configuration data can include a renewal data bit indicating that the print component 1440 includes renewal configuration data. In response to the renewal data bit of the original configuration data being written, the processor 1420 can read renewal status bits and renewal attempt bits of the print component 1440. The renewal status bits and theAtty. Dkt. No.: 86349012 renewal attempt bits can store a record of successful and unsuccessful attempts to write to renewal status memory cells of the print component 1440, as described herein.

[0141] In response to a combination of the renewal status bits and the renewal attempt bits of the print component 1440 being valid, the processor 1420 verifies, using the secure microcontroller 1410, whether renewal configuration data of the print component is valid. The processor 1420 can confirm that the combination of the renewal status bits and the renewal attempt bits of the print component 1440 are valid based on the combination indicating that an attempt bit of the renewal attempt bits was written each time a passcode is presented to the print component (e.g., an attempt was made to write a renewal status bit of the renewal status bits). As described herein, the print component may write an attempt bit each time an attempt is made to write to a renewal status bit. The printer 1400 can confirm that this process was followed without interference by confirming that the renewal status bits and the renewal attempt bits of the print component 1440 reflect this process.

[0142] The processor 1420 can confirm whether the renewal configuration data of the print component 1440 is valid by verifying a digital signature stored in memory cells of the print component. The digital signature can be part of the renewal configuration data, or associated with the renewal configuration data. The digital signature can be computed over an identifier of the print component 1440 included in the original configuration data of the print component as well as a portion of the renewal configuration data. The original configuration data includes the identifier of the print component 1440 to uniquely identify the print component 1440. The processor 1420 verifies, using the secure microcontroller 1410, whether the renewal configuration of the print component is valid by verifying whether the digital signature was computed over the identifier of the print component and the portion of the renewal configuration data.

[0143] The digital signature can be generated by using a key to compute the digital signatureAtty. Dkt. No.: 86349012 over the portion of the renewal configuration data other than the digital signature, also referred to as functional renewal configuration data. The secure microcontroller 1410 can use the same key used to generate the digital signature to generate a digital signature. The secure microcontroller 1410 compares the digital signature generated by the secure microcontroller 1410 to the digital signature included in the renewal configuration data to verify that the digital signatures match.

[0144] In response to the renewal configuration data of the print component being valid, the processor 1420 generates print commands based on the renewal configuration data. Generating print commands based on the renewal configuration data can include using the fill level and / or fill status to estimate an amount of print fluid in the print component 1440. The original print configuration data can include memory bits written in memory cells that can be written, but not erased, such that a use gauge of the print component 1440, once filled, cannot be reset. However, by using the renewal configuration data, including a new use gauge, the printer 1400 can generate print commands for the print component based on the renewed status (e.g., refilled) of the print component 1440.

[0145] In some implementations, the processor 1420 confirms, based on the renewal data bit being set, that the print component 1440 is a renewed print component. The processor 1420 can confirm, based on the renewal configuration data of the print component 1440 being valid, that the print component 1440 is a valid renewed print component. In this way, the processor 1420 can confirm the renewal status of the print component 1440 as a renewed print component and / or as a valid renewed print component. The printer 1400 can generate print commands based on the print component 1440 being a renewed print component and / or a valid renewed print component. In an example, the printer 1400 can generate print commands for a first renewed print component that is not a valid renewed print component (i.e., does not include valid renewal attempt and renewal status bits and / or does not include valid renewalAtty. Dkt. No.: 86349012 configuration data) with a lower degree of certainty as to an amount of print fluid in the first print component and the printer 1400 can generate print commands for a second renewed print component that is a valid renewed print component with a higher degree of certainty as to an amount of print fluid in the second print component.

[0146] The printer 1400 generates print commands for the print component 1440 based on the original configuration data or the renewal configuration data. If the renewal data bit of the original configuration data is not written, the printer 1400 generates print commands using the original configuration data. If the renewal data bit is written, but the combination of the renewal status bits and the renewal attempt bits is not valid, the printer 1400 generates print commands using the original configuration data. If the renewal data bit is written, the combination of the renewal status bits and the renewal attempt bits is valid, but the renewal configuration data is not valid, the printer 1400 generates print commands using the original configuration data. If the renewal data bit is written, the combination of the renewal status bits and the renewal attempt bits is valid, and the renewal configuration data is valid, the printer 1400 generates print commands using the renewal configuration data.

[0147] FIG. 15 is a flow diagram illustrating operations of an example method 1500 for adding renewal configuration data to a print component. The method 1500 may be performed by the print component renewal apparatus 1200 of FIG. 12. The method 1500 may include more, fewer, or different operations than shown. The operations may be performed in the order shown, in a different order, or concurrently.

[0148] At operation 1502, an empty print cartridge is acquired. The empty print cartridge was used within a host device, such as a printer, to dispense print fluid. As the print cartridge dispensed print fluid, memory cells of the print cartridge were written to indicate use of the print cartridge and to track a fill status (e.g., amount of print fluid) of the print cartridge. As the print cartridge was emptied, the memory cells were written to indicate that the print fluidAtty. Dkt. No.: 86349012 of the print cartridge had been used, allowing the host device to generate an alert that the print cartridge was empty. To refill the print cartridge, new print fluid is added to the print cartridge. In order for a host device to recognize the new fill status of the print cartridge, new data (i.e., the renewal configuration data) is written to memory cells of the print cartridge.

[0149] At operation 1504, the empty print cartridge 1502 is sorted. The method 1500 can be applied to hundreds and thousands of empty print cartridges, and the print cartridges can be sorted according to type, condition, compatibility, age, and other characteristics. In response to the empty print cartridge being of an incorrect type, in bad condition, over a predefined age threshold, or otherwise not corresponding to target characteristics, the empty print cartridge is discarded at operation 1506.

[0150] In response to the empty print cartridge being correct, or corresponding to target characteristics, a lid, foam insert and / or interior walls of the empty print cartridge are removed at operation 1508. At operation 1510, print fluid, a foam insert, and a lid are added to the print cartridge to refill the print cartridge. The foam insert may prevent sloshing of the print fluid within the print cartridge and facilitate delivery of the print fluid to fluid ejection nozzles of the print cartridge. In some implementations, the lid, foam insert, and / or interior walls are changed to modify a fill level (i.e., maximum amount of print fluid) of the print cartridge. If the fill level of the print cartridge is not being changed, the lid, foam insert, and interior walls can be left in place. In an example, a print cartridge with lower fill level that is being changed to a higher fill level can have its foam insert replaced with a larger foam insert.

[0151] At operation 1512, renewal configuration data for the print cartridge is obtained. The renewal configuration data includes a fill level indicating a total amount of print fluid added to the print cartridge, a fill status indicating a current amount of print fluid added to the print cartridge, and a region (e.g., geographic region) for use of the print cartridge. The fill level represents a capacity of the cartridge and the fill status represents a current amount of fluidAtty. Dkt. No.: 86349012 present in the cartridge. In this way, the fill level can be analogized to a capacity of a fuel tank, while the fill status can be analogized to a fuel gauge indicating an amount of fuel in the fuel tank. At operation 1514, the renewal configuration data is written to a fluid ejection die of the print cartridge. In some implementations, the renewal configuration data is written to an integrated circuit to be attached to the print cartridge, referred to herein as a man-in-the- middle circuit. Details of the operations 1512 and 1514 are illustrated in FIG. 16.

[0152] At operation 1516, a renewal data bit is written to the fluid ejection die of the print cartridge. As described herein, the renewal data bit indicates to a host device (e.g., printer) that the fluid ejection die includes the renewal configuration data. The renewal data bit can be written to the fluid ejection die within the original configuration data of the fluid ejection die, or in a location associated with the original configuration data such that a host device reading the original configuration data reads the renewal data bit.

[0153] At operation 1518, the print cartridge is tested to confirm correct operation of the print cartridge. The testing can include transmitting print commands to the print cartridge to verify that the fill level, fill status, and / or region of the print cartridge have been correctly written to the print cartridge. In response to the print cartridge failing the testing, or incorrectly responding to the print commands, the print cartridge is discarded at operation 1506. In response to the print cartridge passing the testing, or correctly responding to the print commands, the print cartridge is packaged for shipment at operation 1520. The renewed print cartridge can be used in a host device using the renewal configuration data. In this way, the method 1500 allows for reusing empty print cartridges in a sustainable, eco-friendly way, while providing host devices (e.g., printers) with information for generating print commands for the renewed, reused print cartridges. Additionally, host devices can authenticate the renewal configuration data using information encoded on the print cartridge itself without accessing a network, such as the Internet.Atty. Dkt. No.: 86349012

[0154] FIG. 16 is a flow diagram illustrating details of operations of the method 1500 of FIG. 15. Specifically, FIG. 16 illustrates details of operations 1512 and 1514 of FIG. 15. As discussed in conjunction with FIG. 15, at operation 1512, renewal configuration data for the print cartridge is obtained. In order to obtain the renewal configuration data, at operation 1602, an identifier of the fluid ejection die is read. The identifier of the fluid ejection die is read from memory cells of the fluid ejection die. The identifier of the fluid ejection die can be included in original configuration data of the fluid ejection die. The identifier of the fluid ejection die can be written to the memory cells of the fluid ejection die during manufacturing of the fluid ejection die and can uniquely identify the fluid ejection die.

[0155] At operation 1604, a renewal configuration data request including the identifier and a target renewal status is transmitted to a server. The renewal configuration data request is a request for the renewal configuration data. The identifier can be associated, at the server, with a renewal passcode stored in memory cells of the fluid ejection die. During manufacturing of the fluid ejection die, the identifier and the renewal passcode are written to the memory cells of the fluid ejection die, and the server stores the identifier and the passcode. In response to the renewal configuration data request including the identifier, the server identifies the renewal passcode using the identifier. The target renewal status can describe the target status of the fluid ejection die upon renewal, such as fill level, fill status, region, etc. The server can translate the target renewal status into addresses of memory cells to be written to encode the target renewal status in the memory cells of the fluid ejection die as the renewal configuration data. In some implementations, the renewal configuration data request includes only an indication of a refilled status of the print cartridge, and the server generates the renewal configuration data based on the refilled status of the print cartridge. In an example, the renewal configuration data request indicates that a print cartridge has been refilled and the server determines the fill level and region of the print cartridge based on the identifier of theAtty. Dkt. No.: 86349012 print cartridge, where the renewal configuration data includes the fill level, the region, and a renewed fill status for the print cartridge.

[0156] At operation 1606, the renewal configuration data is received from the server. In some implementations, the renewal configuration data is received from the server (i.e., the server authenticates the configuration data request) in response to an identity of the requesting system, credentials included in the renewal configuration data request, a token included in the renewal configuration data request, or other indication of authorization to request the renewal configuration data.

[0157] As discussed in conjunction with FIG. 15, at operation 1514, the renewal configuration data is written to the fluid ejection die of the print cartridge. At operation 1608, the renewal passcode is transmitted to the fluid ejection die. The fluid ejection die authenticates the renewal passcode, as described herein. As discussed in conjunction with FIG. 7 A, the fluid ejection die writes a renewal attempt bit to a renewal attempt memory cell during operation 1608. Upon authenticating the renewal passcode, the fluid ejection die allows write access to a renewal status memory cell. At operation 1610, a renewal status bit is written to the fluid ejection die (i.e., to the renewal status memory cell).

[0158] At operation 1612, the renewal configuration data is written to the fluid ejection die. The renewal configuration data can be verified by a host device as valid renewal configuration data based on the combination of the renewal attempt bit and the renewal status bit as well as the digital signature included in the renewal configuration data.

[0159] FIG. 17 is a flow diagram illustrating operations of an example method 1700 for using renewal configuration data of a print component. The method 1700 may be performed by the printer 1400 of FIG. 14. The method 1700 may include more, fewer, or different operations than shown. The operations can be performed in the order shown, in a different order, orAtty. Dkt. No.: 86349012 concurrently.

[0160] At operation 1702, the original configuration data of a print component are read. As discussed herein, the original configuration data can be stored in memory cells of a fluid ejection die of a print cartridge. The original configuration data can include a fill level, fill status, and / or region, among other data. The original configuration data can include a renewal data bit that was set during renewal of the print component, as discussed in conjunction with FIG. 15. At operation 1704, a determination is made as to whether the renewal data bit is set, or whether the renewal data bit is written to a renewal data memory cell of the print component. At operation 1706, in response to the renewal data bit not being set or written, the original configuration data is used. Using the original configuration data can include generating print commands using the original configuration data, estimating a time until replacement of the print component, and / or generating alerts regarding replacement of the print component. By checking whether the renewal data bit is set, the original configuration data can be used for a print component that has not been renewed. In an example, a new print component (that has not been renewed) does not have the renewal data bit set and the original configuration data is used.

[0161] At operation 1708, in response to the renewal data bit being set, renewal attempt bits and renewal status bits of the print component are read. The renewal attempt bits and the renewal status bits are written in renewal attempt memory cells and renewal status memory cells, respectively. Reading the renewal attempt bits and the renewal status bits includes reading the renewal attempt memory cells and the renewal status memory cells to determine which of the memory cells are written. As discussed herein, each time a passcode is presented to the print component, (e.g., during an attempt to write to a renewal status memory cell), a renewal attempt memory cell is written to. Thus, only some combinations of written memory cells (bits) represent actual attempts to write to the renewal status memory cells.Atty. Dkt. No.: 86349012

[0162] At operation 1710, a determination is made as to whether the renewal attempt and renewal status bits of the print component are valid. Determining whether the renewal attempt and renewal status bits are valid includes determining whether a combination of the renewal attempt and renewal status bits represents a possible (without interference) combination of bits under the process of writing to a renewal attempt memory cell during each attempt to write to a renewal status memory cell. In an example, if the print component includes one renewal attempt bit and one renewal status bit (a first renewal attempt memory cell and a first renewal status memory cell are written) the combination is valid and the print component has been successfully renewed one time. In an example, if the print component includes two renewal attempt bits and one renewal status bit (two renewal attempt memory cells and one renewal status memory cell are written) the combination is valid and the print component has been unsuccessfully renewed one time and successfully renewed one time. In an example, if the print component includes no renewal attempt bits and one renewal status bit (no renewal attempt memory cells are written and one renewal status memory cell is written) the combination is invalid, as a renewal status bit cannot (without interference) be written without writing a renewal attempt bit.

[0163] By recording the record of renewal attempts in the memory cells of the print component, the method 1700 can be performed without connection to a network (e.g., the internet) and without communication with a server that stores a record of renewal attempts. Instead, the method 1700 can be performed using the information encoded in the memory cells of the print component to determine whether to use the original configuration data or the renewal configuration data.

[0164] In response to the combination of the renewal attempt bits and the renewal status bits being invalid, the original configuration data is used at operation 1706. In response to the combination of the renewal attempt bits and the renewal status bits being valid, the renewalAtty. Dkt. No.: 86349012 configuration data is read at operation 1712. At operation 1714, the renewal configuration data is sent to a secure microcontroller, such as the secure microcontroller 1410 of FIG. 14. The secure microcontroller determines whether the renewal configuration data is valid. The secure microcontroller can determine whether the renewal configuration data is valid by computing a digital signature over data included in the renewal configuration data and comparing the generated digital signature to a digital signature included in the renewal configuration data to verify that the digital signature in the renewal configuration data was computed over the renewal configuration data, including a print component identifier of the print component. If the renewal configuration data were obtained using the method 1500 of FIG. 15, the digital signature included in the renewal configuration data was computed over the print component identifier included in the original configuration data, as read in operation 1702.

[0165] By comparing the digital signature computed over portions of the renewal configuration data to the digital signature in the renewal configuration data, the secure microcontroller can determine whether the renewal configuration data was obtained by an authorized renewal system using the method 1500 of FIG. 15 (e.g., valid).

[0166] At operation 1716, the secure microcontroller returns a pass or fail indication in response to the renewal configuration data. In response to the secure microcontroller returning a fail indication, the original configuration data is used at operation 1706. In response to the secure microcontroller returning a pass indication, the renewal configuration is used at operation 1718. Using the renewal configuration data can include generating print commands using the renewal configuration data, estimating a time until replacement of the print component, and / or generating alerts regarding replacement of the print component. In an example, the renewed print component has a higher fill level than it did prior to renewal, and the renewal configuration data indicates the higher fill level, such that a host printer estimatesAtty. Dkt. No.: 86349012 a time to replacement and ink levels using the higher fill level.

[0167] The herein described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "operably couplable," to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and / or physically interacting components and / or wirelessly interactable and / or wirelessly interacting components and / or logically interacting and / or logically interactable components.

[0168] With respect to the use of substantially any plural and / or singular terms herein, those having skill in the art can translate from the plural to the singular and / or from the singular to the plural as is appropriate to the context and / or application. The various singular / plural permutations may be expressly set forth herein for sake of clarity. For example, recitations of plural elements can be understood to include of the element discussed.

[0169] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" shouldAtty. Dkt. No.: 86349012 be interpreted as "includes but is not limited to," etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and / or "an" should typically be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to "at least one of A, B, and C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, and C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In those instances where a convention analogous to "at least one of A, B, or C, etc." is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., "a system having at least one of A, B, or C" would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). It will beAtty. Dkt. No.: 86349012 further understood by those within the art that virtually any disjunctive word and / or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B." Further, unless otherwise noted, the use of the words “approximate,” “about,” “around,” “substantially,” etc., mean plus or minus ten percent.

[0170] The foregoing description of illustrative examples has been presented for purposes of illustration and of description. It is not intended to be exhaustive or limiting with respect to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the disclosed examples. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims

Atty. Dkt. No.: 86349012WHAT IS CLAIMED IS:

1. An apparatus, comprising: a set of electrical contacts to interface with a print component; a processor; and a non-transitory, computer-readable medium including instructions which, when executed by the processor, cause the processor to: transmit, using the set of electrical contacts, a renewal passcode to the print component; write, using the set of electrical contacts, a renewal status bit to the print component after transmitting the renewal passcode to the print component; and write, using the set of electrical contacts, renewal configuration data to the print component.

2. The apparatus of claim 1, wherein the instructions cause the processor to: read, using the set of electrical contacts, a print component identifier of the print component; transmit a renewal request including the print component identifier to a server; and receive, from the server, in response to the renewal request, the renewal passcode.

3. The apparatus of claim 1, wherein the instructions cause the processor to: transmit a renewal request to a server, the renewal request including information corresponding to the renewal configuration data; and receive, from the server, in response to the renewal request, the renewal configuration data.

4. The apparatus of claim 1, wherein the renewal configuration data includes a digital signature based on a print component identifier of the print component.

5. The apparatus of claim 1, wherein the instructions cause the processor to write, using the set of electrical contacts, a renewal data bit to the print component, theAtty. Dkt. No.: 86349012 renewal data bit indicating that the print component includes the renewal configuration data.

6. A method, comprising: transmitting, by a processor, using a set of electrical contacts to interface with electrical contacts of a print component, a set of signals including an update passcode to the print component; writing, by the processor, using the set of electrical contacts, an update status bit to the print component after transmitting the update passcode to the print component, wherein the update status bit indicates that the updated configuration data was written using the update passcode; and writing, by a processor, using the set of electrical contacts, updated configuration data to the print component.

7. The method of claim 6, further comprising: reading, by the processor, using the set of electrical contacts, an identifier of the print component; transmitting, by the processor, an update request including the identifier to a server; and receiving, by the processor, from the server, in response to the update request, the update passcode.

8. The method of claim 6, further comprising: transmitting, by the processor, an update request to a server, the renewal request including a target update status corresponding to the updated configuration data; and receiving, by the processor, from the server, in response to the update request, the updated configuration data.

9. The method of claim 6, wherein the updated configuration data includes a digital signature based on an identifier of the print component.

10. The method of claim 6, further comprising writing, by the processor, using the set of electrical contacts, an update data bit to the print component, the update data bitAtty. Dkt. No.: 86349012 indicating that the print component includes the updated configuration data.

11. A printer, comprising: a processor; a secure microcontroller; and a non-transitory, computer-readable medium including instructions which, when executed by a processor, cause the processor to: read original configuration data of a print component; in response to a renewal data bit of the original configuration data being written, read renewal status bits and renewal attempt bits of the print component; in response to a combination of the renewal status bits and the renewal attempt bits of the print component being valid, verify, using the secure microcontroller, whether renewal configuration data of the print component is valid; and in response to the renewal configuration data of the print component being valid, generate print commands based on the renewal configuration data.

12. The printer of claim 11, wherein the instructions cause the processor to: confirm, based on the renewal data bit being set, that the print component is a renewed print component; and confirm, based on the renewal configuration data of the print component being valid, that the print component is a valid renewed print component.

13. The printer of claim 11, wherein the instructions cause the processor to confirm that the combination of the renewal status bits and the renewal attempt bits of the print component is valid if the combination indicating that a renewal attempt bit of the renewal attempt bits was written each time an attempt was made to write a renewal status bit of the renewal status bits.

14. The printer of claim 11, wherein the original configuration data of the print component includes an identifier of the print component and the renewal configuration data includes a digital signature, and wherein the instructions causeAtty. Dkt. No.: 86349012 the processor to verify, using the secure microcontroller, whether the renewal configuration data of the print component is valid by verifying whether the digital signature was generated using the identifier of the print component.

15. The printer of claim 11, wherein the instructions cause the processor to, in response to the renewal data bit of the original configuration data not being written, generate print commands based on the original configuration data of the print component.

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