Pixel circuit and driving method therefor, and display substrate

Abstract

A pixel circuit and a driving method therefor, and a display substrate. Content displayed by the display substrate comprises a plurality of display frames. The pixel circuit comprises a driving circuit and a potential adjustment circuit, which are connected to each other, wherein the driving circuit is connected to a first scanning signal line, a data signal line, a light-emitting control line and a light-emitting element, and is configured to receive a data signal of the data signal line under the control of the first scanning signal line, and to drive, under the control of the light-emitting control line and on the basis of the received data signal, the light-emitting element to emit light; and the potential adjustment circuit is connected to the light-emitting control line, and is configured to write the data signal of the data signal line into a first electrode of the light-emitting element under the control of the light-emitting control line before the light-emitting element emits light.

Description

Pixel circuits and their driving methods, display substrates Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a pixel circuit and its driving method, and a display substrate. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a pixel circuit, including a driving circuit and a potential adjustment circuit interconnected thereto. The driving circuit is connected to a first scan signal line, a data signal line, a light emission control line, and a light-emitting element, and is configured to receive a data signal from the data signal line under the control of the first scan signal line; and to drive the light-emitting element to emit light according to the received data signal under the control of the light emission control line. The potential adjustment circuit is connected to the light emission control line and is configured to write the data signal from the data signal line into the first electrode of the light-emitting element under the control of the light emission control line before the light-emitting element emits light.

[0006] Secondly, this disclosure also provides a display substrate, including the aforementioned pixel circuit.

[0007] Thirdly, this disclosure also provides a method for driving a pixel circuit, configured to drive the aforementioned pixel circuit, the method comprising:

[0008] The driving circuit receives the data signal from the data signal line under the control of the first scan signal line; the potential adjustment circuit writes the data signal into the first electrode of the light-emitting element under the control of the light-emitting control line.

[0009] The driving circuit, under the control of the light-emitting control line, drives the light-emitting element to emit light according to the received data signal.

[0010] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood.

[0011] Overview of the attached figures

[0012] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0013] Figure 1 is a schematic diagram of a display substrate;

[0014] Figure 2A is a schematic diagram of a planar structure of a display substrate;

[0015] Figure 2B is a schematic diagram of a planar structure of another type of display substrate;

[0016] Figure 2C is a schematic diagram of another type of display substrate planar structure;

[0017] Figure 3 is a schematic cross-sectional view of a display substrate;

[0018] Figure 4 is an equivalent circuit diagram of a pixel circuit of a display substrate;

[0019] Figure 5 is a schematic diagram illustrating the principle of a display substrate exhibiting a three-screen defect.

[0020] Figure 6 is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure;

[0021] Figure 7 is a schematic diagram of another pixel circuit provided in an embodiment of this disclosure;

[0022] Figure 8 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0023] Figure 9 is a timing diagram of one operation of the pixel circuit provided in Figure 8;

[0024] Figure 10 is a schematic diagram of another pixel circuit provided in an embodiment of this disclosure;

[0025] Figure 11 is an equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure;

[0026] Figure 12 is a timing diagram of one operation of the pixel circuit provided in Figure 11;

[0027] Figure 13 is a schematic flowchart of a pixel circuit driving method provided in an embodiment of this disclosure.

[0028] Detailed Explanation

[0029] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0030] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0031] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0032] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0033] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0034] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0035] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0036] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0037] In this disclosure, the effective level signal includes the level signal for turning on the transistor. For example, the effective level signal for turning on a P-type transistor is a low level signal, and the effective level signal for turning on an N-type transistor is a high level signal.

[0038] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0039] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0040] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0041] Figure 1 is a schematic diagram of a display substrate structure. As shown in Figure 1, the display substrate may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, scan driver, and light-emitting driver. The data driver is connected to multiple data signal lines, the scan driver is connected to multiple scan signal lines, and the light-emitting driver is connected to multiple light-emitting control lines. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel circuit, which may be connected to the scan signal lines, light-emitting control lines, and data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver, and clock signals, emission stop signals, etc., of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines. For example, a data driver can sample grayscale values ​​using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal line on a pixel-by-pixel basis. A scan driver can generate scan signals to be provided to the scan signal lines by receiving clock signals, scan start signals, etc., from a timing controller. For example, a scan driver can sequentially provide scan signals with on-level pulses to the scan signal lines. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. An LED driver can generate transmit signals to be provided to the LED control lines by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, an LED driver can sequentially provide transmit signals with off-level pulses to the LED control lines. For example, an LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal.

[0042] Figure 2A is a schematic diagram of a planar structure of a display substrate (Figure 1), Figure 2B is a schematic diagram of a planar structure of a display substrate (Figure 22), and Figure 2C is a schematic diagram of a planar structure of a display substrate (Figure 23). As shown in Figures 2A to 2C, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel circuit and a light-emitting device. The pixel circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting control line. The pixel circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting control line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel circuit of their respective sub-pixels.

[0043] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0044] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal, and this disclosure does not limit it.

[0045] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; this disclosure does not limit the specific arrangement. Figure 2A illustrates an example where a pixel unit includes three sub-pixels arranged horizontally side-by-side, and Figure 2B illustrates an example where a pixel unit includes three sub-pixels arranged in a triangular arrangement.

[0046] In an exemplary embodiment, a pixel unit may include four sub-pixels. The four sub-pixels may be arranged horizontally side by side, vertically side by side, in a square, or in a diamond shape, etc., and this disclosure does not limit the arrangement. Figure 2C illustrates an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0047] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0048] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0049] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include multiple transistors and storage capacitors constituting the pixel circuit; only one transistor 101 and one capacitor 101A are shown as examples in FIG3. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of the corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting structure layer 103.

[0050] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and metal sheets; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0051] In an exemplary embodiment, the organic light-emitting layer 303 may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

[0052] In an exemplary embodiment, the touch structure layer of each sub-pixel may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0053] Figure 4 shows an equivalent circuit diagram of a pixel circuit. As shown in Figure 4, the pixel circuit includes eight transistors (i.e., transistors T01 to T08) and a storage capacitor Cst. Specifically, the gate electrode of the first transistor T01 is connected to the first reset control line Reset1, the first terminal of the first transistor T01 is connected to the first initial signal line INIT1, and the second terminal of the first transistor T01 is connected to the third node N3. The gate electrode of the second transistor T02 is connected to the second scan signal line Gate2, the first terminal of the second transistor T02 is connected to the third node N3, and the second terminal of the second transistor T02 is connected to the first node N1. The gate electrode of the third transistor T03 is connected to the first node N1, the first terminal of the third transistor T03 is connected to the second node N2, and the second terminal of the third transistor T03 is connected to the third node N3. The gate electrode of the fourth transistor T04 is connected to the first scan signal line Gate1, the first terminal of the fourth transistor T04 is connected to the data signal line DATA, and the second terminal of the fourth transistor T04 is connected to the second node N2. The gate electrode of the fifth transistor T05 is connected to the light-emitting control line EM, the first terminal of the fifth transistor T05 is connected to the first power supply line ELVDD, and the second terminal of the fifth transistor T05 is connected to the second node N2. The gate electrode of the sixth transistor T06 is connected to the light-emitting control line EM, the first terminal of the sixth transistor T06 is connected to the third node N3, and the second terminal of the sixth transistor T06 is connected to the fourth node N4. The gate electrode of the seventh transistor T07 is connected to the second reset control line Reset2, the first terminal of the seventh transistor T07 is connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T07 is connected to the fourth node N4. The gate electrode of the eighth transistor T08 is connected to the second reset control line Reset2, the first terminal of the eighth transistor T08 is connected to the third initial signal line INIT3, and the second terminal of the eighth transistor T08 is connected to the second node N2. The first terminal of the storage capacitor Cst is connected to the first node N1, and the second terminal of the storage capacitor Cst is connected to the first power supply line ELVDD. The first electrode of the light-emitting element L is connected to the fourth node N4, and the second electrode of the light-emitting element L is connected to the second power line ELVSS.

[0054] The second transistor T02 can be an N-type transistor, for example, an N-type metal-oxide-slim (MOS) thin-film transistor. MOS thin-film transistors have low leakage current, thus preventing leakage at the first node N1 during the light-emitting stage. Meanwhile, the first transistor T01, third transistor T03, fourth transistor T04, fifth transistor T05, second transistor T06, seventh transistor T07, and eighth transistor T08 can be P-type transistors, for example, P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors. LTSPS have high carrier mobility, which is beneficial for achieving high-resolution, high-response-speed, high-pixel-density, and high-aperture display panels. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 can output the same or different voltage signals depending on the actual situation.

[0055] To meet high-precision requirements, high-frequency pulse width modulation (PWM) dimming technology can be used to control screen brightness, thereby saving power and protecting eyesight. Taking a maximum refresh rate of 120Hz and an anode initialization control signal frequency of 360Hz as an example, within one frame refresh cycle, the second reset control line Reset2, which controls the reset of the first electrode (i.e., anode) of the light-emitting element corresponding to the same pixel circuit, has three pulses after the data writing phase of that pixel circuit. This means that at the same moment, the second initial signal line needs to charge the anodes of three sub-pixels in the column direction of the display panel, with each position corresponding to one or more rows of sub-pixels. As shown in Figure 5, assuming that at a certain moment, the second initial signal line simultaneously charges the anodes of sub-pixels at positions A, B, and C in the display panel, where position A is the data refresh row. Because there is parasitic capacitance between the data signal line and the anode of each sub-pixel in the panel, the change in data signal voltage causes the anode potential of each sub-pixel in the panel to jump. However, since the anodes of the sub-pixels at positions B and C are reset by the second initial voltage Vinit2, the jump in data signal voltage does not cause the anode voltage of the sub-pixels at positions B and C to jump. As a result, the brightness of the corresponding rows at positions B and C is inconsistent with that of other rows, thus causing the problem of poor screen splitting.

[0056] As shown in Figure 6, this embodiment of the present disclosure provides a pixel circuit, including a driving circuit 1 and a potential adjustment circuit 2 connected to each other. The driving circuit 1 is connected to a first scan signal line Gate1, a data signal line DATA, a light emission control line EM, and a light emission element. It is configured to receive the data signal of the data signal line DATA under the control of the first scan signal line Gate1, and drive the light emission element to emit light according to the received data signal under the control of the light emission control line EM.

[0057] The potential adjustment circuit 2 is connected to the light emission control line EM and is configured to acquire a data signal before the light emission element emits light, and write the data signal into the first electrode of the light emission element under the control of the light emission control line EM.

[0058] In this embodiment, the potential adjustment circuit 2 acquires a data signal before the light-emitting element emits light, and under the control of the light-emitting control line EM, writes the data signal into the first electrode of the light-emitting element. This ensures that the voltage change of the data signal line has a consistent effect on the first electrode of the light-emitting element of the sub-pixels of the entire screen, thereby solving the problem of poor screen splitting.

[0059] Figure 7 is a schematic diagram of the structure of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, the potential adjustment circuit 2 includes a first control sub-circuit 21, a second storage sub-circuit 22, and a second reset sub-circuit 23.

[0060] The second storage sub-circuit 22 is connected to the data signal line DATA and is configured to store the data signal in the data signal line DATA.

[0061] The second reset sub-circuit 23 is connected to the second reset control line Reset2, the first electrode of the light-emitting element, and the second storage sub-circuit 22, respectively, and is configured to write the data signal in the second storage sub-circuit 22 into the first electrode of the light-emitting element under the control of the second reset control line Reset2.

[0062] The first control sub-circuit 21 is connected to the light emission control line EM, the second initial signal line INIT2, and the second storage sub-circuit 22, and is configured to reset the second storage sub-circuit 22 under the control of the light emission control line EM.

[0063] In some examples, as shown in Figure 7, the driving circuit 1 includes a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, and a first storage sub-circuit 14.

[0064] The driving sub-circuit 11 is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the first node N1.

[0065] The compensation sub-circuit 12 is connected to the second scan signal line Gate2, the first node N1 and the third node N3 respectively, and is configured to turn on the first node N1 and the third node N3 under the control of the second scan signal line Gate2, so that the threshold voltage of the driving sub-circuit 11 is written to the first node N1.

[0066] The data writing sub-circuit 13 is connected to the first scan signal line Gate1, the data signal line DATA, and the second node N2, respectively, and is configured to write the data signal provided by the data signal line DATA to the second node N2 under the control of the first scan signal line Gate1.

[0067] The first storage sub-circuit 14 is connected to the first node N1 and the first power line ELVDD, respectively.

[0068] In some examples, the first scan signal line Gate1 can be configured to provide a first scan signal, and the second scan signal line Gate2 can be configured to provide a second scan signal. The first scan signal can be configured to control the data writing sub-circuit 13 to write a data signal to the second node N2. The second scan signal can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the drive sub-circuit 11 to the first node N1. The first scan signal can be different from the second scan signal; for example, the duration of the effective level signal of the second scan signal can be greater than the duration of the effective level signal of the first scan signal.

[0069] In some examples, as shown in Figure 7, the driving circuit 1 may further include a first light-emitting control sub-circuit 15 and a second light-emitting control sub-circuit 16. The first light-emitting control sub-circuit 15 is connected to the light-emitting control line EM, the first power line ELVDD, and the second node N2, respectively, and is configured to write a first power signal provided by the first power line ELVDD to the second node N2 under the control of the light-emitting control line EM. The second light-emitting control sub-circuit 16 is connected to the light-emitting control line EM, a third node N3, and a fourth node N4, respectively, and is configured to turn on the third node N3 and the fourth node N4 under the control of the light-emitting control line EM. The fourth node N4 is connected to the first electrode of the light-emitting element. The second electrode of the light-emitting element is connected to the second power line ELVSS.

[0070] In some examples, the pixel circuit may include a data writing phase (or threshold compensation phase) during driving; during the data writing phase (or threshold compensation phase), the first light emission control sub-circuit 15 is turned on under the control of the light emission control line EM, and the threshold voltage of the driving sub-circuit 11 is written to the first node N1 through the first light emission control sub-circuit 15, the driving sub-circuit 11 and the compensation sub-circuit 12.

[0071] In some examples, the pixel circuit may also include a light emission stage after the data writing stage (or threshold compensation stage) during driving; in the light emission stage, the first light emission control sub-circuit 15 is turned on under the control of the light emission control line EM, the second light emission control sub-circuit 16 is turned on under the control of the light emission control line EM, and the first power line ELVDD provides driving current to the first electrode of the light emission element to drive the light emission element to emit light.

[0072] In some examples, the light-emitting control line EM can be configured to provide a light-emitting control signal. The light-emitting control signal can be configured to control the first light-emitting control sub-circuit 15 to write a first power supply voltage signal to the second node N2, and to control the second light-emitting control sub-circuit 16 to turn on the third node N3 and the fourth node N4 to provide a drive signal to the light-emitting element, causing the light-emitting element to emit light.

[0073] In some examples, the light-emitting element can be an organic light-emitting diode (OLED). The first electrode of the light-emitting element can be an anode, and the second electrode can be a cathode. However, this embodiment is not limited to this.

[0074] In some examples, the first power line ELVDD can continuously provide a constant high-level signal; for example, the first power line ELVDD can provide a first power supply voltage signal. The second power line ELVSS can continuously provide a constant low-level signal; for example, the second power line ELVSS can provide a second power supply voltage signal. The first power supply voltage signal can be greater than the second power supply voltage signal.

[0075] In some examples, as shown in Figure 7, the drive circuit 1 may further include a first reset sub-circuit 17 and a third reset sub-circuit 18. The first reset sub-circuit 17 is connected to the first reset control line Reset1, the first initial voltage line INIT1, and the third node N3, and is configured to reset the third node N3 using the first initial voltage of the first initial voltage line INIT1 under the control of the first reset control line Reset1. The third reset sub-circuit 18 is connected to the second reset control line Reset2, the third initial voltage line INIT3, and the second node N2, and is configured to reset the second node N2 using the third initial voltage of the third initial voltage line INIT3 under the control of the second reset control line Reset2.

[0076] In some examples, the first reset control line Reset1 can be configured to provide a first reset control signal, and the second reset control line Reset2 can be configured to provide a second reset control signal. The first reset control signal can be configured to control the first reset sub-circuit 17 to reset the third node N3, and the second reset control signal can be configured to control the second reset sub-circuit 23 to reset the fourth node N4, and control the third reset sub-circuit 18 to reset the second node N2. The first reset control signal may be different from the second reset control signal.

[0077] In some examples, the first initial voltage line INIT1 can be configured to provide a first initial voltage signal. The second initial voltage line INIT2 can be configured to provide a second initial voltage signal, and the third initial voltage line INIT3 can be configured to provide a third initial voltage signal. The first, second, and third initial voltage signals can be different.

[0078] In some examples, the pixel circuit may also include a second reset phase located between the data writing phase and the light emission phase during driving. In the data writing phase, a data signal voltage is provided to the data signal line so that the data signal voltage is written to the driving circuit 1 (first node N1) and the second storage sub-circuit 22. In the second reset phase, the second reset sub-circuit 23 is turned on under the control of the second reset control line Reset2, and writes the data signal voltage in the second storage sub-circuit 22 to the first electrode of the light emission element, thereby ensuring that the voltage change of the data signal line has a consistent effect on the anode of the sub-pixel across the entire screen. In the light emission phase, the first control sub-circuit 21 resets the second storage sub-circuit 22 under the control of the light emission control line EM.

[0079] This embodiment of the present disclosure resets the fourth node N4 through the second reset sub-circuit 23, which can eliminate the residual positive charge on the surface of the first electrode of the light-emitting element and improve the lifespan of the light-emitting element. This embodiment of the present disclosure, through the first control sub-circuit 21, the second storage sub-circuit 22, and the second reset sub-circuit 23, can adjust the potential on the first electrode (anode) of the light-emitting element, thereby ensuring that changes in the data signal line voltage have a consistent anode effect on all sub-pixels across the screen, solving the problem of poor screen splitting.

[0080] Figure 8 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 8, the driving sub-circuit 11 may include a driving transistor T3; the compensation sub-circuit 12 may include a compensation transistor T2; the data writing sub-circuit 13 may include a data writing transistor T4; the first storage sub-circuit 14 may include a first capacitor Cst1; the first light emission control sub-circuit 15 may include a first light emission control transistor T5; the second light emission control sub-circuit 16 may include a second light emission control transistor T6; the first reset sub-circuit 17 may include a first reset transistor T1; the third reset sub-circuit 18 may include a third reset transistor T8; the first control sub-circuit 21 may include a first control transistor T9; the second storage sub-circuit 22 may include a second capacitor Cst2; and the second reset circuit 23 may include a second reset transistor T7.

[0081] In some examples, as shown in Figure 8, the gate of the first reset transistor T1 is coupled to the first reset control line Reset1, the first terminal of the first reset transistor T1 is coupled to the first initial voltage line INIT1, and the second terminal of the first reset transistor T1 is coupled to the third node N3. The gate of the compensation transistor T2 is coupled to the second scan signal line Gate2, the first terminal of the compensation transistor T2 is coupled to the third node N3, and the second terminal of the compensation transistor T2 is coupled to the first node N1. The gate of the drive transistor T3 is coupled to the first node N1, the first terminal of the drive transistor T3 is coupled to the second node N2, and the second terminal of the drive transistor T3 is coupled to the third node N3. The gate of the data write transistor T4 is coupled to the first scan signal line Gate1, the first terminal of the data write transistor T4 is coupled to the data signal line DATA, and the second terminal of the data write transistor T4 is coupled to the second node N2. The first plate of the first capacitor Cst1 is coupled to the first node N1, and the second plate of the first capacitor Cst1 is coupled to the first power supply line ELVDD. The gate of the first light-emitting control transistor T5 is coupled to the light-emitting control line EM, the first electrode of the first light-emitting control transistor T5 is coupled to the first power supply line ELVDD, and the second electrode of the first light-emitting control transistor T5 is coupled to the second node N2. The gate of the second light-emitting control transistor T6 is coupled to the light-emitting control line EM, the first electrode of the second light-emitting control transistor T6 is coupled to the third node N3, and the second electrode of the second light-emitting control transistor T6 is coupled to the fourth node N4. The gate of the second reset transistor T7 is coupled to the second reset control line Reset2, the first electrode of the second reset transistor T7 is coupled to the fifth node N5, and the second electrode of the second reset transistor T7 is coupled to the fourth node N4. The gate of the third reset transistor T8 is coupled to the second reset control line Reset2, the first electrode of the third reset transistor T8 is coupled to the third initial signal line INIT3, and the second electrode of the third reset transistor T8 is coupled to the second node N2. The first electrode of the light-emitting element L is coupled to the fourth node N4, and the second electrode of the light-emitting element L is coupled to the second power supply line ELVSS. The first plate of the second capacitor Cst2 is coupled to the fifth node N5, and the second plate of the second capacitor Cst2 is coupled to the data signal line DATA. The gate of the first control transistor T9 is coupled to the light-emitting control line EM, the first terminal of the first control transistor T9 is coupled to the second initial signal line INIT2, and the second terminal of the first control transistor T9 is coupled to the fifth node N5.

[0082] In some examples, the first node N1 is the connection point of the first capacitor Cst1, the compensation transistor T2, and the driving transistor T3. The second node N2 is the connection point of the driving transistor T3, the first light-emitting control transistor T5, the data writing transistor T4, and the third reset transistor T8. The third node N3 is the connection point of the first reset transistor T1, the compensation transistor T2, the driving transistor T3, and the second light-emitting control transistor T6. The fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, and the light-emitting element L. The fifth node N5 is the connection point of the second capacitor Cst2, the second reset transistor T7, and the first control transistor T9.

[0083] Figure 8 shows an exemplary structure of the driving sub-circuit 11, compensation sub-circuit 12, data writing sub-circuit 13, first storage sub-circuit 14, first light emission control sub-circuit 15, second light emission control sub-circuit 16, first reset sub-circuit 17, third reset sub-circuit 18, first control sub-circuit 21, second storage sub-circuit 22, and second reset sub-circuit 23. It is readily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0084] In some examples, as shown in Figure 8, the compensation transistor T2 can be an N-type transistor. For example, the compensation transistor T2 can be an N-type metal-oxide-slim (MOS) thin-film transistor. MOS thin-film transistors have low leakage current, thus preventing leakage at the first node N1 during the light-emitting stage. Meanwhile, the first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, third reset transistor T8, and first control transistor T9 can be P-type thin-film transistors. For example, the first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, third reset transistor T8, and first control transistor T9 can be P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors. LTSPS thin-film transistors have high carrier mobility, which is beneficial for achieving high-resolution, high-response-speed, high-pixel-density, and high-aperture-ratio display panels. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 can output the same or different voltage signals depending on the actual situation.

[0085] In some examples, the pixel circuit of this disclosure may include a first working period and a second working period within a frame display cycle, wherein the number of first working periods and the number of second working periods can be set as needed. For example, a frame display cycle may include one first working period and two second working periods; however, this disclosure is not limited thereto. In other examples, the pixel circuit of this disclosure may include only the first working period within a frame display cycle.

[0086] In this embodiment, the difference between the first working period and the second working period is that the first working period includes a data writing phase, while the second working period does not include a data writing phase. In some examples, both the first and second working periods may include a reset phase and a light-emitting phase, respectively. The pixel circuit in this example can adjust the brightness of the light-emitting element by controlling the effective level duration of the light-emitting control signal during the first and second working periods.

[0087] In some examples, the first working period may include a first reset phase, a data writing phase (or threshold compensation phase), a second reset phase, and a light emission phase set sequentially, and the second working period may include a first reset phase, a second reset phase, and a light emission phase set sequentially.

[0088] Figure 9 is a timing diagram of the pixel circuit shown in Figure 8 during the first working period. As shown in Figure 8, the pixel circuit of this example may include: 9 transistors (i.e., transistors T1 to T9), 2 capacitor units (i.e., first capacitor Cst1 and second capacitor Cst2), 9 input terminals (i.e., data signal line DATA, first scan signal line Gate1, second scan signal line Gate2, light emission control line EM, first reset control line Reset1, second reset control line Reset2, first initial voltage line INIT1, second initial voltage line INIT2 and third initial voltage line INIT3), and 2 power supply terminals (i.e., first power supply line ELVDD and second power supply line ELVSS).

[0089] As shown in Figure 9, the pixel circuit includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4 set sequentially during the first working period.

[0090] The first stage t1 can also be called the first reset stage (first node N1 reset stage). In the first stage t1, the signal of the first reset control line Reset1 is a low-level signal, while the signals of the first scan signal line Gate1, the second scan signal line Gate2, the second reset control line Reset2, and the light emission control line EM are all high-level signals. The first reset transistor T1 is turned on under the control of the first reset control signal of the first reset control line Reset1, the compensation transistor T2 is turned on under the control of the second scan signal of the second scan signal line Gate2, and the other transistors are turned off.

[0091] The first reset transistor T1 is turned on, so that the first initial voltage signal of the first initial signal line INIT1 is provided to the third node N3. The compensation transistor T2 is turned on, so that the first node N1 and the third node N3 are connected. The voltage of the first node N1 is reset to the first initial voltage Vinit1, and the driving transistor T3 is turned on.

[0092] The second stage, t2, can also be called the data writing stage or the threshold compensation stage. In the second stage, t2, the signal of the first scan signal line Gate1 is a low-level signal, while the signals of the second scan signal line Gate2, the first reset control line Reset1, the second reset control line Reset2, and the light emission control line EM are all high-level signals. The data writing transistor T4 is turned on under the control of the first scan signal of the first scan signal line Gate1, and the compensation transistor T2 remains on under the control of the second scan signal of the second scan signal line Gate2. Since the voltage of the first node N1 is the first initial voltage Vinit1, the driving transistor T3 is turned on, and the other transistors are turned off.

[0093] The compensation transistor T2 remains on, maintaining communication between the first node N1 and the third node N3. The data write transistor T4 is on, allowing the data voltage signal output from the data signal line DATA to be supplied to the first node N1 via the second node N2, the on-state drive transistor T3, the third node N3, and the on-state compensation transistor T2. The sum of the data voltage output from the data signal line DATA and the threshold voltage of the drive transistor T3 is then charged into the first capacitor Cst1. The voltage at the first node N1 is Vdata + Vth, where Vdata is the data voltage output from the data signal line DATA, and Vth is the threshold voltage of the drive transistor T3. Simultaneously, through the capacitor bootstrap principle, the voltage transition (data signal voltage) at the first plate of the second capacitor Cst2 is transmitted to the second plate of the second capacitor Cst2 (i.e., the fifth node N5).

[0094] The third stage, t3, can also be called the second reset stage (the reset stage of the second node N2 and the fourth node N4). In the third stage, t3, the signal of the second scan signal line Gate2 is a low-level signal, the signal of the second reset control line Reset2 is a low-level signal, and the signals of the first scan signal line Gate1, the first reset control line Reset1, and the light emission control line EM are all high-level signals. The second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal of the second reset control line Reset2, while the other transistors are turned off.

[0095] The second reset transistor T7 turns on, providing the voltage (data signal voltage) on the fifth node N5 to the fourth node N4, thereby ensuring that changes in the data signal line voltage have a consistent anode effect on all sub-pixels. The third reset transistor T8 turns on, providing the third initial voltage signal of the third initial signal line INIT3 to the second node N2, initializing (resetting) the second node N2 so that its potential is the third initial voltage Vinit3.

[0096] During the transition phase t3-1 between the third stage t3 and the fourth stage t4, the second reset signal provided by the second reset control line Reset2 jumps to a high level, while the other signals remain in the state of the third stage t3.

[0097] The fourth stage, t4, can also be called the light-emitting stage. In the fourth stage, t4, the signal of the light-emitting control line EM is a low-level signal, the signal of the second scan signal line Gate2 is a low-level signal, and the signals of the first scan signal line Gate1, the first reset control line Reset1, and the second reset control line Reset2 are all high-level signals. The first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first control transistor T9 are turned on under the control of the light-emitting control signal of the light-emitting control line EM. The first control transistor T9 is turned on, so that the second initial voltage signal of the second initial signal line INIT2 is stored on the second capacitor Cst2. The power supply voltage output by the first power supply line ELVDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting device L to emit light.

[0098] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vdata + Vth, the driving current flowing through the driving transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdd-Vdata)] 2 ;

[0099] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data signal line DATA, and Vdd is the power supply voltage output by the first power supply line ELVDD.

[0100] The pixel circuit in the second operating period may include a first stage t1 (first reset stage), a third stage t3 (second reset stage), and a fourth stage t4 (light emission stage), set sequentially, but does not include the second stage t2 (data writing stage or threshold compensation stage). The specific operating process can be referred to the previous description and will not be repeated here. Since the first electrode of the light-emitting element can still be written with the data signal voltage of the data signal line during the second operating period, the pixel circuit in this example ensures that changes in the data signal line voltage have a consistent anode effect on all sub-pixels across the screen.

[0101] Figure 10 is a schematic diagram of the structure of another pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 10, the pixel circuit of the embodiments of the present disclosure may still include a driving circuit 1 and a potential adjustment circuit 2, wherein the potential adjustment circuit 2 includes a first control sub-circuit 21, a second storage sub-circuit 22 and a second reset sub-circuit 23.

[0102] The second reset sub-circuit 23 is connected to the second reset control line Reset2, the second initial signal line INIT2 and the first electrode of the light-emitting element, respectively, and is configured to reset the first electrode of the light-emitting element using the signal of the second initial signal line INIT2 under the control of the second reset control line Reset2.

[0103] The second storage sub-circuit 22 is connected to the fourth initial signal line INIT4 and is configured to store the voltage jump variable in the fourth initial signal line INIT4.

[0104] The first control sub-circuit 21 is connected to the light-emitting control line EM, the first electrode of the light-emitting element, and the second storage sub-circuit 22, respectively. It is configured to connect the first electrode of the light-emitting element and the second storage sub-circuit 22 under the control of the light-emitting control line EM, so as to write the voltage jump variable stored in the second storage sub-circuit 22 into the first electrode of the light-emitting element, or to reset the second storage circuit 22 using the voltage of the first electrode of the light-emitting element.

[0105] In some examples, the driving circuit 1 may include: a driving sub-circuit 11, a compensation sub-circuit 12, a data writing sub-circuit 13, and a first storage sub-circuit 14.

[0106] The driving sub-circuit 11 is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the first node N1.

[0107] The data writing sub-circuit 13 is connected to the first scan signal line Gate1, the data signal line DATA, and the second node N2, respectively, and is configured to write the data signal provided by the data signal line DATA to the second node N2 under the control of the first scan signal line Gate1.

[0108] The compensation sub-circuit 12 is connected to the second scan signal line Gate2, the first node N1 and the third node N3 respectively, and is configured to turn on the first node N1 and the third node N3 under the control of the second scan signal line Gate2, so that the threshold voltage of the driving sub-circuit 11 is written to the first node N1.

[0109] The first storage sub-circuit 14 is connected to the first node N1 and the first power line ELVDD, respectively.

[0110] In some examples, the first scan signal line Gate1 can be configured to provide a first scan signal, and the second scan signal line Gate2 can be configured to provide a second scan signal. The first scan signal can be configured to control the data writing sub-circuit 13 to write a data signal to the second node N2. The second scan signal can be configured to control the compensation sub-circuit 12 to write the threshold voltage of the drive sub-circuit 11 to the first node N1. The first scan signal can be different from the second scan signal; for example, the duration of the effective level signal of the second scan signal can be greater than the duration of the effective level signal of the first scan signal.

[0111] In some examples, as shown in Figure 10, the driving circuit 1 may further include a first light-emitting control sub-circuit 15 and a second light-emitting control sub-circuit 16. The first light-emitting control sub-circuit 15 is connected to the light-emitting control line EM, the first power line ELVDD, and the second node N2, respectively, and is configured to write a first power signal provided by the first power line ELVDD to the second node N2 under the control of the light-emitting control line EM. The second light-emitting control sub-circuit 16 is connected to the light-emitting control line EM, a third node N3, and a fourth node N4, respectively, and is configured to turn on the third node N3 and the fourth node N4 under the control of the light-emitting control line EM. The fourth node N4 is connected to the first electrode of the light-emitting element. The second electrode of the light-emitting element is connected to the second power line ELVSS.

[0112] In some examples, the pixel circuit may include a data writing phase (or threshold compensation phase) during driving; during the data writing phase (or threshold compensation phase), the first light emission control sub-circuit 15 is turned on under the control of the light emission control line EM, and the threshold voltage of the driving sub-circuit 11 is written to the first node N1 through the first light emission control sub-circuit 15, the driving sub-circuit 11 and the compensation sub-circuit 12.

[0113] In some examples, the pixel circuit may also include a light emission stage after the data writing stage (or threshold compensation stage) during driving; in the light emission stage, the first light emission control sub-circuit 15 is turned on under the control of the light emission control line EM, the second light emission control sub-circuit 16 is turned on under the control of the light emission control line EM, and the first power line ELVDD provides driving current to the first electrode of the light emission element to drive the light emission element to emit light.

[0114] In some examples, the light-emitting control line EM can be configured to provide a light-emitting control signal. The light-emitting control signal can be configured to control the first light-emitting control sub-circuit 15 to write a first power supply voltage signal to the second node N2, and to control the second light-emitting control sub-circuit 16 to turn on the third node N3 and the fourth node N4 to provide a drive signal to the light-emitting element, causing the light-emitting element to emit light.

[0115] In some examples, the light-emitting element can be an organic light-emitting diode (OLED). The first electrode of the light-emitting element can be an anode, and the second electrode can be a cathode. However, this embodiment is not limited to this.

[0116] In some examples, the first power line ELVDD can continuously provide a constant high-level signal; for example, the first power line ELVDD can provide a first power supply voltage signal. The second power line ELVSS can continuously provide a constant low-level signal; for example, the second power line ELVSS can provide a second power supply voltage signal. The first power supply voltage signal can be greater than the second power supply voltage signal.

[0117] In some examples, as shown in Figure 10, the drive circuit 1 may further include a first reset sub-circuit 17 and a third reset sub-circuit 18. The first reset sub-circuit 17 is connected to the first reset control line Reset1, the first initial voltage line INIT1, and the third node N3, and is configured to reset the third node N3 using the first initial voltage of the first initial voltage line INIT1 under the control of the first reset control line Reset1. The third reset sub-circuit 18 is connected to the second reset control line Reset2, the third initial voltage line INIT3, and the second node N2, and is configured to reset the second node N2 using the third initial voltage of the third initial voltage line INIT3 under the control of the second reset control line Reset2.

[0118] In some examples, the first reset control line Reset1 can be configured to provide a first reset control signal, and the second reset control line Reset2 can be configured to provide a second reset control signal. The first reset control signal can be configured to control the first reset sub-circuit 17 to reset the third node N3, and the second reset control signal can be configured to control the second reset sub-circuit 23 to reset the fourth node N4, and control the third reset sub-circuit 18 to reset the second node N2. The first reset control signal may be different from the second reset control signal.

[0119] In some examples, the first initial voltage line INIT1 can be configured to provide a first initial voltage signal. The second initial voltage line INIT2 can be configured to provide a second initial voltage signal, and the third initial voltage line INIT3 can be configured to provide a third initial voltage signal. The first, second, and third initial voltage signals can be different.

[0120] In some examples, the pixel circuit may also include a second reset stage and an anode potential adjustment stage during driving, located before the light emission stage and after the data writing stage. In the second reset stage, the second reset sub-circuit 23 is turned on under the control of the second reset control line Reset2, the first control sub-circuit 21 is turned on under the control of the light emission control line EM, and the second initial signal line INIT2 provides a second initial voltage signal to the first electrode of the light emission element and the second storage sub-circuit 22. In the anode potential adjustment stage, a data signal voltage is provided to the fourth initial signal line INIT4 so that the data signal voltage is written to the first electrode of the light emission element, thereby ensuring that the change in the data signal line voltage has a consistent effect on the first electrode of the light emission element of the entire screen sub-pixel.

[0121] In other examples, the pixel circuit may also include a first reset stage and a second reset stage, which are sequentially set before the data writing stage and the light emission stage, during driving. In the first reset stage, the second reset sub-circuit 23 is turned on under the control of the second reset control line Reset2, the first control sub-circuit 21 is turned on under the control of the light emission control line EM, and the second initial signal line INIT2 provides a second initial voltage signal to the first electrode of the light emission element and the second storage sub-circuit 22. In the second reset stage, a data signal voltage is provided to the fourth initial signal line INIT4 so that the data signal voltage is written to the first electrode of the light emission element, thereby ensuring that the change of the data signal line voltage has a consistent effect on the first electrode of the light emission element of the full-screen sub-pixel.

[0122] This embodiment of the present disclosure resets the fourth node N4 through the second reset sub-circuit 23, which can eliminate the residual positive charge on the surface of the first electrode of the light-emitting element and improve the lifespan of the light-emitting element. This embodiment of the present disclosure, through the first control sub-circuit 21, the second storage sub-circuit 22, and the second reset sub-circuit 23, can adjust the potential on the first electrode of the light-emitting element, thereby ensuring that changes in the data signal line voltage have a consistent anode effect on all sub-pixels across the screen, solving the problem of poor screen splitting.

[0123] Figure 11 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 11, the driving sub-circuit 11 may include a driving transistor T3; the compensation sub-circuit 12 may include a compensation transistor T2; the data writing sub-circuit 13 may include a data writing transistor T4; the first storage sub-circuit 14 may include a first capacitor Cst1; the first light emission control sub-circuit 15 may include a first light emission control transistor T5; the second light emission control sub-circuit 16 may include a second light emission control transistor T6; the first reset sub-circuit 17 may include a first reset transistor T1; the third reset sub-circuit 18 may include a third reset transistor T8; the first control sub-circuit 21 may include a first control transistor T9; the second storage sub-circuit 22 may include a second capacitor Cst2; and the second reset circuit 23 may include a second reset transistor T7.

[0124] In some examples, as shown in Figure 11, the gate of the first reset transistor T1 is coupled to the first reset control line Reset1, the first terminal of the first reset transistor T1 is coupled to the first initial voltage line INIT1, and the second terminal of the first reset transistor T1 is coupled to the third node N3. The gate of the compensation transistor T2 is coupled to the second scan signal line Gate2, the first terminal of the compensation transistor T2 is coupled to the third node N3, and the second terminal of the compensation transistor T2 is coupled to the first node N1. The gate of the drive transistor T3 is coupled to the first node N1, the first terminal of the drive transistor T3 is coupled to the second node N2, and the second terminal of the drive transistor T3 is coupled to the third node N3. The gate of the data write transistor T4 is coupled to the first scan signal line Gate1, the first terminal of the data write transistor T4 is coupled to the data signal line DATA, and the second terminal of the data write transistor T4 is coupled to the second node N2. The first plate of the first capacitor Cst1 is coupled to the first node N1, and the second plate of the first capacitor Cst1 is coupled to the first power supply line ELVDD. The gate of the first light-emitting control transistor T5 is coupled to the light-emitting control line EM, the first electrode of the first light-emitting control transistor T5 is coupled to the first power supply line ELVDD, and the second electrode of the first light-emitting control transistor T5 is coupled to the second node N2. The gate of the second light-emitting control transistor T6 is coupled to the light-emitting control line EM, the first electrode of the second light-emitting control transistor T6 is coupled to the third node N3, and the second electrode of the second light-emitting control transistor T6 is coupled to the fourth node N4. The gate of the second reset transistor T7 is coupled to the second reset control line Reset2, the first electrode of the second reset transistor T7 is coupled to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is coupled to the fourth node N4. The gate of the third reset transistor T8 is coupled to the second reset control line Reset2, the first electrode of the third reset transistor T8 is coupled to the third initial signal line INIT3, and the second electrode of the third reset transistor T8 is coupled to the second node N2. The first electrode of the light-emitting element L is coupled to the fourth node N4, and the second electrode of the light-emitting element L is coupled to the second power supply line ELVSS. The first plate of the second capacitor Cst2 is coupled to the fifth node N5, and the second plate of the second capacitor Cst2 is coupled to the fourth initial signal line INIT4. The gate of the first control transistor T9 is coupled to the light-emitting control line EM, the first terminal of the first control transistor T9 is coupled to the fourth node N4, and the second terminal of the first control transistor T9 is coupled to the fifth node N5.

[0125] In some examples, the first node N1 is the connection point of the first capacitor Cst1, the compensation transistor T2, and the driving transistor T3. The second node N2 is the connection point of the driving transistor T3, the first light-emitting control transistor T5, the data writing transistor T4, and the third reset transistor T8. The third node N3 is the connection point of the first reset transistor T1, the compensation transistor T2, the driving transistor T3, and the second light-emitting control transistor T6. The fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, the light-emitting element L, and the first control transistor T9. The fifth node N5 is the connection point of the second capacitor Cst2 and the first control transistor T9.

[0126] Figure 11 shows an exemplary structure of the driving sub-circuit 11, compensation sub-circuit 12, data writing sub-circuit 13, first storage sub-circuit 14, first light-emitting control sub-circuit 15, second light-emitting control sub-circuit 16, first reset sub-circuit 17, third reset sub-circuit 18, first control sub-circuit 21, second storage sub-circuit 22, and second reset sub-circuit 23. It is readily understood by those skilled in the art that the implementation of the above sub-circuits is not limited to this, as long as their functions can be achieved.

[0127] In some examples, as shown in Figure 11, the compensation transistor T2 and the first control transistor T9 can be N-type transistors. For example, the compensation transistor T2 can be an N-type metal-oxide-slim (MOS) transistor. MOS transistors have low leakage current, thus preventing leakage at the first node N1 during the light-emitting stage. Meanwhile, the first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8 can be P-type thin-film transistors. For example, the first reset transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset transistor T7, and third reset transistor T8 can be P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors. LTSPS have high carrier mobility, which is beneficial for achieving high-resolution, high-response-speed, high-pixel-density, and high-aperture-ratio display panels. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 can output the same or different voltage signals depending on the actual situation.

[0128] In some examples, the pixel circuit of this disclosure may include a first working period and a second working period within a frame display cycle, wherein the number of first working periods and the number of second working periods can be set as needed. For example, a frame display cycle may include one first working period and two second working periods; however, this disclosure is not limited thereto. In other examples, the pixel circuit of this disclosure may include only the first working period within a frame display cycle.

[0129] In this embodiment, the difference between the first working period and the second working period is that the first working period includes a data writing phase, while the second working period does not include a data writing phase. In some examples, both the first and second working periods may include a reset phase and a light-emitting phase, respectively. The pixel circuit in this example can adjust the brightness of the light-emitting element by controlling the effective level duration of the light-emitting control signal during the first and second working periods.

[0130] In some examples, the pixel circuit of this embodiment can be driven by timing as shown in FIG9. Exemplarily, the first working period may include a first reset stage, a data writing stage (or threshold compensation stage), a second reset stage, an anode potential adjustment stage, and a light emission stage arranged sequentially, and the second working period may include the first reset stage, the second reset stage, the anode potential adjustment stage, and the light emission stage arranged sequentially.

[0131] As shown in Figure 9, the pixel circuit includes a first stage t1, a second stage t2, a third stage t3, a transition stage t3-1, and a fourth stage t4 set sequentially during the first working period.

[0132] The first stage t1 can also be called the first reset stage (first node N1 reset stage). In the first stage t1, the signal of the first reset control line Reset1 is a low-level signal, while the signals of the first scan signal line Gate1, the second scan signal line Gate2, the second reset control line Reset2, and the light emission control line EM are all high-level signals. The first reset transistor T1 is turned on under the control of the first reset control signal of the first reset control line Reset1, the compensation transistor T2 is turned on under the control of the second scan signal of the second scan signal line Gate2, the first control transistor T9 is turned on under the control of the light emission control signal of the light emission control line EM, and the other transistors are turned off.

[0133] The first reset transistor T1 is turned on, providing the first initial voltage signal of the first initial signal line INIT1 to the third node N3. The compensation transistor T2 is turned on, connecting the first node N1 and the third node N3. The voltage of the first node N1 is reset to the first initial voltage Vinit1. Since the voltage of the first node N1 is reset to the first initial voltage Vinit1, the driving transistor T3 is turned on. The first control transistor T9 is turned on, connecting the fifth node N5 and the fourth node N4. The voltages of the fifth node N5 and the fourth node N4 are both the anode voltage (second initial voltage Vinit2) when the light-emitting element emitted light last time.

[0134] The second stage, t2, can also be called the data writing stage or the threshold compensation stage. In the second stage, t2, the signal of the first scan signal line Gate1 is a low-level signal, while the signals of the second scan signal line Gate2, the first reset control line Reset1, the second reset control line Reset2, and the light emission control line EM are all high-level signals. The data writing transistor T4 is turned on under the control of the first scan signal of the first scan signal line Gate1, and the compensation transistor T2 remains on under the control of the second scan signal of the second scan signal line Gate2. Since the voltage of the first node N1 is the first initial voltage Vinit1, the driving transistor T3 is turned on, and the first control transistor T9 remains on under the control of the light emission control signal of the light emission control line EM. The other transistors are turned off.

[0135] Compensation transistor T2 remains on, maintaining communication between the first node N1 and the third node N3. Data write transistor T4 is on, allowing the data voltage signal output from the data signal line DATA to be supplied to the first node N1 via the second node N2, the on-state driving transistor T3, the third node N3, and the on-state compensation transistor T2. The sum of the data voltage output from the data signal line DATA and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst. The voltage at the first node N1 is Vdata + Vth, where Vdata is the data voltage output from the data signal line DATA, and Vth is the threshold voltage of the driving transistor T3. The first control transistor T9 remains on, and the voltages at the fifth node N5 and the fourth node N4 remain at the anode voltage (second initial voltage Vinit2) from the previous time the light-emitting element emitted light.

[0136] The third stage, t3, can also be called the second reset stage (the reset stage of the second node N2 and the fourth node N4). In the third stage, t3, the signal of the second scan signal line Gate2 is a low-level signal, the signal of the second reset control line Reset2 is a low-level signal, and the signals of the first scan signal line Gate1, the first reset control line Reset1, and the light emission control line EM are all high-level signals. The second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal of the second reset control line Reset2. The first control transistor T9 remains on under the control of the light emission control signal of the light emission control line EM, and the other transistors are off.

[0137] The second reset transistor T7 turns on, providing the second initial voltage signal of the second initial signal line INIT2 to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device L, clearing the original charge in the first electrode of the light-emitting device L, and setting the potential of the fourth node N4 to the second initial voltage Vinit2. Simultaneously, the first control transistor T9 turns on, causing the second initial voltage Vinit2 of the fourth node N4 to be stored in the second capacitor Cst2. The third reset transistor T8 turns on, providing the third initial voltage signal of the third initial signal line INIT3 to the second node N2, initializing (resetting) the second node N2, and setting the potential of the second node N2 to the third initial voltage Vinit3.

[0138] During the transition phase t3-1 between the third stage t3 and the fourth stage t4, the second reset signal provided by the second reset control line Reset2 jumps to a high level, while the remaining signals remain in the state of the third stage t3. The second reset transistor T7 and the third reset transistor T8 are turned off.

[0139] At this time, since the first control transistor T9 remains on, adjusting the fourth initial signal voltage of the fourth initial signal line INIT4 (the adjustment amount is consistent with the data signal voltage to be written) can cause the voltage of the second capacitor Cst2 to jump (the jump amount is consistent with the data signal voltage to be written), thereby adjusting the voltage of the fourth node N4 (sub-pixel anode) to ensure that the change in the data signal line voltage has a consistent effect on the anode of the sub-pixels across the entire screen.

[0140] The fourth stage, t4, can also be called the light-emitting stage. In the fourth stage, t4, the signal of the light-emitting control line EM is a low-level signal, the signal of the second scan signal line Gate2 is a low-level signal, and the signals of the first scan signal line Gate1, the first reset control line Reset1, and the second reset control line Reset2 are all high-level signals. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal of the light-emitting control line EM. The power supply voltage output from the first power supply line ELVDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting device L to emit light.

[0141] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vdata + Vth, the driving current flowing through the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdd-Vdata)] 2 ;

[0142] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data signal line DATA, and Vdd is the power supply voltage output by the first power supply line ELVDD.

[0143] The pixel circuit of this embodiment may include a first stage t1 (first reset stage), a third stage t3 (second reset stage), a transition stage t3-1 (anode potential adjustment stage), and a fourth stage t4 (light emission stage) set sequentially during the second working period, but does not include the second stage t2 (data writing stage or threshold compensation stage). The specific working process can be referred to the previous text and will not be repeated here. Since the first electrode of the light-emitting element can be written with the data signal voltage of the data signal line during the second working period, the pixel circuit of this embodiment ensures that the voltage change of the data signal line has a consistent anode effect on the sub-pixels of the entire screen within one frame display cycle.

[0144] Figure 12 is another timing diagram of the pixel circuit shown in Figure 11 during the first working period. In other examples, the pixel circuit of this embodiment can also adopt the timing drive shown in Figure 12. Exemplarily, the first working period may include a first reset stage, a second reset stage, a data writing stage (or threshold compensation stage), and a light emission stage arranged in sequence, and the second working period includes a first reset stage, a second reset stage, and a light emission stage arranged in sequence.

[0145] As shown in Figure 12, the pixel circuit includes a first stage A1, a second stage A2, a third stage A3 and a fourth stage A4 set sequentially during the first working period.

[0146] The first stage, A1, can also be called the first reset stage (the reset stages of the second node N2 and the fourth node N4). In the first stage, A1, the signal of the second scan signal line Gate2 is a low-level signal, the signal of the second reset control line Reset2 is a low-level signal, and the signals of the first scan signal line Gate1, the first reset control line Reset1, and the light emission control line EM are all high-level signals. The second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal of the second reset control line Reset2, the first control transistor T9 is turned on under the control of the light emission control signal of the light emission control line EM, and the other transistors are turned off.

[0147] The second reset transistor T7 turns on, providing the second initial voltage signal of the second initial signal line INIT2 to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device L, clearing the original charge in the first electrode of the light-emitting device L, and setting the potential of the fourth node N4 to the second initial voltage Vinit2. Simultaneously, the first control transistor T9 turns on, causing the second initial voltage Vinit2 of the fourth node N4 to be stored in the second capacitor Cst2. The third reset transistor T8 turns on, providing the third initial voltage signal of the third initial signal line INIT3 to the second node N2, initializing (resetting) the second node N2, and setting the potential of the second node N2 to the third initial voltage Vinit3.

[0148] The second stage, A2, can also be called the second reset stage (the first node N1 reset stage). In the second stage, A2, the signal of the first reset control line Reset1 is a low-level signal, while the signals of the first scan signal line Gate1, the second scan signal line Gate2, the second reset control line Reset2, and the light emission control line EM are all high-level signals. The first reset transistor T1 is turned on under the control of the first reset control signal of the first reset control line Reset1, the compensation transistor T2 is turned on under the control of the second scan signal of the second scan signal line Gate2, the first control transistor T9 remains on under the control of the light emission control signal of the light emission control line EM, and the other transistors are off.

[0149] The first reset transistor T1 is turned on, providing the first initial voltage signal of the first initial signal line INIT1 to the third node N3. The compensation transistor T2 is turned on, connecting the first node N1 and the third node N3. The voltage of the first node N1 is reset to the first initial voltage Vinit1. Since the voltage of the first node N1 is reset to the first initial voltage Vinit1, the driving transistor T3 is turned on. In addition, since the first control transistor T9 is turned on, adjusting the fourth initial signal voltage of the fourth initial signal line INIT4 (the adjustment amount is consistent with the data signal voltage to be written) can cause a jump in the voltage of the second capacitor Cst2 (the jump amount is consistent with the data signal voltage to be written), thereby adjusting the sub-pixel anode voltage and ensuring that the change in the data signal line voltage has a consistent effect on the anode of the sub-pixels across the entire screen.

[0150] The third stage, A3, can also be called the data writing stage or the threshold compensation stage. In the third stage, A3, the signal of the first scan signal line Gate1 is a low-level signal, while the signals of the second scan signal line Gate2, the first reset control line Reset1, the second reset control line Reset2, and the light emission control line EM are all high-level signals. The data writing transistor T4 is turned on under the control of the first scan signal of the first scan signal line Gate1, and the compensation transistor T2 remains on under the control of the second scan signal of the second scan signal line Gate2. Since the voltage of the first node N1 is the first initial voltage Vinit1, the driving transistor T3 is turned on, and the first control transistor T9 remains on under the control of the light emission control signal of the light emission control line EM. The other transistors are turned off.

[0151] Compensation transistor T2 remains on, maintaining connectivity between the first node N1 and the third node N3. Data write transistor T4 is on, allowing the data voltage signal output from the data signal line DATA to be supplied to the first node N1 via the second node N2, the on-state driving transistor T3, the third node N3, and the on-state compensation transistor T2. The sum of the data voltage output from the data signal line DATA and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst. The voltage of the first node N1 is Vdata + Vth, where Vdata is the data voltage output from the data signal line DATA, and Vth is the threshold voltage of the driving transistor T3. The first control transistor T9 remains on, ensuring the sub-pixel anode voltage remains consistent with the second stage t2.

[0152] The fourth stage, A4, can also be called the light-emitting stage. In the fourth stage, A4, the signal of the light-emitting control line EM is a low-level signal, the signal of the second scan signal line Gate2 is a low-level signal, and the signals of the first scan signal line Gate1, the first reset control line Reset1, and the second reset control line Reset2 are all high-level signals. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal of the light-emitting control line EM. The power supply voltage output from the first power supply line ELVDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting device L to emit light.

[0153] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the first node N1 is Vdata + Vth, the driving current flowing through the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdata+Vth-Vdd)-Vth] 2 =K*[(Vdd-Vdata)] 2 ;

[0154] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data signal line DATA, and Vdd is the power supply voltage output by the first power supply line ELVDD.

[0155] The pixel circuit of this embodiment may include a first stage A1 (first reset stage), a second stage A2 (second reset stage), and a fourth stage A4 (light emission stage) set sequentially during the second working period, but does not include the third stage A3 (data writing stage or threshold compensation stage). The specific working process can be referred to the previous text and will not be repeated here. Since the first electrode of the light-emitting element can still be written with the data signal voltage of the data signal line during the second working period, the pixel circuit of this embodiment ensures that the voltage change of the data signal line has a consistent impact on the anode of the sub-pixels across the entire screen within one frame display cycle.

[0156] This disclosure also provides a method for driving a pixel circuit to drive the pixel circuit provided in the above embodiments. In an exemplary embodiment, as shown in FIG13, the method for driving the pixel circuit includes:

[0157] Step 1301: Under the control of the first scan signal line, the driving circuit receives the data signal from the data signal line; under the control of the light emission control line, the potential adjustment circuit writes the data signal into the first electrode of the light emission element.

[0158] Step 1302: Under the control of the light-emitting control line, the driving circuit drives the light-emitting element to emit light according to the received data signal.

[0159] In some examples, the potential adjustment circuit includes a second reset sub-circuit, a second storage sub-circuit, and a first control sub-circuit; the pixel circuit includes a first working period and a second working period within a frame display cycle. The first working period includes a first reset stage, a data writing stage, a second reset stage, and a light emission stage arranged sequentially. The second working period includes a first reset stage, a second reset stage, and a light emission stage arranged sequentially.

[0160] Under the control of the light-emitting control line, the potential adjustment circuit writes data signals into the first electrode of the light-emitting element, including:

[0161] During the data writing phase, the second storage sub-circuit stores the data signals in the data signal lines;

[0162] During the second reset phase, the second reset sub-circuit, under the control of the second reset control line, writes the data signal in the second storage sub-circuit into the first electrode of the light-emitting element;

[0163] During the light-emitting stage, the first control sub-circuit resets the second storage sub-circuit under the control of the light-emitting control line.

[0164] In some examples, the driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a third reset sub-circuit, a first light-emitting control sub-circuit, and a second light-emitting control sub-circuit; the driving circuit also includes a first node, a second node, and a third node, wherein the first node is the connection point between the driving sub-circuit and the compensation sub-circuit, the second node is the connection point between the driving sub-circuit, the data writing sub-circuit, the third reset sub-circuit, and the first light-emitting control sub-circuit, and the third node is the connection point between the driving sub-circuit, the compensation sub-circuit, the first reset sub-circuit, and the second light-emitting control sub-circuit;

[0165] The driving circuit, under the control of the first scan signal line, receives data signals from the data signal line, and under the control of the light emission control line, drives the light-emitting element to emit light according to the received data signals, including:

[0166] In the first reset phase, the first reset sub-circuit resets the third node under the control of the first reset control line, and the compensation sub-circuit resets the voltage of the first node using the voltage of the third node under the control of the second scan signal line.

[0167] During the data writing phase, the data writing sub-circuit, under the control of the first scan signal line, writes the data signal of the data signal line to the second node; the compensation sub-circuit, under the control of the second scan signal line, writes the threshold voltage of the driving sub-circuit to the first node.

[0168] During the second reset phase, the third reset sub-circuit resets the second node under the control of the second reset control line;

[0169] During the light-emitting stage, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are turned on under the control of the light-emitting control line, and the driving sub-circuit drives the light-emitting element to emit light.

[0170] In other examples, the potential adjustment circuit includes a second reset sub-circuit, a second storage sub-circuit, and a first control sub-circuit; the pixel circuit includes a first working period and a second working period within a frame display cycle. The first working period includes a first reset stage, a data writing stage, a second reset stage, an anode potential adjustment stage, and a light emission stage arranged sequentially. The second working period includes a first reset stage, a second reset stage, an anode potential adjustment stage, and a light emission stage arranged sequentially.

[0171] Under the control of the light-emitting control line, the potential adjustment circuit writes data signals into the first electrode of the light-emitting element, including:

[0172] In the second reset phase, the second reset sub-circuit, under the control of the second reset control line, uses the signal of the second initial signal line to reset the first electrode of the light-emitting element; the first control sub-circuit, under the control of the light-emitting control line, uses the voltage of the first electrode of the light-emitting element to reset the second storage circuit.

[0173] During the anode potential adjustment phase, the second storage sub-circuit stores the voltage jump variable in the fourth initial signal line, which is the same as the data signal in the data signal line; under the control of the light emission control line, the first control sub-circuit writes the voltage jump variable stored in the second storage sub-circuit into the first electrode of the light emission element.

[0174] In some examples, the driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a third reset sub-circuit, a first light-emitting control sub-circuit, and a second light-emitting control sub-circuit; the driving circuit also includes a first node, a second node, and a third node, wherein the first node is the connection point between the driving sub-circuit and the compensation sub-circuit, the second node is the connection point between the driving sub-circuit, the data writing sub-circuit, the third reset sub-circuit, and the first light-emitting control sub-circuit, and the third node is the connection point between the driving sub-circuit, the compensation sub-circuit, the first reset sub-circuit, and the second light-emitting control sub-circuit;

[0175] The driving circuit, under the control of the first scan signal line, receives data signals from the data signal line, and under the control of the light emission control line, drives the light-emitting element to emit light according to the received data signals, including:

[0176] In the first reset phase, the first reset sub-circuit resets the third node under the control of the first reset control line, and the compensation sub-circuit resets the voltage of the first node using the voltage of the third node under the control of the second scan signal line.

[0177] During the data writing phase, the data writing sub-circuit, under the control of the first scan signal line, writes the data signal of the data signal line to the second node; the compensation sub-circuit, under the control of the second scan signal line, writes the threshold voltage of the driving sub-circuit to the first node.

[0178] During the second reset phase, the third reset sub-circuit resets the second node under the control of the second reset control line;

[0179] During the light-emitting stage, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are turned on under the control of the light-emitting control line, and the driving sub-circuit drives the light-emitting element to emit light.

[0180] In some other examples, the potential adjustment circuit includes a second reset sub-circuit, a second storage sub-circuit, and a first control sub-circuit; the pixel circuit includes a first working period and a second working period within a frame display cycle. The first working period includes a first reset stage, a second reset stage, a data writing stage, and a light emission stage arranged sequentially. The second working period includes a first reset stage, a second reset stage, and a light emission stage arranged sequentially.

[0181] Under the control of the light-emitting control line, the potential adjustment circuit writes the data signal from the data signal line into the first electrode of the light-emitting element, including:

[0182] In the first reset phase, the second reset sub-circuit, under the control of the second reset control line, uses the signal of the second initial signal line to reset the first electrode of the light-emitting element; the first control sub-circuit, under the control of the light-emitting control line, uses the voltage of the first electrode of the light-emitting element to reset the second storage circuit.

[0183] During the second reset phase, the second storage sub-circuit stores the voltage jump variable in the fourth initial signal line, which is the same as the data signal in the data signal line; under the control of the light-emitting control line, the first control sub-circuit writes the voltage jump variable stored in the second storage sub-circuit into the first electrode of the light-emitting element.

[0184] In some examples, the driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a third reset sub-circuit, a first light-emitting control sub-circuit, and a second light-emitting control sub-circuit; the driving circuit also includes a first node, a second node, and a third node, wherein the first node is the connection point between the driving sub-circuit and the compensation sub-circuit, the second node is the connection point between the driving sub-circuit, the data writing sub-circuit, the third reset sub-circuit, and the first light-emitting control sub-circuit, and the third node is the connection point between the driving sub-circuit, the compensation sub-circuit, the first reset sub-circuit, and the second light-emitting control sub-circuit;

[0185] The driving circuit, under the control of the first scan signal line, receives data signals from the data signal line, and under the control of the light emission control line, drives the light-emitting element to emit light according to the received data signals, including:

[0186] During the first reset phase, the third reset sub-circuit resets the second node under the control of the second reset control line;

[0187] In the second reset phase, the first reset sub-circuit resets the third node under the control of the first reset control line, and the compensation sub-circuit resets the voltage of the first node using the voltage of the third node under the control of the second scan signal line.

[0188] During the data writing phase, the data writing sub-circuit, under the control of the first scan signal line, writes the data signal of the data signal line to the second node; the compensation sub-circuit, under the control of the second scan signal line, writes the threshold voltage of the driving sub-circuit to the first node.

[0189] During the light-emitting stage, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are turned on under the control of the light-emitting control line, and the driving sub-circuit drives the light-emitting element to emit light.

[0190] This disclosure also provides a display substrate, which includes the aforementioned pixel circuit.

[0191] This disclosure also provides a display device, which includes the aforementioned display substrate.

[0192] In an exemplary embodiment, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This embodiment of the invention is not limited thereto.

[0193] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0194] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0195] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A pixel circuit, comprising a driving circuit and a potential adjustment circuit interconnected, wherein: The driving circuit is connected to the first scan signal line, the data signal line, the light emission control line, and the light emission element, and is configured to receive the data signal from the data signal line under the control of the first scan signal line. Under the control of the light-emitting control line, the light-emitting element is driven to emit light according to the received data signal; The potential adjustment circuit is connected to the light emission control line and is configured to acquire the data signal before the light emission element emits light, and write the data signal into the first electrode of the light emission element under the control of the light emission control line.

2. The pixel circuit according to claim 1, wherein, The potential adjustment circuit includes a first control sub-circuit, a second reset sub-circuit, and a second storage sub-circuit. The first control sub-circuit is connected to the light emission control line, the second initial signal line, and the second storage sub-circuit, and is configured to reset the second storage sub-circuit under the control of the light emission control line; The second reset sub-circuit is connected to the second reset control line, the first electrode of the light-emitting element, and the second storage sub-circuit, respectively, and is configured to write the data signal in the second storage sub-circuit into the first electrode of the light-emitting element under the control of the second reset control line; The second storage sub-circuit is connected to the data signal line and configured to store the data signal of the data signal line.

3. The pixel circuit according to claim 2, wherein, The first control sub-circuit includes a first control transistor, the second reset sub-circuit includes a second reset transistor, and the second storage sub-circuit includes a second capacitor; The control electrode of the first control transistor is connected to the light-emitting control line, the first electrode of the first control transistor is connected to the second initial signal line, and the second electrode of the first control transistor is connected to the fifth node. The control electrode of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the fifth node, the second electrode of the second reset transistor is connected to the fourth node, and the fourth node is connected to the first electrode of the light-emitting element. One end of the second capacitor is connected to the data signal line, and the other end of the second capacitor is connected to the fifth node.

4. The pixel circuit according to claim 1, wherein, The potential adjustment circuit includes a first control sub-circuit, a second reset sub-circuit, and a second storage sub-circuit. The first control sub-circuit is connected to the light-emitting control line, the first electrode of the light-emitting element, and the second storage sub-circuit, respectively, and is configured to connect the first electrode of the light-emitting element and the second storage sub-circuit under the control of the light-emitting control line, so as to write the voltage jump variable stored in the second storage sub-circuit into the first electrode of the light-emitting element, or to reset the second storage circuit using the voltage of the first electrode of the light-emitting element. The second reset sub-circuit is connected to the second reset control line, the second initial signal line and the first electrode of the light-emitting element, respectively, and is configured to reset the first electrode of the light-emitting element using the signal of the second initial signal line under the control of the second reset control line; The second storage sub-circuit is connected to the fourth initial signal line and configured to store the voltage jump variables in the fourth initial signal line.

5. The pixel circuit according to claim 4, wherein, The first control sub-circuit includes a first control transistor, the second reset sub-circuit includes a second reset transistor, and the second storage sub-circuit includes a second capacitor; The control electrode of the first control transistor is connected to the light-emitting control line, the first electrode of the first control transistor is connected to the fourth node, the second electrode of the first control transistor is connected to the fifth node, and the fourth node is connected to the first electrode of the light-emitting element. The control electrode of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the fourth node. One end of the second capacitor is connected to the fourth initial signal line, and the other end of the second capacitor is connected to the fifth node.

6. The pixel circuit according to claim 1, wherein, The driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a first storage sub-circuit. The driving sub-circuit is connected to the first node, the second node and the third node, and is configured to provide a driving signal to the third node under the control of the first node; The data writing sub-circuit is connected to the first scan signal line, the data signal line and the second node respectively, and is configured to write the data signal of the data signal line to the second node under the control of the first scan signal line; The compensation sub-circuit is connected to the second scan signal line, the first node, and the third node, and is configured to turn on the first node and the third node under the control of the second scan signal line, so that the threshold voltage of the driving sub-circuit is written to the first node; The first storage sub-circuit is connected to the first node and the first power line.

7. The pixel circuit according to claim 6, wherein, The driving sub-circuit includes a driving transistor, the data writing sub-circuit includes a data writing transistor, the compensation sub-circuit includes a compensation transistor, and the first storage sub-circuit includes a first capacitor. The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node; The control electrode of the data writing transistor is connected to the first scan signal line, the first electrode of the data writing transistor is connected to the data signal line, and the second electrode of the data writing transistor is connected to the second node. The control electrode of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the third node; One end of the first capacitor is connected to the first power line, and the other end of the first capacitor is connected to the first node.

8. The pixel circuit according to claim 6, wherein, The driving circuit further includes a first reset circuit and a third reset circuit; The first reset sub-circuit is connected to the first reset control line, the first initial signal line and the third node, and is configured to reset the third node under the control of the first reset control line; The third reset sub-circuit is connected to the second reset control line, the third initial signal line and the second node, and is configured to reset the second node under the control of the second reset control line.

9. The pixel circuit according to claim 8, wherein, The first reset sub-circuit includes a first reset transistor, and the third reset sub-circuit includes a third reset transistor; The control electrode of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the third node. The control electrode of the third reset transistor is connected to the second reset signal line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the second node.

10. The pixel circuit according to claim 8, wherein, The driving circuit also includes a first light-emitting control sub-circuit and a second light-emitting control sub-circuit; The first light-emitting control sub-circuit is connected to the light-emitting control line, the first power line and the second node, and is configured to write the first power signal provided by the first power line to the second node under the control of the light-emitting control line. The second light-emitting control sub-circuit is connected to the light-emitting control line, the third node, and the fourth node, and is configured to conduct the third node and the fourth node under the control of the light-emitting control line, wherein the fourth node is connected to the first electrode of the light-emitting element.

11. The pixel circuit according to claim 10, wherein, The first light-emitting control sub-circuit includes a first light-emitting control transistor, and the second light-emitting control sub-circuit includes a second light-emitting control transistor; The control electrode of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power line, and the second electrode of the first light-emitting control transistor is connected to the second node. The control electrode of the second light-emitting control transistor is connected to the light-emitting control line, the first electrode of the second light-emitting control transistor is connected to the third node, and the second electrode of the second light-emitting control transistor is connected to the fourth node.

12. The pixel circuit according to claim 1, wherein, The driving circuit includes a driving transistor, a compensation transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a third reset transistor, and a first capacitor; the potential adjustment circuit includes a first control transistor, a second reset transistor, and a second capacitor. The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node. The control electrode of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the third node. The control electrode of the data writing transistor is connected to the first scan signal line, the first electrode of the data writing transistor is connected to the data signal line, and the second electrode of the data writing transistor is connected to the second node. The control electrode of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the third node. The control electrode of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the fifth node, and the second electrode of the second reset transistor is connected to the fourth node; The control electrode of the third reset transistor is connected to the second reset signal line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the second node. The control electrode of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power supply line, and the second electrode of the first light-emitting control transistor is connected to the second node. The control electrode of the second light-emitting control transistor is connected to the light-emitting control line, the first electrode of the second light-emitting control transistor is connected to the third node, and the second electrode of the second light-emitting control transistor is connected to the fourth node; The control electrode of the first control transistor is connected to the light emission control line, the first electrode of the first control transistor is connected to the second initial signal line, and the second electrode of the first control transistor is connected to the fifth node. One end of the first capacitor is connected to the first power line, and the other end of the first capacitor is connected to the first node. One end of the second capacitor is connected to the data signal line, and the other end of the second capacitor is connected to the fifth node.

13. The pixel circuit according to claim 12, wherein, The compensation transistor is an N-type transistor, and the driving transistor, data writing transistor, first light-emitting control transistor, second light-emitting control transistor, first reset transistor, second reset transistor, third reset transistor, and first control transistor are P-type transistors.

14. The pixel circuit according to claim 1, wherein, The driving circuit includes a driving transistor, a compensation transistor, a data writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a third reset transistor, and a first capacitor; the potential adjustment circuit includes a first control transistor, a second reset transistor, and a second capacitor. The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node. The control electrode of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the third node. The control electrode of the data writing transistor is connected to the first scan signal line, the first electrode of the data writing transistor is connected to the data signal line, and the second electrode of the data writing transistor is connected to the second node. The control electrode of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the third node. The control electrode of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the fourth node. The control electrode of the third reset transistor is connected to the second reset signal line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the second node. The control electrode of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power supply line, and the second electrode of the first light-emitting control transistor is connected to the second node. The control electrode of the second light-emitting control transistor is connected to the light-emitting control line, the first electrode of the second light-emitting control transistor is connected to the third node, and the second electrode of the second light-emitting control transistor is connected to the fourth node; The control electrode of the first control transistor is connected to the light emission control line, the first electrode of the first control transistor is connected to the fourth node, and the second electrode of the first control transistor is connected to the fifth node. One end of the first capacitor is connected to the first power line, and the other end of the first capacitor is connected to the first node. One end of the second capacitor is connected to the fourth initial signal line, and the other end of the second capacitor is connected to the fifth node.

15. The pixel circuit according to claim 14, wherein, The compensation transistor and the first control transistor are N-type transistors, while the driving transistor, data writing transistor, first light-emitting control transistor, second light-emitting control transistor, first reset transistor, second reset transistor, and third reset transistor are P-type transistors.

16. A display substrate, comprising: The pixel circuit as described in any one of claims 1 to 15.

17. A method for driving a pixel circuit, comprising: The driving circuit receives data signals from the data signal line under the control of the first scan signal line; Under the control of the light-emitting control line, the potential adjustment circuit writes the data signal into the first electrode of the light-emitting element; The driving circuit, under the control of the light-emitting control line, drives the light-emitting element to emit light according to the received data signal.

18. The driving method according to claim 17, wherein, The potential adjustment circuit includes a second reset sub-circuit, a second storage sub-circuit, and a first control sub-circuit; the pixel circuit includes a first working period and a second working period within a frame display cycle, the first working period including a first reset stage, a data writing stage, a second reset stage, and a light emission stage arranged sequentially, and the second working period including a first reset stage, a second reset stage, and a light emission stage arranged sequentially; Under the control of the light-emitting control line, the potential adjustment circuit writes the data signal into the first electrode of the light-emitting element, including: During the data writing phase, the second storage sub-circuit stores the data signal in the data signal line; During the second reset phase, under the control of the second reset control line, the second reset sub-circuit writes the data signal in the second storage sub-circuit into the first electrode of the light-emitting element; During the light-emitting phase, the first control sub-circuit, under the control of the light-emitting control line, resets the second storage sub-circuit.

19. The driving method according to claim 17, wherein, The potential adjustment circuit includes a second reset sub-circuit, a second storage sub-circuit, and a first control sub-circuit; the pixel circuit includes a first working period and a second working period within a frame display cycle. The first working period includes a first reset stage, a data writing stage, a second reset stage, an anode potential adjustment stage, and a light emission stage arranged sequentially. The second working period includes a first reset stage, a second reset stage, an anode potential adjustment stage, and a light emission stage arranged sequentially. Under the control of the light-emitting control line, the potential adjustment circuit writes the data signal into the first electrode of the light-emitting element, including: During the second reset phase, the second reset sub-circuit, under the control of the second reset control line, uses the signal of the second initial signal line to reset the first electrode of the light-emitting element; the first control sub-circuit, under the control of the light-emitting control line, uses the voltage of the first electrode of the light-emitting element to reset the second storage circuit. During the anode potential adjustment phase, the second storage sub-circuit stores the voltage jump variable in the fourth initial signal line, which is the same as the data signal in the data signal line; under the control of the light emission control line, the first control sub-circuit writes the voltage jump variable stored in the second storage sub-circuit into the first electrode of the light emission element.

20. The driving method according to claim 18 or 19, wherein, The driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a third reset sub-circuit, a first light emission control sub-circuit, and a second light emission control sub-circuit; the driving circuit also includes a first node, a second node, and a third node, wherein the first node is the connection point between the driving sub-circuit and the compensation sub-circuit, the second node is the connection point between the driving sub-circuit, the data writing sub-circuit, the third reset sub-circuit, and the first light emission control sub-circuit, and the third node is the connection point between the driving sub-circuit, the compensation sub-circuit, the first reset sub-circuit, and the second light emission control sub-circuit; The driving circuit, under the control of the first scan signal line, receives data signals from the data signal line, and under the control of the light emission control line, drives the light-emitting element to emit light according to the received data signals, including: During the first reset phase, the first reset sub-circuit, under the control of the first reset control line, controls the... The third node is reset, and the compensation sub-circuit, under the control of the second scan signal line, uses the voltage of the third node to reset the voltage of the first node; During the data writing phase, the data writing sub-circuit, under the control of the first scan signal line, writes the data signal of the data signal line to the second node; the compensation sub-circuit, under the control of the second scan signal line, writes the threshold voltage of the driving sub-circuit to the first node. During the second reset phase, the third reset sub-circuit resets the second node under the control of the second reset control line; During the light-emitting stage, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are turned on under the control of the light-emitting control line, and the driving sub-circuit drives the light-emitting element to emit light.

21. The driving method according to claim 17, wherein, The potential adjustment circuit includes a second reset sub-circuit, a second storage sub-circuit, and a first control sub-circuit; the pixel circuit includes a first working period and a second working period within a frame display cycle, the first working period including a first reset stage, a second reset stage, a data writing stage, and a light emission stage arranged sequentially, and the second working period including a first reset stage, a second reset stage, and a light emission stage arranged sequentially; Under the control of the light-emitting control line, the potential adjustment circuit writes the data signal into the first electrode of the light-emitting element, including: During the first reset phase, the second reset sub-circuit, under the control of the second reset control line, uses the signal of the second initial signal line to reset the first electrode of the light-emitting element; Under the control of the light-emitting control line, the first control sub-circuit resets the second storage circuit using the voltage of the first electrode of the light-emitting element; During the second reset phase, the second storage sub-circuit stores the voltage jump variable in the fourth initial signal line, which is the same as the data signal in the data signal line; under the control of the light emission control line, the first control sub-circuit writes the voltage jump variable stored in the second storage sub-circuit into the first electrode of the light emission element.

22. The driving method according to claim 21, wherein, The driving circuit includes a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, a third reset sub-circuit, a first light emission control sub-circuit, and a second light emission control sub-circuit; the driving circuit also includes a first node, a second node, and a third node, wherein the first node is the connection point between the driving sub-circuit and the compensation sub-circuit, the second node is the connection point between the driving sub-circuit, the data writing sub-circuit, the third reset sub-circuit, and the first light emission control sub-circuit, and the third node is the connection point between the driving sub-circuit, the compensation sub-circuit, the first reset sub-circuit, and the second light emission control sub-circuit; The driving circuit, under the control of the first scan signal line, receives data signals from the data signal line, and under the control of the light emission control line, drives the light-emitting element to emit light according to the received data signals, including: During the first reset phase, the third reset sub-circuit resets the second node under the control of the second reset control line; In the second reset phase, the first reset sub-circuit resets the third node under the control of the first reset control line, and the compensation sub-circuit resets the voltage of the first node using the voltage of the third node under the control of the second scan signal line. During the data writing phase, the data writing sub-circuit, under the control of the first scan signal line, writes the data signal of the data signal line to the second node; the compensation sub-circuit, under the control of the second scan signal line, Write the threshold voltage of the driving sub-circuit into the first node; During the light-emitting stage, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are turned on under the control of the light-emitting control line, and the driving sub-circuit drives the light-emitting element to emit light.

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