Pixel driving circuit and display device
By using a 7T2C pixel driving circuit, and by utilizing dual-gate transistors and capacitors to compensate for the charging time of the driving circuit, the problem of uneven display in active-drive organic light-emitting displays is solved, thus improving the display quality of high refresh rate screens.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
- Filing Date
- 2025-03-19
- Publication Date
- 2026-05-15
AI Technical Summary
In active-matrix organic light-emitting displays, variations in the manufacturing process can lead to differences in the threshold voltage of the driving transistors between different pixel circuits, resulting in uneven display, which is particularly noticeable on high refresh rate screens, affecting display quality and user experience.
The pixel driving circuit adopts a 7T2C structure, which increases the TFT VTH compensation time of the high refresh rate pixel circuit through multiple control signals, and uses dual-gate transistors and capacitors to switch the current path to compensate for the charging time of the driving circuit.
It improves the uniformity of display effects, reduces display unevenness, and enhances the display quality of high refresh rate screens.
Smart Images
Figure CN2025083299_15052026_PF_FP_ABST
Abstract
Description
Pixel driving circuit and display device Technical Field
[0001] This invention relates to the field of OLED devices, and particularly to pixel driving circuits and display devices. Background Technology
[0002] Recently, various flat panel displays with smaller weight and volume compared to cathode ray tube displays have been developed, including liquid crystal displays, field emission displays, plasma display panels, and organic light-emitting displays.
[0003] In flat panel displays, organic light-emitting displays (OLEDs) use organic light-emitting diodes (OLEDs) to display images, which generate light through the recombination of electrons and holes. OLEDs have a fast response time and are driven with low power consumption. A typical OLED uses transistors formed in pixels to supply current to the OLED light-emitting device according to a data signal, thereby causing the OLED light-emitting device to emit light.
[0004] Organic light-emitting displays can be classified into passive-matrix OLED (PMOLED) and active-matrix OLED (AMOLED) based on their driving type. Passive-matrix OLEDs do not use thin-film transistor substrates, while active-matrix OLEDs do.
[0005] Each pixel in an actively driven OLED is equipped with a low-temperature polycrystalline silicon thin-film transistor (LTS) that functions as a switch, and each pixel also has a storage capacitor. The peripheral driving circuitry and display components are integrated on the same glass substrate. Each pixel generates a driving current based on a data signal, and the brightness of the OLED is controlled by adjusting the driving current of the OLED light-emitting device. Due to inevitable fluctuations in the manufacturing process, the threshold voltages of the driving transistors in different pixel circuits vary, which can easily lead to IC power supply signal noise and display unevenness. This unevenness is particularly pronounced in displays with high refresh rates, such as 240Hz, reducing display quality and increasing the likelihood of visual fatigue for users.
[0006] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this invention, and therefore may contain information that is unknown to those skilled in the art and does not constitute prior art. Summary of the Invention
[0007] In view of the problems in the prior art, the purpose of the present invention is to provide a pixel driving circuit and a display device, which overcomes the difficulties of the prior art, can compensate for the charging time of the driving circuit, and make the display effect of the display device more uniform.
[0008] An embodiment of the present invention provides a pixel driving circuit, comprising:
[0009] The first transistor is used to switch the current path between the data signal and the first node in response to the first control signal;
[0010] The second transistor is used to switch the current path between the operating voltage signal and the third node in response to the voltage of the second node.
[0011] The third transistor is used to switch the current path between the second node and the third node in response to the second control signal;
[0012] The fourth transistor is used to switch the current path between the third reference voltage and the first node in response to the second control signal;
[0013] The fifth transistor is used to switch the current path between the third node and the anode of the light-emitting diode in response to an enable signal, wherein the cathode of the light-emitting diode is connected to a ground signal;
[0014] The sixth transistor is used to switch the current path between the first reference voltage and the second node in response to the scan signal;
[0015] The seventh transistor is used to switch the current path between the second reference voltage and the anode of the light-emitting diode in response to a scan signal; and
[0016] The second capacitor is coupled between the first node and the second node.
[0017] Optionally, it further includes: a first capacitor coupled between the first node and the operating voltage signal.
[0018] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all N-type thin-film transistors.
[0019] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type thin-film transistors.
[0020] Optionally, the first transistor is a dual-gate transistor.
[0021] Optionally, the third transistor is a dual-gate transistor.
[0022] Optionally, the fourth transistor is a dual-gate transistor.
[0023] Optionally, the sixth transistor is a dual-gate transistor.
[0024] Optionally, the first transistor, the third transistor, the fourth transistor, and the sixth transistor are all dual-gate transistors.
[0025] Embodiments of the present invention also provide a display device, including the pixel driving circuit as described above.
[0026] The pixel driving circuit and display device of the present invention can compensate for the charging time of the driving circuit, specifically by increasing the compensation time of the TFT VTH of the high refresh rate pixel circuit, thereby making the display effect of the display device more uniform.
[0027] To further understand the features and technical content of this application, please refer to the following detailed description and drawings. However, the detailed description and drawings are only for illustrating this application and are not intended to limit the scope of the claims in any way. Attached Figure Description
[0028] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.
[0029] Figure 1 is a schematic diagram of the pixel driving circuit of the present invention.
[0030] Figure 2 is a timing diagram of the pixel driving circuit of the present invention.
[0031] Figure 3 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention in the first timing sequence.
[0032] Figure 4 is a timing diagram of the pixel driving circuit of the present invention in the first timing sequence.
[0033] Figure 5 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention in the second timing.
[0034] Figure 6 is a timing diagram of the pixel driving circuit of the present invention in the second timing sequence.
[0035] Figure 7 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention in the third timing sequence.
[0036] Figure 8 is a timing diagram of the pixel driving circuit of the present invention in the third timing sequence.
[0037] Figure 9 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention in the fourth timing sequence.
[0038] Figure 10 is a timing diagram of the pixel driving circuit of the present invention in the fourth timing sequence. Detailed Implementation
[0039] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.
[0041] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.
[0042] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0043] For the purpose of clearly describing this application, devices that are not relevant to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.
[0044] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.
[0045] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.
[0046] The technical terms used herein are used only in reference to specific embodiments and are not intended to limit this application. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. The word “comprising” as used in the specification means to specify a particular feature, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other features, regions, integers, steps, operations, elements, and / or components. It should be further understood that the terms “comprising” or “including” indicate the presence of a feature, step, operation, component, element, type, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, components, elements, types, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of components, functions, steps, or operations is inherently mutually exclusive in some way.
[0047] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.
[0048] Figure 1 is a schematic diagram of the pixel driving circuit of the present invention. Figure 2 is a timing diagram of the pixel driving circuit of the present invention. As shown in Figures 1 and 2, the pixel driving circuit of the present invention includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. The first transistor T1 is used to switch the current path between the data signal and the first node N1 in response to the first control signal SN_T1. The second transistor T2 is used to switch the current path between the working voltage signal ELVDD and the third node N3 in response to the voltage of the second node N2. The third transistor T3 is used to switch the current path between the second node N2 and the third node N3 in response to the second control signal SN_T3. The fourth transistor T4 is used to switch the current path between the third reference voltage Vint3 and the first node N1 in response to the second control signal SN_T3. The fifth transistor T5, in response to the enable signal EM_T5, switches the current path between the third node N3 and the anode of the LED. The cathode of the LED is connected to the ground signal ELVSS. The sixth transistor T6, in response to the scan signal SN-1, switches the current path between the first reference voltage Vint1 and the second node N2. The seventh transistor T7, in response to the scan signal SN+1, switches the current path between the second reference voltage Vint2 and the anode of the LED. The first capacitor C1 is coupled between the first node N1 and the operating voltage signal ELVDD. The second capacitor C2 is coupled between the first node N1 and the second node N2.
[0049] In one alternative embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all N-type thin-film transistors, but are not limited thereto.
[0050] In one alternative embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type thin-film transistors, but are not limited thereto.
[0051] In one alternative embodiment, the first transistor T1 is a dual-gate transistor, but is not limited thereto.
[0052] In one alternative embodiment, the third transistor T3 is a dual-gate transistor, but is not limited thereto.
[0053] In one alternative embodiment, the fourth transistor T4 is a dual-gate transistor, but is not limited thereto.
[0054] In one alternative embodiment, the sixth transistor T6 is a dual-gate transistor, but is not limited thereto.
[0055] In one alternative embodiment, the first transistor T1, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are all dual-gate transistors, but this is not a limitation.
[0056] The dual-gate transistor in this invention controls the flow of charge carriers through two gates, and it has the following technical advantages:
[0057] 1. Low noise: FETs have high input resistance and low noise figure, making them ideal for amplifying high-frequency signals.
[0058] 2. High input impedance: The input resistance of a FET is greater than that of a bipolar transistor, which prevents it from loading the signal source.
[0059] 3. Low power consumption: FETs only require a small amount of input power (gate voltage and gate current) to control a large output power.
[0060] The pixel driving circuit of the present invention adopts a 7T2C structure and uses multiple control signals, which can increase the compensation time of the TFT VTH (threshold voltage) of the high refresh rate pixel circuit, thereby making the display effect of the display device more uniform.
[0061] The working principle of the pixel driving circuit of the present invention under various timing conditions is specifically described below with reference to Figures 3 to 10. Referring to Figure 3, in this embodiment, the pixel driving circuit of the present invention includes: a first transistor T1 (dual-gate transistor), a second transistor T2, a third transistor T3 (dual-gate transistor), a fourth transistor T4 (dual-gate transistor), a fifth transistor T5, a sixth transistor T6 (dual-gate transistor), a seventh transistor T7, a first capacitor C1, and a second capacitor C2. The first transistor T1 is used to switch the current path between the data signal and the first node N1 in response to the first control signal SN_T1. The second transistor T2 is used to switch the current path between the working voltage signal ELVDD and the third node N3 in response to the voltage of the second node N2. The third transistor T3 is used to switch the current path between the second node N2 and the third node N3 in response to the second control signal SN_T3. The fourth transistor T4 is used to switch the current path between the third reference voltage Vint3 and the first node N1 in response to the second control signal SN_T3. The fifth transistor T5, in response to the enable signal EM_T5, switches the current path between the third node N3 and the anode of the LED. The cathode of the LED is connected to the ground signal ELVSS. The sixth transistor T6, in response to the scan signal SN-1, switches the current path between the first reference voltage Vint1 and the second node N2. The seventh transistor T7, in response to the scan signal SN+1, switches the current path between the second reference voltage Vint2 and the anode of the LED. The first capacitor C1 is coupled between the first node N1 and the operating voltage signal ELVDD. The second capacitor C2 is coupled between the first node N1 and the second node N2.
[0062] Figure 3 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention under the first timing sequence. Figure 4 is a timing diagram of the pixel driving circuit of the present invention under the first timing sequence. Referring to Figures 2 and 3, when the pixel driving circuit of the present invention is in the first timing sequence S1, the scan signal SN+1 is high, and the states of each transistor are as follows: the sixth transistor T6 is turned on. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are all turned off. At this time, the voltage of the second node N2 is the first reference voltage Vint1.
[0063] Figure 5 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention in the second timing sequence. Figure 6 is a timing diagram of the pixel driving circuit of the present invention in the second timing sequence. Referring to Figures 5 and 6, when the pixel driving circuit of the present invention is in the second timing sequence S2, the scan signal SN+1 remains at a high level, and the states of each transistor are as follows: the second transistor T2 and the third transistor T3 are turned on. The first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned off. At this time, the voltage of the first node N1 is the third reference voltage Vint3. Furthermore, the voltage of the second node N2 = ELVDD + VTH (using ELVDD to compensate for the threshold voltage T2_VTH of the second transistor, the time can be greater than the scanning time of one line in the circuit).
[0064] Figure 7 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention in the third timing sequence. Figure 8 is a timing diagram of the pixel driving circuit of the present invention in the third timing sequence. Referring to Figures 7 and 8, when the pixel driving circuit of the present invention is in the third timing sequence S3, the scan signal SN+1 continues to maintain a high level, and the states of each transistor are as follows: the first transistor T1 is turned on. The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned off. At this time, the voltage of the fourth node N4 changes from the fourth reference voltage Vint4 to the data signal, and the voltage difference of the fourth node N4 is = Data - Vint4. Then, the voltage of the second node N2 at this time is = ELVDD + VTH + DATA - Vint4.
[0065] After the third timing sequence S3, the seventh transistor T7 and the eighth transistor T8 will be temporarily turned on only when the scan signal SN+1 temporarily jumps to a low level (the states of the other transistors are the same as those in the third timing sequence S3, and will not be described again here).
[0066] Figure 9 is a schematic diagram of the conduction state of the pixel driving circuit of the present invention in the fourth timing sequence. Figure 10 is a timing diagram of the pixel driving circuit of the present invention in the fourth timing sequence. Referring to Figures 9 and 10, when the pixel driving circuit of the present invention is in the fourth timing sequence S4, the scanning signal SN+1 returns to a high level, and the states of each transistor are as follows: the second transistor T2 and the fifth transistor T5 are turned on. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are all turned off. At this time, the current through the second transistor T2 is:
[0067] I_T2=K(VGS-VTH) 2 =K(N2-ELVDD-VTH) 2 =K(ELVDD+VTH+DATA-Vint4-ELVDD-VTH)=K(DATA-Vint4)2 .
[0068] Therefore, the current of the second transistor T2 is no longer limited by VTH, making the current reaching the light-emitting diode through the second transistor T2 more stable and the display effect more uniform.
[0069] This embodiment also provides a display device, such as an OLED panel, including the pixel driving circuit described above. The display device of the present invention incorporates the structural features, techniques, and effects of the pixel driving circuit described above, which will not be repeated here.
[0070] In summary, the pixel driving circuit and display device of the present invention can compensate for the charging time of the driving circuit, specifically by increasing the compensation time of the TFT VTH of the high refresh rate pixel circuit, thereby making the display effect of the display device more uniform.
[0071] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A pixel driving circuit, characterized in that, include: The first transistor (T1) is used to switch the current path between the data signal and the first node (N1) in response to the first control signal (SN_T1); The second transistor (T2) is used to switch the current path between the operating voltage signal (ELVDD) and the third node (N3) in response to the voltage of the second node (N2); The third transistor (T3) is used to switch the current path between the second node (N2) and the third node (N3) in response to the second control signal (SN_T3); The fourth transistor (T4) is used to switch the current path between the third reference voltage (Vint3) and the first node (N1) in response to the second control signal (SN_T3); The fifth transistor (T5) is used to switch the current path between the third node (N3) and the anode of the light-emitting diode (LED) in response to the enable signal (EM_T5), wherein the cathode of the light-emitting diode (LED) is connected to the ground signal (ELVSS); The sixth transistor (T6) is used to switch the current path between the first reference voltage (Vint1) and the second node (N2) in response to the scan signal (SN-1); The seventh transistor (T7) is used to switch the current path between the second reference voltage (Vint2) and the anode of the light-emitting diode (LED) in response to the scan signal (SN+1); as well as The second capacitor (C2) is coupled between the first node (N1) and the second node (N2).
2. The pixel driving circuit as described in claim 1, characterized in that, Also includes: The first capacitor (C1) is coupled between the first node (N1) and the operating voltage signal (ELVDD).
3. The pixel driving circuit as described in claim 1, characterized in that, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are all N-type thin-film transistors.
4. The pixel driving circuit as described in claim 1, characterized in that, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are all P-type thin-film transistors.
5. The pixel driving circuit as described in claim 1, characterized in that, The first transistor (T1) is a dual-gate transistor.
6. The pixel driving circuit as described in claim 1, characterized in that, The third transistor (T3) is a dual-gate transistor.
7. The pixel driving circuit as described in claim 1, characterized in that, The fourth transistor (T4) is a dual-gate transistor.
8. The pixel driving circuit as described in claim 1, characterized in that, The sixth transistor (T6) is a dual-gate transistor.
9. The pixel driving circuit as described in claim 1, characterized in that, The first transistor (T1), the third transistor (T3), the fourth transistor (T4), and the sixth transistor (T6) are all dual-gate transistors.
10. A display device, characterized in that, include: The pixel driving circuit as described in claim 1.