Data transmission method and data transmission apparatuses for server, and readable storage medium and server

Abstract

The present application relates to the technical field of data transmission. Provided are a data transmission method and data transmission apparatuses for a server, and a readable storage medium and a server. The data transmission method comprises: a first computing chip generating an Ethernet frame on the basis of data to be transmitted, wherein the Ethernet frame comprises an Ethernet packet header, the Ethernet packet header comprises an address field, and the address field is used for indicating an identification number or physical memory address of the first computing chip and a physical memory address of a second computing chip, the second computing chip being a chip that receives the Ethernet frame; and on the basis of the Ethernet packet header, an Ethernet switching chip sending the Ethernet frame to the second computing chip. In the present application, an Ethernet frame header field that is originally invalid overhead is transformed into a valid field carrying payload-related information, thereby avoiding the space waste originally caused by an Ethernet packet header when small-scale AI servers implement inter-chip data transmission via the Ethernet, and improving the efficiency of inter-chip data interaction.

Description

Data transmission method and device of server, readable storage medium and server

[0001] The present application claims priority to the Chinese patent application No. 202411574937.X, filed on November 6, 2024, entitled "Data transmission method and device of server, readable storage medium and server", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of data transmission, in particular to a data transmission method and device of server, readable storage medium and server. BACKGROUND

[0003] In the related art, a large language model and other artificial intelligence need a large number of GPUs (Graphics Processing Units) or AI (Artificial Intelligence) chips to provide computing power during training. The current trend is to integrate multiple GPUs or AI chips in one server to make the server have stronger computing power. Multiple GPUs or AI chips in one server need to be interconnected through high-speed networks to realize data transmission. The common method is to realize non-blocking interconnection between multiple chips based on Ethernet switch chips.

[0004] In the chip interconnection transmission protocol packet format based on Ethernet, an additional TL Hdr (Transport Layer Header) field is added after the fields of the Ethernet packet header. The TL Hdr field contains memory operation types, source chip physical memory addresses, destination chip physical memory addresses, etc. Among them, the MAC (Media Access Control Address) address in the Ethernet packet header carries the packet destination MAC address, which only has local significance and is used to identify the Ethernet card port, and does not carry information related to the payload. In a small-scale Ethernet network, IP (Internet Protocol) routing is not required, so the fields of the Ethernet packet header form an additional address overhead, causing a waste of space and leading to low efficiency of data interaction. SUMMARY

[0005] Therefore, the present application aims to at least solve one of the problems in the prior art or related art.

[0006] To this end, a first aspect of the present application provides a data transmission method of server.

[0007] A second aspect of the present application provides a data transmission device of server.

[0008] The third aspect of the present application provides a data transmission device of a server.

[0009] The fourth aspect of the present application provides a readable storage medium.

[0010] The fifth aspect of the present application provides a server.

[0011] Therefore, the first aspect of the present application provides a data transmission method of a server, the server comprising an Ethernet switch chip and at least two computing chips, the data transmission method comprising: a first computing chip generating an Ethernet frame based on to-be-transmitted data; wherein the Ethernet frame comprises an Ethernet packet header, the Ethernet packet header comprising an address field, the address field being used to indicate an identification number or a physical memory address of the first computing chip and a physical memory address of a second computing chip, the second computing chip being a chip receiving the Ethernet frame; and the Ethernet switch chip sending the Ethernet frame to the second computing chip based on the Ethernet packet header.

[0012] The present application maps the physical memory address of the destination computing chip and the identification number or the physical memory address of the source chip to the destination MAC address and the source MAC address in the original Ethernet packet header which is only used to identify the Ethernet card port respectively, changes the Ethernet frame header field which is originally invalid overhead into an effective field carrying the information related to the payload, avoids the space waste problem caused by the original Ethernet packet header when the small-scale AI server implements the chip data intercommunication through the Ethernet, and improves the efficiency of the chip data interaction.

[0013] The second aspect of the present application provides a data transmission device of a server, the server comprising an Ethernet switch chip and at least two computing chips, the data transmission device comprising: a generation module, configured to control a first computing chip to generate an Ethernet frame based on to-be-transmitted data; wherein the Ethernet frame comprises an Ethernet packet header, the Ethernet packet header comprising an address field, the address field being used to indicate an identification number or a physical memory address of the first computing chip and a physical memory address of a second computing chip, the second computing chip being a chip receiving the Ethernet frame; and a sending module, configured to control the Ethernet switch chip to send the Ethernet frame to the second computing chip based on the Ethernet packet header.

[0014] The present application maps the physical memory address of the destination computing chip and the identification number or the physical memory address of the source chip to the destination MAC address and the source MAC address in the original Ethernet packet header which is only used to identify the Ethernet card port respectively, changes the Ethernet frame header field which is originally invalid overhead into an effective field carrying the information related to the payload, avoids the space waste problem caused by the original Ethernet packet header when the small-scale AI server implements the chip data intercommunication through the Ethernet, and improves the efficiency of the chip data interaction.

[0015] The third aspect of the present application provides a data transmission apparatus of a server, comprising: a memory, wherein the memory stores programs or instructions; and a processor, wherein the processor is configured to execute the programs or instructions to implement the steps of the data transmission method of the server according to any one of the preceding aspects, and thus the same technical effects are achieved. To avoid repetition, details are not described herein.

[0016] The fourth aspect of the present application provides a readable storage medium, wherein the readable storage medium stores programs or instructions, and the programs or instructions are executed by a processor to implement the steps of the data transmission method of the server according to any one of the preceding aspects, and thus the same technical effects are achieved. To avoid repetition, details are not described herein.

[0017] The fifth aspect of the present application provides a server, comprising: a data transmission apparatus of a server according to any one of the preceding aspects; and / or a readable storage medium according to any one of the preceding aspects, and thus the same technical effects are achieved. To avoid repetition, details are not described herein. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the references to the figures, in which:

[0019] FIG. 1 shows a flowchart of a data transmission method of a server according to some embodiments of the present application;

[0020] FIG. 2 shows an Ethernet-based AI chip interconnection transmission layer protocol packet format diagram;

[0021] FIG. 3 shows a schematic diagram of an Ethernet packet header packet format according to some embodiments of the present application;

[0022] FIG. 4 shows a schematic diagram of an Ethernet packet header packet format according to some embodiments of the present application;

[0023] FIG. 5 shows a schematic diagram of an Ethernet packet header packet format according to some embodiments of the present application;

[0024] FIG. 6 shows a structural block diagram of a data transmission apparatus of a server according to some embodiments of the present application;

[0025] FIG. 7 shows a structural block diagram of a data transmission apparatus of a server according to some embodiments of the present application. DETAILED DESCRIPTION

[0026] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0027] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of this application is not limited to the specific embodiments disclosed below.

[0028] The following describes, with reference to Figures 1 to 7, a data transmission method and apparatus for a server, a readable storage medium, and a server according to some embodiments of this application.

[0029] In some embodiments of this application, a data transmission method for a server is provided. The server includes an Ethernet switching chip and at least two computing chips. Figure 1 shows a flowchart of the data transmission method for the server in some embodiments of this application. As shown in Figure 1, the data transmission method includes:

[0030] Step 102: The first computing chip generates an Ethernet frame based on the data to be transmitted; wherein the Ethernet frame includes an Ethernet packet header, the Ethernet packet header includes an address field, the address field is used to indicate the identifier or physical memory address of the first computing chip and the physical memory address of the second computing chip, and the second computing chip is the chip that receives the Ethernet frame.

[0031] Step 104: The Ethernet switching chip sends the Ethernet frame to the second computing chip based on the Ethernet packet header.

[0032] In this embodiment, the server includes an AI server, which comprises multiple computing chips, such as GPUs, NPUs (Neural Processing Units), or AI chips. These computing chips provide computational power for the training or inference processes of artificial intelligence systems, such as large language models. The multiple computing chips in the server are interconnected via an Ethernet chip.

[0033] Figure 2 illustrates a schematic diagram of the Ethernet-based transport layer protocol packet format for AI chip interconnection. As shown in Figure 2, in the traditional Ethernet-based transport layer protocol packet format for AI chip interconnection, the Dst MAC field is 6 bytes long and represents the destination port address; the Src MAC field is 6 bytes long and represents the source port address; the VLAN tag field is 2 bytes long and carries VLAN information defined by IEEE 802.3Q; and the EthType field is 2 bytes long and represents the Ethernet type. An additional TL Hdr field is added after the Ethernet packet header fields. This TL Hdr field contains the memory operation type, source chip identifier or physical memory address, destination chip physical memory address, etc. The Payload field is the payload, and the FCS field is the Frame Check Sequence, which is 4 bytes long.

[0034] The Ethernet packet header typically occupies 14 bytes. However, the Ethernet packet header is only used for packet forwarding within the Ethernet switching chip and does not carry payload-related information. For small-scale Ethernet networks, such as when an AI server contains only a few dozen to a few hundred AI chips, IP routing is not required to achieve data interconnection between the chips. This results in the address space occupied by this part of the Ethernet packet header being wasted, leading to low data transmission efficiency.

[0035] To address the aforementioned issues, this application, when implementing data interconnection between computing chips via Ethernet frames, maps the identifier or physical memory address of the destination computing chip and the physical memory address of the source chip to the destination MAC address and source MAC address in the original Ethernet packet header, which are only used to identify the Ethernet card port. This transforms the Ethernet frame header fields, which were originally invalid overhead, into valid fields carrying payload-related information, preventing the waste of space in the Ethernet frame header.

[0036] The source computing chip is defined as the first computing chip, and the target computing chip is defined as the second computing chip. When the first computing chip needs to send data to the second computing chip to achieve data exchange between them, the first computing chip generates a corresponding Ethernet frame based on the data to be sent. The payload field of this Ethernet frame carries at least a portion of the data to be sent. Simultaneously, the destination MAC address and source MAC address originally used in the Ethernet frame header to identify the Ethernet card port are replaced with the identifier or physical memory address of the first computing chip and the physical memory address of the second computing chip, respectively.

[0037] When forwarding data, the Ethernet interaction chip determines the next hop of the Ethernet packet based on the physical memory address of the second computing chip in the new Ethernet packet header, and forwards the current Ethernet frame to the next hop, which is the output port corresponding to the physical memory address of the second computing chip, thereby realizing chip data transmission based on Ethernet.

[0038] This application maps the physical memory address of the target computing chip and the identifier or physical memory address of the source chip to the destination MAC address and source MAC address in the original Ethernet packet header, which are only used to identify the Ethernet card port. This transforms the Ethernet frame header field, which was originally an invalid overhead, into a valid field carrying payload-related information. This avoids the space waste caused by the original Ethernet packet header when small-scale AI servers transmit chip data over Ethernet, and improves the efficiency of data interaction between chips.

[0039] In some embodiments of this application, optionally, the address field includes a target address field, which is used to indicate the physical memory address of the second computing chip; or, the address field includes a target address field and a source address field, which is used to indicate the physical memory address of the first computing chip or the identification information of the first computing chip; wherein, the target address field is located before the source address field; or, the source address field is located before the target address field.

[0040] In this embodiment, in some implementations, the address field in the updated Ethernet packet header includes a target address field for indicating the physical memory address of the target computing chip, and the Ethernet switching chip forwards data based on the target address field.

[0041] In other implementations, the address field in the updated Ethernet packet header specifically includes a source address field indicating the identifier or physical memory address of the source computing chip, and a destination address field indicating the physical memory address of the target computing chip. For example, taking a GPU as the computing chip, the source address field can be defined as Src GPU Addr, and the destination address field as Dst GPU Addr.

[0042] For example, Figures 3 and 4 illustrate schematic diagrams of the packet format of the Ethernet packet header in some embodiments of this application. As shown in Figures 3 and 4, the Src GPU Addr field is the source address field, and the Dst GPU Addr field is the destination address field. In some embodiments, as shown in Figure 3, the destination address field Dst GPU Addr precedes the source address field Src GPU Addr.

[0043] In other embodiments, the source address field Src GPU Addr precedes the destination address field Dst GPU Addr.

[0044] By mapping the physical memory addresses of the source computing chip and the target computing chip to the Ethernet packet header of the Ethernet frame, the waste of packet space caused by the Ethernet packet header can be prevented without changing the original Ethernet packet format, thereby improving data transmission efficiency.

[0045] In some embodiments of this application, optionally, the target address field includes a chip identifier field, the length of which is less than the length of the target address field, and the chip identifier field is used to indicate the chip identifier of the second computing chip; wherein, the Ethernet switching chip sends Ethernet frames to the second computing chip based on the chip identifier field.

[0046] In this embodiment, the Ethernet switching chip's function is specifically to determine the next Ethernet packet based on the address field carried in the Ethernet packet header—specifically, the target computing chip indicated by the destination address field, i.e., the physical memory address of the second computing chip—and to forward the Ethernet frame to the output port corresponding to the next hop. Therefore, the Ethernet switching chip only needs to use the destination address field, i.e., the physical memory address of the second computing chip. Corresponding to the original Ethernet packet header, the destination address field has 48 bits, but the Ethernet switching chip does not actually need all 48 bits of the destination address field for forwarding. The Ethernet switching chip only needs to use the computing chip ID (Identification) that can uniquely identify a physical memory address to complete data forwarding.

[0047] Therefore, to further improve the utilization of address bits, this application limits the original 48-bit target address field to include an M-bit chip identifier field and a (48-M)-bit computing chip memory sub-address. The aforementioned computing chip memory sub-address indicates the actual physical memory address of the second computing chip, which serves as the target computing chip, where M is a positive integer less than 48. When the Ethernet switching chip forwards data, only the first M-bit chip identifier field needs to be read for packet switching. Based on the TCAM (Ternary Content Addressable Memory) in the Ethernet switching chip, the (48-M)-bit address in the target address field, excluding the M-bit chip identifier field, is removed from the impact on the switching strategy, thus achieving packet forwarding based on the target chip ID. When the packet only requires the M-bit chip identifier field, the remaining (48-M)-bits can be reserved or used to carry useful information defined by the protocol.

[0048] By mapping the target address field to the Dst MAC (target port address) field of the original Ethernet frame, the target computing chip can directly DMA (direct memory access) the data carried by the Ethernet frame to the target computing chip's memory, which is the memory address corresponding to the second computing chip. This eliminates the need for the receiving network card to cache data locally, thus improving data transmission efficiency.

[0049] For example, Figure 5 illustrates a schematic diagram of the packet format of the Ethernet packet header in some embodiments of this application. As shown in Figure 5, the 48-bit length Dst GPU Addr is divided into an M-bit GPU ID and a (48-M)-bit Sub GPU Addr. The first M bits of the destination address field are defined as the GPU ID, used to indicate the chip identifier of the second computing chip that is the data receiver. The (48-M)-bits following the GPU ID in the destination address field are defined as the Sub GPU Addr, used to indicate the GPU memory sub-address.

[0050] For example, in an Ethernet switching chip, the Dst MAC (destination port address) in the Ethernet frame header is set to AND with a number whose first M-bits are 1 and the last (48-M)-bits are 0, thereby achieving the same effect as using TCAM, while reducing the overhead of hardware resources and eliminating the Ethernet switching chip's dependence on TCAM.

[0051] In some embodiments of this application, optionally, the Ethernet packet header further includes a message type field and a data packet type field. The message type field is used to indicate the message type of the Ethernet frame, and the data packet type field is used to indicate the data packet of the Ethernet frame. The message type includes a read operation, a write operation, or an atomic operation; the data packet includes a message start, a message end, or an intermediate message.

[0052] In this embodiment, the original Ethernet packet header includes an EthType field, which indicates the Ethernet type. Generally, the EthType field is 2 bytes long. This application reuses the original EthType field into a message type field and a data packet type field. The message type field indicates the message type corresponding to the current Ethernet frame, such as a read operation, write operation, or atomic operation. The packet type field indicates the data packet corresponding to the current Ethernet frame, such as a message start, message end, or intermediate message.

[0053] For example, as shown in Figure 3, the message type field is defined as Message type, abbreviated as MT. MT has a length of 1 byte and is used to indicate the message type, including read operations, write operations, atomic operations, etc. The data packet type field is defined as Packet type, abbreviated as PT, to indicate the data packet type, indicating whether the current data packet is the beginning of a message, the end of a message, or an intermediate message.

[0054] For example, the data grouping type field PT is located after the message type field MT.

[0055] In some embodiments of this application, optionally, the Ethernet packet header further includes an Ethernet type field, a message type field, and a data packet type field. The message type field is used to indicate the message type of the Ethernet frame, and the data packet type field is used to indicate the data packet of the Ethernet frame. The message type includes a read operation, a write operation, or an atomic operation. The data packet includes a message start, a message end, or an intermediate message. The Ethernet type field precedes the message type field, and the message type field precedes the data packet type field.

[0056] In this embodiment, the original Ethernet packet header includes a VLAN tag and an EthType field, which indicates the Ethernet type. Instead of redefining the original EthType field, one or more EthType fields are applied for the AI ​​chip interconnection transmission protocol. As shown in Figure 4, a message type field (MT) and a data packet type field (PT) are added after the original Ethernet type field. The message type field (MT) indicates the message type, including read, write, and atomic operations, while the data packet type field (PT) indicates the data packet type, i.e., whether the current data packet is a message start, message end, or intermediate message. This improves compatibility with the Ethernet packet format.

[0057] For example, the data grouping type field PT is located after the message type field MT.

[0058] In some embodiments of this application, optionally, the Ethernet packet header further includes a queue number field and a packet number field, wherein the queue number field is used to indicate the connection identifier of the Ethernet frame, and the packet number field is used to indicate the packet sequence number of the Ethernet frame; wherein the queue number field is located after the data packet type field, and the packet number field is located after the queue number field.

[0059] In this embodiment, the updated Ethernet packet header includes a queue number field and a packet sequence number field. The queue number field indicates the connection identifier (connection ID) of the current Ethernet frame, and the packet sequence number field indicates the packet sequence number of the current Ethernet frame.

[0060] For example, the queue sequence number field is defined as QPN (Queue Pair Number), which is used to indicate the connection ID. The packet sequence number field is defined as PSN (Package Sequence Number), which is used to indicate the packet sequence number.

[0061] For example, the queue number field QPN is located after the data packet type field PT, and the packet number field PSN is located after the queue number field QPN.

[0062] In some embodiments of this application, optionally, the Ethernet frame further includes an extension header; wherein, when the message type is a read operation or a write operation, the extension header is used to indicate the read / write length of the Ethernet frame; when the message type is an atomic operation, the extension header is used to indicate the operand of the atomic operation.

[0063] In this embodiment, the Ethernet frame includes an extension header that extends the packet header for specific message and packet types. For example, when the message type is a read or write operation, the extension header can indicate the read / write length of the message. For instance, when the message type is an atomic operation, the extension header indicates the operands of the atomic operation.

[0064] For example, as shown in Figures 3 and 4, the Extended Header is defined as an Extended Header. When the message type field MT is read or write, the Extended Header indicates the message read / write length. When the message type field MT is an atomic operation, the operand of the atomic operation is carried in the Extended Header.

[0065] In some embodiments of this application, optionally, the Ethernet frame further includes a payload field and a frame check sequence field; wherein the payload field is located after the Ethernet packet header, and the frame check sequence field is located after the payload field.

[0066] In this embodiment, as shown in Figures 3 and 4, the length of the Payload field of the Ethernet frame is variable, representing the effective payload of the Ethernet frame, which is the data object transmitted between the first computing chip and the second computing chip. The Frame Check Sequence (FCS) field of the Ethernet frame is 4 bytes long, specifically an error detection code, and its format and meaning are the same as those of the original Ethernet frame.

[0067] In some embodiments of this application, a data transmission device for a server is provided. The server includes an Ethernet switching chip and at least two computing chips. Figure 6 shows a structural block diagram of the data transmission device for a server according to some embodiments of this application. As shown in Figure 6, the data transmission device 600 for the server includes: a generation module 602, used to control a first computing chip to generate an Ethernet frame based on the data to be transmitted; wherein the Ethernet frame includes an Ethernet packet header, the Ethernet packet header includes an address field, the address field is used to indicate the identifier or physical memory address of the first computing chip and the physical memory address of the second computing chip, and the second computing chip is a chip that receives the Ethernet frame; and a sending module 604, used to control the Ethernet switching chip to send the Ethernet frame to the second computing chip based on the Ethernet packet header.

[0068] In this embodiment, the server includes an AI server, which comprises multiple computing chips, such as GPUs, NPUs (Neural Processing Units), or AI chips. These computing chips provide computational power for the training or inference processes of artificial intelligence systems, such as large language models. The multiple computing chips in the server are interconnected via an Ethernet chip.

[0069] In traditional Ethernet-based transport layer protocol packet formats for AI chip interconnection, an additional TL HDR field is added after the Ethernet packet header fields. This TL HDR field contains information such as memory operation type, source chip physical memory address, and destination chip physical memory address. The Ethernet packet header typically occupies 14 bytes and is only used for packet forwarding within the Ethernet switching chip; it does not carry payload-related information. For small-scale Ethernet networks, such as when an AI server contains only tens to hundreds of AI chips, IP routing is not required for data interconnection between chips. This results in wasted address space in the Ethernet packet header, leading to low data transmission efficiency.

[0070] To address the aforementioned issues, this application, when implementing data interconnection between computing chips via Ethernet frames, maps the physical memory address of the destination computing chip and the identifier or physical memory address of the source chip to the destination MAC address and source MAC address in the original Ethernet packet header, which are only used to identify the Ethernet card port. This transforms the Ethernet frame header fields, which were originally invalid overhead, into valid fields carrying payload-related information, preventing the waste of space in the Ethernet frame header.

[0071] For example, a source computing chip is defined as a first computing chip, and a target computing chip is defined as a second computing chip. When the first computing chip needs to send data to the second computing chip to achieve data exchange between them, the first computing chip generates a corresponding Ethernet frame based on the data to be sent. The payload field of this Ethernet frame carries the aforementioned data to be sent. Simultaneously, the destination MAC address and source MAC address originally used in the Ethernet frame header to identify the Ethernet card port are replaced with the physical memory address of the first computing chip and the identifier number or physical memory address of the second computing chip, respectively.

[0072] When forwarding data, the Ethernet interaction chip determines the next hop of the Ethernet packet based on the physical memory address of the second computing chip in the new Ethernet packet header, and forwards the current Ethernet frame to the next hop, which is the output port corresponding to the physical memory address of the second computing chip, thereby realizing chip data transmission based on Ethernet.

[0073] This application maps the physical memory address of the target computing chip and the identifier or physical memory address of the source chip to the destination MAC address and source MAC address in the original Ethernet packet header, which are only used to identify the Ethernet card port. This transforms the Ethernet frame header field, which was originally an invalid overhead, into a valid field carrying payload-related information. This avoids the space waste caused by the original Ethernet packet header when small-scale AI servers transmit chip data over Ethernet, and improves the efficiency of data interaction between chips.

[0074] In some embodiments of this application, a data transmission device for a server is provided. FIG7 shows a structural block diagram of a data transmission device for a server according to some embodiments of this application. As shown in FIG7, the data transmission device 700 for the server includes: a memory 702, on which a program or instructions are stored; and a processor 704, which is used to implement the steps of the data transmission method for the server provided in any of the above embodiments when executing the program or instructions, and therefore also includes the same technical effects. To avoid repetition, it will not be described again here.

[0075] In some embodiments of this application, a readable storage medium is provided on which a program or instructions are stored. When the program or instructions are executed by a processor, they implement the steps of the data transmission method of the server provided in any of the above embodiments, and therefore also include the same technical effects. To avoid repetition, they will not be described again here.

[0076] In some embodiments of this application, a server is provided, which includes a data transmission device as provided in any of the above embodiments; and / or a readable storage medium as provided in any of the above embodiments, and therefore also includes the same technical effects. To avoid repetition, it will not be described again here.

[0077] The methods can be implemented in various ways depending on specific features and / or example applications. For example, these methods can be implemented by a combination of hardware, firmware, and / or software. For instance, in a hardware implementation, the processor can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, electronic devices, other device units for performing the functions described above, and / or combinations thereof.

[0078] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. A computer-readable storage medium can be an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing, but is not limited thereto. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or flash memory, static random-access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital video disc (DVD), memory cards, floppy disks, encoding mechanisms (e.g., punched cards or grooves with raised structures for recording instructions), and any suitable combination of the foregoing. The computer-readable storage medium used herein should not be construed as the transmission signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media, or electrical signals transmitted through wires.

[0079] In the description of this application, the term "multiple" refers to two or more. Unless otherwise expressly defined, the terms "upper," "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. The terms "connection," "installation," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0080] In the description of this application, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0081] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data transmission method for a server, wherein, The server includes an Ethernet switching chip and at least two computing chips, and the data transmission method includes: The first computing chip generates an Ethernet frame based on the data to be transmitted; wherein the Ethernet frame includes an Ethernet packet header, the Ethernet packet header includes an address field, the address field is used to indicate the identifier or physical memory address of the first computing chip and the physical memory address of the second computing chip, and the second computing chip is the chip that receives the Ethernet frame; The Ethernet switching chip sends the Ethernet frame to the second computing chip based on the Ethernet packet header.

2. The data transmission method of the server according to claim 1, wherein, The address field includes a target address field, which is used to indicate the physical memory address of the second computing chip; Alternatively, the address field may include the target address field and the source address field, wherein the source address field is used to indicate the physical memory address of the first computing chip or the identification information of the first computing chip; Wherein, the target address field is located before the source address field; or, the source address field is located before the target address field.

3. The data transmission method of the server according to claim 2, wherein, The target address field includes a chip identifier field, the length of which is less than the length of the target address field, and the chip identifier field is used to indicate the chip identifier of the second computing chip; The Ethernet switching chip sends the Ethernet frame to the second computing chip based on the chip identification field.

4. The data transmission method of the server according to claim 1, wherein, The Ethernet packet header also includes a message type field and a data packet type field, wherein the message type field is used to indicate the message type of the Ethernet frame, and the data packet type field is used to indicate the data packets of the Ethernet frame; The message types include read operations, write operations, or atomic operations; the data groups include message start, message end, or intermediate messages.

5. The data transmission method of the server according to claim 1, wherein, The Ethernet packet header also includes an Ethernet type field, a message type field, and a data packet type field. The message type field is used to indicate the message type of the Ethernet frame, and the data packet type field is used to indicate the data packets of the Ethernet frame. The message type includes read operation, write operation, or atomic operation; the data packet includes message start, message end, or intermediate message; the Ethernet type field precedes the message type field, and the message type field precedes the data packet type field.

6. The data transmission method of the server according to claim 4 or 5, wherein, The Ethernet packet header also includes a queue number field and a packet number field. The queue number field is used to indicate the connection identifier of the Ethernet frame, and the packet number field is used to indicate the packet number of the Ethernet frame. The queue number field is located after the data grouping type field, and the packet number field is located after the queue number field.

7. The data transmission method of the server according to claim 4 or 5, wherein, The Ethernet frame also includes an extended header; Specifically, when the message type is a read operation or a write operation, the extended header is used to indicate the read / write length of the Ethernet frame; when the message type is an atomic operation, the extended header is used to indicate the operands of the atomic operation.

8. The data transmission method of the server according to any one of claims 1 to 5, wherein, The Ethernet frame also includes a payload field and a frame check sequence field; The payload field is located after the Ethernet packet header, and the frame check sequence field is located after the payload field.

9. A data transmission device for a server, wherein, The server includes an Ethernet switching chip and at least two computing chips, and the data transmission device includes: A generation module is used to control a first computing chip to generate an Ethernet frame based on the data to be transmitted; wherein the Ethernet frame includes an Ethernet packet header, the Ethernet packet header includes an address field, the address field is used to indicate the identifier or physical memory address of the first computing chip and the physical memory address of the second computing chip, and the second computing chip is a chip that receives the Ethernet frame; The sending module is used to control the Ethernet switching chip to send the Ethernet frame to the second computing chip based on the Ethernet packet header.

10. A data transmission apparatus for a server, wherein, include: A memory, on which programs or instructions are stored; A processor, which executes the program or instructions to implement the steps of the data transmission method of the server as described in any one of claims 1 to 8.

11. A readable storage medium having a program or instructions stored thereon, wherein, When the program or instructions are executed by the processor, they implement the steps of the data transmission method of the server as described in any one of claims 1 to 8.

12. A server, wherein, The server includes: The data transmission apparatus of the server as described in claim 9 or 10; and / or The readable storage medium as described in claim 11.

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