Timing sign off method and apparatus, electronic device, and storage medium

Abstract

Embodiments of the present application relate to the technical field of integrated circuits. Disclosed are a timing sign off method and apparatus, an electronic device, and a storage medium, which can effectively reduce pessimism and complexity of timing sign off of a three-dimensional integrated chip. The method comprises: acquiring a first standard cell library corresponding to each die in a chip to be signed off, wherein each standard cell in the first standard cell library has its own three-dimensional process corner timing parameter, the three-dimensional process corner timing parameter comprises an average delay of each standard cell at a three-dimensional process corner and a standard deviation of the delay of the standard cell at the three-dimensional process corner, and said chip is obtained by means of three-dimensional integration of at least two dies; and using the first standard cell library to perform timing sign off on said chip. The present application is applicable to the timing sign off of chips.

Description

A time-series signature method and apparatus, electronic device, and storage medium

[0001] This application claims priority to Chinese Patent No. 202411615169.8, filed on November 11, 2024, entitled “A Time-Sequenced Sign-Off Method and Apparatus, Electronic Device, and Storage Medium”, all contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, and in particular to a timing verification method and apparatus, electronic device, and storage medium. Background Technology

[0003] Before a chip is manufactured by a wafer fab, it needs to undergo timing sign-off. Timing sign-off refers to checking the timing of the chip design to ensure that the chip can function properly under different PVT (Process Voltage Temperature) scenarios.

[0004] Because of process variations (or deviations) in chip manufacturing, timing estimates are often pessimistic during the approval process. However, overly pessimistic estimates can severely impact chip performance. To avoid overly pessimistic timing estimates, for 2D chips, a combination of global corner (or global standard deviation) and local variation (POCV, or parametric on chip variation) is typically used for timing approval.

[0005] However, for 3D integrated chips, due to the significant randomness of the process conditions of each die, if the above method is used for cross-die signing, on the one hand, there will be many signing process corner combinations (or signing off conditions), making timing analysis too complex. On the other hand, as the number of stacked dies increases, the above signing method will become increasingly pessimistic, leading to over-design and loss of product performance.

[0006] This application content

[0007] In view of this, embodiments of this application provide a timing signature method and apparatus, electronic device, and storage medium, which can effectively reduce the pessimism and complexity of timing signature for 3D integrated chips.

[0008] In a first aspect, embodiments of this application provide a timing verification method, comprising: obtaining a first standard cell library corresponding to each die in a chip to be verified, wherein each standard cell in the first standard cell library has its own 3D process corner timing parameters, the 3D process corner timing parameters including the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner; wherein the chip to be verified is obtained by 3D integration of at least two dies; and performing timing verification on the chip to be verified using the first standard cell library.

[0009] In one embodiment, before obtaining the first standard cell library corresponding to each die in the chip to be signed, the method further includes: obtaining a second standard cell library corresponding to each die in the chip to be signed, wherein each standard cell in the second standard cell library has its own 2D process corner timing parameters, the 2D process corner timing parameters including: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions; determining the average delay of the standard cell under the 3D process corner based on the average delay of each standard cell under 2D conditions to obtain a first average delay, and determining the standard deviation of the delay of the standard cell under the 3D process corner based on the local standard deviation of the delay of each standard cell under 2D conditions to obtain a first standard deviation; configuring each of the first average delays and each of the first standard deviations into the second standard cell library to form the first standard cell library.

[0010] In one embodiment, determining the average delay of the standard unit under the 3-dimensional process angle based on the average delay of each standard unit under 2-dimensional conditions to obtain the first average delay includes: determining the average delay of the standard unit under the 3-dimensional process angle based on the average delay of each standard unit under a typical process angle under 2-dimensional conditions to obtain the first average delay.

[0011] In one embodiment, determining the standard deviation of the delay of each standard unit under the 3D process angle based on the local standard deviation of the delay of each standard unit under 2D conditions to obtain the first standard deviation includes: determining the total standard deviation of the delay of each device in each die of the chip to be signed off and the local standard deviation of the delay of the device through a device model provided by the wafer fab or through simulation; determining the standard deviation expansion coefficient of the device based on the total standard deviation of the delay of each device and the local standard deviation of the delay of the device; and determining the standard deviation of the delay of the standard unit under the 3D process angle based on the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit to obtain the first standard deviation.

[0012] In one embodiment, the standard deviation expansion coefficient of each device is equal to the ratio of the total standard deviation of the device's delay to the local standard deviation of the device's delay; the first standard deviation of each standard unit is equal to the product of the local standard deviation of the standard unit's delay under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

[0013] In one embodiment, the timing verification of the chip to be verified using the first standard cell library includes: determining the delay parameters of a first segment of the target path in the chip to be verified based on the first standard cell library, and determining the delay parameters of a second segment of the target path based on a metal wire delay model, wherein the first segment is the part of the target path located inside each die, and the second segment is the part of the target path located between adjacent dies; determining the delay parameters of the target path based on the delay parameters of the first segment and the delay parameters of the second segment; and determining whether the target path has been verified based on whether the delay parameters of the target path are within a preset parameter range.

[0014] In one implementation, the delay parameters of the first road segment include the average delay of the first road segment and the standard deviation of the delay of the first road segment; the delay parameters of the second road segment include the average delay of the second road segment and the standard deviation of the delay of the second road segment; determining the delay parameters of the target path based on the delay parameters of the first road segment and the delay parameters of the second road segment includes: adding the average delay of each first road segment and the average delay of each second road segment to obtain the average delay of the target path; adding the sum of the squares of the standard deviations of the delays of each first road segment and the sum of the squares of the standard deviations of the delays of each second road segment, and taking the square root of the sum to obtain the standard deviation of the delay of the target path.

[0015] Secondly, embodiments of this application also provide a timing verification device, comprising: a first acquisition unit, configured to acquire a first standard cell library corresponding to each die in the chip to be verified, wherein each standard cell in the first standard cell library has its own 3D process angle timing parameters, the 3D process angle timing parameters including the average delay of each standard cell under the 3D process angle and the standard deviation of the delay of the standard cell under the 3D process angle; wherein the chip to be verified is obtained by 3D integration of at least two dies; and a verification unit, configured to perform timing verification on the chip to be verified using the first standard cell library.

[0016] In one embodiment, the apparatus further includes: a second acquisition unit, configured to acquire a second standard cell library corresponding to each die in the chip to be signed before acquiring a first standard cell library corresponding to each die in the chip to be signed, wherein each standard cell in the second standard cell library has its own 2D process corner timing parameters, the 2D process corner timing parameters including: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions; a determination unit, configured to determine the average delay of the standard cell under the 3D process corner based on the average delay of each standard cell under 2D conditions to obtain a first average delay, and to determine the standard deviation of the delay of the standard cell under the 3D process corner based on the local standard deviation of the delay of each standard cell under 2D conditions to obtain a first standard deviation; and a configuration unit, configured to configure each of the first average delays and each of the first standard deviations to the second standard cell library to form the first standard cell library.

[0017] In one embodiment, the determining unit includes a first determining module, configured to determine the average delay of the standard unit under the 3-dimensional process angle based on the average delay of each standard unit under a typical process angle in 2-dimensional conditions, thereby obtaining the first average delay.

[0018] In one embodiment, the determining unit includes a second determining module, configured to: determine the total standard deviation of the delay of each device in each die of the chip to be signed off, using a device model provided by the wafer fab or through simulation; determine the standard deviation expansion coefficient of the device based on the total standard deviation of the delay of each device and the local standard deviation of the delay of the device; and determine the standard deviation of the delay of the standard unit under the 3-dimensional process angle based on the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit, thereby obtaining the first standard deviation.

[0019] In one embodiment, the standard deviation expansion coefficient of each device is equal to the ratio of the total standard deviation of the device's delay to the local standard deviation of the device's delay; the first standard deviation of each standard unit is equal to the product of the local standard deviation of the standard unit's delay under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

[0020] In one embodiment, the approval unit includes: a third determining module, configured to determine the delay parameters of a first segment of the target path in the chip to be approved based on the first standard cell library, and to determine the delay parameters of a second segment of the target path based on a metal wire delay model, wherein the first segment is the part of the target path located inside each die, and the second segment is the part of the target path located between adjacent dies; a fourth determining module, configured to determine the delay parameters of the target path based on the delay parameters of the first segment and the delay parameters of the second segment; and a fifth determining module, configured to determine whether the target path has been approved based on whether the delay parameters of the target path are within a preset parameter range.

[0021] In one implementation, the delay parameters of the first road segment include the average delay of the first road segment and the standard deviation of the delay of the first road segment; the delay parameters of the second road segment include the average delay of the second road segment and the standard deviation of the delay of the second road segment; the fourth determining module is specifically used to: add the average delay of each first road segment and the average delay of each second road segment to obtain the average delay of the target path; add the sum of the squares of the standard deviations of the delays of each first road segment and the sum of the squares of the standard deviations of the delays of each second road segment, and take the arithmetic square root of the sum to obtain the standard deviation of the delay of the target path.

[0022] Thirdly, embodiments of this application also provide an electronic device, the electronic device comprising: a processor and a memory, the processor being electrically connected to the memory; the memory being used to store executable program code; the processor running a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby implementing any of the timing signature methods provided by embodiments of this application.

[0023] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the timing signature method provided in any embodiment of this application.

[0024] The timing signature method, apparatus, electronic device, and storage medium provided in the embodiments of this application can obtain the first standard cell library corresponding to each die in the chip to be signed, and perform timing signature on the chip to be signed using the first standard cell library. Since the chip to be signed is obtained by 3D integration of at least two dies, and each standard cell in the first standard cell library corresponding to each die has its own 3D process corner timing parameters, the 3D process corner timing parameters include the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner, when performing timing signing on the chip to be signed, the timing signing can be performed directly using the 3D process corner timing parameters of each standard cell. Since the 3D process corner timing parameters are timing parameters under the process corner specifically customized for 3D integration, they are closer to the 3D integration application scenario, and do not need to use the 2D signing process corner of each die for various combinations as in the prior art, which leads to excessive pessimism and complexity in signing, thus effectively reducing the pessimism and complexity of timing signing of 3D integrated chips. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 is a flowchart of a timing verification method provided in an embodiment of this application;

[0027] Figure 2 is a schematic diagram showing the relationship between different standard deviations in the embodiments of this application;

[0028] Figure 3 is a flowchart of a timing signature of the chip to be signed in an embodiment of this application;

[0029] Figure 4 is a detailed flowchart of a timing verification method provided in an embodiment of this application;

[0030] Figure 5 is a schematic diagram of a timing verification device provided in an embodiment of this application;

[0031] Figure 6 is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0033] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0034] Firstly, embodiments of this application provide a timing signature method that can effectively reduce the pessimism and complexity of timing signature for 3D integrated chips.

[0035] As shown in Figure 1, an embodiment of this application provides a time-series signature method, including:

[0036] S11, Obtain the first standard cell library corresponding to each die in the chip to be signed. Each standard cell in the first standard cell library has its own 3D process corner timing parameters. The 3D process corner timing parameters include the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner. The chip to be signed is obtained by 3D integration of at least two dies.

[0037] In the embodiments of this application, the chip to be signed is the chip that needs to undergo timing signing. The chip to be signed may include at least two dies, which can be integrated together in a 3D manner, for example, through through silicon vias (TSVs), hybrid bonding, etc., to achieve electrical interconnection between different dies. It should be noted that in the embodiments of this application, 3D integration is a broad concept and can refer to 2.5D integration, 3D integration, 3.5D integration, etc.

[0038] Each die in the chip to be signed can include many different devices. During circuit design, these devices can be implemented using different standard cells from the first standard cell library. Devices in different dies can be designed using the same first standard cell library or different first standard cell libraries. In the embodiments of this application, the first standard cell library differs from traditional standard cell libraries applicable to 2D chip scenarios at least in that each standard cell in the first standard cell library has its own 3D process angle timing parameters. These 3D process angle timing parameters include the average delay of each standard cell at the 3D process angle and the standard deviation of the delay at the 3D process angle. Here, the 3D process angle can refer to the process angle corresponding to the die in a 3D integration scenario, the delay can refer to the time spent transmitting a signal along a preset path within the chip to be signed, the average delay can refer to the average value of this time, and the standard deviation of the delay can refer to the standard deviation of this time.

[0039] Specifically, for chips in 2D scenarios, the standard cell library typically contains timing parameters for standard cells at various process corners in 2D scenarios. For example, the delay at the FFG (fast N fast P Global) process corner is 20 nanoseconds, and the delay at the SSG (slow N slow P Global) process corner is 45 nanoseconds. Therefore, it is convenient to sign off on chips in 2D scenarios. However, if such a standard cell library is used to sign off on 3D integrated chips, problems such as increased pessimism and excessive complexity in the signing process will be encountered. To address this, in this step, a first standard cell library corresponding to each die in the chip to be signed off can be obtained. Each standard cell in the first standard cell library has its own 3D process corner timing parameters. These 3D process corner timing parameters include the average delay of each standard cell at the 3D process corner and the standard deviation of the delay at the 3D process corner. This allows the 3D process corner timing parameters in the first standard cell library to be used for signing off on the chip to be signed off.

[0040] S12, perform timing verification on the chip to be verified using the first standard unit library.

[0041] Once the first standard cell library is obtained, it can be used to perform timing verification on the chip to be verified. Timing verification using the first standard cell library involves calculating the delay of each path in the chip to be verified using the timing parameters of the standard cells in the library to determine if it meets the requirements, such as whether it is within a preset range. This transforms the timing analysis of 3D integrated chips across dies into a statistical analysis based on a single process corner (Statistical On 3DIC Variation).

[0042] The timing verification method provided in this application can obtain the first standard cell library corresponding to each die in the chip to be verified, and perform timing verification on the chip to be verified using the first standard cell library. Since the chip to be verified is obtained by 3D integration of at least two dies, and each standard cell in the first standard cell library corresponding to each die has its own 3D process corner timing parameters, the 3D process corner timing parameters include the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner, when performing timing verification on the chip to be verified, the 3D process corner timing parameters of each standard cell can be directly used for timing verification. Since the 3D process corner timing parameters are timing parameters under the process corner specifically customized for 3D integration, they are closer to the 3D integration application scenario, and do not need to use the 2D verification process corner of each die for various combinations as in the prior art, which leads to overly pessimistic and complex verification, thereby effectively reducing the pessimism and complexity of timing verification for 3D integrated chips.

[0043] Specifically, in one embodiment of this application, in order to perform timing verification using a first standard cell library, a first standard cell library can be established first. For example, before obtaining the first standard cell library corresponding to each die in the chip to be verified in step S11, the timing verification method provided in this application embodiment may further include: obtaining a second standard cell library corresponding to each die in the chip to be verified, wherein each standard cell in the second standard cell library has its own 2D process corner timing parameters, the 2D process corner timing parameters including: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions; determining the average delay of the standard cell under the 3D process corner based on the average delay of each standard cell under 2D conditions to obtain a first average delay, and determining the standard deviation of the delay of the standard cell under the 3D process corner based on the local standard deviation of the delay of each standard cell under 2D conditions to obtain a first standard deviation; configuring each of the first average delays and each of the first standard deviations to the second standard cell library to form the first standard cell library.

[0044] In other words, in this embodiment, the 3D process angle timing parameters of each standard cell in the first standard cell library can be obtained based on the 2D process angle timing parameters of that standard cell. Specifically, the 2D process angle timing parameters may include: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of that standard cell under 2D conditions.

[0045] The average delay here can refer to the average value of any delay parameter of the standard cell, such as the average arrival time of a signal from point A to point B of the standard cell, the average setup time of a signal at point B of the standard cell, or the average hold time of a signal at point B of the standard cell. Optionally, the 2D process angle can include various types, such as FF process angle, TT process angle, SS process angle, etc. The average delay can have different values ​​under different process angles; for example, the average delay under the FF process angle can be relatively small, while the average delay under the SS process angle can be relatively large.

[0046] In specific implementation, determining the average delay of each standard unit under the 3D process angle based on the average delay of each standard unit under 2D conditions to obtain the first average delay may include: determining the average delay of each standard unit under the 3D process angle based on the average delay of each standard unit under the typical process angle under 2D conditions, thus obtaining the first average delay. That is, in the embodiments of this application, the average delay of a typical process angle under 2D conditions can be used as the average delay under the 3D process angle. For example, in one example, if the average delay of the arrival time from point P1 to point P2 in standard unit A1 under the typical process angle under 2D conditions is 56 nanoseconds, then it can be determined that the average delay of the arrival time of standard unit A1 from point P1 to point P2 under the 3D process angle is also 56 nanoseconds.

[0047] In this embodiment, the average value of the typical process angle of the standard unit under 2D conditions is used as the average delay of the standard unit under 3D process angles. However, the embodiments of this application are not limited to this. In other embodiments of this application, the average delay of the standard unit under 3D process angles can also be determined as needed based on the average delay of the standard unit under other process angles under 2D conditions. For example, in one example, the average delay t3 of the standard unit under 3D process angles can also be determined based on the average delay t1 of the standard unit under FF process angle and / or the average delay t2 of the standard unit under SS process angle under 2D conditions (e.g., t3 = (t1 + t2) / 2). The embodiments of this application do not limit this.

[0048] The average delay has been introduced above. The following section will introduce the local standard deviation of the delay.

[0049] In the embodiments of this application, the local standard deviation of delay can refer to the standard deviation of any delay parameter of the standard unit, such as the standard deviation of the arrival time of the signal from point A to point B, the standard deviation of the establishment time of the signal at point A, etc. In one example, determining the standard deviation of the delay of the standard unit under the 3D process angle based on the local standard deviation of the delay of each standard unit under 2D conditions, and obtaining the first standard deviation, may include: determining the total standard deviation of the delay of each device in each die of the chip to be signed off and the local standard deviation of the delay of the device through the device model provided by the wafer fab or through simulation; determining the standard deviation expansion coefficient of the device based on the total standard deviation of the delay of each device and the local standard deviation of the delay of the device; determining the standard deviation of the delay of the standard unit under the 3D process angle based on the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit, and obtaining the first standard deviation.

[0050] In one embodiment of this application, the device model provided by the wafer fab can be a SPICE model. In the chip to be signed off, each die contains various devices with its own corresponding device model. Based on this device model, the total standard deviation and local standard deviation of the delay for the corresponding device can be determined. In another embodiment of this application, simulations can also be performed on various devices within the die to determine the total standard deviation and local standard deviation of the delay for each device.

[0051] Furthermore, the standard deviation expansion coefficient of each device can be determined based on the total standard deviation of its delay and the local standard deviation of its delay. In one example, the standard deviation expansion coefficient of each device can be equal to the ratio of the total standard deviation of its delay to the local standard deviation of its delay; therefore, the first standard deviation of each standard unit can be equal to the product of the local standard deviation of its delay under 2D conditions and the standard deviation expansion coefficient of the device corresponding to that standard unit. For example, the relationship between the delay standard deviation (i.e., the first standard deviation), the total standard deviation of device delay, and the local standard deviation of device delay under 3D process angles can be shown in Figure 2. Here, TT represents the delay under typical process angles, FF represents the delay under fast N-fast P process angles, and SS represents the delay under slow N-slow P process angles. As can be seen from Figure 2, after the ellipse represented by the local standard deviation of device delay is enlarged by a certain factor (the enlargement factor is determined by the standard deviation expansion coefficient), the ellipse represented by the delay standard deviation under 3D process angles is obtained.

[0052] For example, in one embodiment of this application, according to the device model provided by the wafer fab, for the inverter inv1 in the die, the total standard deviation of the propagation delay from the input to the output is a, and the local standard deviation is b. Then, the standard deviation expansion coefficient of the propagation delay of the inverter inv1 from the input to the output is k = a / b. Based on this, the first standard deviation of the standard cell corresponding to the inverter inv1 can be equal to the product of the local standard deviation of the delay of the standard cell under 2D conditions (e.g., c) and the standard deviation expansion coefficient of the device corresponding to the standard cell (e.g., k) (k*c), that is, the first standard deviation is equal to k*c.

[0053] After obtaining the first average delay and the first standard deviation, the first average value and the first standard deviation can be added to the standard cells corresponding to the second standard cell library, thereby forming the first standard cell library. Based on this, in step S11, the first standard cell library corresponding to each die in the chip to be signed can be obtained, and further in step S12, the first standard cell library can be used to perform timing signing on the chip to be signed.

[0054] In one embodiment of this application, a first standard cell library is used to perform timing verification of the chip to be verified. Specifically, the timing parameters in the first standard cell library are used to calculate whether the delay parameters of each path in the chip to be verified are within a preset parameter range. Each path can include one or more standard cells, and the delay parameters of each path can be determined by the delay parameters of each standard cell on that path.

[0055] In one example, each path in the chip to be signed can include segments within the die and segments between dies, and the delay parameter of that path can be obtained based on the delay parameters of these two types of segments.

[0056] Specifically, in one embodiment of this application, performing timing verification of the chip to be verified using the first standard cell library may include: determining the delay parameters of a first segment of the target path in the chip to be verified based on the first standard cell library, and determining the delay parameters of a second segment of the target path based on a metal wire delay model, wherein the first segment is the part of the target path located inside each die, and the second segment is the part of the target path located between adjacent dies; determining the delay parameters of the target path based on the delay parameters of the first segment and the delay parameters of the second segment; and determining whether the target path has been verified based on whether the delay parameters of the target path are within a preset parameter range.

[0057] The target path can be any path in the chip to be signed that requires timing signing. The target path can involve all the dies in the chip to be signed, or it can involve only a portion of the dies; the embodiments of this application do not limit this. For example, in one example, the chip to be signed may include die1, die2, and die3. Target path 1 can pass through die1, die2, and die3, that is, target path 1 involves 3 dies in the chip to be signed. Target path 2 can pass through die1 and die2, that is, target path 2 involves 2 dies in the chip to be signed.

[0058] When the target path involves two or more dies in the chip to be signed, the target path may include two types of segments: a first segment and a second segment. The first segment may refer to the part of the target path located inside each die. For example, the part of the target path located in die1 is one first segment, and the part located in die2 is another first segment. The second segment may refer to the part of the target path located between adjacent dies, for example, the part that interconnects die1 and die2.

[0059] In one embodiment of this application, when performing timing verification on the target path, the first segment and the second segment can calculate their delay parameters using different methods. Specifically, since the first segment refers to the part of the target path located inside each die, its delay parameters can be calculated based on the standard cells in the first standard cell library corresponding to that die. Since the second segment refers to the part of the target path located between adjacent dies, and the delay of this part of the path is mostly caused by the resistance, capacitance, etc., of the metal lines, its delay parameters can be calculated based on the metal line delay model.

[0060] After obtaining the delay parameters of the first road segment and the second road segment, the delay parameters of the target path can be determined based on the delay parameters of the first road segment and the second road segment. Specifically, in one embodiment of this application, the delay parameters of the first road segment may include the average delay of the first road segment and the standard deviation of the delay of the first road segment; the delay parameters of the second road segment may include the average delay of the second road segment and the standard deviation of the delay of the second road segment; therefore, determining the delay parameters of the target path based on the delay parameters of the first road segment and the delay parameters of the second road segment may specifically include: adding the average delay of each first road segment and the average delay of each second road segment to obtain the average delay of the target path; adding the sum of the squares of the standard deviations of the delays of each first road segment and the sum of the squares of the standard deviations of the delays of each second road segment, and taking the square root of the sum to obtain the standard deviation of the delay of the target path.

[0061] For example, in one embodiment of this application, the chip to be signed includes die0 and die1. Die0 and die1 are 3D integrated through hybrid bonding or other methods to obtain the chip to be signed. As shown in Figure 3, when signing the chip to be signed, the corresponding first standard cell library can be linked to die0 and die1 respectively to obtain information such as the netlist of the path to be signed, design constraints, and parasitic parameters in die0 and die1. For the path to be signed for the inter-die interconnection between die0 and die1, the corresponding standard delay format file can be obtained. Further, the delay parameters of each standard cell in the path to be signed in die0 and die1, as well as the delay parameters of the path to be signed for the inter-die interconnection, can be obtained. Each delay parameter is a delay parameter suitable for 3D integrated chips obtained after the aforementioned coefficient processing, thereby enabling timing analysis of the chip to be signed.

[0062] The following comparison between the signing method provided in the embodiments of this application and the signing method in the prior art is made.

[0063] Existing technical solutions

[0064] The chip to be signed consists of three stacked dies, which have the same voltage and temperature conditions and are synchronized across dies.

[0065] TTG delay=100ps (picosecond), FFG delay=85ps, SSG delay=115ps; Local variation sigma=5ps.

[0066] Wherein, TTG delay is the average arrival time of the target path segment located in each die under a typical process angle; FFG delay is the average arrival time of the target path segment located in each die under a fast N fast P process angle; and SSG delay is the average arrival time of the target path segment located in each die under a slow N slow P process angle.

[0067] Using a scheme combining global corner and local variation, if the global process corners (TTGs) of the three dies in the chip to be signed are all typical process corners (TTGs), then the combination of global process corners of the three dies is TTG+TTG+TTG. Under this combination of process corners, the following timing parameters are obtained:

[0068] Path arrival mean=delay_die0+delay_die1+delay_die2=100+100+100=300(ps)

[0069] Path arrival

[0070] Wherein, Path arrival mean is the average arrival time of the target path in the chip to be signed (i.e., passing through the three dies of the chip to be signed), and Path arrival sigma is the standard deviation of the arrival time of the target path in the chip to be signed.

[0071] Similarly, the timing parameters of the three grains under other process corner combinations can be calculated, as shown in Table 1.

[0072] Table 1

[0073] As shown in Table 1, there are 3*3*3 = 27 possible process corner combinations for 3 dies, meaning there are 27 possible process corner combinations for approval. Under various process corner combinations, the minimum allowable path arrival time at 3 times the standard deviation occurs with the FFG+FFG+FFG process corner combination, specifically 255 - 8.5*3 = 229.5 (see * in Table 1). The maximum allowable path arrival time at 3 times the standard deviation occurs with the SSG+SSG+SSG process corner combination, specifically 345 + 8.5*3 = 370.5 (see * in Table 1). The difference between the two is 370.5 - 229.5 = 141, covering a wide range, but the probability of actual extreme scenarios occurring is very low. Therefore, approval in this way would be rather pessimistic.

[0074] The scheme of the embodiments of this application

[0075] In one embodiment of this application, the chip to be signed can be signed based on a 3D process angle. In this signing scenario, the signing process angle combination for each die corresponding to the 3D process angle is only one combination: TTG+TTG+TTG. Therefore, the number of signing process angle combinations is 1, which is much smaller than the 27 signing process angle condition combinations in the prior art, thereby effectively reducing the complexity of timing signing of 3D integrated chips.

[0076] Optionally, during the approval process, if only the average delay and standard deviation of the delay within the die are considered, without considering the average delay and standard deviation of the delay between dies, then the standard deviation of the delay of the target path in each die at the 3D process angle (i.e., the standard deviation of the arrival time) can be determined based on the standard deviation of the delay of each standard unit in each die of the chip to be approved at the 3D process angle. For example, the standard deviation of the delay of the target path in each die at the 3D process angle is 10.

[0077] Then, Path arrival mean=delay_die0+delay_die1+delay_die2=100+100+100=300(ps)

[0078] Path arrival

[0079] Wherein, Path arrival mean is the average arrival time of the target path in the chip to be signed (i.e., passing through the three dies of the chip to be signed), and Path arrival sigma is the standard deviation of the arrival time of the target path in the chip to be signed.

[0080] Therefore, the minimum allowable target path arrival time under 3 standard deviations is 300 - 17 * 3 = 249, and the maximum allowable target path arrival time under 3 standard deviations is 300 + 17 * 3 = 351. The difference between the two is 351 - 249 = 102 ps, which is much smaller than the 141 ps in the existing technical solution, thus effectively reducing the pessimism. See Table 2 for details of each timing parameter.

[0081] Table 2

[0082] In another embodiment of this application, if the average delay and standard deviation of the delay of the target path between dies are considered, in addition to determining the average delay and standard deviation of the delay of the first segment as described in the foregoing embodiments, the average delay and standard deviation of the portion of the target path located between each die in the chip to be signed can be further determined (i.e., the average delay and standard deviation of each second segment of the target path). For example, in one example, the average delay of the portion of the target path located between each die is 10, and the standard deviation of the delay is 5.

[0083] The following conclusions can be drawn:

[0084] Path arrival mean=delay_die0+delay_0-1+delay_die1+delay_1-2+delay_die2=100+10+100+10+100=320(ps)

[0085] Path arrival

[0086] The timing verification method provided by the embodiments of this application will be described in detail below through a specific example.

[0087] As shown in Figure 4, the timing verification method provided in the embodiments of this application may include:

[0088] S201. Obtain the second standard cell library corresponding to each die in the chip to be signed. Each standard cell in the second standard cell library has its own 2D process corner timing parameters. The 2D process corner timing parameters include: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions.

[0089] S202. Based on the average delay of each standard unit under a typical process angle in 2D conditions, determine the average delay of the standard unit under a 3D process angle to obtain the first average delay.

[0090] S203. Using the device model provided by the wafer fab or through simulation, determine the total standard deviation of the delay of each device in each die of the chip to be signed off and the local standard deviation of the device's delay.

[0091] S204. Determine the standard deviation expansion coefficient of each device based on the total standard deviation of its delay and the local standard deviation of its delay.

[0092] S205. Based on the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit, determine the standard deviation of the delay of the standard unit under 3D process angle, and obtain the first standard deviation.

[0093] S206. All first average delays and first standard deviations are configured into the second standard cell library to form the first standard cell library.

[0094] S207. Determine the delay parameters of the first segment of the target path in the chip to be signed based on the first standard cell library, and determine the delay parameters of the second segment of the target path based on the metal line delay model, wherein the first segment is the part of the target path located inside each die, and the second segment is the part of the target path located between adjacent dies.

[0095] S208. Determine the delay parameters of the target path based on the delay parameters of the first road segment and the delay parameters of the second road segment.

[0096] For example, the average delay of each first road segment and the average delay of each second road segment can be added together to obtain the average delay of the target path. The sum of the squares of the standard deviations of the delays of each first road segment and the sum of the squares of the standard deviations of the delays of each second road segment can be added together, and the arithmetic square root of the sum can be obtained to obtain the standard deviation of the delay of the target path.

[0097] S209. Determine whether the target path has been approved based on whether the delay parameters of the target path are within the preset parameter range.

[0098] Secondly, embodiments of this application provide a timing verification device that can effectively reduce the pessimism and complexity of timing verification for 3D integrated chips.

[0099] As shown in Figure 5, an embodiment of this application also provides a time-series signature verification device, comprising:

[0100] The first acquisition unit 31 is used to acquire the first standard cell library corresponding to each die in the chip to be signed. Each standard cell in the first standard cell library has its own 3D process corner timing parameters. The 3D process corner timing parameters include the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner. The chip to be signed is obtained by 3D integration of at least two dies.

[0101] The signing unit 32 is used to perform timing signing on the chip to be signed using the first standard unit library.

[0102] The timing verification device provided in the embodiments of this application can obtain the first standard cell library corresponding to each die in the chip to be verified, and perform timing verification on the chip to be verified using the first standard cell library. Since the chip to be verified is obtained by 3D integration of at least two dies, and each standard cell in the first standard cell library corresponding to each die has its own 3D process corner timing parameters, the 3D process corner timing parameters include the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner, when performing timing verification on the chip to be verified, the 3D process corner timing parameters of each standard cell can be directly used for timing verification. Since the 3D process corner timing parameters are timing parameters under the process corner specifically customized for 3D integration, they are closer to the 3D integration application scenario, and do not need to use the 2D verification process corner of each die for various combinations as in the prior art, which leads to excessive pessimism and complexity in verification, thereby effectively reducing the pessimism and complexity of timing verification for 3D integrated chips.

[0103] In one embodiment, the timing verification device provided in the embodiments of this application may further include:

[0104] The second acquisition unit is used to acquire the second standard cell library corresponding to each die in the chip to be signed before acquiring the first standard cell library corresponding to each die in the chip to be signed. Each standard cell in the second standard cell library has its own 2D process corner timing parameters. The 2D process corner timing parameters include: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions.

[0105] The determining unit is configured to determine the average delay of the standard unit under the 3-dimensional process angle based on the average delay of each standard unit under 2-dimensional conditions, to obtain a first average delay, and to determine the standard deviation of the delay of the standard unit under the 3-dimensional process angle based on the local standard deviation of the delay of each standard unit under 2-dimensional conditions, to obtain a first standard deviation.

[0106] A configuration unit is configured to configure each of the first average delays and each of the first standard deviations into the second standard cell library to form the first standard cell library.

[0107] In one embodiment, the determining unit includes a first determining module, configured to determine the average delay of the standard unit under the 3-dimensional process angle based on the average delay of each standard unit under a typical process angle in 2-dimensional conditions, thereby obtaining the first average delay.

[0108] In one embodiment, the determining unit includes a second determining module, configured to:

[0109] The total standard deviation of the delay of each device in each die of the chip to be signed is determined by using device models provided by the wafer fab or by simulation.

[0110] The standard deviation expansion coefficient of each device is determined based on the total standard deviation of the delay and the local standard deviation of the delay of each device.

[0111] Based on the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit, the standard deviation of the delay of the standard unit under the 3D process angle is determined, and the first standard deviation is obtained.

[0112] In one embodiment, the standard deviation expansion coefficient of each device is equal to the ratio of the total standard deviation of the device's delay to the local standard deviation of the device's delay; the first standard deviation of each standard unit is equal to the product of the local standard deviation of the standard unit's delay under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

[0113] In one embodiment, the approval unit 31 includes:

[0114] The third determining module is used to determine the delay parameters of the first segment of the target path in the chip to be signed based on the first standard cell library, and to determine the delay parameters of the second segment of the target path based on the metal line delay model, wherein the first segment is the part of the target path located inside each grain, and the second segment is the part of the target path located between adjacent grains;

[0115] The fourth determining module is used to determine the delay parameters of the target path based on the delay parameters of the first road segment and the delay parameters of the second road segment;

[0116] The fifth determining module is used to determine whether the target path has been approved based on whether the delay parameter of the target path is within a preset parameter range.

[0117] In one implementation, the delay parameters of the first road segment include the average delay of the first road segment and the standard deviation of the delay of the first road segment; the delay parameters of the second road segment include the average delay of the second road segment and the standard deviation of the delay of the second road segment; the fourth determining module is specifically used to: add the average delay of each first road segment and the average delay of each second road segment to obtain the average delay of the target path; add the sum of the squares of the standard deviations of the delays of each first road segment and the sum of the squares of the standard deviations of the delays of each second road segment, and take the arithmetic square root of the sum to obtain the standard deviation of the delay of the target path.

[0118] Thirdly, embodiments of this application also provide an electronic device that can effectively reduce the pessimism and complexity of timing signature of 3D integrated chips.

[0119] As shown in Figure 6, the electronic device provided in the embodiments of this application may include: a processor 51 and a memory 52, with the processor 51 and the memory 52 electrically connected; the memory 52 is used to store executable program code; the processor 51 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 52, so as to implement any of the timing signature methods provided in the embodiments of this application.

[0120] The specific execution process of the above steps by the processor 51, as well as the steps further executed by the processor 51 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0121] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the timing signature methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0122] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0123] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0124] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0125] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0126] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0127] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A time-series signature method, wherein, include: Obtain the first standard cell library corresponding to each die in the chip to be signed. Each standard cell in the first standard cell library has its own 3D process corner timing parameters. The 3D process corner timing parameters include the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner. The chip to be signed is obtained by 3D integration of at least two dies. The chip to be signed is time-series signed using the first standard cell library.

2. The method according to claim 1, wherein, Before obtaining the first standard cell library corresponding to each die in the chip to be signed, the method further includes: Obtain the second standard cell library corresponding to each die in the chip to be signed. Each standard cell in the second standard cell library has its own 2D process corner timing parameters. The 2D process corner timing parameters include: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions. Based on the average delay of each standard unit under 2D conditions, the average delay of the standard unit under the 3D process angle is determined to obtain the first average delay. Based on the local standard deviation of the delay of each standard unit under 2D conditions, the standard deviation of the delay of the standard unit under the 3D process angle is determined to obtain the first standard deviation. Each of the first average delays and each of the first standard deviations are configured into the second standard cell library to form the first standard cell library.

3. The method according to claim 2, wherein, The step of determining the average delay of each standard unit under the 3D process angle based on the average delay of each standard unit under 2D conditions, and obtaining the first average delay, includes: Based on the average delay of each standard unit at a typical process angle under 2D conditions, the average delay of the standard unit at the 3D process angle is determined, and the first average delay is obtained.

4. The method according to claim 2, wherein, The step of determining the standard deviation of the delay of each standard unit under the 3D process angle based on the local standard deviation of the delay under the 2D condition, and obtaining the first standard deviation, includes: The total standard deviation of the delay of each device in each die of the chip to be signed is determined by using the device model provided by the wafer fab or by simulation. The standard deviation expansion coefficient of each device is determined based on the total standard deviation of the delay and the local standard deviation of the delay of each device. Based on the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit, the standard deviation of the delay of the standard unit under the 3D process angle is determined, and the first standard deviation is obtained.

5. The method according to claim 4, wherein, The standard deviation expansion coefficient of each of the devices is equal to the ratio of the total standard deviation of the device's delay to the local standard deviation of the device's delay; The first standard deviation of each of the standard units is equal to the product of the local standard deviation of the delay of the standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

6. The method according to any one of claims 1 to 5, wherein, The step of performing time-series signing of the chip to be signed using the first standard cell library includes: Based on the first standard cell library, the delay parameters of the first segment of the target path in the chip to be signed are determined, and the delay parameters of the second segment of the target path are determined based on the metal line delay model. The first segment is the part of the target path located inside each die, and the second segment is the part of the target path located between adjacent dies. The delay parameters of the target path are determined based on the delay parameters of the first road segment and the delay parameters of the second road segment; Whether the target path is approved is determined based on whether the delay parameter of the target path is within the preset parameter range.

7. The method according to claim 6, wherein, The delay parameters for the first road segment include the average delay of the first road segment and the standard deviation of the delay of the first road segment; the delay parameters for the second road segment include the average delay of the second road segment and the standard deviation of the delay of the second road segment. Determining the delay parameters of the target path based on the delay parameters of the first road segment and the delay parameters of the second road segment includes: The average delay of the target path is obtained by adding the average delay of each first road segment and the average delay of each second road segment. The sum of the squares of the standard deviations of the delays of each of the first road segments and the sum of the squares of the standard deviations of the delays of each of the second road segments are added together, and the arithmetic square root of the sum is taken to obtain the standard deviation of the delay of the target path.

8. A time-series signature device, wherein, include: The first acquisition unit is used to acquire the first standard cell library corresponding to each die in the chip to be signed. Each standard cell in the first standard cell library has its own 3D process corner timing parameters. The 3D process corner timing parameters include the average delay of each standard cell under the 3D process corner and the standard deviation of the delay of the standard cell under the 3D process corner. The chip to be signed is obtained by 3D integration of at least two dies. The signing unit is used to perform timing signing on the chip to be signed using the first standard unit library.

9. The apparatus according to claim 8, wherein, Also includes The second acquisition unit is used to acquire the second standard cell library corresponding to each die in the chip to be signed before acquiring the first standard cell library corresponding to each die in the chip to be signed. Each standard cell in the second standard cell library has its own 2D process corner timing parameters. The 2D process corner timing parameters include: the average delay of each standard cell under 2D conditions and the local standard deviation of the delay of the standard cell under 2D conditions. The determining unit is configured to determine the average delay of the standard unit under the 3-dimensional process angle based on the average delay of each standard unit under 2-dimensional conditions, to obtain a first average delay, and to determine the standard deviation of the delay of the standard unit under the 3-dimensional process angle based on the local standard deviation of the delay of each standard unit under 2-dimensional conditions, to obtain a first standard deviation. A configuration unit is configured to configure each of the first average delays and each of the first standard deviations into the second standard cell library to form the first standard cell library.

10. The apparatus according to claim 9, wherein, The determining unit includes a first determining module, which is used to determine the average delay of the standard unit under the 3-dimensional process angle based on the average delay of each standard unit under the typical process angle in 2-dimensional conditions, and obtain the first average delay.

11. The apparatus according to claim 9, wherein, The determining unit includes a second determining module, used for: The total standard deviation of the delay of each device in each die of the chip to be signed is determined by using the device model provided by the wafer fab or by simulation. The standard deviation expansion coefficient of each device is determined based on the total standard deviation of the delay and the local standard deviation of the delay of each device. Based on the local standard deviation of the delay of each standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit, the standard deviation of the delay of the standard unit under the 3D process angle is determined, and the first standard deviation is obtained.

12. The apparatus according to claim 11, wherein, The standard deviation expansion coefficient of each of the devices is equal to the ratio of the total standard deviation of the device's delay to the local standard deviation of the device's delay; The first standard deviation of each of the standard units is equal to the product of the local standard deviation of the delay of the standard unit under 2D conditions and the standard deviation expansion coefficient of the device corresponding to the standard unit.

13. The apparatus according to any one of claims 8 to 12, wherein, The approval unit includes: The third determining module is used to determine the delay parameters of the first segment of the target path in the chip to be signed based on the first standard cell library, and to determine the delay parameters of the second segment of the target path based on the metal line delay model, wherein the first segment is the part of the target path located inside each grain, and the second segment is the part of the target path located between adjacent grains; The fourth determining module is used to determine the delay parameters of the target path based on the delay parameters of the first road segment and the delay parameters of the second road segment; The fifth determining module is used to determine whether the target path has been approved based on whether the delay parameter of the target path is within a preset parameter range.

14. The apparatus according to claim 13, wherein, The delay parameters for the first road segment include the average delay of the first road segment and the standard deviation of the delay of the first road segment; the delay parameters for the second road segment include the average delay of the second road segment and the standard deviation of the delay of the second road segment. The fourth determining module is specifically used for: The average delay of the target path is obtained by adding the average delay of each first road segment and the average delay of each second road segment. The sum of the squares of the standard deviations of the delays of each of the first road segments and the sum of the squares of the standard deviations of the delays of each of the second road segments are added together, and the arithmetic square root of the sum is taken to obtain the standard deviation of the delay of the target path.

15. An electronic device, wherein, The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the timing signature method of any one of claims 1 to 7.

16. A computer-readable storage medium, wherein, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the timing signature method according to any one of claims 1 to 7.

Images