Method for quickly solving plane segmentation of via in multi-layer integrated circuit board

Abstract

A method for quickly solving plane segmentation of a via in a multi-layer integrated circuit board, comprising: calculating connection relationships between all elements in the multi-layer integrated circuit board; determining a vertical position of each via; identifying plane layers intersecting the via; recording connection information; assigning a priority value to each plane layer; performing sorting according to priority values; creating a data structure; converting the data structure, the data structure comprising an instance representing a pair of plane layers, and an instance of a corresponding via intersecting the pair of plane layers; and converting the data structure into a key-value pair mapping data structure; and thus, on the basis of an obtained relationship of each via being segmented by planes, cutting out the via segmented by the planes.

Description

A method for quickly solving planar vias in multilayer integrated circuit boards Technical Field

[0001] This invention relates to the field of integrated circuit board technology, and more specifically, to a method for rapidly solving planar vias in multilayer integrated circuit boards. Background Technology

[0002] Traditional via partitioning methods rely on complex meshing and iterative geometric modeling techniques. These methods often require significant computational resources and time when dealing with multi-layer PCB structures, especially in high-density circuit designs, where their efficiency and accuracy fall short of the demands of industrial applications. Furthermore, existing technologies often employ approximate calculations when handling the interaction between electromagnetic fields and vias, which can lead to substantial errors in high-frequency applications, impacting circuit performance and reliability.

[0003] As electronic devices evolve towards higher performance and more complex functions, higher demands are placed on the design of multilayer PCBs. In high-frequency, high-speed, and high-power applications, the electromagnetic characteristics of vias have an increasingly significant impact on signal integrity and power integrity. Therefore, how to quickly and accurately segment vias in multilayer PCBs has become a pressing technical challenge in circuit design and manufacturing. Existing mesh-based segmentation methods and geometric modeling techniques suffer from low computational efficiency when dealing with large-scale problems and are difficult to adapt to constantly changing design requirements.

[0004] To address these issues, researchers have proposed several improved via segmentation techniques, such as feature recognition-based segmentation methods and multi-layer modeling and mapping techniques. These methods have improved segmentation efficiency and accuracy to some extent, but still have limitations. For example, feature recognition-based methods require high feature recognition capabilities, while multi-layer modeling and mapping techniques still face challenges in organizing and processing data structures when dealing with complex multi-layer structures. Summary of the Invention

[0005] In a first aspect of the present invention, a method for rapidly solving planar vias in a multilayer integrated circuit board is provided, comprising the following steps:

[0006] Calculate the connection relationships of all elements within a multilayer integrated circuit board;

[0007] For each hole, find the plane that connects to it, either from top to bottom or bottom to top;

[0008] Sort the layers of the connected planes;

[0009] QMap, a data structure that combines two planar segmented holes. <QPair<int,int> QSet<via>>;

[0010] Convert the data structure to QMap <Via,QSet<QPair<int,int> >>, and you can get the relationship between each Via and the plane phase cutting;

[0011] Based on the relationship between each Via and the plane, holes divided by the plane are cut out.

[0012] As a further improvement to this application, calculating the interconnection relationships of all elements within a multilayer integrated circuit board includes the following steps:

[0013] Use graph theory algorithms to construct the connection diagram of the circuit board;

[0014] Identify and record the connection relationship between each via and the plane layer using the circuit board connection diagram.

[0015] As a further improvement to this application, for each hole, finding the plane connected to it from top to bottom or bottom to top includes:

[0016] Determine the vertical position of each via;

[0017] Identify the intersecting planar layers based on the vertical position of the via;

[0018] Record the connection information between each via and the intersecting plane layer.

[0019] As a further improvement to this application, the sorting of layers in the connected plane includes:

[0020] Assign a priority value to each plane layer based on its physical location or electrical characteristics.

[0021] The planar layers are sorted according to their priority values.

[0022] As a further improvement to this application, a data structure QMap is used to combine two planar segmented holes. <QPair<int,int> QSet <via>>Including:

[0023] For each pair of intersecting planar layers, create a QPair.<int,int> An example represents this pair of planar layers;

[0024] For each QPair<int,int> Example: Create a QSet <via>Instances are used to store vias that intersect with this pair of planar layers;

[0025] Add each via to the QSet corresponding to the plane layer that intersects with it. <via>middle.

[0026] As a further improvement to this application, the data structure is converted to QMap. <Via,QSet<QPair<int,int> >>Including:

[0027] For each via, create a QSet. <QPair<int,int> An instance is used to store the planar layer pairs that intersect with the via;

[0028] Traversing the original data structure QMap <QPair<int,int> QSet <via>> For each QPair<int,int> and the corresponding QSet <via>Add each via to the corresponding QSet of its intersecting planar layer pair. <QPair<int,int> >China;

[0029] The new data structure QMap has been built. <Via,QSet<QPair<int,int> >>

[0030] As a further improvement to this application, based on the relationship that each Via is cut by a plane, the holes divided by the plane are cut out, including:

[0031] Traversing the QMap data structure <Via,QSet<QPair<int,int> >> For each via, obtain its intersecting planar layer pairs;

[0032] Determine the via segmentation position based on the intersecting planar layer pairs;

[0033] Based on the determined segmentation position of the via, the holes are cut out by the plane.

[0034] In a second aspect of the present invention, a via partitioning system for a multilayer integrated circuit board is provided, the system comprising:

[0035] The calculation module is used to calculate the connection relationships of all elements within a multilayer integrated circuit board.

[0036] The connecting plane module is used to find the plane to which each hole is connected, either from top to bottom or bottom to top.

[0037] The sorting module is used to sort the layers of the connected planes;

[0038] The combination module is used to combine the data structure QMap of two plane-divided holes. <QPair<int,int> QSet <via>>;

[0039] The conversion module is used to convert the data structure to QMap. <Via,QSet<QPair<int,int> >>, and you can get the relationship between each Via and the plane phase cutting;

[0040] The cutting module is used to cut out holes divided by the plane based on the relationship between each Via and the plane.

[0041] In a third aspect of the invention, an electronic device is provided, comprising:

[0042] At least one processor; and

[0043] A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method for rapidly solving planar vias in a multilayer integrated circuit board, as described in any one aspect of the invention.

[0044] In a fourth aspect of the invention, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are configured to cause the computer to execute a method for rapidly solving planar vias in a multilayer integrated circuit board, as described in any one of the first aspects of the invention.

[0045] The embodiments of the present invention have at least the following beneficial effects: According to the embodiments of the present invention, the method for rapidly solving planar via segmentation in multilayer integrated circuit boards has significant beneficial effects: by accurately calculating the connection relationships of all elements within the circuit board and innovatively using the QMap data structure to organize the relationship between vias and planar layers, the present invention greatly improves the efficiency and accuracy of via segmentation. This method not only reduces the number of iterations in the design phase but also reduces the error rate in the manufacturing process, thereby shortening the overall production cycle and reducing costs. Furthermore, the automated data processing reduces manual intervention, further improving the reliability of the design and providing strong technical support for the design and manufacturing of multilayer integrated circuit boards. Attached Figure Description

[0046] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0047] Figure 1 is a flowchart illustrating a method for rapidly solving planar vias in a multilayer integrated circuit board according to an embodiment of the present invention. Detailed Implementation

[0048] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make the invention more thorough and complete, and to fully convey the scope of the invention to those skilled in the art.

[0049] Those skilled in the art will understand that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, the present invention can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0050] It should be noted that the number of any elements in the accompanying drawings is for illustrative purposes only and not as a limitation, and any naming is for distinction only and has no limiting meaning.

[0051] Referring to Figure 1 below, a method for quickly solving for planar vias in a multilayer integrated circuit board includes the following steps:

[0052] Calculate the connection relationships of all elements within a multilayer integrated circuit board;

[0053] It should be noted that a multilayer integrated circuit board refers to a complex circuit structure composed of multiple conductive layers and insulating material layers, widely used in modern electronic devices. The interconnections of all elements encompass the details of the inter-connection between vias, conductive layers, insulating layers, and other circuit components on the circuit board.

[0054] Specifically, this can be achieved by applying algorithms from graph theory to construct a circuit board connection diagram that details the connection paths between all components on the board. During this process, the connection relationships between each via and the plane layer are meticulously recorded to ensure accurate identification and processing of these connections in subsequent steps.

[0055] Preferably, the process of calculating the connection relationships can use depth-first search (DFS) or breadth-first search (BFS) algorithms in graph theory to traverse the connection graph of the circuit board, ensuring that the connection path of each component is detected; for each via, its connection status with the adjacent plane layer is recorded, including the type of connection (such as direct connection or connection through a conductive path) and the strength of the connection; this information is integrated into a database or data structure for easy access and processing in subsequent steps.

[0056] For each hole, find the plane that connects to it, either from top to bottom or bottom to top;

[0057] It's important to note that each via on the circuit board is analyzed to determine which planar layers it connects to. Vias are through-holes that pass through the circuit board and are used to connect different conductive layers to achieve electrical connections. Planar layers, on the other hand, refer to the conductive layers on the circuit board; these can be single or multiple layers and are used to form the transmission paths of the circuit.

[0058] Specifically, this step can be achieved by determining the vertical position of each via, i.e., its exact location within the circuit board stack. Then, based on this positional information, the intersecting planar layers are identified. In this process, a coordinate system can be used to precisely locate each via and, based on these coordinates, determine which planar layers it intersects with. For example, automated image recognition technology can be introduced to automatically identify and record the positions of vias and the connected planar layers. Furthermore, machine learning algorithms can be used to predict and verify the connectivity between vias and planar layers, thereby improving the accuracy and efficiency of this step.

[0059] Sort the layers of the connected planes;

[0060] It should be noted that the identified planar layers connected to vias are sorted to facilitate subsequent analysis and processing. Sorting refers to rearranging the planar layers according to certain criteria or rules to ensure they are processed in a specific order.

[0061] Specifically, this can be achieved by assigning a priority value to each plane layer, which can be based on the plane layer's physical location, electrical characteristics, or other relevant factors. For example, priority values ​​can be assigned based on the plane layer's connection strength with vias, the plane layer's conductivity, or the plane layer's functional role on the circuit board.

[0062] Preferably, the sorting process can employ various algorithms, such as quicksort, mergesort, or heapsort, to ensure efficiency and accuracy. Furthermore, a weighted sorting mechanism can be introduced, considering multiple factors during the sorting process, such as the electrical characteristics and physical location of the planar layers, to achieve finer-grained sorting control.

[0063] QMap, a data structure that combines two planar segmented holes. <QPair<int,int> QSet <via>>;

[0064] It's worth noting that QMap is a key-value pair mapping data structure, commonly used to store and manage ordered key-value pair data. QPair, on the other hand...<int,int> This represents a pair of two integers used to represent the numbers or identifiers of two planar layers. QSet <via>This represents a set containing via identifiers used to store vias that intersect with a specific plane layer pair.

[0065] Specifically, this can be achieved by creating a QPair<int,int> This is implemented using instances, where each instance represents a pair of intersecting planar layers. Then, for each pair of planar layers, a QSet is created. <via>An instance is used to store all vias that intersect with this pair of planar layers. Thus, each via is recorded in the QSet corresponding to the pair of planar layers it intersects with.

[0066] Preferably, this step can be further optimized, for example, by introducing a hash table to improve the speed of data access and retrieval. Furthermore, more complex data structures, such as graph databases or network analysis tools, can be used to support larger-scale and more complex circuit board designs.

[0067] Convert the data structure to QMap <Via,QSet<QPair<int,int> >>, and you can get the relationship between each Via and the plane phase cutting;

[0068] It should be noted that the data structure transformation is to obtain the relationship between each via and the plane phase, thereby providing accurate data support for via segmentation.

[0069] Specifically, this can be achieved by traversing the original QMap. <QPair<int,int> QSet <via>>Data structure implementation, for each QPair<int,int> and the corresponding QSet <via>Add each via to the corresponding QSet of its intersecting planar layer pair. <QPair<int,int> In this way, each via establishes a direct connection with its intersecting planar layer pair.

[0070] Preferably, multiple algorithms can be used, such as hash table conversion algorithms and shortest path algorithms from graph theory, to ensure the efficiency and accuracy of the conversion process. Furthermore, parallel computing techniques, such as GPU acceleration or distributed computing, can be introduced to handle large-scale data structure conversion tasks.

[0071] Based on the relationship between each Via and the plane, holes divided by the plane are cut out.

[0072] It should be noted that cutting refers to the precise physical division of vias during the circuit board manufacturing process, according to design requirements, in order to achieve layered connections of the circuit.

[0073] Specifically, this can be achieved by traversing the transformed data structure QMap. <Via,QSet<QPair<int,int> >> This is achieved by obtaining the intersecting planar layer pairs for each via, determining the via's segmentation position based on this information, and then performing a cutting operation.

[0074] Preferably, various cutting technologies can be employed, such as laser cutting, plasma cutting, or mechanical drilling, to ensure the precision and quality of the cutting. Furthermore, an automated cutting control system can be introduced to improve the automation and repeatability of the cutting process.

[0075] In some embodiments, calculating the connectivity of all elements within a multilayer integrated circuit board includes the following steps:

[0076] Use graph theory algorithms to construct the connection diagram of the circuit board;

[0077] Identify and record the connection relationship between each via and the plane layer using the circuit board connection diagram.

[0078] First, define each element on the circuit board (e.g., vias, pads, conductive layers, etc.) as a node in the graph. Then, define edges in the graph based on the physical or electrical connections between these elements. For example, if two vias are connected through a conductive layer, draw an edge between the corresponding nodes. In this way, the entire circuit board's interconnections can be abstracted as a graph structure.

[0079] Preferably, the process of constructing the connectivity graph can employ various graph theory algorithms, such as Depth-First Search (DFS) or Breadth-First Search (BFS), to traverse the elements of the circuit board and determine the connections between them. Furthermore, existing graph databases or graph processing software can be used to assist in constructing and storing this connectivity graph for subsequent processing and analysis. For example, a graph database like Neo4j can be used to store the connectivity graph, and its provided graph algorithms can be used for efficient querying and analysis.

[0080] More specifically, the process of constructing a connection diagram may include: First, numbering or labeling all elements on the circuit board for easy identification in the diagram. Then, based on the circuit board's design documents or manufacturing data, determining the connections between these elements and adding corresponding edges to the diagram. Furthermore, weights or labels can be added to the edges in the diagram to indicate the strength, type, or other attributes of the connections. For example, weights can be added to edges representing conductive connections to indicate the conductivity or signal transmission characteristics of the connections. In this way, the connection diagram not only represents the topology of the circuit board but also provides detailed information about the connection characteristics.

[0081] In some embodiments, for each hole, finding the plane connected to it from top to bottom or bottom to top includes:

[0082] Determine the vertical position of each via;

[0083] Identify the intersecting planar layers based on the vertical position of the via;

[0084] Record the connection information between each via and the intersecting plane layer.

[0085] Precisely determining the vertical position of each via is a crucial step in identifying the connection between the via and the planar layer. Vertical position refers to the relative location of the via within the PCB stack-up structure.

[0086] Specifically, determining the vertical position of vias can be achieved through various techniques, such as X-ray imaging or mechanical probe scanning to measure the specific location of the vias within the PCB. Alternatively, the via positions can be pre-determined using computer-aided design (CAD) data from the design phase. Once the vertical position of the via is determined, the intersecting planar layers can be identified based on this positional information. This step is accomplished by analyzing the PCB's laminated structure, involving an understanding of the physical and electrical characteristics of each layer within the PCB.

[0087] Preferably, automated optical inspection equipment can be used to identify and verify the vertical position of vias. Such equipment can provide high-precision measurement results and process large amounts of data quickly. Furthermore, machine learning algorithms can be employed to analyze the connection relationship between vias and planar layers, thereby improving the accuracy and efficiency of the identification process. For example, a machine learning model can be trained to identify connection patterns between vias and planar layers, thus reducing manual intervention and improving production efficiency.

[0088] When recording the connection information of each via to the intersecting plane layer, barcode or QR code labels can be used to mark the vias, and the connection information can be automatically recorded by scanning these labels. Such an automated recording system can not only reduce human error, but also improve the speed and accuracy of data recording. In addition, this data can be integrated into the PCB Manufacturing Execution System (MES) to facilitate the tracking and analysis of the entire production process.

[0089] In some embodiments, sorting the layers of a connected plane includes:

[0090] Assign a priority value to each plane layer based on its physical location or electrical characteristics.

[0091] The planar layers are sorted according to their priority values.

[0092] Sequencing the connected planar layers ensures that each planar layer is processed according to a specific priority during subsequent via partitioning. Planar layers typically refer to the various layers on a printed circuit board (PCB) used to arrange circuitry, and these layers are arranged sequentially according to certain rules or standards.

[0093] Specifically, this can be done by analyzing the physical location or electrical characteristics of each plane layer. For example, a priority value can be assigned to each plane layer based on factors such as the proximity of the plane layer to vias, current capacity requirements, and signal integrity requirements. In practice, power and ground layers typically need to be tightly coupled to increase the capacitance between them, thereby increasing the resonant frequency. Furthermore, high-speed signal transmission layers should be signal interlayers sandwiched between two inner power layers to provide electromagnetic shielding and limit signal radiation.

[0094] Preferably, the sorting process can also consider the symmetry of the stacked structure to reduce crosstalk between signal layers. For example, avoiding direct adjacency between two signal layers and adding a ground plane between them can effectively prevent crosstalk. Simultaneously, automated algorithms, such as Kruskal's algorithm or topological sorting, can be used to handle the sorting problem, ensuring that each signal layer is adjacent to a suitable reference layer. In this way, the performance of the circuit board can be optimized, and signal integrity and power supply stability can be improved.

[0095] In some embodiments, the data structure QMap combines two planar segmented holes. <QPair<int,int> QSet <via>>Including:

[0096] For each pair of intersecting planar layers, create a QPair.<int,int> An example represents this pair of planar layers;

[0097] For each QPair<int,int> Example: Create a QSet <via>Instances are used to store vias that intersect with this pair of planar layers;

[0098] Add each via to the QSet corresponding to the plane layer that intersects with it. <via>middle.

[0099] It should be noted that the data structure QMap <QPair<int,int> QSet <via>> is used to store and organize the relationships between vias and intersecting planar layers. QMap is a key-value pair-based associative container that allows relationships to be stored based on the key (in this case, QPair).<int,int> Quick lookup value (QSet in this example) <via>QPair<int,int> It's a template class used to store a pair of values, here representing the numbers of two planar layers. QSet <via>It is an unordered set used to store unique via identifiers (Via).

[0100] First, iterate through all possible planar layer pairs in the multilayer integrated circuit board. For each intersecting planar layer pair, create a QPair.<int,int> Instances are used to represent this pair of planar layers. Then, for each QPair...<int,int> Example: Create a QSet <via>An instance is used to store the vias that intersect with this pair of planar layers. During this process, QSet... <via>By leveraging its unordered set property, the stored via identifiers are ensured to be unique, thus avoiding duplication.

[0101] Preferably, when creating QPair<int,int> When instantiating a QMap, you can also override the global hash function (qHash()) to ensure that QMap can efficiently handle the hash value of the key. Additionally, you can do so in QSet. <via>Custom comparison functions can be used to further optimize the storage and retrieval efficiency of vias. For example, a struct or class can be defined for Via, and comparison operators (such as <) can be overloaded in it so that QSet can sort or retrieve vias according to specific criteria.

[0102] In some embodiments, the data structure is converted to QMap. <Via,QSet<QPair<int,int> >>Including:

[0103] For each via, create a QSet. <QPair<int,int> An instance is used to store the planar layer pairs that intersect with the via;

[0104] Traversing the original data structure QMap <QPair<int,int> QSet <via>> For each QPair<int,int> and the corresponding QSet <via>Add each via to the corresponding QSet of its intersecting planar layer pair. <QPair<int,int> >China;

[0105] The new data structure QMap has been built. <Via,QSet<QPair<int,int> >>

[0106] To reorganize the information in the original data structure, detailed information about the intersecting planar layer pairs is provided for each via. This transformation makes the data more directly reflect the relationship between vias and planar layers, facilitating subsequent analysis and processing.

[0107] Specifically, this step can be achieved as follows: First, create a QSet for each via. <QPair<int,int> This instance, this collection, will be used to store the planar layer pairs that intersect with this via. Then, the original data structure QMap is traversed. <QPair<int,int> QSet <via>Each entry in > for each plane layer pair (QPair)<int,int> ) and its corresponding via set (QSet) <via>Add these vias to the corresponding QSet of the plane layer pairs where they intersect. <QPair<int,int> >in China.

[0108] In some embodiments, iterators can be used during traversal to avoid unnecessary data copying, or range-based for loops in C++11 can be used to simplify the code. Furthermore, exception handling mechanisms can be introduced to handle any errors that may occur during traversal or insertion, ensuring the robustness of data structure transformations.

[0109] In some embodiments, based on the relationship between each Via and the plane, cutting out the holes divided by the plane includes:

[0110] Traversing the QMap data structure <Via,QSet<QPair<int,int> >> For each via, obtain its intersecting planar layer pairs;

[0111] Determine the via segmentation position based on the intersecting planar layer pairs;

[0112] Based on the determined segmentation position of the via, the holes are cut out by the plane.

[0113] Based on the obtained relationship between each via and the planar layer, precise via segmentation is performed. This step is the key part of the entire method, ensuring that the vias are correctly segmented according to the specific design requirements of the multilayer integrated circuit board.

[0114] First, traverse the QMap data structure. <Via,QSet<QPair<int,int> For each entry in the data structure, retrieve all intersecting planar layer pairs corresponding to each via. During this process, the keys (via identifiers) and values ​​(the set of planar layer pairs intersecting with that via) of the QMap are used to determine the precise location of each via and the planar layers that need to be segmented.

[0115] Automated software tools can be used to assist in this process. For example, an algorithm can be developed that reads data from a QMap and calculates the via splitting position based on the intersection relationship between the via and the plane layer. This algorithm can be integrated into PCB design software to automate the via splitting process.

[0116] When determining the segmentation location of vias, advanced computational geometry algorithms, such as line segment intersection algorithms or polygon clipping algorithms, can be employed to ensure the accuracy of the segmentation location. Furthermore, machine learning techniques can be introduced to predict and optimize the cutting path of vias, further improving the efficiency and accuracy of the cutting process. For example, machine learning models can be used to analyze historical cutting data, learn the optimal cutting strategies for different types of vias, and apply these strategies to guide the actual cutting process.

[0117] The above embodiments of the present invention have the following beneficial effects:

[0118] The embodiments of the present invention significantly improve the accuracy and efficiency of via segmentation by accurately calculating the connection relationship between vias and planar layers in a multilayer integrated circuit board and utilizing efficient data structures to organize and process this information. This method not only reduces the number of iterations in the design phase but also lowers the error rate in the manufacturing process, thereby shortening the overall production cycle and reducing costs. Furthermore, the automated data processing reduces manual intervention, further enhancing design reliability and providing strong technical support for the design and manufacturing of multilayer integrated circuit boards.

[0119] A via partitioning system for a multilayer integrated circuit board according to some embodiments, the system comprising:

[0120] The calculation module is used to calculate the connection relationships of all elements within a multilayer integrated circuit board.

[0121] The connecting plane module is used to find the plane to which each hole is connected, either from top to bottom or bottom to top.

[0122] The sorting module is used to sort the layers of the connected planes;

[0123] The combination module is used to combine the data structure QMap of two plane-divided holes. <QPair<int,int> QSet <via>>;

[0124] The conversion module is used to convert the data structure to QMap. <Via,QSet<QPair<int,int> >>, and you can get the relationship between each Via and the plane phase cutting;

[0125] The cutting module is used to cut out holes divided by the plane based on the relationship between each Via and the plane.

[0126] It is understood that the modules described in the via partitioning system of this multilayer integrated circuit board correspond to the steps in the via partitioning system method of the multilayer integrated circuit board described with reference to FIG1. ​​Therefore, the operation, features, and beneficial effects described above for the via partitioning system of the multilayer integrated circuit board are also applicable to the via partitioning system of the multilayer integrated circuit board and the modules contained therein, and will not be repeated here.

[0127] The electronic devices in some embodiments of the present invention may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers.

[0128] Electronic devices may include processing units (such as central processing units, graphics processing units, etc.) that can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or loaded from storage devices into random access memory (RAM). RAM also stores various programs and data required for the operation of the electronic device. The processing unit, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0129] Typically, the following devices can be connected to the I / O interface: input devices such as touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices such as liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices such as magnetic tapes, hard disks, etc.; and communication devices. Communication devices allow electronic devices to communicate wirelessly or wiredly with other devices to exchange data. It should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Each box shown may represent one device or, as needed, multiple devices.

[0130] Furthermore, the storage medium in the embodiments of this application stores program instructions capable of implementing all the above methods. These program instructions can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0131] The above description is merely a selection of preferred embodiments of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention as described in the embodiments is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention.< / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via> < / via>

Claims

1. A method for rapidly solving planar vias in a multilayer integrated circuit board, characterized in that, Includes the following steps: Calculate the connection relationships of all elements within a multilayer integrated circuit board; For each hole, find the plane that connects to it, either from top to bottom or bottom to top; Sort the layers of the connected planes; QMap, a data structure that combines two planar segmented holes. <QPair<int,int> QSet <via> >；< / via> Convert the data structure to QMap <Via,QSet<QPair<int,int> >>, and you can get the relationship between each Via and the plane phase cutting; Based on the relationship between each Via and the plane, holes divided by the plane are cut out.

2. The method according to claim 1, characterized in that, Calculating the interconnections of all elements within a multilayer integrated circuit board includes the following steps: Use graph theory algorithms to construct the connection diagram of the circuit board; Identify and record the connection relationship between each via and the plane layer using the circuit board connection diagram.

3. The method according to claim 1 or 2, characterized in that, For each hole, find the planes connected to it from top to bottom or bottom to top, including: Determine the vertical position of each via; Identify the intersecting planar layers based on the vertical position of the via; Record the connection information between each via and the intersecting plane layer.

4. The method according to claim 1 or 3, characterized in that, Sorting the layers of a connected plane includes: Assign a priority value to each plane layer based on its physical location or electrical characteristics. The planar layers are sorted according to their priority values.

5. The method according to claim 1 or 4, characterized in that, QMap, a data structure that combines two planar segmented holes. <QPair<int,int> QSet <via> >Including:< / via> For each pair of intersecting planar layers, create a QPair.<int,int> An example represents this pair of planar layers; For each QPair<int,int> Example: Create a QSet <via> Instances are used to store vias that intersect with this pair of planar layers;< / via> Add each via to the QSet corresponding to the plane layer that intersects with it. <via> middle.< / via> 6. The method according to claim 1 or 5, characterized in that, Convert the data structure to QMap <Via,QSet<QPair<int,int> >>Including: For each via, create a QSet. <QPair<int,int> An instance is used to store the planar layer pairs that intersect with the via; Traversing the original data structure QMap <QPair<int,int> QSet <via>> For each QPair<int,int> and the corresponding QSet <via> Add each via to the corresponding QSet of its intersecting planar layer pair. <QPair<int,int> >China;< / via> < / via> The new data structure QMap has been built. <Via,QSet<QPair<int,int> >> 7. The method according to claim 1 or 6, characterized in that, Based on the relationship between each Via and the plane, the holes divided by the plane are cut out as follows: Traversing the QMap data structure <Via,QSet<QPair<int,int> >> For each via, obtain its intersecting planar layer pairs; Determine the via segmentation position based on the intersecting planar layer pairs; Based on the determined segmentation position of the via, the holes are cut out by the plane.

8. A via partitioning system for a multilayer integrated circuit board, characterized in that, The system includes: The calculation module is used to calculate the connection relationships of all elements within a multilayer integrated circuit board. The connecting plane module is used to find the plane to which each hole is connected, either from top to bottom or bottom to top. The sorting module is used to sort the layers of the connected planes; The combination module is used to combine the data structure QMap of two plane-divided holes. <QPair<int,int> QSet <via> >；< / via> The conversion module is used to convert the data structure to QMap. <Via,QSet<QPair<int,int> >>, and you can get the relationship between each Via and the plane phase cutting; The cutting module is used to cut out holes divided by the plane based on the relationship between each Via and the plane.

9. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method for rapidly solving planar vias in a multilayer integrated circuit board according to any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute a method for rapidly solving planar vias in a multilayer integrated circuit board according to any one of claims 1-7.

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