Semiconductor device and manufacturing method therefor

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: multiple active regions disposed in a first region, each active region comprising a first connecting end and a second connecting end; multiple first capacitors disposed in the first region, each first capacitor comprising a first upper electrode and a first lower electrode, and the first lower electrode of each first capacitor being connected to a corresponding first connection end; multiple second capacitors disposed in a second region, each second capacitor comprising a second upper electrode and a second lower electrode; multiple first bonding pads disposed in the first region, at least one of the first bonding pads being connected to the second connection end of at least one of the active regions; and multiple second bonding pads disposed in the second region, at least one of the second bonding pads being connected to the second lower electrode of at least one of the second capacitors. The semiconductor device provided in the embodiments of the present disclosure has capacitors located in different regions, which can be used to implement different functions, thereby improving the level of integration of the semiconductor device.

Description

Semiconductor devices and their manufacturing methods

[0001] Cross-references

[0002] This application claims priority to Chinese Patent Application No. 202411605386.9, filed on November 11, 2024, entitled "Semiconductor Device and Method of Manufacturing Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] Transistors and capacitors are essential components of DRAM devices. In DRAM devices, transistors primarily function as switches, controlling the charging and discharging of capacitors, i.e., data writing and reading. A transistor generally comprises three key components: the source, drain, and gate. The source and drain are typically created by introducing dopants (such as arsenic or boron) through ion implantation to form n-type or p-type semiconductor regions. The implanted dopant atoms may initially be in an inactive state, meaning they do not effectively participate in the semiconductor's electrical conduction process. Activation of the source and drain regions requires a thermal treatment process, commonly known as activation annealing, with annealing temperatures typically exceeding 500°C.

[0005] HK material, used as the dielectric layer in capacitors, can significantly reduce the physical size of capacitors while maintaining or increasing their capacitance. Generally speaking, HK material crystallizes at around 500℃, leading to increased leakage current. In addition, since DRAM devices include multiple different regions with varying pattern compositions, these differences can cause localized thermal stress due to high temperatures, resulting in product defects and affecting production yield. Summary of the Invention

[0006] This disclosure provides embodiments of semiconductor devices with higher integration and methods for manufacturing the same.

[0007] The technical spirit of this disclosure aims to solve problems not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] Some embodiments of this disclosure provide a semiconductor device, including: a first region and a second region; a plurality of active regions, each active region being disposed in the first region, each active region including a first connection terminal and a second connection terminal; a plurality of first capacitors, each first capacitor being disposed in the first region, each first capacitor including a first upper electrode and a first lower electrode, the first lower electrode of each first capacitor being connected to each first connection terminal; a plurality of second capacitors, each second capacitor being disposed in the second region, each second capacitor including a second upper electrode and a second lower electrode; a plurality of first bonding pads, each first bonding pad being disposed in the first region, at least one first bonding pad being connected to a second connection terminal of at least one active region; and a plurality of second bonding pads, each second bonding pad being disposed in the second region, at least one second bonding pad being connected to a second lower electrode of at least one second capacitor.

[0009] In some embodiments, each first connection terminal of each active region is spaced apart from each other in a first direction and a second direction, each second connection terminal of each active region is isolated from each other in the first direction, and each second connection terminal of each active region is connected to each other in the second direction.

[0010] In some embodiments, the system further includes a first interconnect structure located in a first region and a second interconnect structure located in a second region. The first interconnect structure is disposed between each second connection terminal of each active region and each first bonding pad, connecting each second connection terminal to each first bonding pad. The second interconnect structure is disposed between each second lower electrode of each second capacitor and each second bonding pad, connecting each second lower electrode to each second bonding pad.

[0011] In some embodiments, the system further includes a first dielectric layer assembly located in a first region and a second dielectric layer assembly located in a second region. The first dielectric layer assembly includes a first isolation dielectric layer, and the second dielectric layer assembly includes a second isolation dielectric layer. The first isolation dielectric layer is disposed between each of the second connection terminals arranged in a first direction, and the second isolation dielectric layer is disposed between each of the second interconnect structures.

[0012] In some embodiments, the first dielectric layer assembly further includes a first insulating dielectric layer, and the second dielectric layer assembly further includes a second insulating dielectric layer. The first insulating dielectric layer is disposed between each of the first connection terminals, and the second insulating dielectric layer is disposed between each of the second lower electrodes of each of the second capacitors.

[0013] In some embodiments, the second region further includes a common connection terminal, to which the second lower electrode of each second capacitor is connected, and the common connection terminal is connected to at least one second bonding pad.

[0014] In some embodiments, a second interconnect structure located in the second region is further included, the second interconnect structure being disposed between a common connection end and a second bonding pad, connecting the common connection end and the second bonding pad.

[0015] Some embodiments of this disclosure also provide a method for manufacturing a semiconductor device, comprising: providing a substrate having a first region and a second region; patterning a portion of the substrate to form a plurality of active regions in the first region, each active region including a first connection terminal and a second connection terminal; forming a plurality of first capacitors and a plurality of second capacitors in the first region and the second region respectively, each first capacitor including a first upper electrode and a first lower electrode, the first lower electrode of each first capacitor being connected to each first connection terminal, and each second capacitor including a second upper electrode and a second lower electrode; removing an unpatterned portion of the substrate; forming a plurality of first bonding pads in the first region and a plurality of second bonding pads in the second region, wherein at least one first bonding pad is connected to a second connection terminal of at least one active region, and at least one second bonding pad is connected to a second lower electrode of at least one second capacitor.

[0016] In some embodiments, a plurality of active regions are formed in a first region, including: a patterned substrate, forming a plurality of active regions extending along a third direction in the first region, each active region including a first connection end and a second connection end disposed along the third direction, wherein each first connection end of each active region is spaced apart from each other in a first direction and a second direction, and each second connection end of each active region is connected to each other in the first direction and the second direction.

[0017] In some embodiments, when the patterned substrate forms each active region, a first groove is formed between each first connection end, and a second groove is formed between each second connection end in the second direction; when a portion of the substrate in the patterned first region forms each active region, a portion of the substrate in the second region is also patterned, and a third groove is formed in the substrate in the second region; a first insulating dielectric layer and a first isolation dielectric layer are formed in the first groove and the second groove, respectively, and a second isolation dielectric layer is formed in the third groove.

[0018] In some embodiments, after filling and forming a first insulating dielectric layer, a first isolation dielectric layer, and a second isolation dielectric layer, a second insulating dielectric layer is formed on the second isolation dielectric layer, and after forming the first insulating dielectric layer and the second insulating dielectric layer, a first capacitor and a second capacitor are formed.

[0019] In some embodiments, prior to forming the first capacitor and the second capacitor, a common connection terminal is formed in the second insulating dielectric layer, the common connection terminal being connected to the second lower electrode of at least one second capacitor.

[0020] In some embodiments, removing the unpatterned portion of the substrate includes: thinning the unpatterned portion of the substrate such that each second connection terminal of each active region is isolated from each other in a first direction, and each second connection terminal of each active region remains connected to each other in a second direction, while the surfaces of each second connection terminal, the first isolation dielectric layer, and the second isolation dielectric layer are exposed; after removing the unpatterned portion of the substrate, forming a first sacrificial layer on the exposed surfaces of each second connection terminal, the first isolation dielectric layer, and the second isolation dielectric layer; after forming the first sacrificial layer, performing a laser annealing process to activate each second connection terminal; after activating each second connection terminal, removing the first sacrificial layer, and forming a first bonding pad and a second bonding pad in the first region and the second region, respectively.

[0021] In some embodiments, before forming the first bonding pad and the second bonding pad, a first interconnect structure connected to each of the second connection ends and a second interconnect structure connected to each of the second lower electrodes are formed.

[0022] In some embodiments, the thickness of the first sacrificial layer is one-quarter of the wavelength of the laser used in the laser annealing process.

[0023] In some embodiments, an ion implantation process is performed on each of the exposed second connectors before the formation of the first sacrificial layer.

[0024] In some embodiments, a first capacitor is formed in a first region while a second capacitor is formed in a second region.

[0025] The semiconductor device provided in this embodiment has capacitors disposed on both the first and second regions. The capacitors corresponding to each region are connected to each bonding pad in different ways, thereby distributing the capacitors of each region to different functional areas to achieve different functions, further increasing the integration of the semiconductor device. At the same time, the semiconductor device provided in this embodiment has good process stability, stable performance, and higher production yield. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0027] Figure 1 is a planar schematic diagram of a semiconductor device provided in an embodiment of this disclosure.

[0028] Figures 2 and 3 are cross-sectional views of the semiconductor device provided in the embodiments of this disclosure.

[0029] Figure 4A is a planar schematic diagram of a semiconductor device provided in an embodiment of this disclosure.

[0030] Figures 4B and 4C are cross-sectional views taken from lines BB and CC in Figure 4A, respectively.

[0031] Figures 5 and 6 are cross-sectional views of the semiconductor device provided in the embodiments of this disclosure.

[0032] Figure 7 is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this disclosure.

[0033] Figures 8-11B are schematic cross-sectional views of the semiconductor devices corresponding to the respective steps in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0034] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0035] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant disclosure and not for limiting the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described.

[0036] Figure 1 shows a top view of a semiconductor device provided in some embodiments of the present disclosure. The semiconductor device includes a substrate 1 having a first region 10 and a second region 20. A memory cell, such as a memory cell consisting of a transistor and a capacitor, is formed in the first region 10. Non-memory cells, such as non-memory cells consisting only of a capacitor or having other functions, are formed in the second region 20. The second region 20 may surround the first region 10, or may be disposed on one or more sides of the first region 10. The positional relationship between the first region 10 and the second region 20 is not limited to the positions shown in Figure 1.

[0037] The substrate 1 may be or may include a wafer, comprising silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, or GaSb. In some example embodiments, the substrate 1 may be a silicon-on-insulator (SOI) wafer or a germanium-on-insulator (GOI) wafer, and may be doped or undoped. In some example embodiments, the substrate 1 may simultaneously comprise silicon, germanium, silicon-germanium, or III-V compound crystalline and non-semiconductor materials such as GaP, GaAs, or GaSb, for example, an insulating dielectric layer and a metal wiring layer. In some embodiments, the substrate 1 may simply be the portion carrying a semiconductor device, and its material is not particularly limited.

[0038] Referring again to Figure 2, which is a cross-sectional view of a semiconductor device provided in some embodiments of this disclosure. Specifically, Figure 2 is a cross-sectional view taken along line AA in Figure 1. A first region 10 is provided with a plurality of active regions 111, each active region 111 extending along a third direction Z and spaced apart along a first direction X. The third direction Z can be perpendicular to the substrate 1, and the first direction X can be parallel to the substrate 1. An angle exists between the first direction X and the third direction Z, for example, the angle between the first direction X and the third direction Z is 90°. Each active region 111 includes a first connection end 101 and a second connection end 102, which can be portions of the ends of each active region 111. The active region 111 can be the actual operating area of ​​an active device such as a transistor or diode, i.e., the area in the device involved in the transport and control of charge carriers (electrons and holes). The active region 111 typically includes a source, a drain, and a channel region. These regions are doped to form specific electrical characteristics, enabling the transistor to control the flow of current. In some embodiments of this disclosure, the first connection terminal 101 of each active region 111 can be a source, and the second connection terminal 102 of each active region 111 can be a drain.

[0039] Referring again to Figure 2, a plurality of first capacitors 100 are disposed in the first region 10 of the semiconductor device. Each first capacitor 100 includes a first upper electrode 103, a first lower electrode 104, and a first dielectric layer 105 disposed between the first upper electrode 103 and the first lower electrode 104. In some embodiments, each first capacitor 100 may be a capacitor of a DRAM memory cell. In this case, the first upper electrodes 103 of each first capacitor 100 are connected to each other, the first dielectric layers 105 of each first capacitor 100 are connected to each other, the first lower electrodes 104 of each first capacitor 100 are isolated from each other, and the first lower electrodes 104 of each first capacitor 100 are correspondingly connected to the first connection terminals 101 of each active region 111. The first dielectric layer 105 is disposed around the outer peripheral surface of each first lower electrode 104, and the first upper electrode 103 is disposed around the outer peripheral surface of each first dielectric layer 105. The first capacitor 100 shown in Figure 2 is a pillar capacitor, but the first capacitor 100 may also be other types of capacitors.

[0040] In some embodiments, the first upper electrode 103 is disposed above the first dielectric layer 105 and is made of a conductive material, which may be polysilicon, a metal, or a composite layer of polysilicon and metal. The metal may be, for example, tungsten or other metal materials suitable for DRAM upper electrodes. The first lower electrode 104 is typically made of a conductive material, such as doped polysilicon or a metal material. The first dielectric layer 105 may be an HK (high dielectric constant) material, such as hafnium oxide (HfO2) or hafnium silicate (HfSiO2). x ( ), to increase the capacitance value.

[0041] Referring again to Figure 2, a plurality of second capacitors 200 are disposed in the second region 20 of the semiconductor device. Each second capacitor 200 includes a second upper electrode 201, a second lower electrode 202, and a second dielectric layer 203 disposed between the second upper electrode 201 and the second lower electrode 202. In some embodiments, each second capacitor 200 may be a capacitor of the same type as each first capacitor 100. In this case, the second upper electrodes 201 of each second capacitor 200 are connected to each other, the second dielectric layers 203 of each second capacitor 200 are connected to each other, the second lower electrodes 202 of each second capacitor 200 are isolated from each other, the second dielectric layer 203 is disposed around the outer peripheral surface of each second lower electrode 202, and the second upper electrode 201 is disposed around the outer periphery of the second dielectric layer 203. In some embodiments, each second upper electrode 201 adopts the same composition as each first upper electrode 103, each second lower electrode 202 adopts the same composition as each first lower electrode 104, and the second dielectric layer 203 adopts the same composition as the first dielectric layer 105.

[0042] Referring again to Figure 2, a plurality of first bonding pads 112 are disposed in the first region 10 of the semiconductor device, and a plurality of second bonding pads 210 are disposed in the second region 20 of the semiconductor device. The first bonding pads 112 and the second bonding pads 210 can be conductive pads formed of metal or other conductive materials. The first bonding pads 112 and the second bonding pads 210 can be disposed on the surface of the semiconductor device for connection with other semiconductor devices. For example, the first bonding pads 112 and the second bonding pads 210 are both conductive pads for direct bonding, such as copper pads. A material layer for direct bonding is also disposed between the first bonding pads 112 and the second bonding pads 210. This layer not only provides mutual isolation between the first bonding pads 112 and the second bonding pads 210, but also increases the bonding strength between the first bonding pads 112 and the second bonding pads 210, together forming a hybrid bonding interface.

[0043] In some embodiments, at least one first bonding pad 112 is electrically connected to at least one second connection terminal 102, and at least one second bonding pad 210 is electrically connected to at least one second lower electrode 202. In some embodiments, a portion of the first bonding pad 112 and a portion of the second bonding pad 210 may be dummy connection pads that are not electrically connected to any structure in the semiconductor device. In some embodiments, all of the first bonding pads 112 and all of the second bonding pads 210 may be active connection pads that are electrically connected to structures in the semiconductor device.

[0044] Referring again to Figure 2, in some embodiments, a first interconnect structure 113 and a second interconnect structure 211 are respectively disposed in the first region 10 and the second region 20 of the semiconductor device. The first interconnect structure 113 is disposed between each second connection terminal 102 of each active region 111 and each first bonding pad 112, for connecting the second connection terminal 102 and the first bonding pad 112, thereby enabling communication between the second connection terminal 102 and the first bonding pad 112 of the active region 111. The second interconnect structure 211 is disposed between each second lower electrode 202 of each second capacitor 200 and each second bonding pad 210, for connecting each second lower electrode 202 of each second capacitor 200 and each second bonding pad 210.

[0045] In some embodiments, the first interconnect structure 113 may be an interconnect structure composed of multiple layers of metal wiring, such as an interconnect structure composed of two or more layers of tungsten metal. The second interconnect structure 211 may be an interconnect structure composed of one or more layers of metal wiring, such as an interconnect structure formed of one layer of tungsten metal.

[0046] In some embodiments, the first capacitor 100 and the second capacitor 200 are capacitors that perform different functions. The first capacitor 100 is used for charge storage and is connected to the corresponding read / write circuit via the first bonding pad 112, thereby using the first capacitor 100 to read or write data. The second capacitor 200 may be a capacitor used to stabilize the power supply voltage and reduce signal noise, such as a decoupling capacitor. It is connected to the corresponding functional circuit via the second bonding pad 210 and can reduce noise, such as high-frequency noise, in the internal power supply voltage supplied to the address decoder.

[0047] In some embodiments, a portion of the first bonding pad 112 may also be connected to the first upper electrode 103 of each first capacitor 100, and a portion of the second bonding pad 210 may also be connected to the second upper electrode 201 of each second capacitor 200, respectively for connecting the first upper electrode 103 and the second upper electrode 201 to a specific signal circuit.

[0048] In some embodiments, as shown in FIG3, FIG3 is a cross-sectional view of a semiconductor device provided in some embodiments of the present disclosure. A common connection terminal 212 is also provided in the second region 20 of the semiconductor device. The common connection terminal 212 is disposed below each of the second capacitors 200 and is used to simultaneously connect multiple second lower electrodes 202, serving as the common lower electrode of the multiple second capacitors 200. At this time, a second interconnect structure 211 is disposed between the common connection terminal 212 and the second bonding pads 210, for connecting the common connection terminal 212 and each of the second bonding pads 210. In these embodiments, since the multiple second lower electrodes 203 are connected through the common connection terminal 212, the number of second interconnect structures 211 can be reduced, and some of the second bonding pads 210 can be virtual connection terminals not connected to the common connection terminal 212. In these embodiments, the lower electrodes of the multiple second capacitors 200 are connected through the common connection terminal 212, thereby obtaining a larger capacitance.

[0049] In some embodiments, the first connection terminals 101 of each active region 111 in the first region 10 are arranged at intervals, as shown in Figures 4A to 4C. Figure 4A is a planar schematic diagram of the distribution of each active region 111, Figure 4B is a cross-sectional view taken along line BB in Figure 4A, and Figure 4C is a cross-sectional view taken along line CC in Figure 4A. As shown in Figures 4A to 4C, the first connection terminals 101 of each active region 111 are arranged at intervals in the first direction X and the second direction Y. Each first connection terminal 101 may be cylindrical or of other shapes. The second connection terminals 102 of each active region 111 are isolated from each other in the first direction X and connected to each other in the second direction Y. In some embodiments, the semiconductor device further includes a gate structure 125 disposed in each active region 111. The gate structure 125 surrounds the active region between the first connection terminal 101 and the second connection terminal 102 for controlling the switching on and off of the first connection terminal 101 and the second connection terminal 102. In the first direction X, the gate structures 125 are interconnected, and in the second direction Y, the gate structures 125 are isolated from each other. Each gate structure 125 may include a gate dielectric layer 1250 and a gate conductive layer 1251. The gate dielectric layer 1250 may be disposed between the gate conductive layer 1251 and each active region 111. The second direction Y may be parallel to the substrate 1, and there is an angle between the second direction Y and the first direction X, for example, a 90° angle.

[0050] Please continue with Figures 4A-4C and 5. Figure 5 is a cross-sectional view of a semiconductor device. The semiconductor device further includes a first dielectric layer assembly 120 disposed in a first region 10 and a second dielectric layer assembly 220 located in a second region 20. The first dielectric layer assembly 120 includes a first isolation dielectric layer 122 disposed between each of the second connection terminals 102 arranged along a first direction X, for isolating each of the second connection terminals 102. The second isolation dielectric layer 222 is disposed between each of the second interconnect structures 211, for isolating each of the second interconnect structures 211. The first isolation dielectric layer 122 and the second isolation dielectric layer 222 can be a single-layer structure or a multi-layer composite structure. The materials of the first isolation dielectric layer 122 and the second isolation dielectric layer 222 may be the same or different. For example, in some embodiments, the first isolation dielectric layer 122 and the second isolation dielectric layer 222 are both silicon nitride, silicon oxide, or LK (low dielectric constant) dielectric materials; in some embodiments, the first isolation dielectric layer 122 is silicon oxide or silicon nitride, and the second isolation dielectric layer 222 is silicon nitride or silicon oxide.

[0051] Referring again to Figure 5, the first dielectric layer assembly 120 further includes a first insulating dielectric layer 121, which is disposed between each of the first connection terminals 101 to isolate each of the first connection terminals 101. The second dielectric layer assembly 220 further includes a second insulating dielectric layer 221, which is disposed between each of the second lower electrodes 202 to isolate each of the second lower electrodes 202. The first insulating dielectric layer 121 and the second insulating dielectric layer 221 can be a single-layer structure or a multi-layer composite structure. The materials of the first insulating dielectric layer 121 and the second insulating dielectric layer 221 may be the same or different. For example, in some embodiments, the first insulating dielectric layer 121 and the second insulating dielectric layer 221 are both silicon nitride, silicon oxide, or LK dielectric materials; in some embodiments, the first insulating dielectric layer 121 is silicon oxide and the second insulating dielectric layer 221 is silicon nitride.

[0052] In some embodiments, the materials of the first insulating dielectric layer 122 and the first insulating dielectric layer 121 may be the same or different. In some embodiments, the first insulating dielectric layer 122 and the first insulating dielectric layer 121 are silicon oxide and silicon nitride, respectively; in some embodiments, the first insulating dielectric layer 122 and the first insulating dielectric layer 121 are both silicon nitride or silicon oxide. The materials of the second insulating dielectric layer 222 and the second insulating dielectric layer 221 may be the same or different. In some embodiments, the second insulating dielectric layer 222 and the second insulating dielectric layer 221 are silicon oxide and silicon nitride, respectively; in some embodiments, the second insulating dielectric layer 222 and the second insulating dielectric layer 221 are both silicon nitride or silicon oxide.

[0053] Referring again to Figures 3 and 6, Figure 6 is a cross-sectional view of the semiconductor device. When the second lower electrodes 202 of each second capacitor 200 are connected to each other through a common connection terminal 212, the first dielectric layer assembly 120 and the second dielectric layer assembly 220 are respectively disposed in the first region 10 and the second region 20. The first dielectric layer assembly 120 includes a first isolation dielectric layer 122 and a first insulating dielectric layer 121. The second dielectric layer assembly 220 includes a second isolation dielectric layer 222 and a second insulating dielectric layer 221. The first isolation dielectric layer 122 is disposed between each of the second connection terminals 102 arranged along the first direction X, for isolating each of the second connection terminals 102 in the first direction X. The first insulating dielectric layer 121 is disposed between each of the first connection terminals 101, for isolating each of the first connection terminals 101. The second isolation dielectric layer 222 is disposed between each of the second interconnect structures 211, for isolating each of the second interconnect structures 211. The second insulating dielectric layer 221 is disposed between each of the second lower electrodes 202, for isolating each of the second lower electrodes 202. In these embodiments, the materials of the first isolation dielectric layer 122, the first insulating dielectric layer 121, the second isolation dielectric layer 222, and the second insulating dielectric layer 221 may be the same or different. For example, the first isolation dielectric layer 122 and the second isolation dielectric layer 222 may both be silicon oxide, and the first insulating dielectric layer 121 and the second insulating dielectric layer 221 may both be silicon nitride.

[0054] Referring again to Figure 5, in some embodiments, the first dielectric layer assembly 120 further includes a first isolation layer 123. The first isolation layer 123 may be disposed on the first insulating dielectric layer 121 and between each of the first lower electrodes 104 to isolate each of the first lower electrodes 104. In some embodiments, the first isolation layer 123 and the first insulating dielectric layer 121 may be made of the same or different materials. For example, the first isolation layer 123 and the first insulating dielectric layer 121 may be either silicon oxide or silicon nitride. When the first isolation layer 123 and the first insulating dielectric layer 121 are made of the same material, there may be no clear boundary between the first isolation layer 123 and the first insulating dielectric layer 121.

[0055] Referring again to Figures 3 and 6, in some embodiments, the second dielectric layer assembly 220 further includes a second isolation layer 223 disposed between the second isolation dielectric layer 222 and the second insulating dielectric layer 221. The second isolation layer 223 is also disposed between adjacent common connection terminals 212 for isolating the common connection terminals 212. In some embodiments, the second isolation layer 223 and the second insulating dielectric layer 221 may be made of the same or different materials; for example, the second isolation layer 223 and the second insulating dielectric layer 221 may be either silicon oxide or silicon nitride, respectively. When the second isolation layer 223 and the second insulating dielectric layer 221 are made of the same material, there may be no clear boundary between them. In some embodiments, both the second isolation layer 223 and the second insulating dielectric layer 221 are silicon nitride, and the second isolation dielectric layer 222 is silicon oxide.

[0056] Referring again to Figures 5 and 6, in some embodiments, the first region 10 of the semiconductor device further includes an insulating dielectric layer 114 and an insulating dielectric layer 224 located in the second region 20. The insulating dielectric layer 114 is disposed between each of the first interconnect structures 113, isolating each of the first interconnect structures 113; the insulating dielectric layer 224 is disposed between each of the second interconnect structures 211, isolating each of the second interconnect structures 211. In some embodiments, the insulating dielectric layer 114 and the insulating dielectric layer 224 can be a single-layer structure or a multilayer composite structure, for example, they can be one or more combinations of silicon nitride, silicon oxide, or LK dielectric materials.

[0057] Referring again to Figure 4C, the semiconductor device further includes an isolation dielectric layer 124 disposed between each of the second connection terminals 102 in the second direction Y. The isolation dielectric layer 124 can be a single-layer or multi-layer composite structure. The material of the isolation dielectric layer 124 can be the same as, partially the same as, or different from the materials of the first isolation dielectric layer 122 and the first insulating dielectric layer 121. For example, the isolation dielectric layer 124 can be a composite structure composed of silicon oxide and silicon nitride, with the first isolation dielectric layer 122 being silicon oxide and the first insulating dielectric layer 121 being silicon nitride. In other embodiments, the isolation dielectric layer 124, the first isolation dielectric layer 122, and the first insulating dielectric layer 121 can also be other types of dielectric materials, which will not be elaborated here.

[0058] The semiconductor device provided in this embodiment has capacitors disposed on both the first and second regions. The capacitors corresponding to each region are connected to each bonding pad in different ways, thereby distributing the capacitors of each region to different functional areas to achieve different functions, further broadening the application value of the semiconductor device. At the same time, the semiconductor device provided in this embodiment has good process stability, stable performance, and higher production yield.

[0059] The embodiments of this disclosure also provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device provided by the embodiments of this disclosure will now be described in detail with reference to the corresponding steps and accompanying drawings.

[0060] As shown in Figure 7, which is a schematic flowchart of a manufacturing method for semiconductor devices according to some embodiments of the present disclosure, specifically including:

[0061] S101, a substrate is provided, the substrate having a first region and a second region. Referring to Figure 8, Figure 8 is a schematic cross-sectional view of the semiconductor device structure corresponding to step S101. A substrate 11 is provided, the substrate 11 having a first region 10 and a second region 20. The substrate 10 may be or may include a wafer, which includes silicon, germanium, silicon-germanium, or III-V compounds such as GaP, GaAs, or GaSb. In some example embodiments, the substrate 11 may be a silicon-on-insulator (SOI) wafer or a germanium-on-insulator (GOI) wafer, and may be doped or undoped. In some example embodiments, the substrate 11 may simultaneously include silicon, germanium, silicon-germanium, or III-V compound crystalline and non-semiconductor materials such as GaP, GaAs, or GaSb. The first region 10 may be the region subsequently used to form memory cells, such as memory cells consisting of transistors and capacitors, and the second region 20 may be the region subsequently used to form non-memory cells, such as non-memory cells consisting only of capacitors or having other functions. The second region 20 may be disposed around the first region 10, or may be disposed on one or more sides of the first region 10.

[0062] In step S102, a portion of the substrate is patterned to form multiple active regions in a first region. Each active region includes a first connection terminal and a second connection terminal. See Figures 9A to 9D for details; Figures 9A to 9D are schematic cross-sectional views of the semiconductor device structure corresponding to step S102. A first region 10 of the patterned substrate 11 is partially removed, thereby forming multiple active regions 111 in the first region 10. Each active region 111 has a first connection terminal 101 and a second connection terminal 102. Each active region 111 extends in the third direction Z. The first connection terminals 101 of each active region 111 are spaced apart from each other in the first direction X and the second direction Y. The second connection terminals 102 of each active region 111 are also spaced apart from each other in the first direction X. Referring again to Figures 9A and 9B, when the active region 111 is formed on the patterned substrate 11, a first groove 1210 is formed between each first connection end 101 in the first direction X and the second direction Y, and a second groove 1220 is formed between each second connection end 102 in the first direction C and the second direction Y. When the active regions 111 are formed on the substrate 11 of the patterned first region 10, the substrate 11 of the second region 20 is also patterned, and a third groove 2220 is formed in the substrate 11 of the second region 20.

[0063] In some embodiments, the depth of the third groove 2220 in the first direction X in the third direction Z is less than the depth of the third groove 2220 in the second direction Y.

[0064] Referring again to Figures 9C to 9D, after forming the first groove 1210, the second groove 1220, and the third groove 2220, the first groove 1210 is filled to form a first insulating dielectric layer 121, which is used to isolate each of the first connection ends 101 from each other. The second groove 1220 is filled to form a first insulating dielectric layer 122 in the first direction X and an insulating dielectric layer 124 in the second direction Y. The first insulating dielectric layer 122 and the insulating dielectric layer 124 can be composed of the same or different materials. The first insulating dielectric layer 122 and the insulating dielectric layer 124 can be formed in the same thin film deposition process or in steps, which is not limited in this disclosure. The third groove 2220 is filled to form a second insulating dielectric layer 222. The formation of the first insulating dielectric layer 122, the first insulating dielectric layer 121, the insulating dielectric layer 124, and the second insulating dielectric layer 222 can be obtained by thin film deposition process. The materials of each film layer can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0065] The process of patterning the substrate 11 can be achieved by combining photolithography, etching, mask deposition and other processes.

[0066] In step S103, multiple first capacitors and multiple second capacitors are formed in the first region and the second region, respectively. Each first capacitor includes a first upper electrode and a first lower electrode, and the first lower electrode of each first capacitor is connected to a first connection terminal. Each second capacitor includes a second upper electrode and a second lower electrode. The process of forming each first capacitor and second capacitor can be seen in Figures 10A to 10C, which are schematic cross-sectional views of the semiconductor device structure corresponding to step S103. It should be noted that after forming each active region 111, a gate structure 125 is formed around the active region 111 between the first connection terminal 101 and the second connection terminal 102 of each active region 111. In the first direction X, each gate structure 125 is connected to each other. In the second direction Y, each gate structure 125 is isolated from each other. The gate structure 125 can be formed before forming the first insulating dielectric layer 121, the first insulating dielectric layer 122, the insulating dielectric layer 124, and the second insulating dielectric layer 222. The specific formation process of the gate structure 125 will not be described here.

[0067] As shown in Figure 10A, after forming each active region 111, a first isolation layer 123 is deposited on the surface of the first region 10. The surfaces of the first connection ends 101 of each active region 111 and the surface of the first insulating dielectric layer 121 are both covered by the first isolation layer 123. A second insulating dielectric layer 221 is formed in the second region 20 and covers the surface of the second isolation dielectric layer 222. In some embodiments, the first isolation layer 123 and the second insulating dielectric layer 221 are formed in the same deposition process. After forming the first isolation layer 123 and the second insulating dielectric layer 221, a mask layer 106 is deposited in the first region 10 and the second region 20. The mask layer 106 can be a single-layer structure or a multi-layer composite structure. The mask layer 106 can be used as an intermediate film layer for forming patterns, for example, it can be a silicon oxide or silicon nitride film layer or a composite film layer of both. After the mask layer 106 is formed, a patterning process is performed, using photolithography, etching, and other processes to form a first capacitor hole 1040 in the mask layer 106 of the first region 10 and a second capacitor hole 2020 in the mask layer 106 of the second region 20. The first capacitor hole 1040 and the second capacitor hole 2020 are also formed in the first isolation layer 123 and the second insulating dielectric layer 221, respectively.

[0068] Referring again to Figure 10B, after forming the first capacitor hole 1040 and the second capacitor hole 2020, lower electrode material is filled into the first capacitor hole 1040 and the second capacitor hole 2020 to form the first lower electrode 104 and the second lower electrode 202, respectively. After forming the first lower electrode 104 and the second lower electrode 202, the mask layer 106 is removed. Filling the lower electrode material can be achieved using a thin film deposition process.

[0069] Referring again to Figure 10C, after forming the first lower electrode 104 and the second lower electrode 202, dielectric layers are deposited on the outer peripheral surfaces of the first lower electrode 104 and the second lower electrode 202 to form the first dielectric layer 105 and the second dielectric layer 203, respectively. After forming the first dielectric layer 105 and the second dielectric layer 203, upper electrode material is deposited on the outer peripheral surfaces of the first dielectric layer 105 and the second dielectric layer 203 to form the first upper electrode 103 and the second upper electrode 201, respectively. The first capacitor 100 and the second capacitor 200 are thus formed.

[0070] In some embodiments, the first capacitor 100 and the second capacitor 200 are formed simultaneously, and the first capacitor 100 and the second capacitor are formed using the same process steps.

[0071] Step S104 is performed to remove the unpatterned portion of the substrate. Referring again to Figures 10D and 10E, which are schematic cross-sectional views of the semiconductor device structure corresponding to step S104. After forming the first capacitor 100 and the second capacitor 200, as shown in Figure 10D, the semiconductor device shown in Figure 10C is flipped to expose the substrate 11. The exposed substrate 11 is then removed, causing the second connection terminals 102 connected to each other in the first direction X to be disconnected. That is, in the first direction X, each second connection terminal 102 is isolated from each other by the first isolation dielectric layer 122. A portion of the substrate on the second connection terminals 102 connected to each other in the second direction Y is retained, thus keeping the second connection terminals 102 in the second direction Y interconnected. Simultaneously, the substrate 11 in the second region 20 is also removed.

[0072] In some embodiments, the unpatterned portion of the substrate is removed using a thinning process. Specifically, the substrate 11 can be removed using processes such as chemical mechanical polishing (CMP), wet etching, or dry etching.

[0073] After the unpatterned portion of the substrate is removed, the surfaces of each second connection terminal 102, the first isolation dielectric layer 122, and the second isolation dielectric layer 222 are exposed in the first direction X, and the surface of the second isolation dielectric layer 222 and the surfaces connected to each second connection terminal 102 are exposed in the second direction Y.

[0074] Referring again to Figures 10F to 10G, in some embodiments, after removing the unpatterned portion of the substrate, an ion implantation process is performed on the surface of the exposed second connection terminal 102. Figures 10F to 10G are schematic cross-sectional views of the semiconductor device in the first direction X and the second direction Y, respectively, during the ion implantation process. In some embodiments, the ion implantation process can be a source / drain ion implantation process. This process introduces dopants (such as arsenic or boron) into specific regions of each active region 111, such as the first connection terminal 101 and the second connection terminal 102, to form n-type or p-type semiconductor regions, which will serve as the source and drain of transistors. In some embodiments, the ion implantation energy ranges from 1 keV to 30 keV, and the ion dose ranges from 1E14 to 1E16.

[0075] In some embodiments, continuing to refer to Figures 10H to 10I, after removing the unpatterned portion of the substrate, a first sacrificial layer 130 is formed on the exposed surfaces of each of the second connection terminals 102, the first isolation dielectric layer 122, and the second isolation dielectric layer 222. The first sacrificial layer 130 can be formed using a thin-film deposition process, such as CVD, where the thin-film deposition temperature is less than 500°C. The material of the first sacrificial layer 130 may differ from that of the first isolation dielectric layer 122 and the second isolation dielectric layer 222. In some embodiments, the first sacrificial layer 130 may be silicon nitride, and the first isolation dielectric layer 122 and the second isolation dielectric layer 222 may be silicon oxide. In some embodiments, the first sacrificial layer 130 may also be other materials with high wavelength absorption rates that allow the phase difference of reflected light at the interfaces between the first sacrificial layer 130 and the first isolation dielectric layer 122, and between the first sacrificial layer 130 and the second isolation dielectric layer 222, to cancel each other out.

[0076] In some embodiments, after the formation of the first sacrificial layer 130, a laser annealing process is performed to activate the ions implanted in each of the second connection terminals 102, thereby activating each of the second connection terminals 102. In some embodiments, the laser annealing process employs an ultrashort pulse or other short-wavelength ultrafast thermal annealing process to ensure that the HK material in the first dielectric layer 105 and the second dielectric layer 203 of the first capacitor 100 and the second capacitor 200 is not crystallized. This includes, but is not limited to, single or multiple activation ultrashort pulse lasers, with pulsed laser energy density (ED) provided by a laser. Multiple lasers can adjust the delay time between pulses or lasers to allow heat to diffuse to the desired depth, causing the amorphous silicon in the channel to fully melt and eliminate voids. The energy density of the ultrashort pulse laser is 0.01–4 J / cm². 2 The pulse duration is 10ns to 1ms, the delay time can be 1ns to 1000ns, and the wavelength can be selected from 193nm to 980nm, such as 532nm. The crystal used in the laser includes, but is not limited to, yttrium aluminum garnet (YAG) lasers.

[0077] In some embodiments, the thickness of the first sacrificial layer 130 can be one-quarter of the wavelength of the laser used in the laser annealing process. In some embodiments, by using a first sacrificial layer 130 of a specific thickness, the transmittance of the laser entering the second connection terminal 102 can be improved. For example, taking silicon nitride (SiN) as the first sacrificial layer 130 and the laser wavelength as 527nm, when the first sacrificial layer 130 is not formed on the surface of the second connection terminal 102, the transmittance of the laser entering the second connection terminal 102 is 0.63. When the first sacrificial layer 130 is formed on the surface of the second connection terminal 102, the transmittance of the laser entering the second connection terminal 102 is 0.9 or more. Compared with the absence of the first sacrificial layer 130, the transmittance increases by 46%, and the laser absorption rate increases. Meanwhile, in the second region 20, for the second upper electrode 201 of the second region 20, the laser needs to pass through the second isolation dielectric layer 222 and the second insulating dielectric layer 221 to enter the second upper electrode 201. If the first sacrificial layer 130 is not formed, the laser will enter the second upper electrode 201 with a transmittance of more than 0.8. After the first sacrificial layer 130 is formed, the transmittance of the laser to the second upper electrode 201 will drop to below 0.5. Therefore, for each second connection terminal 102 in the first region 10, by adding the first sacrificial layer 30, the laser energy entering the second connection terminal 102 can be increased, thereby allowing the use of a lower energy laser, reducing costs, and ensuring the full activation of the second connection terminal 102. For each second upper electrode 201 in the second region 20, the reduced laser energy absorption can reduce the damage of laser energy to the second upper electrode 201, thereby effectively preventing defects such as peeling and detachment of the second upper electrode.

[0078] In some embodiments, the first sacrificial layer 130 is formed after the ion implantation process.

[0079] In some embodiments, after performing the laser annealing process, the first sacrificial layer 130 is removed by dry etching or wet etching.

[0080] Referring again to Figures 10J to 10K, after removing the first sacrificial layer 130, a first interconnect structure 113 and a second interconnect structure 211 are formed in the first region 10 and the second region 20, respectively. Figures 10J to 10K are schematic cross-sectional views of the semiconductor device in the first direction X and the second direction Y when the first interconnect structure 113 and the second interconnect structure 211 are formed.

[0081] When forming the first interconnect structure 113 and the second interconnect structure 211, insulating dielectric layers 114 and 224 are formed simultaneously to achieve isolation between the interconnect structures. In some embodiments, the first interconnect structure 113 may be a multilayer metal interconnect formed in the insulating dielectric layer 114, connected at least to each of the second connection terminals 102. The second interconnect structure 211 may be a single-layer metal interconnect formed in the insulating dielectric layer 224 and the second insulating dielectric layer 222, connected at least to each of the second lower electrodes 202.

[0082] In step S105, a plurality of first bonding pads and second bonding pads are formed in the first region and the second region. At least one first bonding pad is connected to a second connection terminal of at least one active region, and at least one second bonding pad is connected to the second lower electrode of at least one second capacitor. In some embodiments, the first bonding pads and second bonding pads are formed after the formation of the first interconnect structure and the second interconnect structure. In some embodiments, both the first bonding pad 112 and the second bonding pad 210 are metal pads for direct bonding. The process for forming the first bonding pad 112 and the second bonding pad 210 adopts the process for forming direct bonding metal pads. The final structure is not described in detail here; see Figures 2, 3, 5, and 6.

[0083] In some embodiments, a common connection terminal is first formed in the second insulating dielectric layer before forming the first capacitor and the second capacitor. As shown in Figures 11A and 11B, these figures are schematic cross-sectional views of the semiconductor device in the first direction X and the second direction Y, respectively, when the common connection terminal is formed. Before forming the first isolation layer 123 and the second insulating dielectric layer 221, the second isolation layer 223 is first formed on the surface of the second isolation dielectric layer 222 in the second region 20. Then, a pattern for the common connection terminal 212 is formed in the second isolation layer 223 using a patterning process. The pattern for the common connection terminal 212 is then filled in to form the common connection terminal 212. After forming the common connection terminal 212, the aforementioned processes for forming the first capacitor and the second capacitor, as well as subsequent steps, are performed. For details, please refer to the foregoing description. The final structure is shown in Figures 3 and 6.

[0084] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, comprising: First region (10) and second region; Multiple active regions (111) are provided in the first region (10), and each active region (111) includes a first connection terminal (101) and a second connection terminal (102); A plurality of first capacitors (100) are disposed in the first region (10). Each first capacitor (100) includes a first upper electrode (103) and a first lower electrode (104). The first lower electrode (104) of each first capacitor (100) is connected to each first connection terminal (101). A plurality of second capacitors (200) are disposed in the second region (20), and each second capacitor (200) includes a second upper electrode (201) and a second lower electrode (202); Multiple first bonding pads (112) are disposed in the first region (10), and at least one first bonding pad (112) is connected to at least one second connection end (102) of the active region (111); Multiple second bonding pads (210) are disposed in the second region (20), and at least one second bonding pad (210) is connected to the second lower electrode (202) of at least one second capacitor (200).

2. The semiconductor device according to claim 1, characterized in that, Each of the first connection terminals (101) of each active region (111) is arranged at intervals from each other in a first direction (X) and a second direction (Y). Each of the second connection terminals (102) of each active region (111) is isolated from each other in the first direction (X). Each of the second connection terminals (102) of each active region (111) is connected to each other in the second direction (Y).

3. The semiconductor device according to claim 2, characterized in that, It also includes a first interconnect structure (113) located in the first region (10) and a second interconnect structure (211) located in the second region (20). The first interconnect structure (113) is disposed between each second connection terminal (102) of each active region (111) and each first bonding pad (112), connecting each second connection terminal (102) and each first bonding pad (112). The second interconnect structure (211) is disposed between each second lower electrode (202) of each second capacitor (200) and each second bonding pad (210), connecting each second lower electrode (202) and each second bonding pad (210).

4. The semiconductor device according to claim 3, characterized in that, It also includes a first dielectric layer assembly (120) located in the first region (10) and a second dielectric layer assembly (220) located in the second region (20). The first dielectric layer assembly (120) includes a first isolation dielectric layer (122), and the second dielectric layer assembly (220) includes a second isolation dielectric layer (222). The first isolation dielectric layer (122) is disposed between each of the second connection terminals (102) arranged in the first direction (X), and the second isolation dielectric layer (222) is disposed between each of the second interconnect structures (211).

5. The semiconductor device according to claim 4, characterized in that, The first dielectric layer assembly (120) further includes a first insulating dielectric layer (121), and the second dielectric layer assembly (220) further includes a second insulating dielectric layer (221). The first insulating dielectric layer (121) is disposed between each of the first connection terminals (101), and the second insulating dielectric layer (221) is disposed between each of the second lower electrodes (202) of each of the second capacitors (200).

6. The semiconductor device according to claim 1, characterized in that, The second region (20) also includes a common connection terminal (212), to which the second lower electrode (202) of each of the second capacitors (200) is connected, and the common connection terminal (212) is connected to at least one of the second bonding pads (210).

7. The semiconductor device according to claim 6, characterized in that, It also includes a second interconnect structure (211) located in the second region (20), the second interconnect structure (211) being disposed between the common connection end (212) and the second bonding pad (210), connecting the common connection end (212) and the second bonding pad (210).

8. A method for manufacturing a semiconductor device, comprising: A substrate (11) is provided, the substrate (11) having a first region (10) and a second region (20); The patterned portion of the substrate (11) forms a plurality of active regions (111) in the first region (10), each of the active regions (111) including a first connection terminal (101) and a second connection terminal (102); A plurality of first capacitors (100) and a plurality of second capacitors (200) are formed in the first region (10) and the second region (20), respectively. Each first capacitor (100) includes a first upper electrode (103) and a first lower electrode (104). The first lower electrode (104) of each first capacitor (100) is connected to each first connection terminal (101). Each second capacitor (200) includes a second upper electrode (201) and a second lower electrode (202). Remove the unpatterned portion of the substrate (11); A plurality of first bonding pads (112) are formed in the first region (10), and a plurality of second bonding pads (210) are formed in the second region (20), wherein at least one first bonding pad (112) is connected to at least one of the second connection terminals (102) of the active region (111), and at least one second bonding pad (210) is connected to at least one of the second lower electrodes (202) of the second capacitor (200).

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Multiple active regions (111) are formed in the first region (10), including: The substrate (11) is patterned, and a plurality of active regions (111) extending along a third direction (Z) are formed in the first region (10). Each active region (111) includes a first connection terminal (101) and a second connection terminal (102) disposed along the third direction (Z). The first connection terminals (101) of each active region (111) are spaced apart from each other in a first direction (X) and a second direction (Y). The second connection terminals (102) of each active region (111) are connected to each other in the first direction (X) and the second direction (Y).

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, When the substrate (11) is patterned to form each of the active regions (111), a first groove (1210) is formed between each of the first connection ends (101), and a second groove (1220) is formed between each of the second connection ends (102) in the second direction (Y); When the portion of the substrate (11) of the first region (10) is patterned to form each of the active regions (111), the portion of the substrate (11) of the second region (20) is also patterned, and a third groove (2220) is formed in the substrate (11) of the second region (20); A first insulating dielectric layer (121) and a first insulating dielectric layer (122) are formed in the first groove (1210) and the second groove (1220), respectively, and a second insulating dielectric layer (222) is formed in the third groove (2220).

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, After filling and forming the first insulating dielectric layer (121), the first isolation dielectric layer (122) and the second isolation dielectric layer (222), a second insulating dielectric layer (221) is formed on the second isolation dielectric layer (222). After forming the first insulating dielectric layer (121) and the second insulating dielectric layer (221), the first capacitor (100) and the second capacitor (200) are formed.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Before forming the first capacitor (100) and the second capacitor (200), a common connection terminal (212) is formed in the second insulating dielectric layer (221), the common connection terminal (212) being connected to the second lower electrode (202) of at least one of the second capacitors (200).

13. The method for manufacturing a semiconductor device according to claim 10, characterized in that, Removing the unpatterned portion of the substrate (11) includes: thinning the unpatterned portion of the substrate (11) such that each of the second connection terminals (102) of each of the active regions (111) is isolated from each other in the first direction (X), and each of the second connection terminals (102) of each of the active regions (111) remains connected to each other in the second direction (Y), while the surfaces of each of the second connection terminals (102), the first isolation dielectric layer (122), and the second isolation dielectric layer (222) are exposed; After removing the unpatterned portion of the substrate (11), a first sacrificial layer (130) is formed on the exposed surfaces of each of the second connection ends (102), the first isolation dielectric layer (122), and the second isolation dielectric layer (222); After the first sacrificial layer (130) is formed, a laser annealing process is performed to activate each of the second connection ends (102); After activating each of the second connection ends (102), the first sacrificial layer (130) is removed, and the first bonding pad (112) and the second bonding pad (210) are formed in the first region (10) and the second region (20), respectively.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, Before forming the first bonding pad (112) and the second bonding pad (210), a first interconnect structure (113) connected to each of the second connection ends (102) and a second interconnect structure (211) connected to each of the second lower electrodes (202) are formed.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The thickness of the first sacrificial layer (130) is one-quarter of the wavelength of the laser used in the laser annealing process.

16. The method for manufacturing a semiconductor device according to claim 13, characterized in that, Before the formation of the first sacrificial layer (130), an ion implantation process is performed on each of the exposed second connection ends (102).

17. The method for manufacturing a semiconductor device according to claim 8, characterized in that, While the first capacitor (100) is formed in the first region (10), the second capacitor (200) is formed in the second region (20).

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