Semiconductor device and manufacturing method therefor
By widening the trench gate and setting a buried layer at its bottom, the problem of poor high voltage resistance at the bottom and corners of the trench gate is solved, thereby improving the device's withstand voltage and reducing its on-resistance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- CHONGQING INNOEVSIC TECHNOLOGY CO LTD
- Filing Date
- 2025-11-04
- Publication Date
- 2026-05-15
AI Technical Summary
In vertical transistors with trench gates, the high voltage withstand capability at the bottom and corners of the trench gate is poor, affecting the overall voltage withstand capability of the device.
By widening the width of the trench grid and setting a narrower buried layer at its bottom, the voltage withstand capability of the trench grid is enhanced. Furthermore, buried layers are set on both sides of the trench grid to improve the electric field concentration problem and achieve electrical connection between the buried layer and the source region.
It improves the overall withstand voltage capability of the device, reduces the obstruction of carrier flow by the buried layer, reduces the on-resistance, and stabilizes the electric field shielding function.
Smart Images
Figure CN2025132313_15052026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their manufacturing methods Cross-reference to related applications
[0001] This application claims priority to Chinese Patent Application No. 202411595233.0, filed on November 8, 2024, entitled "Semiconductor Device and Method of Manufacturing Thereof", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates to the field of semiconductor device technology, and more specifically, to a semiconductor device having a trench gate structure and a method for manufacturing the same. Background Technology
[0003] In vertical transistors with trench gates, the drain of the transistor needs to be able to withstand high voltages. Because there is a PN junction between the drain and source, it has good voltage withstand capability.
[0004] However, the presence of the gate dielectric layer between the drain and the trench gate makes it difficult to withstand high voltages. This is especially true at the bottom and corners of the trench gate, where the high voltage withstand capability is poor, reducing the overall withstand voltage of the device. Therefore, device improvements are needed to address these issues. Summary of the Invention
[0005] In view of the above problems, the purpose of this disclosure is to provide a semiconductor device and a method for manufacturing the same, which reduces the obstruction of the buried layer to the flow of charge carriers by widening the width of the trench gate and providing a narrower buried layer at its bottom, and improves the overall withstand voltage capability of the device.
[0006] According to one aspect of the present disclosure, a semiconductor device is provided, including a semiconductor layer and a trench gate, the semiconductor layer having opposing first and second surfaces, and the trench gate being located in a trench on the first surface of the semiconductor layer.
[0007] The semiconductor layer includes:
[0008] The first buried layer is located at the bottom of the trench grid and is connected to the trench grid;
[0009] The body region is connected to the sidewall of the trench grid;
[0010] A source region, connected to the sidewall of the trench gate, extending from the first surface toward the body region and connected to the body region; and
[0011] The drift region, at least a portion of which is located between the body region and the second surface, and connected to the first buried layer and the body region.
[0012] The width of the trench grid is not less than the depth of the trench grid, and the width of the trench grid is greater than the width of the first buried layer.
[0013] Optionally, the source region and the drift region are of a first conductivity type, and the first buried layer and the body region are of a second conductivity type, wherein the first conductivity type is the opposite of the second conductivity type.
[0014] Optionally, the semiconductor layer further includes a second buried layer, which is separated from both the trench gate and the first buried layer, wherein the second buried layer has the same conductivity type as the first buried layer.
[0015] The body region is located between the second buried layer and the first surface, and is connected to the second buried layer; the drift region is connected to the second buried layer.
[0016] Optionally, the bottom of the first buried layer is flush with the bottom of the second buried layer.
[0017] Optionally, both the first buried layer and the second buried layer extend along the length direction of the trench grid.
[0018] Optionally, along the width direction of the trench grid, the body region, the source region, and the second buried layer are all located on both sides of the trench grid.
[0019] Optionally, the semiconductor layer further includes a third buried layer located between the first buried layer and the second buried layer, and connected to the first buried layer, the second buried layer and the body region, wherein the conductivity type of the third buried layer is the same as that of the first buried layer.
[0020] Optionally, a plurality of the third buried layers are spaced apart along the length direction of the trench grid.
[0021] Optionally, along the length direction of the trench grid, the interval between adjacent third buried layers is greater than the length of the third buried layer.
[0022] Optionally, the third buried layer is flush with the bottom of the first buried layer.
[0023] Optionally, a plurality of trench gates are arranged at intervals along the length direction of the trench gates.
[0024] Along the length of the trench gate, the body region and the source region are also located between adjacent trench gates.
[0025] Optionally, along the length of the trench grid, the spacing between adjacent trench grids corresponds to a portion of the third buried layer.
[0026] Optionally, the trench grid extends continuously along its length.
[0027] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising:
[0028] A first buried layer is formed in a semiconductor layer, the semiconductor layer having a first surface and a second surface opposite to each other, and the first buried layer being at a predetermined distance from the first surface;
[0029] A well region is formed in the semiconductor layer, the well region extending from the first surface toward the first buried layer and connected to the first buried layer;
[0030] A doped region is formed in the well region, the doped region extending from the first surface into the well region; and
[0031] A trench is formed extending from the first surface to the first buried layer, and a trench grid is formed in the trench.
[0032] The width of the trench grid is not less than the depth of the trench grid, and the width of the trench grid is greater than the width of the first buried layer.
[0033] Optionally, it also includes forming a second buried layer in the semiconductor layer.
[0034] The second buried layer is separated from the trench grid and the first buried layer, and the trap area is located between the second buried layer and the first surface and is connected to the second buried layer.
[0035] Optionally, it also includes forming a third buried layer in the semiconductor layer.
[0036] The third buried layer is located between the first buried layer and the second buried layer, and is connected to the first buried layer, the second buried layer and the well area.
[0037] Optionally, the first buried layer, the second buried layer, and the third buried layer are formed simultaneously using an ion implantation process.
[0038] One of the above technical solutions has the following beneficial effects:
[0039] By setting a first buried layer at the bottom of the trench gate, the withstand voltage capability at the bottom of the trench gate is increased. Furthermore, by setting the width of the trench gate to be no less than the depth of the trench gate, compared to the narrow trench scheme where the width of the trench gate is less than the depth, this scheme widens the width of the trench gate. This allows the first buried layer to only contact the bottom of the trench gate without covering the corners of the trench gate, greatly reducing the obstruction of the first buried layer to the flow of charge carriers and thus reducing the on-resistance of the device.
[0040] In some embodiments, by disposing both the body region and the source region on both sides of the trench gate and connecting them to the trench gate sidewalls, both sides of the trench gate can serve as conductive channels, thereby reducing the resistance of the device in the on state.
[0041] In some embodiments, by providing a second buried layer on both sides of the trench gate, the problem of electric field concentration at the corner of the trench gate is improved, and the withstand voltage capability at the corner of the trench gate is increased.
[0042] In some embodiments, by setting a third buried layer to achieve electrical connection between the first buried layer and the source region, the first buried layer will no longer be in a floating state, making the electric field shielding function of the first buried layer at the bottom of the trench gate more stable.
[0043] In some embodiments, a third buried layer is provided at intervals along the length of the trench gate. This can stabilize the electric field shielding function of the first buried layer on the bottom of the trench gate, and also utilize the interval area between adjacent third buried layers to arrange the current distribution between the source and drain.
[0044] In some embodiments, the first buried layer, the second buried layer, and the third buried layer are formed simultaneously in the semiconductor layer using an ion implantation process, which saves the number of photomasks, eliminates the need for additional alignment of the patterns of the first to third buried layers, reduces process complexity, and saves costs.
[0045] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description
[0046] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only involve some embodiments of this disclosure, and are not intended to limit this disclosure.
[0047] Figure 1 shows a top view of the semiconductor device according to the first embodiment of this disclosure.
[0048] Figure 2 shows a schematic diagram of the cross-sectional structure cut along line AA in Figure 1.
[0049] Figure 3 shows a schematic diagram of the cross-sectional structure cut along line BB in Figure 1.
[0050] Figure 4 shows a top view of the semiconductor device according to the second embodiment of this disclosure.
[0051] Figures 5 to 9 show three-dimensional structural schematic diagrams of a portion of the manufacturing process of a semiconductor device according to the first embodiment of this disclosure. Detailed Implementation
[0052] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.
[0053] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.
[0054] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".
[0055] Power devices typically include an active element region, an edge-terminating region, and a crack-stop or shielding region. The active element region includes an array of active elements. This disclosure relates to active element structures. The dimensions of the active elements may vary depending on product requirements, and there may be volume regions between active elements within the active element region.
[0056] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.
[0057] In vertical transistors, such as SiC MOSFETs, the ability to withstand high voltages applied to the drain is crucial. The PN junction between the drain and source provides good high-voltage withstand capability. However, the presence of the gate dielectric layer between the drain and the trench gate hinders high-voltage withstand. This is particularly true at the bottom and corners of the trench gate, where the gate dielectric layer's high-voltage withstand capability is poor, requiring separate shielding structures. To address these issues, this disclosure aims to provide a semiconductor device that, by widening the trench gate and creating a narrower buried layer at its bottom, improves the overall voltage withstand capability of the device while reducing the obstruction of carrier flow by the buried layer.
[0058] Figure 1 shows a top view of the semiconductor device according to the first embodiment of the present disclosure, Figure 2 shows a cross-sectional view along line AA in Figure 1, and Figure 3 shows a cross-sectional view along line BB in Figure 1. In Figure 1, only the buried layer and trench gate are shown, and other structures are omitted in order to more clearly express the positional relationship between the various structures.
[0059] As shown in Figures 1 to 3, the semiconductor device of the first embodiment of this disclosure includes a semiconductor layer, a plurality of trench gates 150, an interlayer dielectric layer 160, a first conductive layer 171, and a second conductive layer 172. The semiconductor layer has opposing first surfaces 101 and second surfaces 102, and a plurality of trenches extending from the first surface 101 toward the second surface 102 into the semiconductor layer. The plurality of trench gates 150 are located in corresponding trenches. The semiconductor layer may be, for example, a SiC, GaN, Ga2O3, or Al2O3 substrate, or a stacked structure consisting of a substrate and an epitaxial layer. However, the embodiments of this disclosure are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer as needed, such as other wide-bandgap semiconductor materials.
[0060] The semiconductor layer includes a drift region 110, a first buried layer 121, a second buried layer 122, a third buried layer 123, a body region 131, a source region 141, and a body contact region 142. The source region 141 and the drift region 110 are of a first conductivity type, while the first buried layer 121, the second buried layer 122, the third buried layer 123, the body region 131, and the body contact region 142 are of a second conductivity type. The doping concentration of the body contact region 142 is greater than that of the body region 131. The first conductivity type is the opposite of the second conductivity type. The first conductivity type is either P-type or N-type, and the second conductivity type is either P-type or N-type.
[0061] The semiconductor device in this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). For example, a drain contact region can be formed on the second surface 102 of the semiconductor layer, and the conductivity type of the drain contact region can be set to either a first conductivity type or a second conductivity type. However, this embodiment is not limited to this. Those skilled in the art can make other settings for the conductivity type of each region in the semiconductor layer as needed to make the semiconductor device a MOSFET or an IGBT.
[0062] The trench gate 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench, and the gate conductor 152 is located in the trench. The gate dielectric layer 151 is located between the semiconductor layer and the gate conductor 152, serving to separate the semiconductor layer from the gate conductor 152. The width direction of the trench gate 150 is the X-axis direction, the depth direction is the Z-axis direction, and the length direction is the Y-axis direction. Optionally, the X-axis, Y-axis, and Z-axis directions are mutually perpendicular.
[0063] The first buried layer 121 is located at the bottom of the trench grid 150. Along the X-axis, the second buried layer 122, the body region 131, the source region 141, and the body contact region 142 are all located on both sides of the trench grid 150.
[0064] The first buried layer 121 is connected to the trench grid 150, wherein the trench grid 150 has a wide trench structure, and the width of the trench grid 150 is not less than the depth of the trench grid 150. This allows the width of the first buried layer 121 to be less than the width of the trench grid 150 in the actual manufacturing process, ensuring that the first buried layer 121 is only located at the bottom of the trench grid 150 and does not cover the corners of the trench grid 150. In some specific embodiments, the depth of the trench grid 150 is less than the width of the trench grid 150, and the depth of the first buried layer 121 is greater than the depth of the trench grid 150.
[0065] The first buried layer 121 and the second buried layer 122 both extend along the Y-axis and are separated from each other. The second buried layer 122 is not connected to the trench grid 150. Along the X-axis, the third buried layer 123 is located between the first buried layer 121 and the second buried layer 122, and connects the first buried layer 121 and the second buried layer 122 respectively. Along the Y-axis, multiple third buried layers 123 are spaced apart. Optionally, the spacing Sp between adjacent third buried layers 123 is greater than the length Wp of the third buried layer 123. Optionally, the bottoms of the first buried layer 121, the second buried layer 122, and the third buried layer 123 are flush. Optionally, in the XY plane, the third buried layer 123 can extend along the X-axis or extend at a preset angle to the X-axis.
[0066] Along the X-axis, the body region 131 is connected to both sidewalls of the trench gate 150 and the second buried layer 122. The source region 141 extends from the first surface 101 of the semiconductor layer toward the body region 131 and is connected to the body region 131. The body contact region 142 extends from the first surface 101 of the semiconductor layer toward the body region 131 and is connected to the body region 131. Optionally, the source region 141 and the body contact region 142 can be connected or separated by the body region 131. At least a portion of the drift region 110 is located between the body region 131 and the second surface 102 of the semiconductor layer and is connected to the first buried layer 121, the second buried layer 122, the third buried layer 123, and the body region 131.
[0067] An interlayer dielectric layer 160 is located on the first surface 101 of the semiconductor layer and covers the trench gate 150. A first conductive layer 171 serves as the source and covers the first surface 101 of the semiconductor layer and the interlayer dielectric layer 160. A second conductive layer 172 serves as the drain and covers the second surface 102 of the semiconductor layer.
[0068] In this embodiment, multiple trench grids 150 are arranged at intervals along the Y-axis, and the body region 131 and the source region 141 are also located between adjacent trench grids 150 along the Y-axis. Optionally, the interval region between adjacent trench grids 150 corresponds to a portion of the third buried layer 123 along the Y-axis.
[0069] In this embodiment, when the device is turned on, the portion of the body region 131 adjacent to the sidewall of the trench gate 150 forms a channel through inversion. Charge carriers flow in from the source (first conductive layer 171), then flow through the source region 141 and the channel to the drift region 110, and finally flow out from the drain (second conductive layer 172), as shown by the dashed line in Figure 1.
[0070] By providing a first buried layer 121 at the bottom of the trench gate 150, the first buried layer 121 forms a PN junction with the drift region 110, thereby increasing the withstand voltage capability at the bottom of the trench gate 150. Furthermore, the trench gate 150 is configured as a wide trench structure with a width not less than its depth. Compared to a narrow trench scheme where the width of the trench gate is less than its depth, this embodiment widens the width of the trench gate 150, thereby enabling the first buried layer 121 to only contact the bottom of the trench gate 150 without covering the corners of the trench gate 150. This significantly reduces the obstruction of the first buried layer 121 to the flow of charge carriers, thereby reducing the on-resistance of the device.
[0071] Furthermore, by placing both the body region 131 and the source region 141 on both sides of the trench gate 150 and connecting them to the trench gate sidewall 150, both sides of the trench gate 150 can serve as conductive channels, thereby reducing the resistance of the device in the on state.
[0072] Furthermore, by providing a second buried layer 122 on both sides of the trench grid 150, the problem of electric field concentration at the corner of the trench grid 150 is improved, and the withstand voltage capability at the corner of the trench grid 150 is increased.
[0073] Furthermore, by setting a third buried layer 123 to achieve electrical connection between the first buried layer 121 and the source region 141, the first buried layer 141 will no longer be in a floating state, making the electric field shielding function of the first buried layer 121 at the bottom of the trench gate 150 more stable.
[0074] Furthermore, a third buried layer 123 is spaced along the Y-axis, which not only stabilizes the electric field shielding function of the first buried layer 121 on the bottom of the trench gate 150, but also allows for the layout of the current distribution between the source and drain using the spaced areas between adjacent third buried layers 123. Referring to Figures 1 and 2, the charge carriers flowing out from the conductive channels on both sides of the trench gate 150 diffuse evenly into the entire drift region 110 through the individual regions enclosed by the first buried layer 121, the second buried layer 122, and the third buried layer 123, thus exhibiting a low on-resistance.
[0075] Figure 4 shows a top view of the semiconductor device according to the second embodiment of this disclosure.
[0076] As shown in Figure 4, the similarities between the semiconductor device of the second embodiment and the first embodiment will not be repeated here, but can be found in the descriptions of Figures 1 to 3. The difference is that, in this embodiment, the trench gate 150 extends continuously along the Y-axis direction.
[0077] Figures 5 to 9 show three-dimensional structural schematic diagrams of a portion of the manufacturing process of a semiconductor device according to the first embodiment of this disclosure.
[0078] Referring to Figure 5, an epitaxial layer 104 is formed on a substrate 103 using an epitaxial process, wherein the epitaxial layer 104 and the substrate 103 constitute a semiconductor layer 100.
[0079] Furthermore, a first buried layer 121, a second buried layer 122, and a third buried layer 123 are simultaneously formed in the epitaxial layer 104 using a high-energy ion implantation process, as shown in Figure 6. The first buried layer 121, the second buried layer 122, and the third buried layer 123 are at a predetermined distance from the first surface of the semiconductor layer 100.
[0080] By employing an ion implantation process to simultaneously form a first buried layer 121, a second buried layer 122, and a third buried layer 123 in the semiconductor layer 100, the number of photomasks is reduced, and there is no need to additionally align the patterns of the first to third buried layers, thereby reducing process complexity and saving costs.
[0081] Furthermore, a well region 130 is formed in the semiconductor layer 100. The well region 130 extends from the first surface of the semiconductor layer 100 toward the first buried layer 121 and is connected to the top of the first buried layer 121, the second buried layer 122 and the third buried layer 123, respectively, as shown in FIG7.
[0082] Furthermore, a doped region 140 and a body contact region 142 are formed in the well region 130, extending from the first surface of the semiconductor layer 100 into the well region 130, as shown in FIG8.
[0083] Further, a trench is formed extending from the first surface of the semiconductor layer 100 to the first buried layer 121, and a trench gate 150 is formed in the trench, as shown in FIG9. The depth of the trench is less than the depth of the first buried layer 121. The doped region 140 serves as the source region 141, the undoped well region 130 serves as the body region 131, and the undoped epitaxial layer 104 and the substrate 103 serve as the drift region 110.
[0084] In this step, multiple grooves are formed along the Y-axis, thereby arranging multiple groove grids 150 at intervals.
[0085] Furthermore, an interlayer dielectric layer 160 and a first conductive layer 171 are formed on the first surface of the semiconductor layer 100, and a second conductive layer 172 is formed on the second surface of the semiconductor layer 100, thereby forming the semiconductor device shown in Figures 1 to 3.
[0086] The semiconductor device of the second embodiment of this disclosure is generally similar to the semiconductor device of the first embodiment in terms of manufacturing method. Please refer to the relevant description of the first embodiment. The difference is that when forming the trench, it is necessary to form a continuously extending trench along the Y-axis direction so that the trench gate 150 extends continuously.
[0087] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor device comprising a semiconductor layer and a trench gate, the semiconductor layer having opposing first and second surfaces, the trench gate being located in a trench on the first surface of the semiconductor layer. The semiconductor layer includes: The first buried layer is located at the bottom of the trench grid and is connected to the trench grid; The body region is connected to the sidewall of the trench grid; The source region is connected to the sidewall of the trench gate, and extends from the first surface toward the body region and is connected to the body region. as well as The drift region, at least a portion of which is located between the body region and the second surface, and connected to the first buried layer and the body region. The width of the trench grid is not less than the depth of the trench grid, and the width of the trench grid is greater than the width of the first buried layer.
2. The semiconductor device according to claim 1, wherein, The source region and the drift region are of a first conductivity type, and the first buried layer and the body region are of a second conductivity type, wherein the first conductivity type is the opposite of the second conductivity type.
3. The semiconductor device according to claim 1, wherein, The semiconductor layer further includes a second buried layer, which is separated from both the trench gate and the first buried layer. The second buried layer has the same conductivity type as the first buried layer. The body region is located between the second buried layer and the first surface, and is connected to the second buried layer; the drift region is connected to the second buried layer.
4. The semiconductor device according to claim 3, wherein, The bottom of the first buried layer is flush with the bottom of the second buried layer.
5. The semiconductor device according to claim 3, wherein, Both the first buried layer and the second buried layer extend along the length direction of the trench grid.
6. The semiconductor device according to claim 3, wherein, Along the width direction of the trench grid, the body region, the source region, and the second buried layer are all located on both sides of the trench grid.
7. The semiconductor device according to any one of claims 3 to 6, wherein, The semiconductor layer further includes a third buried layer located between the first buried layer and the second buried layer, and connected to the first buried layer, the second buried layer and the body region. The conductivity type of the third buried layer is the same as that of the first buried layer.
8. The semiconductor device according to claim 7, wherein, Multiple third buried layers are spaced apart along the length of the trench grid.
9. The semiconductor device according to claim 8, wherein, Along the length of the trench grid, the distance between adjacent third buried layers is greater than the length of the third buried layer.
10. The semiconductor device according to claim 7, wherein, The bottom of the third buried layer is flush with the bottom of the first buried layer.
11. The semiconductor device according to claim 7, wherein, Along the length of the trench grid, a plurality of trench grids are arranged at intervals. Along the length of the trench gate, the body region and the source region are also located between adjacent trench gates.
12. The semiconductor device according to claim 11, wherein, Along the length of the trench grid, the interval between adjacent trench grids corresponds to a portion of the third buried layer.
13. The semiconductor device according to claim 7, wherein, The trench grid extends continuously along its length.
14. A method for manufacturing a semiconductor device, comprising: A first buried layer is formed in a semiconductor layer, the semiconductor layer having a first surface and a second surface opposite to each other, and the first buried layer being at a predetermined distance from the first surface; A well region is formed in the semiconductor layer, the well region extending from the first surface toward the first buried layer and connected to the first buried layer; A doped region is formed in the well region, the doped region extending from the first surface into the well region; as well as A trench is formed extending from the first surface to the first buried layer, and a trench grid is formed in the trench. The width of the trench grid is not less than the depth of the trench grid, and the width of the trench grid is greater than the width of the first buried layer.
15. The manufacturing method according to claim 14, further comprising forming a second buried layer in the semiconductor layer, in, The second buried layer is separated from the trench grid and the first buried layer respectively, and the trap area is located between the second buried layer and the first surface and is connected to the second buried layer.
16. The manufacturing method according to claim 15, further comprising forming a third buried layer in the semiconductor layer, in, The third buried layer is located between the first buried layer and the second buried layer, and is connected to the first buried layer, the second buried layer and the trap area.
17. The manufacturing method according to claim 16, wherein, The first buried layer, the second buried layer, and the third buried layer are formed simultaneously using an ion implantation process.