Method for synchronising a switch-on operation of parallel-connected transistors

Abstract

The invention relates to a method (100) for synchronising a switch-on operation of parallel-connected transistors (2), comprising: - detecting (101) a respective curve of a gate-source voltage (V GS) during the switch-on operation of the transistors (2); - determining (102) individual delays (∆td1, ∆td2) of switching transients within the switch-on operation for each transistor (2) on the basis of slope changes in the respective curve of the gate-source voltage; - initiating (103) configuration of at least one gate driver (3) on the basis of the determined individual delays in order to synchronise the switch-on operation of the parallel-connected transistors (2), wherein the at least one gate driver (3) is used to control the transistors (2). The invention also relates to a power module, a computer program, a device, and a storage medium for this purpose.

Description

[0001] R.415053

[0002] - 1 -

[0003] Description

[0004] title

[0005] Method for synchronizing the switch-on process of parallel-connected transistors

[0006] The invention relates to a method for synchronizing the switch-on process of parallel-connected transistors. Furthermore, the invention relates to a power module, a computer program, a device, and a storage medium for this purpose.

[0007] State of the art

[0008] The parallel connection of transistors such as silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs) in a power module to increase output power is a proven and well-known technique. Due to tolerances in the MOSFET manufacturing process, parameter variations can occur in the transistors in connection with the switching transitions. These parameter variations, i.e.,

[0009] Threshold voltage, transconductance, Miller charge, and input capacitance lead to asymmetrical switching between parallel-connected transistors. In the prior art, only a few solutions for correcting this switching asymmetry have been described, and most of them use either an additional fast circuit in the power path to detect the parameters or an ASIC current source gate driver to detect and correct the asymmetry.

[0010] Disclosure of the invention

[0011] The invention relates to a method with the features of claim 1, a power module with the features of claim 7, an R.415053

[0012] - 2 -

[0013] A computer program with the features of claim 9, a device with the features of claim 10, and a computer-readable storage medium with the features of claim 11. Further features and details of the invention will become apparent from the respective dependent claims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the power module, the computer program, the device, and the computer-readable storage medium according to the invention, and vice versa, so that a reciprocal reference is always possible with regard to the disclosure of the invention.

[0014] The invention relates in particular to a method for synchronizing a switch-on process of parallel-connected transistors such as metal oxide semiconductor field-effect transistors (MOSFETs), IGBTs (bipolar transistors with insulated gate electrodes) or GaN transistors, comprising:

[0015] Capturing a specific waveform, in particular a change in the slope of the respective waveform, of a gate-source voltage (VGS) during the turn-on process of the transistors; determining individual delays of switching transients during the turn-on process for each transistor based on changes in the slope of the respective waveform of the gate-source voltage; initiating a configuration of at least one gate driver based on the determined individual delays to synchronize the turn-on process of the parallel-connected transistors, so that, particularly advantageously, current commutation in the parallel-connected transistors begins simultaneously, wherein the at least one gate driver is used to control the transistors.

[0016] A MOSFET switches on, in particular, when a sufficiently high voltage is applied between the gate and the source (VGS). This voltage ensures, in particular, that the MOSFET transitions to the conducting state and current flows through the drain-source channel. The gate driver preferably provides this voltage and can build it up and then reduce it again, R.415053

[0017] - 3 - to precisely control the switching process. The method according to the invention makes it possible to ensure that the parallel-connected transistors simultaneously reach their threshold voltage and thus become current-carrying synchronously. This leads in particular to a reduced switching asymmetry in the current flow during the turn-on process, which in turn can enable an improvement in overall performance, a reduction in losses and / or lower electromagnetic emissions. Furthermore, a reduced blanking time and thus higher short-circuit robustness can be provided.

[0018] Furthermore, it is conceivable that determining includes:

[0019] Analyzing the recorded gate-source voltage profile, for example using a slope detector circuit, preferably analyzing the slope of the profile, and identifying a point in time at which the drain-source voltage of the respective transistor begins to commutate. This point in time is reflected as a change in the slope of the gate-source voltage in the profile, with the individual delays corresponding to a time interval from power-on until the identified points in time. In other words, this enables, in particular, a precise determination of the delay of each transistor by analyzing the gate-source voltage and identifying the point in time at which the drain-source voltage changes.The specific individual delays can then allow for fine-tuning of the driver parameters, which can lead to improved synchronization of the current commutation of all transistors.

[0020] Optionally, one of the transistors can be used as a reference, and during configuration, the specific individual delay of at least one other transistor is adjusted to match the specific individual delay of the reference transistor, for example, by adding an additional delay corresponding to the difference between the respective individual delays. This ensures that all other transistors have the same individual delay as the reference transistor. R.415053

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[0022] This allows for precise synchronization of the switching-on processes of all transistors. Adjusting the delays to the reference transistor enables efficient and accurate control of even more than one additional transistor connected in parallel.

[0023] Within the scope of the invention, it can be provided that the transistors are used in a half-bridge configuration with a full DC link voltage and no load current during the acquisition process. This allows for a precise determination of the individual delays of each transistor, as there is no influence from current flow. This can lead to a more accurate analysis of the transistors' turn-on behavior and consequently to more efficient synchronization. Furthermore, the method enables a precise determination of semiconductor parameters.

[0024] Advantageously, the invention may provide that the method further comprises:

[0025] Using at least one gate driver with the applied specific individual delays in a regular operating mode to drive the transistors.

[0026] The regular operating mode can also be understood as normal operation or operational mode. Thus, the synchronization of the MOSFET current commutation according to the method of the present invention can be ensured in the regular operating mode. By using specific delays, the transistors can remain synchronized, and the advantages of reduced switching asymmetry and improved performance can be continuously utilized in the regular operating mode.

[0027] It is also conceivable that, during the acquisition process, a higher resistance value is used for the transistors' turn-on resistance than in the regular operating mode after configuring the at least one gate driver, with the turn-on resistance being located in a respective turn-on path of the transistors. The higher resistance value during the turn-on process can, for example, be at least one or more kΩ and advantageously minimize unwanted current flow, thereby enabling more targeted control and analysis of the transistors. R.415053

[0028] - 5 - A higher resistance value (especially without load current) can allow a very slow rise in the Vgs signal.

[0029] The invention also relates to a power module comprising: at least two transistors connected in parallel, such as metal oxide semiconductor field-effect transistors (MOSFETs), IGBTs (bipolar transistors with insulated gate electrodes), or GaN transistors; at least one gate driver for controlling a respective transistor C (single drive) or at least two transistors (parallel drive); a respective on-resistor arranged in a respective on-path of the transistors; a slope detector circuit for detecting a respective curve, in particular a change in slope in the respective curve, a gate-source voltage of the respective transistors; and a device for data processing for carrying out the method according to the invention.

[0030] The power module according to the invention thus offers the same advantages as described in detail with reference to the method according to the invention.

[0031] According to the present invention, improved synchronization and control of transistors, such as SiC MOSFETs in parallel circuits, can be achieved. The power module, in particular, enables individual analysis of the delays of each transistor, which can lead to more precise control and a reduction of switching asymmetries. The integration of the slope detector circuit for monitoring the gate-source voltage signal allows, in particular, efficient detection of the threshold voltage of each transistor. By adjusting the gate driver parameters with respect to the individual delays, synchronized current commutation of all transistors can be achieved. This minimizes, in particular, energy losses.

[0032] It can be provided that the at least two transistors connected in parallel are arranged in a half-bridge configuration, and that at least one transistor is a high-side transistor and the at least one other transistor is a low-side transistor. R.415053

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[0034] In other words, a specific circuit configuration is preferred in which the transistors are arranged in a half-bridge configuration. This allows, in particular, efficient control of circuits and a reduction in losses during the turn-on process. By using one high-side transistor and one low-side transistor, a wider voltage range can be controlled.

[0035] The invention also relates to a computer program, in particular a computer program product, comprising instructions which, when executed by a computer, cause the computer to execute the method according to the invention. Thus, the computer program according to the invention offers the same advantages as those described in detail with reference to a method according to the invention.

[0036] The invention also relates to a data processing device configured to execute the method according to the invention. The device can, for example, be a computer that executes the computer program according to the invention. The computer can have at least one processor for executing the computer program. Alternatively, a non-volatile data storage device can be provided in which the computer program is stored and from which the computer program can be read by the processor for execution.

[0037] The invention may also relate to a computer-readable storage medium which contains the computer program according to the invention and / or includes instructions which, when executed by a computer, cause the computer to execute the method according to the invention. The storage medium is, for example, designed as a data storage device such as a hard drive and / or non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0038] Furthermore, the method according to the invention can also be implemented as a computer-implemented method. Alternatively or additionally, at least one of the disclosed method steps can be computer-implemented and / or carried out automatically. R.415053

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[0040] Further advantages, features, and details of the invention will become apparent from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description can each be essential to the invention individually or in any combination. The drawings show:

[0041] Fig. 1 shows a schematic visualization of a method, a device, a storage medium and a computer program according to exemplary embodiments of the invention.

[0042] Fig. 2 shows a schematic representation of a power module according to exemplary embodiments of the invention.

[0043] Fig. 3 shows a schematic representation of a circuit diagram of a power module according to exemplary embodiments of the invention.

[0044] Fig. 4 Voltage waveforms during an HS and LS switching sequence according to exemplary embodiments of the invention,

[0045] Fig. 5 shows a slope determination from a gate-source voltage curve according to exemplary embodiments of the invention.

[0046] Fig. 6 shows the relative individual delays between the reference MOSFET and the further MOSFET connected in parallel according to exemplary embodiments of the invention.

[0047] Fig. 1 schematically shows a method 100, a device 10, a storage medium 15 and a computer program 20 according to exemplary embodiments of the invention.

[0048] Fig. 1 shows in particular an embodiment of a method 100 for synchronizing a switch-on process of parallel-connected transistors 2. In a first step 101, a respective gate-source waveform is measured. R.415053

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[0050] The voltage during the turn-on process of transistors 2 is detected. In a second step 102, individual delays of switching transients during the turn-on process are determined for each transistor 2 based on changes in the slope of the respective gate-source voltage. In a third step 103, a configuration of at least one gate driver 3 is initiated based on the determined individual delays in order to synchronize the turn-on process of the parallel-connected transistors 2, wherein the at least one gate driver 3 is used to control the transistors 2.

[0051] Fig. 2 shows in particular a schematic representation of a power module 1 according to exemplary embodiments of the invention, which comprises two transistors 2, in particular MOSFETs, a gate driver 3 for controlling the transistors 2, a switching resistor 4, a slope detector circuit 5 and a device for data processing 10.

[0052] Fig. 3 shows, in particular, a schematic representation of a circuit diagram of a power module 1 according to exemplary embodiments of the invention. The power module 1 has two transistors 2 connected in parallel, in particular silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs), each of which is connected to a gate driver 3 and a turn-on resistor 4. Furthermore, the power module 1 has a high-voltage power supply 6 and a filter capacitor 7.

[0053] According to exemplary embodiments, the present invention relates to a determination of parameters of transistors 2, in particular silicon carbide metal oxide semiconductor field-effect transistors, in connection with switching transients and a method for correcting the switching transient asymmetry based on a result of the determination.

[0054] According to the invention, a gate driver 3 can be connected to a voltage source 6 and a high-impedance resistor R. gin 4 can be used to switch on MOSFET 2. MOSFET 2 can be connected to a separate gate driver 3, or both transistors 2 can be connected in parallel with a common gate driver 3 in the power module 1 (not shown). The R.415053

[0055] - 9 -

[0056] Transistors 2 are preferably used in a half-bridge configuration with a full DC link voltage and no load current, as shown in Fig. 3. A slope detector circuit 5, for example, detects a change in the slope and the corresponding time of this gate-source voltage VGS. The voltage waveforms thus determined by the parallel transistors 2 can then be used to determine a reference time and the respective individual delays of each transistor 2, for example, using a simple algorithm. The individual delays thus determined can then be applied in each individual gate driver 3, so that the current commutation in the parallel-connected transistors 2 starts simultaneously.

[0057] The transistors 2 in a power module 1 can be connected in parallel, with each component in a logic switch using a separate voltage source gate driver 3 (also referred to as a "single drive"), or parallel-connected transistors 2 with a common gate driver 3 (also referred to as a "parallel drive"). Using the method according to exemplary embodiments of the invention, the parameters, i.e., in particular the individual delays, of each parallel-connected MOSFET 2 in a logic switch can be detected when each MOSFET 2 is driven by a separate gate driver 3, and in the case of a common gate driver 3, the representative value of the parameters of the parallel-connected transistors 2 can be extracted. In a detection phase, a high value for an on-resistance 4 of the transistors 2 is preferably selected, for example, from an FPGA-based resistance matrix.This on-resistance 4 is, for example, in the range of several kΩ. This on-resistance 4 is located in particular in the turn-on path of the "single drive" or "parallel drive" transistors 2 and is shown in Fig. 3 as "R". gin ,Ls” or “R gin 'Hs' is represented, where LS stands for Low Side and HS for High Side with respect to transistors 2. The turn-on voltage pulse is preferably applied to each of the transistors 2 in the case of single drive, and to the parallel-connected transistors 2 in the logic switch in the other case. R.415053

[0058] - 10 -

[0059] Fig. 4 shows, in particular, voltage waveforms during a switching sequence of HS and LS, where HS denotes the high-side MOSFET 2 and LS the low-side MOSFET 2. Fig. 4 shows, in particular, that in the unloaded state, there is a transition in the slope of the gate-source signal when the drain-source voltage begins to commutate at time t1 for LS and at time t6 for HS. This change in the slope of the gate-source signal is then preferably detected by a slope detector circuit 5 or a signal processing algorithm. The voltage Vth.in, which is present at the time of the slope change, correlates, in particular, directly with the threshold voltage of the respective MOSFET 2.

[0060] Figure 4 shows in particular that when the gate-source voltage reaches a value Vth.in, the drain-source voltage VDS begins to commutate, and at the corresponding time t1, the slope (d(Vcs) / dt) of the gate-source voltage VGS changes. This time ti for each individual MOSFET or each parallel-connected module can be stored in an array for further processing, in order to apply it to at least one gate driver.

[0061] Fig. 5 shows the determination of the slope from a waveform of the gate-source voltage VGS. The waveform is shown in the upper diagram, and the change in the slope is shown in the lower diagram.

[0062] The following example explains how these delays, or times t1, are used to achieve the synchronous start of current commutation in the parallel-connected transistors.

[0063] Initially, the gate resistors 4 of each MOSFET 2 are preferably set to the value R gin The voltage is set to, for example, the value in the kQ range. It can be assumed that Vcs.ref is the gate-source voltage of one of the transistors 2, which can be used as a reference MOSFET 2. Subsequently, a change in transconductance at time Atd2 can be detected. The other MOSFET 2, whose delay is to be corrected, preferably goes through the same routine. This other MOSFET is R.415053.

[0064] - 11 -

[0065] 2 preferably with the same value of the gate resistance as the reference MOSFET 2, i.e. R g in, switched on. The change in the transconductance of the further transistor 2 occurs particularly at time Atd1. In a regular operating mode, the transistors 2 preferably use a different, lower, gate resistance value, namely R. gon .

[0066] Fig. 6 shows the relative individual delays between the reference MOSFET 2 (ref) and the parallel-connected further MOSFET 2 (DUT) according to exemplary embodiments of the invention. This is represented in the form of the voltage waveforms of the reference MOSFET 2 Vcs.ref and the parallel-connected further MOSFET 2 VGS.DUT. Vcs.DUT new corresponds to the new voltage waveform of the parallel-connected further MOSFET 2 after adjustment based on the determined delay of the reference MOSFET 2.

[0067] The delay that can then be set in regular operating mode can be determined, for example, using the following formula:

[0068] Delay operation (DUT) = (Rgon / Rgin) Delay detection = (Rgon / Rgin) * (Atd2-Atd1) (1)

[0069] This formula can be applied to any number of transistors 2 in parallel by taking a maximum of the times, or individual delays, for the slope change as a reference and then applying the delay accordingly to the individual transistors 2.

[0070] If the delay is set correctly, each of the parallel-connected transistors 2 can advantageously reach its threshold voltage at the same time, since the threshold voltage is directly related to the V t h,i n The value from the detection phase corresponds to this. Since the threshold voltages of each of these parallel-connected transistors 2 are synchronized to the reference value, current commutation advantageously begins at the same time, thus reducing the asymmetry of the current commutation. R.415053

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[0072] The preceding explanation of the embodiments describes the present invention exclusively by way of examples.

[0073] Of course, individual features of the embodiments can be freely combined with one another, provided this is technically feasible, without leaving the scope of the present invention.

Claims

R.415053 - 13 - Claims 1. Method (100) for synchronizing a switch-on process of parallel-connected transistors (2), comprising: Recording (101) a respective gate-source voltage profile during the turn-on process of the transistors (2), Determining (102) individual delays of switching transients during the turn-on process for each transistor (2) based on changes in the slope of the respective gate-source voltage profile, Initiating (103) a configuration of at least one gate driver (3) based on the determined individual delays to synchronize the turn-on process of the parallel-connected transistors (2), wherein the at least one gate driver (3) is used to drive the transistors (2).

2. Method (100) according to claim 1 , characterized in that the determining (102) comprises: Analyzing the recorded respective gate-source voltage curves, Identifying a time point at which a drain-source voltage of the respective transistor (2) begins to commutate, wherein this time point is reflected in the form of a change in the slope of the gate-source voltage in the respective curve, wherein the individual delays correspond to a time interval from a switch-on until the respective identified time points.

3. Method (100) according to claim 1 or 2, characterized in that one of the transistors (2) is used as a reference transistor. R.415053 - 14 - is and, as part of the configuration, the specific individual delay of at least one further transistor (2) is adjusted to the specific individual delay of the reference transistor (2).

4. Method (100) according to one of the preceding claims, characterized in that the transistors (2) are used in a half-bridge configuration with a full DC link voltage and without load current during the detection (101).

5. Method (100) according to one of the preceding claims, characterized in that the method (100) further comprises: Using the at least one gate driver (3) with the applied specific individual delays in a regular operating mode to drive the transistors (2).

6. Method (100) according to claim 5, characterized in that, during the detection (101), a higher resistance value is used for a turn-on resistor (4) of the transistors (2) than in the regular operating mode after configuring the at least one gate driver (3), wherein the turn-on resistor (4) is arranged in a respective turn-on path of the transistors (2). R.415053 - 15 - 7. Power module (1) comprising: at least two transistors (2) connected in parallel, at least one gate driver (3) for controlling a respective transistor (2) or at least two transistors (2), a respective on-resistor (4) which is arranged in a respective on-path of the transistors (2), a slope detector circuit (5) for detecting a respective course of a gate-source voltage of the respective transistors (2), a device for data processing (10) for carrying out the method (100) according to one of the preceding claims.

8. Power module (1) according to claim 7, characterized in that the at least two parallel-connected transistors (2) are arranged in a half-bridge configuration and at least one transistor (2) is a high-side transistor and the at least one further transistor (2) is a low-side transistor.

9. Computer program (20), comprising instructions which, when the computer program (20) is executed by a computer (10), cause it to execute the method (100) according to any one of claims 1 to 6.

10. Device (10) for data processing, which is configured to carry out the method (100) according to any one of claims 1 to 6.

11. Computer-readable storage medium (15) comprising instructions which, when executed by a computer (10), cause it to perform the steps of the method (100) according to any one of claims 1 to 6.

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