Phase synchronization circuit and semiconductor integrated circuit

Abstract

This phase synchronization circuit comprises: a clock generating circuit that generates a clock signal; a phase detecting circuit that compares the phase of the clock signal with the phase of a feedback signal to generate a phase detection signal; a frequency detecting circuit that compares the frequency of the clock signal with the frequency of the feedback signal to generate a frequency detection signal; an intermediate signal generating circuit that generates an intermediate signal on the basis of the phase detection signal and the frequency detection signal; a first amplification circuit that amplifies the phase detection signal and outputs a first output signal; a second amplification circuit that amplifies the intermediate signal and outputs a second output signal; an oscillation control circuit that generates an oscillation control signal on the basis of the first output signal and the second output signal; an oscillation circuit that generates an output clock signal on the basis of the oscillation control signal; and a feedback circuit that generates the feedback signal on the basis of the output clock signal.

Description

Phase synchronization circuit and semiconductor integrated circuit

[0001] The present invention relates to a phase synchronization circuit and a semiconductor integrated circuit.

[0002] It is known to use a phase difference detection signal and a frequency difference detection signal in a loop filter of a phase synchronization circuit (PLL circuit: Phase Locked Loop circuit) (for example, Patent Document 1). It is known to use a BBP D (Bang-Bang Phase Detector) in a phase detection circuit (for example, Patent Document 2). It is known to use a PLL circuit in a reception circuit (for example, Patent Document 3).

[0003] Japanese Patent Application Laid-Open No. 2005-033550, Japanese Patent Application Laid-Open No. 2012-147195, U.S. Patent Application Publication No. 2009 / 0110136

[0004] In a phase synchronization circuit, in a state where the frequency is locked, the phases may not be synchronized.

[0005] An object of the present disclosure is to provide a phase synchronization circuit and a semiconductor integrated circuit capable of appropriately synchronizing phases.

[0006] An embodiment of the present disclosure includes a clock generation circuit that generates a clock signal, a phase detection circuit that compares the phase of the clock signal with the phase of a feedback signal to generate a phase detection signal, a frequency detection circuit that compares the frequency of the clock signal with the frequency of the feedback signal to generate a frequency detection signal, an intermediate signal generation circuit that generates an intermediate signal based on the phase detection signal and the frequency detection signal, a first amplification circuit that amplifies the phase detection signal and outputs a first output signal, a second amplification circuit that amplifies the intermediate signal and outputs a second output signal, an oscillation control circuit that generates an oscillation control signal based on the first output signal and the second output signal, an oscillation circuit that generates an output clock signal based on the oscillation control signal, and a feedback circuit that generates the feedback signal based on the output clock signal. It is a phase synchronization circuit provided with.

[0007] Embodiments of this disclosure are semiconductor integrated circuits comprising the above-mentioned phase-locking circuit, a receiving circuit that generates a received signal from an input signal based on the output clock signal, and a transmitting circuit that generates an output signal from a transmitted signal based on the output clock signal.

[0008] According to the disclosed technology, the phase can be properly synchronized.

[0009] Figure 1 is a block diagram of a phase-locked circuit according to the first embodiment. Figure 2 is a block diagram of a phase-locked circuit according to the second embodiment. Figure 3 is a block diagram of a phase-locked circuit according to the first comparative form. Figure 4 is a block diagram of a frequency detector in the second embodiment. Figure 5 is a timing chart showing the operation of a phase detection circuit in the second embodiment. Figure 6 is a timing chart of the clock signal R, the delayed clock signal R2, and the feedback signal V in the second embodiment. Figure 7 is a timing chart of the phase detection signals pd1 and pd2 in the second embodiment. Figure 8 is a diagram showing the state of the FPD state machine in the second embodiment. Figure 9 is a block diagram of the frequency detection circuit of a phase-locked circuit according to the second comparative form. Figure 10 is a timing chart of the frequency detection signal, phase detection signal, and oscillation control signal in the second embodiment and the second comparative form. Figure 11 is a timing chart of the frequency detection signal, phase detection signal, and oscillation control signal in the second embodiment and the second comparative form. Figure 12 is a block diagram of a semiconductor integrated circuit according to the third embodiment.

[0010] The embodiments for implementing this disclosure will be described in detail below with reference to the drawings. The embodiments described below are examples for realizing the technical concept of the invention and do not limit this disclosure to the configurations and numerical values ​​described. In each drawing, the same reference numerals are used for the same components, and redundant explanations may be omitted as appropriate.

[0011] (First Embodiment) Figure 1 is a block diagram of a phase-synchronous circuit in the first embodiment. As shown in Figure 1, the phase-synchronous circuit 100 according to the first embodiment includes a clock generation circuit 10, a phase detection circuit 12, a frequency detection circuit 14, an intermediate signal generation circuit 15, amplification circuits 16A and 16B, an oscillation control circuit 17, an oscillation circuit 18, and a feedback circuit 19.

[0012] The clock generation circuit 10 generates a clock signal R. The phase detection circuit 12 compares the phase of the clock signal R and the feedback signal V to generate a phase detection signal pd1. The frequency detection circuit 14 compares the frequencies of the clock signal R and the feedback signal V to detect a frequency detection signal FPD. The intermediate signal generation circuit 15 generates an intermediate signal M2 based on the phase detection signal pd1 and the frequency detection signal FPD. The amplification circuit 16A (first amplification circuit) amplifies the intermediate signal M1 corresponding to the phase detection signal pd1 based on the coefficient Ki and outputs an output signal O1 (first output signal). The amplification circuit 16B (second amplification circuit) amplifies the intermediate signal M2 based on the coefficient Kp and outputs an output signal O2 (second output signal). The oscillation control circuit 17 generates an oscillation control signal DCO-F based on the output signals O1 and O2. The oscillation circuit 18 generates an output clock signal OUT with a controlled frequency based on the oscillation control signal DCO-F. The feedback circuit 19 generates a feedback signal V based on the output clock signal OUT.

[0013] In the phase-synchronization circuit 100 according to the first embodiment, the intermediate signal generation circuit 15 generates an intermediate signal M2 based on the phase detection signal pd1 and the frequency detection signal FPD. The oscillation control circuit 17 generates an oscillation control signal DCO-F based on the output signal O1, which is an amplified version of the phase detection signal pd1, and the output signal O2, which is an amplified version of the intermediate signal M2. This allows for proper phase synchronization.

[0014] (Second Embodiment) The second embodiment is an example of an ADPLL (All Digital Phase Locked Loop) circuit. Figure 2 is a block diagram of the phase-locked circuit according to the second embodiment. As shown in Figure 2, the phase-locked circuit 102 according to the second embodiment includes, in addition to the phase-locked circuit 100 according to the first embodiment, an arithmetic unit 21, a reference clock generation circuit 22, a calibration circuit 11, and a frequency detector 14A. The reference clock generation circuit 22 generates a reference clock signal OSC and supplies the reference clock signal OSC to the clock generation circuit 10. The arithmetic unit 21 generates a frequency control signal FC by integrating the frequency control word FCW and performing a modulo operation. The clock generation circuit 10 is a DTC (Digital Time Converter) and generates a clock signal R by controlling the phase of the reference clock signal OSC based on the calibration control signal CC. For example, the clock generation circuit 10 generates a clock signal R by delaying the reference clock signal OSC based on the calibration control signal CC.

[0015] The phase detection circuit 12 is a BBPD (Bang-Bang Phase Detector) that compares the phase of the feedback signal V with the phase of the clock signal R and outputs a phase detection signal pd1 indicating whether the phase of the feedback signal V is leading or lagging the phase of the clock signal R. The phase detection circuit 12 includes a Bang-Bang type phase detection circuit that operates based on the clock signal R and the feedback signal V to generate the phase detection signal pd1. The calibration circuit 11 calibrates the clock generation circuit 10 based on the phase detection signal pd1, for example, by correcting the gain of the clock generation circuit 10 based on the phase detection signal pd1.

[0016] The frequency detector 14A compares the frequency of the feedback signal V with the frequency of the clock signal R and generates an intermediate signal M2 that indicates whether the frequency of the feedback signal V is higher or lower than the frequency of the clock signal R.

[0017] Amplifier circuits 16A and 16B amplify the intermediate signals M1 (corresponding to the phase detection signal pd1) and M2, respectively, based on coefficients Kp and Ki, and output output signals O1 and O2, respectively. A relay circuit that generates the intermediate signal M1 based on the phase detection signal pd1 may be provided between the phase detection circuit 12 and the amplifier circuit 16A. The relay circuit is, for example, a buffer circuit.

[0018] The oscillation control circuit 17 includes a smoothing circuit 17A and an adder 26. The smoothing circuit 17A includes an adder 24 and a delay circuit 25. The adder 24 adds the output of the delay circuit 25 and the output signal O2 and outputs it to the delay circuit 25. The delay circuit 25 delays the input signal by one clock cycle and outputs it to the adder 24. As a result, a smoothed signal Integ, which is the output signal O2 smoothed in time, is output from the smoothing circuit 17A. The adder 26 adds the output signal O1 and the smoothed signal Integ to generate an oscillation control signal DCO-F.

[0019] The oscillation circuit 18 is a DCO (Digitally Controlled Oscillator), a digitally controlled oscillation circuit that outputs an output clock signal OUT with a frequency based on the oscillation control signal DCO-F. For example, when the value of the oscillation control signal DCO-F decreases, the oscillation frequency of the oscillation circuit 18 (DCO) increases. The feedback circuit 19 is a 1 / N (N is an integer of 2 or more) frequency divider that generates a feedback signal V having a frequency of 1 / N of the output clock signal OUT frequency.

[0020] In the second embodiment, the phase-locked circuit 102 generates the output clock signal OUT generated by the oscillator circuit 18 based on the clock signal R and a feedback signal V obtained by dividing the output clock signal OUT by 1 / N. This makes it possible to set the frequency of the output clock signal OUT to N times the frequency of the clock signal R.

[0021] (First Comparative Embodiment) Figure 3 is a block diagram of the phase-locked circuit according to the first comparative embodiment. As shown in Figure 3, the phase-locked circuit 110 according to the first comparative embodiment does not have a frequency detector 14A. The phase detection signal pd1 generated by the phase detection circuit 12 is input to the amplification circuits 16A and 16B. The other configurations are the same as the phase-locked circuit 102 of the second embodiment, and their explanation is omitted.

[0022] In the first comparative form of the phase-locked circuit 110, a proportional term obtained by multiplying the phase detection signal pd1 by a coefficient Kp and an integral term obtained by multiplying the phase detection signal pd1 by a coefficient Ki are added together to generate the oscillation control signal DCO-F. As a result, the frequency of the output clock signal OUT is controlled so that the phase difference between the clock signal R and the feedback signal V is reduced, and the frequency and phase of the output clock signal OUT are locked.

[0023] However, the phase detection signal pd1 does not compare the frequencies of the clock signal R and the feedback signal V. For this reason, when the frequency difference between the clock signal R and the feedback signal V is large, it is difficult to control the frequency of the output clock signal OUT.

[0024] (Frequency detection circuit of the second embodiment) In the phase-locked circuit 102 of the second embodiment, a frequency detector 14A is provided. Figure 4 is a block diagram showing the frequency detector 14A in the second embodiment. As shown in Figure 4, the frequency detector 14A includes a frequency detection circuit 14 and an intermediate signal generation circuit 15.

[0025] The frequency detection circuit 14 includes a delay circuit 30, a phase detection circuit 32, and an FPD state machine 33. The delay circuit 30 delays the clock signal R by approximately 1 / 4 of the period of the clock signal R to generate a delayed clock signal R2. The phase detection circuit 32 is a BBPD and compares the phase of the feedback signal V with the phase of the delayed clock signal R2 to output a phase detection signal pd2 indicating whether the phase of the feedback signal V is ahead or behind the phase of the delayed clock signal R2. The phase detection circuit 32 includes a Bang-Bang type phase detection circuit that operates based on the delayed clock signal R2 and the feedback signal V to generate the phase detection signal pd2. The FPD state machine 33 compares the phase detection signals pd1 and pd2 to generate a frequency detection signal FPD.

[0026] The intermediate signal generation circuit 15 includes logic circuits 34C, 34D, and an adder 35. Logic circuit 34C converts the level of the frequency detection signal FPD. When the frequency detection signal FPD is "1", logic circuit 34C sets the input signal to the adder 35 to "+0.5", and when the frequency detection signal FPD is "0", it sets the input signal to the adder 35 to "-0.5". Logic circuit 34D converts the level of the phase detection signal pd1. When the phase detection signal pd1 is "1", logic circuit 34D sets the input signal to the adder 35 to "+0.5", and when the phase detection signal pd1 is "0", it sets the intermediate signal M1 to "-0.5". The adder 35 adds the phase detection signals pd1 and pd2 to generate the intermediate signal M2. Logic circuit 34B converts the level of the phase detection signal pd1 to generate the intermediate signal M1. The logic circuit 34B sets the intermediate signal M1 to "+1" when the phase detection signal pd1 is "1", and sets the intermediate signal M1 to "-1" when the phase detection signal pd1 is "0".

[0027] Figure 5 is a timing chart showing the operation of the phase detection circuit in the second embodiment. Phase detection circuits 12 and 32 are, for example, BBPDs. BBPD is, for example, a D-FF (Delay Flip Flop). In phase detection circuit 12, for example, the clock signal R and the feedback signal V are input to the clock terminal CK and data terminal D of the D-FF, respectively. The phase detection signal pd1 is output from the output terminal Q of the D-FF. In phase detection circuit 32, the delayed clock signal R2 and the feedback signal V are input to the clock terminal CK and data terminal D of the D-FF, respectively. The phase detection signal pd2 is output from the output terminal Q of the D-FF.

[0028] As a result, at time t1, when the clock signal R rises, the feedback signal V is "1" and the phase detection signal pd1 is "1". This "1" state is maintained thereafter. If the frequency of the feedback signal V is higher than the frequency of the clock signal R, the rising edge timing of the feedback signal V gradually becomes earlier than the rising edge timing of the clock signal R. At times t2 and t3, the feedback signal V is "1" and the phase detection signal pd1 is "1". At time t4, when the clock signal R rises, the feedback signal V becomes "0". At this time, the phase detection signal pd1 becomes "0" and this "0" state is maintained thereafter. At time t5, the feedback signal V is "0" and the phase detection signal pd1 is "0".

[0029] As described above, the phase detection signals pd1 (and pd2) become "1" when the phase of the feedback signal V leads the phase of the clock signal R (and the delayed clock signal R2), and remain "1" thereafter until the phase of the feedback signal V lags behind the phase of the clock signal R (and the delayed clock signal R2). The phase detection signals pd1 (and pd2) become "0" when the phase of the feedback signal V lags behind the phase of the clock signal R (and the delayed clock signal R2), and remain "0" thereafter until the phase of the feedback signal V leads the phase of the clock signal R (and the delayed clock signal R2).

[0030] Figure 6 is a timing chart of the clock signal R, the delayed clock signal R2, and the feedback signal V in the second embodiment. As shown in Figure 6, the delayed clock signal R2 is delayed from the clock signal R. The delay time is Td. Time ts1 is the sampling time of the phase detection circuit 12. Time ts2 is the sampling time of the phase detection circuit 32. The feedback signals V(A) to V(D) indicate a state where they are out of phase with each other. At times ts1 and ts2, feedback signals V(A) are "0" and "0", feedback signals V(B) are "1" and "0", feedback signals V(C) are "1" and "1", and feedback signals V(D) are "0" and "1".

[0031] When the frequency of the feedback signal V is lower than the frequency of the clock signal R (this is called L: late), the feedback signal V repeatedly undergoes the state transitions (A) → (B) → (C) → (D) → (A) over time. When the frequency of the feedback signal V is higher than the frequency of the clock signal R (this is called E: early), the feedback signal V repeatedly undergoes the state transitions (D) → (C) → (B) → (A) → (D) over time.

[0032] Figure 7 is a timing chart of phase detection signals pd1 and pd2 in the second embodiment. The time on the horizontal axis is longer than that in Figures 5 and 6. V:L indicates that the frequency of the feedback signal V is lower than the frequency of the clock signal R, which is L. V:E indicates that the frequency of the feedback signal V is higher than the frequency of the clock signal R, which is E. As shown in Figure 7, when the feedback signal V is L, it repeats the state transition of (A) → (B) → (C) → (D) → (A) in Figure 6. Therefore, when the feedback signal V is L, (pd1, pd2) repeats the state transition of (0,0) → (1,0) → (1,1) → (0,1) → (0,0). Therefore, when the feedback signal V is E, it repeats the state transition of (D) → (C) → (B) → (A) → (D) in Figure 6. Therefore, when the feedback signal V is E, (pd1, pd2) repeatedly undergoes the state transitions of (0,1) → (1,1) → (1,0) → (0,0) → (0,1).

[0033] Figure 8 shows the state of the FPD state machine in the second embodiment. As shown in Figure 8, states 50A to 50D correspond to (A) to (D) in Figure 7, respectively. State 50A is pd1=0 and pd2=0. State 50B is pd1=1 and pd2=0. State 50C is pd1=1 and pd2=1. State 50D is pd1=0 and pd2=1. When the feedback signal V is L, the FPD state machine 33 transitions through states 50A, 50B, 50C, and 50D in the order shown over time. When the feedback signal V is E, the FPD state machine 33 transitions through states 50A, 50D, 50C, and 50B in the order shown over time. The FPD state machine 33 can determine whether the feedback signal V is L or E depending on whether it is transitioning between states 50A, 50B, 50C, and 50D, or between states 50A, 50D, 50C, and 50B.

[0034] As described above, the frequency detection circuit 14 includes a delay circuit 30, a phase detection circuit 32, and an FPD state machine 33. This allows the frequency detection circuit 14 to generate a frequency detection signal FPD that indicates whether the frequency of the feedback signal V is higher or lower than the frequency of the clock signal R.

[0035] (Second Comparison Embodiment) Figure 9 is a block diagram showing the frequency detection circuit 14 of the phase-locked circuit according to the second comparison embodiment. As shown in Figure 9, the frequency detection circuit 14 includes a delay circuit 30, a phase detection circuit 32, an FPD state machine 33, and a logic circuit 34A. The operation of the delay circuit 30, the phase detection circuit 32, and the FPD state machine 33 is the same as the operation of the frequency detection circuit 14 in the second embodiment. The FPD state machine 33 sets the frequency detection signal FPD to "1" when the feedback signal V is L, and sets the frequency detection signal FPD to "0" when the feedback signal V is E. The logic circuit 34A converts the level of the frequency detection signal FPD. The logic circuit 34A sets the intermediate signal M2 to "+1" when the frequency detection signal FPD is "1", and sets the intermediate signal M2 to "-1" when the frequency detection signal FPD is "0".

[0036] Thus, the phase detection signal pd1 is input as an intermediate signal M1 to the amplifier circuit 16A, which corresponds to the proportional term of the loop filter, and the frequency detection signal FPD is input as an intermediate signal M2 to the amplifier circuit 16B, which corresponds to the integral term of the loop filter.

[0037] Figures 10 and 11 are timing charts of the frequency detection signal, phase detection signal, and oscillation control signal in the second embodiment and the second comparative embodiment. Figure 10 shows a normal locked state, and Figure 11 shows an abnormal locked state. Before time tL is the convergence period, during which the oscillation control signal DCO-F is controlled to converge the frequency of the output clock signal OUT. After time tL, the system enters a locked state, where the frequency of the output clock signal OUT is locked.

[0038] Table 1 shows the signal states for normal and abnormal lock conditions in the second comparison mode.

[0039]

[0040] As shown in Figure 10, during the convergence period, the FPD is approximately 1 and the feedback signal V is L. Based on the phase detection signals pd1 and pd2, the oscillation control signal DCO-F changes. As a result, the frequency of the feedback signal V increases, and the difference between the frequency of the feedback signal and the frequency of the clock signal R decreases. Therefore, the periods between "1" and "0" for the phase detection signals pd1 and pd2 become longer. The oscillation control signal DCO-F continues to change, and the frequency of the feedback signal V increases. At time tL, the frequency of the feedback signal V is locked to the frequency of the clock signal R.

[0041] As shown in Figure 10 and Table 1, in a normal locked state, the frequency detection signal FPD is in a 1 / 0 toggle state, the phase detection signal pd1 is in a 1 / 0 toggle state, and the phase detection signal pd2 is fixed at "1". As a result, the intermediate signal M1 is in a +1 / -1 toggle state, and the intermediate signal M2 is in a +1 / -1 toggle state. Since the average value of intermediate signals M1 and M2 is approximately 0, the oscillation control signal DCO-F is fixed, resulting in a locked state.

[0042] As shown in Figure 11, even in an abnormal lock state, the convergence period converges in the same way as in Figure 10. As shown in Figure 11 and Table 1, in an abnormal lock state, the frequency detection signal FPD is in a 1 / 0 toggle state, the phase detection signal pd1 is fixed at "0", and the phase detection signal pd2 is in a 1 / 0 toggle state. As a result, the intermediate signal M1 is fixed at "-1", and the intermediate signal M2 is in a +1 / -1 toggle state. Although the intermediate signal M1 is -1, the average value of the intermediate signal M2 is almost 0, so the oscillation control signal DCO-F is fixed, resulting in a lock state.

[0043] As shown in Figure 11, in an abnormal lock state, the phase detection signal pd1 is 0, and the feedback signal V and the clock signal R are locked in a phase-shifted state, resulting in a lack of phase synchronization. Whether the phase synchronization circuit enters a normal lock state or an abnormal lock state is influenced by various factors and cannot be controlled.

[0044] (Intermediate Signal Generation Circuit of the Second Embodiment) Returning to FIG. 4, in the intermediate signal generation circuit 15 of the second embodiment, the adder 35 adds the frequency detection signal FPD of +0.5 / -0.5 and the phase detection signal pd1 of +0.5 / -0.5 to generate a three-valued signal of +1 / 0 / -1 as the intermediate signal M2.

[0045] Table 2 is a table showing the states of signals in normal and abnormal lock states in the second embodiment.

[0046]

[0047] As shown in Table 2, in the normal lock state and the abnormal lock state, the states of the frequency detection signal FPD, the phase detection signals pd1, pd2, and the intermediate signal M1 are the same as those in the second comparison form of Table 1. In the normal lock state, the intermediate signal M2 is in a toggle state of +1 / 0 / -1. Similar to Table 1 of the second comparison form, since the average values of the intermediate signals M1 and M2 are almost 0, the oscillation control signal DCO-F is fixed and enters the lock state.

[0048] In the abnormal lock state, the frequency detection signal FPD is in a toggle state of 1 / 0. However, in the second embodiment, different from the case of the second comparison form, the intermediate signal M2 is generated by the adder 35 to which the phase detection signal pd1 in a fixed state of -0.5 is input in addition to the frequency detection signal FPD in the toggle state. From this, the intermediate signal M2 is in a toggle state of 0 / -1, and since the average value of the intermediate signal M2 is a negative value, the integral term becomes large and the oscillation control signal DCO-F changes. As a result, when the value of the oscillation control signal DCO-F changes, the oscillation frequency of the oscillation circuit 18 (DCO) also changes. From this, the abnormal lock state is not stable. Therefore, only the normal lock state is stable.

[0049] As in the second comparative configuration, when amplifier circuit 16A amplifies the intermediate signal M1 corresponding to the phase detection signal pd1 and amplifier circuit 16B amplifies the intermediate signal M2 corresponding to the frequency detection signal FPD, it is possible that the system may stabilize in an abnormal locked state. This is for the following reason: Since intermediate signals M1 and M2 are independent signals, if the state of intermediate signal M1 stabilizes in a state that is not a normal locked state (abnormal locked state), intermediate signal M2 will stabilize in the same state as a normal locked state, as shown in Table 1. Since the state of intermediate signal M2 does not change from the normal locked state, the phase-locking circuit does not change the frequency of the output clock signal OUT to change the oscillation control signal DCO-F. In this way, the phase-locking circuit does not operate to change the state of intermediate signal M1 to a normal locked state. Therefore, it stabilizes in an abnormal locked state.

[0050] Therefore, in the second embodiment, the intermediate signal generation circuit 15 generates an intermediate signal M2 based on the phase detection signal pd1 and the frequency detection signal FPD corresponding to the intermediate signal M1. As a result, if the state of the intermediate signal M1 stabilizes in a state that is not a normal locked state (an abnormal locked state), the state of the intermediate signal M2 will become unstable due to the action of the intermediate signal M1, which is different from the normal locked state. Therefore, the phase synchronization circuit changes the oscillation control signal DCO-F so as to change the frequency of the output clock signal OUT. This operates to change the state of the intermediate signal M2 to a normal locked state. As a result, the oscillation control signal DCO-F is a signal that moves the frequency of the output clock signal OUT, so stabilization in an abnormal locked state is suppressed, and the phase can be appropriately synchronized in the locked state.

[0051] The phase detection circuit 12 outputs "1" (first level) as the phase detection signal pd1 when the phase of the feedback signal V leads the phase of the clock signal R, and outputs "0" (second level) as the phase detection signal pd1 when the phase of the feedback signal V lags behind the phase of the clock signal R. The frequency detection circuit 14 outputs "0" (third level) as the frequency detection signal FPD when the frequency of the feedback signal V is higher than the frequency of the clock signal R, and outputs "1" (fourth level) as the frequency detection signal FPD when the frequency of the feedback signal V is lower than the frequency of the clock signal R. Thus, the phase detection signal pd1 is a digital signal indicating whether the phase of the feedback signal V leads or lags behind the phase of the clock signal R, and the frequency detection signal FPD is a digital signal indicating whether the frequency of the feedback signal V is higher or lower than the frequency of the clock signal R. In this case, an abnormal lock state is likely to occur, as in the second comparison form. Therefore, it is preferable to generate an intermediate signal M2 based on the phase detection signal pd1 and the frequency detection signal FPD.

[0052] The intermediate signal generation circuit 15 generates an intermediate signal M2 by adding the phase detection signal pd1 and the frequency detection signal FPD. This allows the circuit to change the state of intermediate signal M2 to a state different from the normal lock state (an abnormal lock state) if the state of intermediate signal M1 becomes stable in a state other than the normal lock state. Therefore, the phase can be properly synchronized in the locked state.

[0053] When the intermediate signal generation circuit 15 adds the phase detection signal pd1 and the frequency detection signal FPD, one of the first level and the second level of the phase detection signal pd1 is a negative level, and the other of the first level and the second level is a positive level. This makes it possible to change the state of the intermediate signal M2 when the level of the phase detection signal pd1 is fixed to the state of the intermediate signal M2 when the level of the phase detection signal pd1 is toggled. Therefore, the phase can be properly synchronized in the locked state.

[0054] The intermediate signal M2 is a 3-value or 2-bit signal. This allows the state of the intermediate signal M2 to change when the level of the phase detection signal pd1 is fixed, depending on whether the phase detection signal pd1 is in a toggle state or not. Therefore, the phase can be properly synchronized in the locked state.

[0055] As shown in Figure 2, the oscillation control circuit 17 generates an oscillation control signal DCO-F based on the output signal O1 and a smoothed signal Integ, which is obtained by smoothing the output signal O2 over time. This smooths the intermediate signal M2, which is generated based on the phase detection signal pd1 and the frequency detection signal FPD. Therefore, when the phase detection signal pd1 is in a state different from the normal locked state, the smoothed signal Integ can be changed. Thus, the phase can be properly synchronized in the locked state.

[0056] The smoothing signal Integ corresponds to the integral term of the oscillation control circuit 17, and the output signal O1 corresponds to the proportional term of the oscillation control circuit 17. This allows the integral term to be changed when the phase detection signal pd1 is in a state different from the normal locked state. Therefore, the phase can be properly synchronized in the locked state.

[0057] As shown in Figure 4, in the frequency detection circuit 14, the delay circuit 30 delays the clock signal R and outputs a delayed clock signal R2. Another phase detection circuit 32 compares the phase of the feedback signal V with the phase of the delayed clock signal R2 and generates another phase detection signal pd2. The FPD state machine 33 (frequency detection signal generation circuit) generates the frequency detection signal FPD based on the phase detection signal pd1 and the other phase detection signal pd2. This allows the frequency detection circuit 14 to be realized with a simple configuration.

[0058] The delay time Td of the delay circuit 30 can be greater than 0 times the period of the clock signal R and less than 1 / 2 times. As a result, as shown in Figure 6, the FPD state machine 33 can generate a frequency detection signal FPD by comparing the frequency of the feedback signal V with the frequency of the clock signal R. The delay time Td may be between 1 / 8 and 3 / 8 times the period of the clock signal R.

[0059] (Third Embodiment) The third embodiment is an example of a semiconductor integrated circuit comprising the phase-locked circuit of the first or second embodiment. Figure 12 is a block diagram of the semiconductor integrated circuit according to the third embodiment. As shown in Figure 12, the semiconductor integrated circuit 104 according to the third embodiment comprises a phase-locked circuit 40, a receiving circuit 41R, a transmitting circuit 41T, and a processing circuit 48. The receiving circuit 41R comprises a low-noise amplifier 42R, a phase shifter 43R, mixers 44R, 45R, and a distributor 46R. The transmitting circuit 41T comprises a power amplifier 42T, a phase shifter 43T, mixers 44T, 45T, and a combiner 46T.

[0060] The phase-locking circuit 40 is a phase-locking circuit according to the first or second embodiment. The phase-locking circuit 40 outputs a locked clock signal CK0 based on an external clock signal X'tal. The phase shifters 43R and 43T generate clock signals CK1 and CK2 from the clock signal CK0, which have the same frequency as the clock signal CK0 but are shifted in phase by 90° from each other.

[0061] In the receiving circuit 41R, the low-noise amplifier 42R amplifies the input signal RX. The distributor 46R distributes the amplified input signal RX into two signals, RX1 and RX2. The mixer 44R mixes the clock signal CK1 and signal RX1 to generate the received signal RX-I. The mixer 45R mixes the clock signal CK2 and signal RX2 to generate the received signal RX-Q. The processing circuit 48 acquires the received signals RX-I and RX-Q and processes them based on the acquired received signals RX-I and RX-Q.

[0062] The processing circuit 48 outputs the transmission signals TX-I and TX-Q. In the transmission circuit 41T, the mixer 44T mixes the clock signal CK1 and the transmission signal TX-I to generate signal TX1. The mixer 45T mixes the clock signal CK2 and the transmission signal TX-Q to generate signal TX2. The combiner 46T combines signals TX1 and TX2. The power amplifier 42T amplifies the combined signal and outputs it as the output signal TX.

[0063] According to the third embodiment, the semiconductor integrated circuit 104 includes the phase-locking circuit 40 of the first or second embodiment. The receiving circuit 41R generates received signals RX-I and RX-Q from the input signal RX based on the clock signal CK0 (output clock signal) output by the phase-locking circuit 40. The transmitting circuit 41T generates an output signal TX from the transmitted signals TX-I and TX-Q based on the clock signal CK0. As a result, the phase-locking circuit 40 is properly synchronized in phase, so it can properly generate received signals RX-I and RX-Q and properly generate the output signal TX.

[0064] The example given was the case where a phase-modulated signal is transmitted and received as a semiconductor integrated circuit 104, but the semiconductor integrated circuit 104 only needs to include a receiving circuit and a transmitting circuit.

[0065] Furthermore, the semiconductor integrated circuit 104 can be realized as a chiplet, which is an element that constitutes a chiplet system. In a chiplet system, multiple chiplets are arranged on an interposer. Each chiplet is equipped with a receiving circuit 41R and a transmitting circuit 41T, and communication between chiplets is performed via connecting wiring provided within the interposer.

[0066] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified to the extent that they do not impair the spirit of the present invention, and can be appropriately determined according to their application.

[0067] 10 Clock generation circuit 11 Calibration circuit 12, 32 Phase detection circuit 14 Frequency detection circuit 15 Intermediate signal generation circuit 16A, 16B Amplifier circuit 17 Oscillation control circuit 17A Smoothing circuit 19 Feedback circuit 21 Arithmetic unit 22 Reference clock generation circuit 24, 26, 35 Adder 25, 30 Delay circuit 33 FPD state machine 41R Receiver circuit 41T Transmitter circuit

Claims

1. A phase-locking circuit comprising: a clock generation circuit for generating a clock signal; a phase detection circuit for generating a phase detection signal by comparing the phase of the clock signal with the phase of a feedback signal; a frequency detection circuit for generating a frequency detection signal by comparing the frequency of the clock signal with the frequency of the feedback signal; an intermediate signal generation circuit for generating an intermediate signal based on the phase detection signal and the frequency detection signal; a first amplification circuit for amplifying the phase detection signal and outputting a first output signal; a second amplification circuit for amplifying the intermediate signal and outputting a second output signal; an oscillation control circuit for generating an oscillation control signal based on the first output signal and the second output signal; an oscillation circuit for generating an output clock signal based on the oscillation control signal; and a feedback circuit for generating the feedback signal based on the output clock signal.

2. The phase-synchronization circuit according to claim 1, wherein the phase detection circuit outputs a first level as the phase detection signal when the phase of the feedback signal is ahead of the phase of the clock signal, and outputs a second level as the phase detection signal when the phase of the feedback signal is behind the phase of the clock signal, and the frequency detection circuit outputs a third level as the frequency detection signal when the frequency of the feedback signal is higher than the frequency of the clock signal, and outputs a fourth level as the frequency detection signal when the frequency of the feedback signal is lower than the frequency of the clock signal.

3. The phase-synchronization circuit according to claim 2, wherein the intermediate signal generation circuit generates the intermediate signal by adding the phase detection signal and the frequency detection signal.

4. The phase-synchronized circuit according to claim 3, wherein when the intermediate signal generation circuit adds the phase detection signal and the frequency detection signal, either the first level or the second level is a negative level, and the other of the first level or the second level is a positive level.

5. The phase-locked circuit according to claim 4, wherein the oscillator circuit is a digitally controlled oscillator circuit, and the intermediate signal is a trivalued or 2-bit signal.

6. The phase-locked circuit according to any one of claims 1 to 5, wherein the oscillation control circuit generates the oscillation control signal based on a smoothed signal obtained by smoothing the second output signal in time and the first output signal.

7. The phase-locked circuit according to claim 6, wherein the smoothed signal corresponds to the integral term of the oscillation control circuit, and the first output signal corresponds to the proportional term of the oscillation control circuit.

8. The phase synchronization circuit according to any one of claims 1 to 5, wherein the frequency detection circuit comprises: a delay circuit that delays the clock signal and outputs a delayed clock signal; another phase detection circuit that compares the phase of the feedback signal with the phase of the delayed clock signal and generates another phase detection signal; and a frequency detection signal generation circuit that generates the frequency detection signal based on the phase detection signal and the other phase detection signal.

9. The phase-locked circuit according to claim 8, wherein the delay circuit delays the clock signal for a time greater than 0 times and less than 1 / 2 times the period of the clock signal.

10. The phase-synchronized circuit according to claim 8, wherein the other phase detection circuit includes a Bang-Bang type phase detection circuit that operates on the delayed clock signal and the feedback signal to generate the other phase detection signal.

11. The phase-synchronized circuit according to any one of claims 1 to 5, wherein the phase detection circuit includes a Bang-Bang type phase detection circuit that operates based on the clock signal and the feedback signal and generates the phase detection signal.

12. A phase-locked circuit according to any one of claims 1 to 5, comprising a reference clock generation circuit that supplies a reference clock signal to the clock generation circuit, wherein the clock generation circuit generates the clock signal based on the reference clock signal.

13. A phase-synchronization circuit according to any one of claims 1 to 5, comprising a calibration circuit that performs calibration of the clock generation circuit based on the phase detection signal.

14. A semiconductor integrated circuit comprising: a phase-locked circuit according to any one of claims 1 to 5; a receiving circuit that generates a received signal from an input signal based on the output clock signal; and a transmitting circuit that generates an output signal from a transmitting signal based on the output clock signal.

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