Phase synchronization circuit and semiconductor integrated circuit

Abstract

This phase synchronization circuit comprises: a clock generation circuit that generates a clock signal by controlling the phase of a reference clock signal on the basis of a control signal; a phase detection circuit that compares the phase of the clock signal and the phase of a feedback signal so as to generate a phase detection signal; an oscillation control circuit that generates an oscillation control signal on the basis of the phase detection signal; an oscillation circuit that generates an output clock signal in which the frequency is controlled on the basis of the oscillation control signal; a feedback circuit that generates the feedback signal on the basis of the output clock signal; a lock determination circuit that determines whether the phase of the output clock signal is locked; and a calibration circuit that corrects the control signal on the basis of the phase detection signal and keeps a correction value of the control signal constant during a period in which the lock determination circuit has determined that the phase of the output clock signal is not locked.

Description

Phase synchronization circuit and semiconductor integrated circuit

[0001] The present invention relates to a phase synchronization circuit and a semiconductor integrated circuit.

[0002] It is known to use a DTC (Digital to Tine Convertor) in a phase synchronization circuit (PLL circuit: Phase Locked Loop circuit) (for example, Patent Documents 1 and 2). It is known to calibrate the gain of the DTC (for example, Patent Document 1).

[0003] U.S. Patent Application Publication No. 2009 / 0310587 Specification U.S. Patent Application Publication No. 2009 / 0212703 Specification

[0004] In a clock generation circuit such as a DTC, a phase error of the generated clock signal occurs due to a temperature change or a change over time. By correcting a control signal for controlling the clock generation circuit, the phase error of the clock signal can be reduced. However, when the phase of the output clock signal output by the phase synchronization circuit is not locked, correcting the control signal may cause the feedback for controlling the phase of the output clock signal to malfunction appropriately.

[0005] An object of the present disclosure is to provide a phase synchronization circuit and a semiconductor integrated circuit capable of appropriately performing feedback for controlling the phase of an output clock signal.

[0006] Embodiments of the present disclosure are phase-synchronization circuits comprising: a clock generation circuit that generates a clock signal by controlling the phase of a reference clock signal based on a control signal; a phase detection circuit that generates a phase detection signal by comparing the phase of the clock signal with the phase of a feedback signal; an oscillation control circuit that generates an oscillation control signal based on the phase detection signal; an oscillation circuit that generates an output clock signal with a controlled frequency based on the oscillation control signal; a feedback circuit that generates the feedback signal based on the output clock signal; a lock determination circuit that determines whether or not the phase of the output clock signal is locked; and a calibration circuit that corrects the control signal based on the phase detection signal and maintains a constant correction value of the control signal during the period when the lock determination circuit determines that the signal is not locked.

[0007] Embodiments of this disclosure are semiconductor integrated circuits comprising the above-mentioned phase-locking circuit, a receiving circuit that generates a received signal from an input signal based on the output clock signal, and a transmitting circuit that generates an output signal from a transmitted signal based on the output clock signal.

[0008] According to the disclosed technology, it is possible to properly implement feedback to control the phase of the output clock signal.

[0009] Figure 1 is a block diagram of the phase-synchronous circuit in the first embodiment. Figure 2 is a block diagram of the phase-synchronous circuit in the second embodiment. Figure 3 is a block diagram of the phase-synchronous circuit according to the first comparison form. Figure 4 is a block diagram of the calibration circuit in the second embodiment and the first comparison form. Figure 5 is a timing chart showing the operation of the phase detection circuit in the second embodiment and the first comparison form. Figure 6 is a diagram showing the delay time with respect to the control signal, showing the operation of the clock generation circuit in the second embodiment and the first comparison form. Figure 7 is a diagram showing the calibration control signal CC against time, showing the operation of the clock generation circuit in the second embodiment and the first comparison form. Figure 8 is a diagram showing the phase error against time, showing the operation of the calibration circuit in the second embodiment and the first comparison form. Figure 9 is a diagram showing the virtual signal Spd1 against time, showing the operation of the calibration circuit in the second embodiment and the first comparison form. Figure 10 is a diagram showing the virtual signal SCo against time, showing the operation of the calibration circuit in the second embodiment and the first comparison form. Figure 11 is a block diagram of the lock determination circuit in the second embodiment. Figure 12 is a timing chart of each signal showing the operation of the lock determination circuit in the second embodiment. Figure 13 is a block diagram of a semiconductor integrated circuit according to the third embodiment.

[0010] The embodiments for implementing this disclosure will be described in detail below with reference to the drawings. The embodiments described below are examples for realizing the technical concept of the invention and do not limit this disclosure to the configurations and numerical values ​​described. In each drawing, the same reference numerals are used for the same components, and redundant explanations may be omitted as appropriate.

[0011] (First Embodiment) Figure 1 is a block diagram of a phase-synchronous circuit in the first embodiment. As shown in Figure 1, the phase-synchronous circuit 100 according to the first embodiment includes a clock generation circuit 10, a calibration circuit 11, a phase detection circuit 12, a lock determination circuit 14, an oscillation control circuit 17, an oscillation circuit 18, and a feedback circuit 19.

[0012] The clock generation circuit 10 generates a clock signal R by controlling the phase of the reference clock signal OSC based on the calibration control signal CC. The phase detection circuit 12 compares the phase of the clock signal R with the phase of the feedback signal V and generates a phase detection signal pd1. The oscillation control circuit 17 generates an oscillation control signal DCO-F based on the phase detection signal pd1. The oscillation circuit 18 generates an output clock signal OUT with its frequency controlled based on the oscillation control signal DCO-F. The feedback circuit 19 generates a feedback signal V based on the output clock signal OUT. The lock determination circuit 14 determines whether the phase of the output clock signal OUT is locked and outputs a lock determination signal LD. The calibration circuit 11 performs calibration of the clock generation circuit 10. The calibration circuit 11 corrects the calibration control signal CC based on the phase detection signal pd1, and maintains a constant correction value for the calibration control signal CC based on the lock determination signal LD ​​during the period when the lock determination circuit 14 determines that it is not in a locked state.

[0013] In the phase-locking circuit 100 according to the first embodiment, the correction value of the calibration control signal CC is kept constant during periods when the phase of the output clock signal OUT is not locked. This prevents the control of the calibration circuit 11 from adversely affecting the control that locks the phase of the output clock signal OUT.

[0014] (Second Embodiment) The second embodiment is an example of an ADPLL (All Digital Phase Locked Loop) circuit. Figure 2 is a block diagram of the phase-locked circuit according to the second embodiment. As shown in Figure 2, the phase-locked circuit 102 according to the second embodiment includes, in addition to the phase-locked circuit 100 according to the first embodiment, an arithmetic unit 21, a reference clock generation circuit 22, a logic circuit 23, and amplification circuits 16A and 16B. The reference clock generation circuit 22 generates a reference clock signal OSC to be supplied to the clock generation circuit 10. The arithmetic unit 21 generates a frequency control signal FC by integrating the frequency control word FCW and performing a modulo operation. The clock generation circuit 10 is a DTC (Digital Time Converter) and generates a clock signal R having a specified frequency by controlling the phase of the reference clock signal OSC based on a calibration control signal CC. For example, the clock generation circuit 10 generates the clock signal R by delaying the reference clock signal OSC based on the calibration control signal CC.

[0015] The phase detection circuit 12 is a BBPD (Bang-Bang Phase Detector) that compares the phase of the feedback signal V with the phase of the clock signal R and outputs a phase detection signal pd1 indicating whether the phase of the feedback signal V is leading or lagging the phase of the clock signal R. The phase detection circuit 12 includes a Bang-Bang type phase detection circuit that operates based on the clock signal R and the feedback signal V and outputs a phase detection signal pd1. The logic circuit 23 converts the level of the phase detection signal pd1 output by the phase detection circuit 12. When the phase detection signal pd1 is "1", the logic circuit 23 sets the input signal to the calibration circuit 11 to "+1", and when the phase detection signal pd1 is "0", it sets the input signal to the calibration circuit 11 to "-1". Based on the phase detection signal pd1, the calibration circuit 11 corrects the frequency control signal FC to generate a calibration control signal CC. The correction of the frequency control signal FC is, for example, a correction to correct the gain of the clock generation circuit 10. The lock determination circuit 14 determines whether the phase of the output clock signal OUT is in a locked state based on the phase detection signal pd1, and outputs the determination result as a lock determination signal LD.

[0016] Amplifier circuits 16A and 16B amplify the phase detection signal pd1 based on coefficients Kp and Ki, respectively, and output output signals O1 and O2, respectively. Amplifier circuit 16A (first amplifier circuit) amplifies the phase detection signal pd1 and outputs output signal O1 (first output signal) corresponding to the proportional term of the oscillation control circuit 17. Amplifier circuit 16B (second amplifier circuit) amplifies the phase detection signal pd1 and outputs output signal O2 (second output signal) corresponding to the integral term of the oscillation control circuit 17. The oscillation control circuit 17 includes a smoothing circuit 17A and an adder 26. The smoothing circuit 17A includes an adder 24 and a delay circuit 25. The adder 24 adds the output of the delay circuit 25 and the output signal O2 and outputs it to the delay circuit 25. The delay circuit 25 delays the input signal by 1 clock cycle and outputs it to the adder 24. As a result, a smoothed signal Integ, obtained by smoothing the output signal O2 over time, is output from the smoothing circuit 17A. The adder 26 adds the output signal O1 and the smoothed signal Integ to generate an oscillation control signal DCO-F.

[0017] The oscillation circuit 18 is a DCO (Digitally Controlled Oscillator), a digitally controlled oscillation circuit that outputs an output clock signal OUT with a frequency based on the oscillation control signal DCO-F. The feedback circuit 19 is a 1 / N (N is an integer of 2 or more) frequency divider that generates a feedback signal V having a frequency of 1 / N of the output clock signal OUT frequency.

[0018] In the second embodiment, the phase-locked circuit 102 generates the output clock signal OUT generated by the oscillator circuit 18 based on the clock signal R and a feedback signal V obtained by dividing the output clock signal OUT by 1 / N. This makes it possible to set the frequency of the output clock signal OUT to N times the frequency of the clock signal R.

[0019] (First Comparison Configuration) Figure 3 is a block diagram of the phase-synchronous circuit according to the first comparison configuration. As shown in Figure 3, the phase-synchronous circuit 110 according to the first comparison configuration does not include a lock determination circuit 14. As a result, the calibration circuit 11 corrects the frequency control signal FC and outputs a calibration control signal CC to the clock generation circuit 10 regardless of whether the phase of the output clock signal OUT is in a locked state or not. The other configurations are the same as the phase-synchronous circuit 102 of the second embodiment and will not be described further.

[0020] Figure 4 is a block diagram of the calibration circuit in the second embodiment and the first comparative embodiment. As shown in Figure 4, the calibration circuit 11 includes multipliers 30, 34, an amplifier circuit 31, a smoothing circuit 32, and an adder 33.

[0021] The multiplier 30 multiplies the phase detection signal pd1 and the frequency control signal FC to generate the signal Co. The amplifier circuit 31 amplifies the signal Co by a coefficient Kc and outputs the signal Co'. The smoothing circuit 32 performs a smoothing process to smooth the signal Co'. The smoothing circuit 32 includes an adder 32A and a delay circuit 32B. The adder 32A adds the output of the delay circuit 32B and the signal Co' and outputs it to the delay circuit 32B. The delay circuit 32B delays the input signal by one clock cycle and outputs it to the adder 32A. As a result, a signal with the signal Co' smoothed in time is output from the smoothing circuit 32 as the signal GE. The lock determination signal LD ​​is input to the smoothing circuit 32 as a reset signal Reset. When the lock determination signal LD ​​indicates that the phase-locked circuit is not in a locked state, the smoothing circuit 32 is initialized and outputs a constant value, for example, "0", as the signal GE. When the lock determination signal LD ​​indicates that the phase-locked circuit is locked, the initialization of the smoothing circuit 32 is released, and the smoothing circuit 32 performs the smoothing process described above. The adder 33 adds a constant level LE (e.g., 1.0) to the signal GE and outputs the signal GE'. The multiplier 34 multiplies the signal GE' by the frequency control signal FC and outputs the calibration control signal CC. As will be described later, the signal GE is a signal that indicates the gain error (gain error) of the delay time relative to the calibration control signal CC.

[0022] (Operation of Phase Detection Circuit 12) Figure 5 is a timing chart showing the operation of the phase detection circuit in the second embodiment and the first comparative embodiment. The phase detection circuit 12 is, for example, a BBPD. The BBPD is, for example, a D-FF (Delay Flip Flop). In the phase detection circuit 12, for example, the clock signal R and the feedback signal V are input to the clock terminal CK and data terminal D of the D-FF, respectively. The phase detection signal pd1 is output from the output terminal Q of the D-FF.

[0023] As a result, at time t1, when the clock signal R rises, the feedback signal V is "1" and the phase detection signal pd1 is "1". This "1" state is maintained thereafter. If the frequency of the feedback signal V is higher than the frequency of the clock signal R, the rising edge timing of the feedback signal V gradually becomes earlier than the rising edge timing of the clock signal R. At times t2 and t3, the feedback signal V is "1" and the phase detection signal pd1 is "1". At time t4, when the clock signal R rises, the feedback signal V becomes "0". At this time, the phase detection signal pd1 becomes "0" and this "0" state is maintained thereafter. At time t5, the feedback signal V is "0" and the phase detection signal pd1 is "0".

[0024] As described above, the phase detection signal pd1 becomes "1" when the phase of the feedback signal V leads the phase of the clock signal R, and remains "1" until the phase of the feedback signal V lags behind the phase of the clock signal R. The phase detection signal pd1 becomes "0" when the phase of the feedback signal V lags behind the phase of the clock signal R, and remains "0" until the phase of the feedback signal V leads the phase of the clock signal R.

[0025] (Operation of Clock Generation Circuit 10) Figure 6 is a diagram showing the delay time relative to the calibration control signal, illustrating the operation of the clock generation circuit in the second embodiment and the first comparative embodiment. The clock generation circuit 10, which is a DTC, outputs a reference clock signal OSC with a delay according to the calibration control signal CC, which is a control code. The horizontal axis is the calibration control signal CC, and the vertical axis is the delay time for delaying the reference clock signal OSC. The straight line 50A shows the relationship between the reference calibration control signal CC and the delay time. The smaller the calibration control signal CC, the shorter the delay time, and the larger the calibration control signal CC, the longer the delay time. When the calibration control signal CC is 0, the delay time is T0.

[0026] Figure 7 is a diagram showing the calibration control signal CC with respect to time, illustrating the operation of the clock generation circuit in the second embodiment and the first comparative embodiment. Line 51A shows the relationship between the reference time and the calibration control signal CC. For example, in Figure 4, if the gain of the delay time relative to the calibration control signal CC matches the desired reference value and there is no gain error, the signal GE in Figure 4 is a signal indicating the gain error. From this, when GE = 0 and LE = 1.0, GE' = 1.0, and the calibration control signal CC becomes the frequency control signal FC itself. The arithmetic unit 21 integrates the frequency control word FCW and performs a modulo operation. The frequency control word FCW is a constant value corresponding to the frequency of the clock signal R generated by the clock generation circuit 10. As a result, the frequency control signal FC corresponds to the calibration control signal CC on line 51A, becoming C1 at time t6, 0 at time t7, and C2 at time t8. Immediately after time t8, the frequency control signal FC returns to C1, and becomes 0 and C2 at times t9 and t10. As a result, the frequency control signal FC increases linearly from C1 over time, and returns to C1 after a certain period, becoming a sawtooth wave.

[0027] As shown in Figure 7, when the calibration control signal CC gradually increases from time t6 to t8, the delay time gradually increases from time t6 to t8, as shown in Figure 6. As a result, the clock generation circuit 10 generates a clock signal R with a frequency lower than the reference clock signal OSC. By setting the gain of the delay time for the calibration control signal CC so that the phase of the clock signal R when the calibration control signal CC is C1 matches the phase of the clock signal R when the calibration control signal CC is C2 at time t8, the phase of the clock signal R changes continuously at time t8. The frequency of the clock signal R can be changed by changing the slope of the calibration control signal CC with respect to time.

[0028] (Operation of Calibration Circuit 11) Due to temperature changes or changes over time in the clock generation circuit 10, the gain of the delay time relative to the calibration control signal CC may change from the desired reference value. As shown in Figure 6, when the gain changes, the slope of the straight line 50A changes. The straight line 50B has a larger gain than the reference straight line 50A, and the straight line 50C has a smaller gain than the reference straight line 50A. When the calibration control signal CC is 0, the delay time T0 does not change even if the gain changes.

[0029] Figure 8 shows the phase error with respect to time, illustrating the operation of the calibration circuit in the second embodiment and the first comparative embodiment. The vertical axis shows the phase error in the clock signal R. Lines 52A, 52B, and 52C show the phase error when the relationship between the calibration control signal CC and the delay time is as shown by lines 50A, 50B, and 50C in Figure 6, respectively.

[0030] As shown by the line 52A in Figure 8, when the relationship between the calibration control signal CC and the delay time is the line 50A, the phase error of the clock signal R is almost zero, and there is almost no phase error. When the relationship between the calibration control signal CC and the delay time is the line 50B, at time t6, the delay time is smaller than that of line 50A. Therefore, the phase of the clock signal R leads the desired phase. Thus, the phase error is positive, as shown by line 52B. At time t7, the phase error is almost zero. At time t8, the delay time is greater than that of line 50A. Therefore, the phase of the clock signal R lags behind the desired phase. Thus, the phase error is negative, as shown by line 52B. The phase errors at times t9 and t10 are the same as the phase errors at times t7 and t8. When the relationship between the calibration control signal CC and the delay time is the line 50C, at time t6, the phase error is negative, as shown by line 52C. At time t7, the phase error is almost zero. At time t8, the phase error is positive, as shown by line 52C. The phase errors at times t9 and t10 are the same as the phase errors at times t7 and t8.

[0031] As shown in Figure 6, if the gain of the delay time for the calibration control signal CC deviates from the desired reference value, a phase error occurs, as shown in Figure 8. At time t8, the phase of the clock signal R becomes discontinuous, causing spurious signals and other problems.

[0032] Figure 9 shows the virtual signal Spd1 against time, illustrating the operation of the calibration circuit in the second embodiment and the first comparative embodiment. The phase detection signal pd1 becomes a toggle signal when the phase of the output clock signal OUT is locked, as will be described later. The vertical axis represents the virtual signal Spd1 obtained by virtually smoothing the phase detection signal pd1. The logic circuit 23 converts the level of the phase detection signal pd1 so that when the phase detection signal pd1 is "1" and "0" in Figure 5, it becomes "+1" and "-1", respectively. Figures 9(A), (B), and (C) correspond to the cases of the lines 52A, 52B, and 52C in Figure 8.

[0033] As shown in Figure 8, the phase error affects the output signal of the phase detection circuit 12, which operates based on the clock signal R, and thus appears in the virtual signal Spd1. In the case of lines 52A, 52B, and 52C in Figure 8, the virtual signals Spd1 are lines 53A, 53B, and 53C, respectively.

[0034] As shown in Figure 9(A), in the case of the straight line 52A in Figure 8, the phase error is almost 0, so the virtual signal Spd1 obtained by smoothing the phase detection signal pd1 is almost 0. As shown in (B), between times t6 and t7, the phase of the clock signal R is earlier than the reference phase. The feedback signal V is later than the phase of the clock signal R, and the line 53B of the virtual signal Spd1 becomes negative. Between times t7 and t8, the phase of the clock signal R is later than the reference phase. The feedback signal V is earlier than the phase of the clock signal R, and the line 53B of the virtual signal Spd1 becomes positive. As shown in (C), in the case of the straight line 52C in Figure 8, between times t6 and t7, the line 53C of the virtual signal Spd1 is positive, and between times t7 and t8, the line 53C of the virtual signal Spd1 is negative.

[0035] Figure 10 is a diagram showing the operation of the calibration circuit in the second embodiment and the first comparative embodiment, representing a virtual signal SCo with respect to time. As is clear from Figure 4, the virtual signal SCo is a virtual signal obtained by multiplying the virtual signal Spd1 in Figure 9 with the frequency control signal FC corresponding to line 51A in Figure 7, taking into consideration that the phase detection signal pd1 becomes a toggle signal when the phase of the output clock signal OUT is locked. The virtual signals SCo obtained by multiplying the virtual signals Spd1 corresponding to lines 53A, 53B, and 53C in Figure 9 with the frequency control signal FC corresponding to line 51A in Figure 7 are lines 54A, 54B, and 54C, respectively.

[0036] As shown in Figure 10, when line 53A and line 51A are multiplied, line 53A is approximately 0, so the virtual signal SCo is approximately 0 regardless of time, as shown by line 54A. When line 53B and line 51A are multiplied, between times t6 and t7, both line 53B and line 51A are negative, and line 54B is positive. Between times t7 and t8, both line 53C and line 51A are positive, so the virtual signal SCo is positive, as shown by line 54B. When line 53C and line 51A are multiplied, between times t6 and t7, line 53C is positive and line 51A is negative, so the virtual signal SCo is negative, as shown by line 54C. Between times t7 and t8, line 53C is negative and line 51A is positive, so the virtual signal SCo is negative, as shown by line 54C. As described above, when the line 50B in Figure 6 is followed, the virtual signal SCo is positive, and when the straight line 50C in Figure 6 is followed, the virtual signal SCo is negative.

[0037] The calibration circuit 11 corrects lines 51B and 51C in Figure 7 using the virtual signal SCo. Returning to Figure 4, the operation of the calibration circuit 11 will now be explained. Signal GE is obtained by multiplying the phase detection signal pd1 and the frequency control signal FC, amplifying the multiplication result, and smoothing it. Signal GE corresponds to the signal obtained by averaging the virtual signal SCo, and is a signal that indicates the error (gain error) in the delay time gain (gain of the clock generation circuit 10) with respect to the calibration control signal CC. Here, in order to realize a negative feedback calibration loop that compensates for the gain error, the coefficient Kc of the amplification circuit 31 is set to negative.

[0038] As shown by line 50A in Figure 6, when the gain of the clock generation circuit 10 is at the desired reference value, the virtual signal SCo is 0, as shown by line 54A in Figure 10. Therefore, signal GE is 0, and when LE = 1.0, signal GE' is 1. When the multiplier 34 multiplies the frequency control signal FC by signal GE', the calibration control signal CC becomes the frequency control signal FC itself.

[0039] As shown by the line 50B in Figure 6, when the gain of the clock generation circuit 10 is greater than the desired reference value, the virtual signal SCo is positive, as shown by line 54B in Figure 10. Since the coefficient Kc of the amplifier circuit 31 is negative, the signal GE is negative. Therefore, the signal GE' becomes less than 1. When the multiplier 34 multiplies the frequency control signal FC by the signal GE', the calibration control signal CC becomes a straight line with a smaller slope than line 51A, as shown by line 51B in Figure 7. Therefore, as shown by the line 50B in Figure 6, if the gain increases due to temperature changes or changes over time, the gain can be corrected by reducing the slope of the calibration control signal CC.

[0040] As shown by the line 50C in Figure 6, when the gain of the clock generation circuit 10 is smaller than the desired reference value, the virtual signal SCo is negative and the signal GE is positive, as shown by line 54C in Figure 10. Therefore, the signal GE' becomes greater than 1. When the multiplier 34 multiplies the frequency control signal FC by the signal GE', the calibration control signal CC becomes a straight line with a steeper slope than line 51A, as shown by line 51C in Figure 7. Thus, as shown by the line 50C in Figure 6, if the gain decreases due to temperature changes or changes over time, the gain can be corrected by increasing the slope of the calibration control signal CC.

[0041] (Problems with the first comparative configuration) In the first comparative configuration shown in Figure 3, the calibration circuit 11 performs calibration of the clock generation circuit 10 regardless of the phase lock state of the output clock signal OUT. When the calibration circuit 11 operates when the phase is not locked, it will simultaneously control the oscillation control circuit 17 and the calibration circuit 11, and the phase-locking circuit may not be able to control the phase to a locked state or it may take a long time to reach a locked state.

[0042] (Description of the Second Embodiment) (Operation of the Lock Determination Circuit 14) Therefore, in the phase synchronization circuit 102 of the second embodiment, a lock determination circuit 14 is provided. FIG. 11 is a block diagram of the lock determination circuit in the second embodiment. As shown in FIG. 11, the lock determination circuit 14 includes a D-FF circuit 35, an XOR circuit 36, a switch 37, an adder 38, a saturation circuit 39, a D-FF circuit 28, and a comparator 29.

[0043] FIG. 12 is a timing chart of each signal showing the operation of the lock determination circuit in the second embodiment. Before time tL is the convergence period, which is a period for controlling the oscillation control signal DCO-F to converge the frequency and phase of the output clock signal OUT. After time tL, it is in the locked state, where the frequency and phase of the output clock signal OUT are locked. During the convergence period, the periods between "1" and between "0" of the phase detection signal pd1 gradually become longer. At time tL, when it enters the locked state, the phase detection signal pd1 becomes a 1 / 0 toggle signal.

[0044] As shown in FIGS. 11 and 12, the phase detection signal pd1 is input to the data terminal D of the D-FF circuit 35, and the output signal from the output terminal Q of the D-FF circuit 35 and the phase detection signal pd1 are input to the XOR circuit 36. The clock signal R is input to the clock terminal CK of the D-FF circuit 35, and the D-FF circuit 35 operates in response to the clock signal R. The XOR circuit 36 outputs a signal ST. The signal ST becomes "1" when the phase detection signal pd1 shifts from "0" to "1" or from "1" to "0", and is "0" otherwise.

[0045] The switch 37 outputs "-1" and "16" when the signal ST is 0 and 1, respectively. The switch 37 outputs negative and positive values when the signal ST is 0 and 1, respectively, as long as the positive value is sufficiently larger than the absolute value of the negative value.

[0046] The adder 38 adds the signal from the switch 37 and the output signal TC of the D-FF circuit 28. The saturation circuit 39 outputs 0 if the output signal of the adder 38 is, for example, 0 or less, outputs 255 if it is, for example, 255 or more, and outputs the output signal of the adder 38 as is otherwise. The output signal of the saturation circuit 39 is input to the data terminal D of the D-FF circuit 28, and the output signal TC from the output terminal Q of the D-FF circuit 28 and a signal indicating the threshold Th are input to the comparator 29. The clock signal R is input to the clock terminal CK of the D-FF circuit 28, and the D-FF circuit 28 operates in response to the clock signal R. The adder 38, saturation circuit 39, and D-FF circuit 28 constitute an up-down counter circuit. The up-down counter circuit is, for example, an 8-bit counter.

[0047] As shown in 55A of Figure 12, when signal ST becomes "1", switch 37 outputs "16", so signal TC becomes, for example, "16", as in 55B. Subsequently, if signal ST continues to be "0", switch 37 continues to output "-1", so signal TC gradually decreases. Due to the saturation circuit 39, signal TC cannot go below 0, so signal TC becomes 0. Subsequently, if the period during which phase detection signal pd1 switches between "1" and "0" is long, as in 55B, signal TC will return to "0" even if it becomes "16".

[0048] When in the locked state, the phase detection signal pd1 becomes a toggle signal. Therefore, the interval during which the signal ST becomes "1" is narrow. Thus, before the signal TC returns to 0, the output signal of the switch 37 becomes "16" and gradually increases like 55C. When the signal TC is less than the threshold Th, the comparator 29 sets the lock determination signal LD to 0, and the lock determination circuit 14 determines that the phase synchronization circuit 102 is not in the locked state. When the signal TC is greater than or equal to the threshold Th, the comparator 29 sets the lock determination signal LD to 1, and the lock determination circuit 14 determines that the phase synchronization circuit 102 is in the locked state. In FIG. 12, at time tL, when the signal TC becomes greater than or equal to the threshold Th (for example, 240), the comparator 29 sets the lock determination signal LD to 1, and the lock determination circuit 14 determines that the phase synchronization circuit 102 is in the locked state. By appropriately setting the value of the switch 37 and the value of the threshold Th, it is possible to determine whether the period of the phase detection signal pd1 is a toggle signal with a period less than a predetermined threshold, and it is possible to appropriately determine whether the phase synchronization circuit is in the locked state.

[0049] As described above, the lock determination circuit 14 drives the up / down counter based on the 1 / 0 toggle signal generated by detecting the transition point of the phase detection signal pd1. Thereby, when the signal is a toggle signal, the lock determination circuit 14 determines that it is in the locked state, and when the phase detection signal pd1 is not a toggle signal, it determines that it is not in the locked state. Thereby, during the period when the lock determination signal LD is "0", the calibration circuit 11 does not perform calibration of the gain of the clock generation circuit 10, and during the period when the lock determination signal LD is "1", the calibration circuit 11 performs calibration of the gain of the clock generation circuit 10. Thereby, when not in the locked state, the calibration circuit 11 does not operate, so that it is possible to suppress the situation where the phase synchronization circuit cannot be controlled to the locked state or it takes time to reach the locked state.

[0050] According to the second embodiment, the lock determination circuit 14 determines whether the phase of the output clock signal OUT is locked or not. The calibration circuit 11 maintains a constant correction value for the calibration control signal CC during the period when the lock determination circuit 14 determines that the signal is not locked. For example, in Figure 4, based on the lock determination signal LD ​​of "0", the smoothing circuit 32 maintains its initial state and maintains the value of the signal GE at a constant value, for example, "0". As a result, the calibration circuit 11 does not correct the calibration control signal CC during the period when the lock determination circuit 14 determines that the signal is not locked. Therefore, it is possible to suppress the phase synchronization circuit from being unable to control the output clock signal OUT to a locked state or from taking a long time to reach a locked state, and to appropriately perform feedback to control the phase of the output clock signal OUT.

[0051] The calibration circuit 11 stops maintaining a constant correction value for the calibration control signal CC during the period when the lock determination circuit 14 determines that the device is in a locked state, and corrects the calibration control signal CC based on the phase detection signal pd1. For example, in Figure 4, based on the lock determination signal LD ​​labeled "1", the initialization of the smoothing circuit 32 is released, the smoothing circuit 32 performs smoothing processing, and outputs a signal with signal Co' smoothed over time as signal GE. This suppresses spurious signals caused by discontinuities in the phase of the clock signal R, etc.

[0052] As shown in Figure 6, the clock generation circuit 10 generates a clock signal R by delaying the reference clock signal OSC by a delay time represented by the value obtained by multiplying the calibration control signal CC by a gain. In such a clock generation circuit 10, if the gain changes due to temperature changes or changes over time, a phase discontinuity occurs in the clock signal R. Therefore, when the lock determination circuit 14 determines that the system is not in a locked state, it is preferable to keep the correction value of the calibration control signal CC constant.

[0053] Correcting the calibration control signals CC, such as lines 51B and 51C in Figure 7, corresponds to correcting the slope (i.e., gain) of the straight line in Figure 6. This allows the gain of the clock generation circuit 10 to be corrected.

[0054] As shown in Figure 7, the calibration control signal CC is a sawtooth wave. This allows the clock generation circuit 10 to generate the clock signal R by changing the frequency of the reference clock signal OSC.

[0055] As shown in Figure 5, the phase detection circuit 12 outputs a first level as the phase detection signal pd1 when the phase of the feedback signal V leads the phase of the clock signal R, and outputs a second level as the phase detection signal pd1 when the phase of the feedback signal V lags behind the phase of the clock signal R. When such a phase detection signal pd1 is used to control the oscillation control circuit 17, spurious signals are likely to occur if there is a discontinuity in the phase of the clock signal R. Therefore, it is preferable to keep the correction value of the calibration control signal CC constant during the period when the lock determination circuit 14 determines that the system is not in a locked state.

[0056] As shown in Figure 10, the calibration circuit 11 calculates a correction value for the calibration control signal CC based on the value obtained by multiplying the phase detection signal pd1 by the calibration control signal CC. This allows detection of whether the gain of the clock generation circuit 10 is greater than or less than the desired reference value linear curve 50A. The calibration circuit 11 may also calibrate the clock generation circuit 10 using a circuit configuration other than the one shown in Figure 4.

[0057] The phase detection signal pd1 becomes a toggle signal in the locked state. Therefore, as shown in Figures 11 and 12, the lock determination circuit 14 determines that the system is locked when the period of the phase detection signal pd1 is a toggle state with a period shorter than the threshold determined by the value of the switch 37 and the threshold Th. In this way, the lock determination circuit 14 can determine whether or not the system is locked. Note that the lock determination circuit 14 may also determine whether or not the phase detection signal pd1 is in a toggle state using a circuit configuration other than those shown in Figures 11 and 12. The lock determination circuit 14 may also determine whether or not the system is locked using a method other than the method used to determine whether or not the phase detection signal pd1 is in a toggle state.

[0058] (Third Embodiment) The third embodiment is an example of a semiconductor integrated circuit equipped with a phase-locked circuit of the first or second embodiment. Figure 13 is a block diagram of the semiconductor integrated circuit according to the third embodiment. As shown in Figure 13, the semiconductor integrated circuit 104 according to the third embodiment includes a phase-locked circuit 40, a receiving circuit 41R, a transmitting circuit 41T, and a processing circuit 48. The receiving circuit 41R includes a low-noise amplifier 42R, a phase shifter 43R, mixers 44R, 45R, and a distributor 46R. The transmitting circuit 41T includes a power amplifier 42T, a phase shifter 43T, mixers 44T, 45T, and a combiner 46T.

[0059] The phase-locking circuit 40 is a phase-locking circuit according to the first or second embodiment. The phase-locking circuit 40 outputs a locked clock signal CK0 based on an external clock signal X'tal. The phase shifters 43R and 43T generate clock signals CK1 and CK2 from the clock signal CK0, which have the same frequency as the clock signal CK0 but are shifted in phase by 90° from each other.

[0060] In the receiving circuit 41R, the low-noise amplifier 42R amplifies the input signal RX. The distributor 46R distributes the amplified input signal RX into two signals, RX1 and RX2. The mixer 44R mixes the clock signal CK1 and signal RX1 to generate the received signal RX-I. The mixer 45R mixes the clock signal CK2 and signal RX2 to generate the received signal RX-Q. The processing circuit 48 acquires the received signals RX-I and RX-Q and processes them based on the acquired received signals RX-I and RX-Q.

[0061] The processing circuit 48 outputs the transmission signals TX-I and TX-Q. In the transmission circuit 41T, the mixer 44T mixes the clock signal CK1 and the transmission signal TX-I to generate signal TX1. The mixer 45T mixes the clock signal CK2 and the transmission signal TX-Q to generate signal TX2. The combiner 46T combines signals TX1 and TX2. The power amplifier 42T amplifies the combined signal and outputs it as the output signal TX.

[0062] According to the third embodiment, the semiconductor integrated circuit 104 includes the phase-locking circuit 40 of the first or second embodiment. The receiving circuit 41R generates received signals RX-I and RX-Q from the input signal RX based on the clock signal CK0 (output clock signal) output by the phase-locking circuit 40. The transmitting circuit 41T generates the output signal TX from the transmitted signals TX-I and TX-Q based on the clock signal CK0, so the phase-locking circuit 40 is properly synchronized in phase. As a result, the received signals RX-I and RX-Q can be properly generated, and the output signal TX can be properly generated.

[0063] The example given was when a semiconductor integrated circuit 104 transmits and receives a phase-modulated signal, but the semiconductor integrated circuit 104 only needs to include a receiving circuit and a transmitting circuit.

[0064] Furthermore, the semiconductor integrated circuit 104 can be formed as a chiplet, which is an element that constitutes a chiplet system. In a chiplet system, multiple chiplets are arranged on an interposer. Each chiplet is equipped with a receiving circuit 41R and a transmitting circuit 41T, and communication between chiplets is performed via connecting wiring provided within the interposer.

[0065] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application.

[0066] 10 Clock generation circuit 11 Calibration circuit 12 Phase detection circuit 14 Lock determination circuit 16A, 16B, 31 Amplifier circuit 17 Oscillator control circuit 17A, 32 Smoothing circuit 19 Feedback circuit 24, 26, 32A Adder 25, 32B Delay circuit 21 Arithmetic unit 22 Reference clock generation circuit 28 D-FF circuit 29 Comparator 30, 34 Multiplier 35 D-FF circuit 36 ​​XOR circuit 37 Switch 39 Saturation circuit 41R Receiver circuit 41T Transmitter circuit

Claims

1. A phase-synchronization circuit comprising: a clock generation circuit that generates a clock signal by controlling the phase of a reference clock signal based on a control signal; a phase detection circuit that generates a phase detection signal by comparing the phase of the clock signal with the phase of a feedback signal; an oscillation control circuit that generates an oscillation control signal based on the phase detection signal; an oscillation circuit that generates an output clock signal with a controlled frequency based on the oscillation control signal; a feedback circuit that generates the feedback signal based on the output clock signal; a lock determination circuit that determines whether or not the phase of the output clock signal is locked; and a calibration circuit that corrects the control signal based on the phase detection signal and maintains a constant correction value for the control signal during the period when the lock determination circuit determines that the signal is not locked.

2. The phase-locked circuit according to claim 1, wherein the calibration circuit does not correct the control signal during the period in which the lock determination circuit determines that the device is not in a locked state.

3. The phase-locked circuit according to claim 1, wherein the calibration circuit stops maintaining a constant correction value for the control signal and corrects the control signal during the period when the lock determination circuit determines that the state is locked.

4. The phase-locked circuit according to any one of claims 1 to 3, wherein the clock generation circuit generates the clock signal by delaying the reference clock signal by a delay time represented by a value obtained by multiplying the control signal by a gain.

5. The phase-locked circuit according to claim 4, wherein the correction of the control signal corresponds to the correction of the gain.

6. The phase-locked circuit according to any one of claims 1 to 3, wherein the control signal is a sawtooth wave.

7. The phase-synchronization circuit according to claim 6, wherein the phase detection circuit outputs a first level as the phase detection signal when the phase of the feedback signal is ahead of the phase of the clock signal, and outputs a second level as the phase detection signal when the phase of the feedback signal is behind the phase of the clock signal.

8. The phase-synchronization circuit according to claim 7, wherein the calibration circuit calculates a correction value for the control signal based on the value obtained by multiplying the phase detection signal by the control signal.

9. The phase synchronization circuit according to any one of claims 1 to 3, wherein the lock determination circuit determines that the state is locked when the period of the phase detection signal is in a toggle state with a period shorter than a threshold.

10. The phase-synchronous circuit according to any one of claims 1 to 3, wherein the lock determination circuit determines the lock state by driving an up-down counter based on a toggle signal generated by detecting the transition point of the phase detection signal.

11. The phase-synchronous circuit according to any one of claims 1 to 3, wherein the lock determination circuit outputs a lock determination signal indicating whether or not the phase of the output clock signal is locked, and the calibration circuit operates based on the lock determination signal.

12. A phase-locked circuit according to any one of claims 1 to 3, comprising a reference clock generation circuit that supplies the reference clock signal to the clock generation circuit.

13. The phase-locking circuit according to any one of claims 1 to 3, wherein the oscillation circuit is a digitally controlled oscillation circuit, the phase detection circuit includes a Bang-Bang type phase detection circuit that operates based on the clock signal and the feedback signal and outputs the phase detection signal, and the phase-locking circuit comprises a first amplification circuit that amplifies the phase detection signal and outputs a first output signal corresponding to the proportional term of the oscillation control circuit, and a second amplification circuit that amplifies the phase detection signal and outputs a second output signal corresponding to the integral term of the oscillation control circuit.

14. A semiconductor integrated circuit comprising: a phase-locked circuit according to any one of claims 1 to 3; a receiving circuit that generates a received signal from an input signal based on the output clock signal; and a transmitting circuit that generates an output signal from a transmitting signal based on the output clock signal.

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