Photodetector and electronic apparatus

Abstract

A photodetector includes a first substrate and a second substrate. The first substrate includes a photoelectric converter, an electric charge accumulator, and a first bonding surface. The second substrate includes a semiconductor material including a first semiconductor part and a second semiconductor part, a through via, a second bonding surface, and a first wiring layer. The first wiring layer includes a coupling part. Each of the first semiconductor part and the second semiconductor part includes a semiconductor surface having at least one semiconductor element. The at least one semiconductor element is included in a readout circuit that outputs a first signal based on the electric charge. The second bonding surface is positioned on an opposite side of the semiconductor material to the semiconductor element formation surface and is bonded to the first bonding surface. The first wiring layer is positioned between the semiconductor material and the second bonding surface.

Description

PHOTODETECTOR AND ELECTRONIC APPARATUSCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP2024-196243 filed November 8, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a photodetector including multiple semiconductor layers that are stacked on each other, and to an electronic apparatus.

[0003] For example, NPTL 1 discloses a Complementary Metal Oxide Semiconductor (CMOS) image sensor of a three-layered structure in which a top wafer, a middle wafer, and a bottom wafer are stacked. The top wafer includes a photodiode, a transfer gate, and the like. The middle wafer includes a pixel transistor. The bottom wafer includes a logic circuit.

[0004] [NPTL 1] Gwi-Deok Ryan Lee et al., "A 0.5 μm Pixel 3-layer Stacked CMOS Image Sensor with Deep Contact and In-pixel Cu-Cu Bonding Technology", 2023 International Electron Devices Meeting (IEDM).Summary

[0005] It is desired for such a photodetector to achieve higher integration without being deteriorated in photodetection performance.

[0006] It is therefore desirable to provide a photodetector and an electronic apparatus that each makes it possible to achieve both improvement in performance and higher integration.

[0007] A photodetector according to an embodiment of the present disclosure includes a first substrate and a second substrate. The first substrate includes a photoelectric converter, an electric charge accumulator, and a first bonding surface. The photoelectric converter generates electric charge by performing photoelectric conversion on light. The electric charge accumulator accumulates the electric charge. The second substrate includes a semiconductor layer, a through via, a second bonding surface, and a first wiring layer. The semiconductor layer includes an element formation surface and has a through hole. The element formation surface is a surface on which a semiconductor element is provided. The semiconductor element is included in a readout circuit that outputs a first signal based on the electric charge. The through hole extends in a first direction from the element formation surface. The through via is disposed in the through hole and is electrically coupled to the electric charge accumulator. The second bonding surface is positioned on the opposite side of the semiconductor layer to the element formation surface and is bonded to the first bonding surface. The first wiring layer is positioned between the semiconductor layer and the second bonding surface.

[0008] An electronic apparatus according to an embodiment of the present disclosure includes the photodetector according to the embodiment described above.

[0009] In the photodetector and the electronic apparatus according to the embodiments of the present disclosure, the wiring layer is provided on the opposite side of the semiconductor layer to the element formation surface in the second substrate. This reduces complication of wirings on the element formation surface side. In addition, it is possible to electrically couple, via the first wiring layer, a part, of the semiconductor layer, around the through via that is coupled to the electric charge accumulator and extends through the semiconductor layer, and the semiconductor element. Therefore, it is possible to reduce parasitic capacitance between the through via and the semiconductor around the through via by the Miller effect. As a result, photoelectric conversion efficiency improves.

[0010] Fig. 1 is a block diagram illustrating an example of a functional configuration of an imaging device according to an embodiment of the present disclosure.Fig. 2 is an equivalent circuit diagram of a pixel sharing unit illustrated in Fig. 1.Fig. 3 is a schematic diagram illustrating a configuration example of a stack cross-section of the imaging device illustrated in Fig. 1.Fig. 4 is a schematic diagram illustrating, in an enlarged manner, a part of the imaging device illustrated in Fig. 3.Fig. 5A is a first schematic view of a horizontal cross-section representing a part of the imaging device illustrated in Fig. 3.Fig. 5B is a second schematic view of the horizontal cross-section representing a part of the imaging device illustrated in Fig. 3.Fig. 6A is a schematic cross-sectional diagram describing a process in a method of manufacturing a coupling part in the imaging device illustrated in Fig. 3.Fig. 6B is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6A.Fig. 6C is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6B.Fig. 6D is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6C.Fig. 6E is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6D.Fig. 6F is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6E.Fig. 6G is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6F.Fig. 6H is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6G.Fig. 6I is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6H.Fig. 6J is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6I.Fig. 6K is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6J.Fig. 6L is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 6K.Fig. 7A is a schematic diagram illustrating a cross-sectional configuration example of a second substrate as a first modification example of the present disclosure.Fig. 7B is a schematic diagram illustrating a cross-sectional configuration example of a second substrate as a second modification example of the present disclosure.Fig. 7C is a schematic diagram illustrating a cross-sectional configuration example of a second substrate as a third modification example of the present disclosure.Fig. 7D is a schematic diagram illustrating a cross-sectional configuration example of a second substrate as a fourth modification example of the present disclosure.Fig. 7E is a schematic diagram illustrating a cross-sectional configuration example of a second substrate as a fifth modification example of the present disclosure.Fig. 8 is a schematic diagram illustrating a cross-sectional configuration example of an imaging device as a sixth modification example of the present disclosure.Fig. 9 is a schematic diagram illustrating a cross-sectional configuration example of an imaging device according to a seventh modification example of the present disclosure.Fig. 10A is a schematic cross-sectional diagram describing a process in a method of manufacturing the imaging device illustrated in Fig. 9.Fig. 10B is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 10A.Fig. 10C is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 10B.Fig. 10D is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 10C.Fig. 10E is a schematic cross-sectional diagram illustrating a process following the process illustrated in Fig. 10E.Fig. 11 is a block diagram illustrating a configuration example of an electronic apparatus including the imaging device illustrated in Fig. 1.Fig. 12A is a schematic diagram illustrating an example of an overall configuration of a photodetection system in which the imaging device illustrated in Fig. 1, etc. is used.Fig. 12B is a diagram illustrating an example of a circuit configuration of the photodetection system illustrated in Fig 12A.Fig. 13 is a view depicting an example of a schematic configuration of an endoscopic surgery system.Fig. 14 is a block diagram depicting an example of a functional configuration of a camera head and a camera control unit (CCU).Fig. 15 is a block diagram depicting an example of a schematic configuration of a vehicle control system.Fig. 16 is a diagram of example installation positions of an outside-vehicle information detecting section and an imaging section.

[0011] Hereinafter, a description is given in detail of embodiments of the present disclosure with reference to the drawings. It is to be noted that the description is given in the following order. 1. Embodiment 2. Modification Examples 3. Application Examples 4. Practical Application Examples <1. Embodiment>Functional Configuration of Imaging Device 1

[0012] Fig. 1 is a block diagram illustrating an example of an overall configuration of an imaging device 1 as one specific example of a photodetector according to an embodiment of the present disclosure. The imaging device 1 is a device that receives incident light and performs photoelectric conversion. The imaging device 1 performs photoelectric conversion on the received light to generate a signal. The imaging device 1 takes in incident light (image light) from a subject via, for example, an optical lens system. The imaging device 1 is, for example, a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and captures an image of a subject.

[0013] The imaging device 1 includes a pixel array unit 240 in which multiple pixels P are arranged in a matrix. That is, the pixel array unit 240 is a region in which the pixels P are repeatedly arranged in an array. Each of the multiple pixels P includes a photoelectric converter. The imaging device 1 includes, for example, an inputter 210, a row driver 220, a timing controller 230, a column signal processor 250, an image signal processor 260, and an outputter 270 in a peripheral region of the pixel array unit 240.

[0014] In the imaging device 1, pixel sharing units 40 each including multiple pixels P are repeatedly arranged in an array. More specifically, the pixel sharing units 40 each including the multiple pixels P are repeatedly arranged in both a row direction and a column direction, with the pixel sharing unit 40 that includes the multiple pixels P serving as a repeating unit. In the example illustrated in Fig. 1, the pixel sharing unit 40 includes four pixels (a pixel Pa, a pixel Pb, a pixel Pc, and a pixel Pd). The pixels Pa to Pd are arranged in, for example, two rows and two columns. Each of the pixels Pa to Pd includes, for example, a photodiode PD as the photoelectric converter.

[0015] In the imaging device 1, a readout circuit 45 (see Fig. 2 to be described later) is provided for each of the pixel sharing units 40. The readout circuit 45 includes semiconductor elements including, without limitation, an amplification transistor and a reset transistor. The readout circuit 45 outputs a pixel signal based on electric charge on which photoelectric conversion has been performed by the photoelectric converter of each of the pixels P. The pixel sharing unit 40 is a unit for sharing one readout circuit 45, and the multiple pixels P (the pixels Pa to Pd in Fig. 1) of the pixel sharing unit 40 share one readout circuit. In the pixel array unit 240, one readout circuit 45 is provided for each of four pixels (the pixel Pa to Pd). Causing the readout circuit 45 to operate in a time-division manner allows a pixel signal of each of the pixels Pa to Pd to be read out.

[0016] As illustrated in Fig. 1, the imaging device 1 is provided with multiple row driving signal lines Lread (row selection lines, reset control lines, etc.) and multiple vertical signal lines (column readout lines) Lsig. For example, the row driving signal line Lread is wired in the pixel array unit 240, for each pixel row including multiple pixels P arranged in a horizontal direction (a row direction). In addition, the vertical signal line Lsig is wired in the pixel array unit 240, for each pixel column including multiple pixels P arranged in a vertical direction (a column direction). The row driving signal line Lread transmits, for example, a signal that drives each of the transistors in the pixel sharing unit 40. In the vertical signal line Lsig, the pixel signal may be read out from each of the pixels Pa to Pd included in the pixel sharing unit 40.

[0017] The row driver 220 includes a shift register, an address decoder, etc. The row driver 220 generates a driving signal for driving the pixel P, and outputs the generated driving signal to each of the pixel sharing units 40 in the pixel array unit 240 via the row driving signal line Lread. The row driver 220 generates, for example, a signal TRGs for controlling a transfer transistor, a signal SELs for controlling a selection transistor, a signal RSTs for controlling a reset transistor, etc., and outputs, using the row driving signal lines Lread, the signal TRGs, the signal SELs, and the signal RSTs to each of the pixel sharing units 40.

[0018] As described above, the row driving signal line Lread transmits the driving signal (such as the signal TRGs, the signal SELs, or the signal RSTs) from the pixel P. The row driver 220 is a row address controller. The row driver 220 selectively scans each of the pixels P in the pixel array unit 240, and drives, for example, multiple pixels P arranged in the pixel array unit 240 on a row unit basis. The pixel signal of each of the pixels P selected and scanned by the row driver 220 is output to the column signal processor 250 via the vertical signal line Lsig coupled to a corresponding one of the pixels P.

[0019] The column signal processor 250 includes, for example, a load circuit section coupled to the vertical signal lines Lsig. The load circuit section forms a source follower circuit together with an amplifier transistor of the readout circuit. It is to be noted that the column signal processor 250 may include an amplifier circuit section that amplifies a pixel signal read out from the pixel sharing unit 40 via the vertical signal line Lsig. In addition, the column signal processor 250 may include a noise processor that removes a noise component from the pixel signal.

[0020] In addition, the column signal processor 250 includes an analog-to-digital converter (ADC). The ADC includes, for example, a comparator section and a counter section. The comparator section compares an analog signal with a reference signal. The counter section measures the time until the comparison result obtained by the comparator section is inverted.

[0021] The ADC of the column signal processor 250 converts the pixel signal, which is an analog signal output from the pixel sharing unit 40, into a digital signal. The ADC may perform AD conversion on the pixel signal before being subjected to noise processing by the noise processor or may perform the AD conversion on the pixel signal after being subjected to the noise processing by the noise processor. It is to be noted that the column signal processor 250 may include a horizontal scanning circuit section that performs scanning of the column to be read.

[0022] The timing controller 230 supplies a signal for controlling a timing to the row driver 220 and the column signal processor 250 based on, for example, a reference clock signal and a timing control signal input from outside to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, and the like. The timing controller 230 includes, for example, a timing generator that generates various timing signals, and performs drive controls of the row driver 220, the column signal processor 250, etc. based on the various generated timing signals.

[0023] The image signal processor 260 is a circuit that performs various kinds of signal processing on the pixel signal. The image signal processor 260 may include a processor and a memory. For example, the image signal processor 260 performs signal processing such as tone curve correction processing for black-level adjustment and gray scale adjustment on the pixel signal that has been subjected to the AD conversion. It is to be noted that characteristic data of a tone curve indicating a gray scale correction amount may be stored in advance in the memory inside the image signal processor 260.

[0024] The inputter 210 and the outputter 270 exchange signals with the outside. The inputter 210 receives, for example, the reference clock signal, the timing control signal, the characteristic data, etc. described above from outside of the imaging device 1. The outputter 270 may output, to the outside, for example, the pixel signal after being subjected to the signal processing by the image signal processor 260 or the pixel signal before being subjected to the signal processing by the image signal processor 260.

[0025] Fig. 2 is an equivalent circuit diagram illustrating a configuration example of the pixel sharing unit 40 of the imaging device 1 according to an embodiment of the present disclosure. The pixel sharing unit 40 includes the multiple pixels P (Pa to Pd), one readout circuit 45 coupled to the multiple pixels P, and the vertical signal line Lsig coupled to the readout circuit 45. In the following, as illustrated in Figs. 1 and 2, an example case where four pixels P (Pa to Pd) share one readout circuit 45 will be described. The four pixels Pa to Pd include respective photodiodes PD (PD1 to PD4) as the photoelectric converters, respective transfer transistors TR (TR1 to TR4), and respective floating diffusions FD (FD1 to FD4).

[0026] The readout circuit 45 includes, for example, a reset transistor RST, a FD conversion gain switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL. The pixel sharing unit 40 sequentially outputs the respective pixel signals of the four pixels Pa to Pd included in the pixel sharing unit 40 to the vertical signal line Lsig by causing the one readout circuit 45 to operate in a time division manner. A state in which one readout circuit 45 is coupled to the four pixels Pa to Pd, and the pixel signals of the four pixels Pa to Pd are output by the one readout circuit 45 in the time division manner as described above is described as "the multiple pixels P share one readout circuit 45".

[0027] Each of the photodiodes PD1 to PD4, which is a photoelectric converter, converts incident light into electric charge. Each of the photodiodes PD1 to PD4 performs photoelectric conversion to generate electric charge corresponding to an amount of received light. A cathode of each of the photodiodes PD1 to PD4 is electrically coupled to a source of a corresponding one of the transfer transistors TR1 to TR4, and an anode of each of the photodiodes PD1 to PD4 is electrically coupled to a reference potential line (e.g., a ground GND).

[0028] Each of the transfer transistors TR1 to TR4 is electrically coupled to a corresponding one of the photodiodes PD1 to PD4. Each of the transfer transistors TR1 to TR4 is, for example, an n-type CMOS (transistor. A drain of each of the transfer transistors TR1 to TR4 is electrically coupled to a corresponding one of the floating diffusions FD1 to FD4, and a gate of each of the transfer transistors TR1 to TR4 is electrically coupled to a driving signal line. This driving signal line is a part of the multiple row driving signal lines Lread (see Fig. 1) coupled to the one pixel sharing unit 40. Each of the transfer transistors TR1 to TR4 is controlled by a corresponding one of the signals TRG1 to TRG4, and transfers, to a corresponding one of the floating diffusions FD1 to FD4, the electric charge that has been subjected to photoelectric conversion and accumulated in a corresponding one of the photodiodes PD1 to PD4.

[0029] Each of the floating diffusions FD1 to FD4 is an n-type diffusion layer formed in a p-type semiconducting layer. Each of the floating diffusions FD1 to FD4 is an electric charge holder, and holds the electric charge transferred from a corresponding one of the photodiodes PD1 to PD4. Each of the floating diffusions FD1 to FD4 may also be described as an electric charge accumulator that accumulates the electric charge transferred from a corresponding one of the photodiodes PD1 to PD4. Each of the floating diffusions FD1 to FD4 accumulates the transferred electric charge and converts the electric charge into a voltage corresponding to a capacitance of a corresponding one of the floating diffusions FD1 to FD4. The electric charge converted by each of the photodiodes PD1 to PD4 is transferred to a corresponding one of the floating diffusions FD1 to FD4 by a corresponding one of the transfer transistors TR1 to TR4 and is converted into a voltage corresponding to the capacitance of a corresponding one of the floating diffusions FD1 to FD4.

[0030] The four floating diffusions FD1 to FD4 included in the one pixel sharing unit 40 are electrically coupled to each other and are electrically coupled to a gate of the amplification transistor AMP and a source of the FD conversion gain switching transistor FDG. A drain of the FD conversion gain switching transistor FDG is coupled to a source of the reset transistor RST, and a gate of the FD conversion gain switching transistor FDG is coupled to a driving signal line. This driving signal line is a part of the multiple row driving signal lines Lread coupled to the one pixel sharing unit 40. A drain of the reset transistor RST is coupled to a power supply line VDD, and a gate of the reset transistor RST is coupled to a driving signal line. This driving signal line is a part of the multiple row driving signal lines Lread coupled to the one pixel sharing unit 40. The gate of the amplification transistor AMP is coupled to the floating diffusions FD1 to FD4, a drain of the amplification transistor AMP is coupled to the power supply line VDD, and a source of the amplification transistor AMP is coupled to a drain of the selection transistor SEL. A source of the selection transistor SEL is coupled to the vertical signal line Lsig, and a gate of the selection transistor SEL is coupled to a driving signal line. This driving signal line is a part of the multiple row driving signal lines Lread coupled to the one pixel sharing unit 40.

[0031] When each of the transfer transistors TR1 to TR4 is turned on, each of the transfer transistors TR1 to TR4 transfer the electric charge of a corresponding one of the photodiodes PD1 to PD4 to a corresponding one of the floating diffusions FD1 to FD4. The reset transistor RST resets a potential of each of the floating diffusions FD1 to FD4 to a predetermined potential. When the reset transistor RST is turned on, the potential of each of the floating diffusions FD1 to FD4 is reset to a potential of the power supply line VDD. The selection transistor SEL controls the timing of outputting the pixel signal from the readout circuit 45. The amplification transistor AMP generates, as the pixel signal, a signal of a voltage corresponding to a level of the electric charge held in the floating diffusions FD1 to FD4. The amplification transistor AMP is coupled to the vertical signal line Lsig via the selection transistor SEL. The amplification transistor AMP forms the source follower in the column signal processor 250, together with the load circuit section coupled to the vertical signal line Lsig. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusions FD1 to FD4 to the column signal processor 250 via the vertical signal line Lsig. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0032] The FD conversion gain switching transistor FDG is used to change the gain of electric-charge-voltage conversion in the floating diffusions FD1 to FD4. In general, the pixel signal is small at the time of photographing in a dark place. Based on Q = CV, when the electric-charge-voltage conversion is performed, if the capacitance (an FD capacitance C) of the floating diffusions FD1 to FD4 is large, V in the conversion to the voltage performed by the amplification transistor AMP becomes small. In contrast, because the pixel signal becomes large in a bright place, if the FD capacitance C is not large, the floating diffusions FD1to FD4 cannot receive all the electric charge of the photodiodes PD1 to PD4. In addition, it is desirable that the FD capacitance C be large so that the V in the conversion to the voltage performed by the amplification transistor AMP does not become excessively large (in other words, so that V becomes small). In view of the above, when the FD conversion gain switching transistor FDG is turned on, the total FD capacitance C increases because it is increased by the amount corresponding to the gate capacitance of the FD conversion gain switching transistor FDG. In contrast, when the FD conversion gain switching transistor FDG is turned off, the total FD capacitance C decreases. Switching on and off of the FD conversion gain switching transistor FDG thus allows the FD capacitance C to be variable, making it possible to switch conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an n-type CMOS transistor.

[0033] It is to be noted that a configuration in which the FD conversion gain switching transistor FDG is not provided may be employed. In this case, for example, the readout circuit 45 includes three transistors, for example, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST. The readout circuit 45 includes, for example, at least one of pixel transistors including, without limitation, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0034] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically coupled to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically coupled to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically coupled to the row driving signal line Lread. The source of the amplification transistor AMP (an output terminal of the readout circuit 45) is electrically coupled to the row driving signal line Lread, and the gate of the amplification transistor AMP is electrically coupled to the source of the reset transistor RST. It is to be noted that the number of the pixels P sharing the one read circuit 45 may be other than four. For example, two or eight pixels P may share the one readout circuit 45.Schematic Configuration of Imaging Device 1

[0035] Fig. 3 is a cross-sectional stack diagram illustrating an example of a schematic configuration of the imaging device 1. Fig. 3 is a schematic representation for clarity of a positional relationship of the components and may be different from the actual cross section. The imaging device 1 has a structure in which three substrates, i.e., a first substrate 101, a second substrate 102, and a third substrate 103, are stacked in order. Each of the first substrate 101, the second substrate 102, and the third substrate 103 includes, for example, a semiconductor substrate such as a silicon (Si) substrate. It is to be noted that, in this specification, a stacking direction of the first substrate 101, the second substrate 102, and the third substrate 103 is defined as a Z-axis direction. The Z-axis direction coincides with an incident direction of light from the subject. In addition, a left-right direction of the paper surface orthogonal to the Z-axis direction is defined as an X-axis direction, and a direction orthogonal to a Z-axis and an X-axis is defined as a Y-axis direction. In the following drawings, directions are sometimes expressed with reference to the directions of arrows in Fig. 3.

[0036] The first substrate 101 includes a light receiving layer 110 and a wiring section 111. The second substrate 102 includes a semiconductor layer 120, a wiring section 121, and a wiring section 122. The third substrate 103 includes a semiconductor layer 130 and a wiring section 131. The light receiving layer 110, the semiconductor layer 120, and the semiconductor layer 130 respectively have first surfaces 11S1, 12S1, 13S1, and respectively have second surfaces 11S2, 12S2, and 13S2. The first surfaces 11S1, 12S1, and 13S1 and the second surfaces 11S2, 12S2, and 13S2 each extend along an XY plane.

[0037] Each of the first surfaces 11S1, 12S1, and 13S1 is an element formation surface on which a semiconductor element such as a transistor is provided. Each of the first surfaces 11S1, 12S1, and 13S1 is provided with, for example, a gate electrode, a gate oxide film, a source-drain region, etc. of the transistor. For example, a transfer transistor TR, the floating diffusion FD, etc. are provided on the first surface 11S1 of the light receiving layer 110. In addition, the amplification transistor AMP, the selection transistor SEL, etc. are provided on the first surface 12S1 of the semiconductor layer 120.

[0038] In the first substrate 101, the wiring section 111 is stacked on the first surface 11S1 of the light receiving layer 110. In the second substrate 102, the wiring section 121 is stacked on the first surface 12S1 of the semiconductor layer 120, and the wiring section 122 is stacked on the second surface 12S2 of the second substrate 102. Further, in the third substrate 103, the wiring section 131 is stacked on the first surface 13S1 of the semiconducting layer 130. Each of the wiring sections 111, 121, 122, and 131 includes, for example, a conductor film and an insulating film, and includes multiple wirings, vias, etc. Each of the wiring sections 111, 121, 122, and 131 includes, for example, two or more layers of wirings. Each of the wiring sections 122 and 131 may include three or more layers of wirings.

[0039] Each of the wiring sections 111, 121, 122, and 131 has, for example, a configuration in which one or more wiring layers are stacked with an interlayer insulating layer (an interlayer insulating film) interposed therebetween. Specifically, in the wiring section 111, for example, wiring layers 11M1, 11M2, and 11M3 stacked in order from a side of a bonding surface 101S1 (to be described later) are embedded in an interlayer insulating layer 11Z. Further, in the wiring section 121, for example, wiring layers 21M1, 21M2, and 21M3 stacked in order from a side of a bonding surface 102S1 (to be described later) are embedded in an interlayer insulating layer 21Z. Further, in the wiring section 122, for example, wiring layers 22M1 and 22M2 stacked in order from a side of a bonding surface 102S2 (to be described later) are embedded in an interlayer insulating layer 22Z. Further, in the wiring section 131, for example, wiring layers 31M1, 31M2, 31M3, 31M4, and 31M5 stacked in order from a side of a bonding surface 103S1 (to be described later) are embedded in an interlayer insulating layer 31Z. It is to be noted that, in this specification, the wiring layers included in the wiring sections 111, 121, 122, and 131 are sometimes collectively referred to as wiring layers M. In addition, in the present specification, the interlayer insulating layers included in the wiring sections 111, 121, 122, and 131 may be collectively referred to as interlayer insulating layers Z.

[0040] Each of the wiring layers M of the wiring sections 111, 121, 122, and 131 includes, for example, aluminum (Al), copper (Cu), tungsten (W), polysilicon (Poly-Si), or the like. Each of the interlayer insulating layers Z of the wiring sections 111, 121, 122, and 131 includes, for example, a single-layer film including one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or the like, or a stacked film including two or more thereof.

[0041] The first substrate 101 and the second substrate 102 are so stacked, by bonding between electrodes, that the first surface 11S1, which is the element formation surface on which an element such as the transistor is formed, and the second surface 12S2 on the opposite side to the element formation surface face each other. In other words, the first substrate 101 and the second substrate 102 are so bonded to each other that a front surface of the first substrate 101 and a back surface of the second substrate 102 face each other. This bonding method is called face-to-back bonding. Specifically, the bonding surface 101S1 as the front surface of the first substrate 101, which is a surface of the wiring section 111 on the opposite side to the light receiving layer 110, is bonded to the bonding surface 102S2 as the back surface of the second substrate 102, which is a surface of the wiring section 122 on the opposite side to the semiconductor layer 120. It is to be noted that the bonding surface 101S1 is one specific example of a "first bonding surface" as an embodiment of the present disclosure, and the bonding surface 102S2 is one specific example of a "second bonding surface" as an embodiment of the present disclosure. The first substrate 101 and the second substrate 102 may be bonded to each other by what is called hybrid bonding. More specifically, the wiring layer 11M1 as a first pad exposed on the bonding surface 101S1 and the wiring layer 22M1 as a second pad exposed on the bonding surface 102S2 are bonded to each other to form a first bonding terminal pair, and the interlayer insulating layer 11Z exposed on the bonding surface 101S1 and the interlayer insulating layer 22Z exposed on the bonding surface 102S2 are bonded to each other. In a case where both the wiring layer 11M1 and the wiring layer 22M1 include copper (Cu), the bonding between the wiring layer 11M1 and the wiring layer 22M1 is sometimes referred to as Cu-Cu bonding. It is to be noted that the electrode used for bonding may include a metal material other than copper (Cu), for example, nickel (Ni), cobalt (Co), tin (Sn), or the like, or may include any other material. For example, the second surface 12S2, which is the back surface of the semiconductor layer 120, may be provided with a metal oxide film including, for example, a metal element such as Ta (tantalum), Hf (hafnium), W (tungsten), or Al (aluminum), as a light anti-reflection film or a light shielding film.

[0042] In contrast, the second substrate 102 and the third substrate 103 are so stacked, by bonding between electrodes, that the first surface 12S1 and the first surface 13S1 on each of which an element such as the transistor is formed face each other. In other words, the second substrate 102 and the third substrate 103 are so bonded to each other that their respective front surfaces face each other. This bonding method is called face-to-face bonding. Specifically, the bonding surface 102S1 as the front surface of the second substrate 102, which is a surface of the wiring section 121 on the opposite side to the semiconductor layer 120, is bonded to the bonding surface 103S1 as the front surface of the third substrate 103, which is a surface of the wiring section 131 on the opposite side to the semiconductor layer 130. The second substrate 102 and the third substrate 103 may be bonded to each other by what is called hybrid bonding. More specifically, the wiring layer 21M1 as an electrode exposed on the bonding surface 102S1 and the wiring layer 31M1 as an electrode exposed on the bonding surface 103S1 are bonded to each other, and the interlayer insulating layer 21Z exposed on the bonding surface 102S1 and the interlayer insulating layer 31Z exposed on the bonding surface 103S1 are bonded to each other. In a case where both the wiring layer 21M1 and the wiring layer 31M1 include copper (Cu), the bonding between the wiring layer 21M1 and the wiring layer 31M1 is sometimes referred to as Cu-Cu bonding. It is to be noted that the electrode used for bonding may include a metal material other than copper (Cu), for example, nickel (Ni), cobalt (Co), tin (Sn), or the like, or may include any other material.

[0043] In the imaging device 1, the photodiode PD, the transfer transistor TR1, and the floating diffusion FD described above are disposed in the first substrate 101, and the readout circuit 45 is disposed in the second substrate 102. Because the photodiode PD and the readout circuit 45 are disposed in different substrates, it is possible to allow the photodiode PD to be sufficiently large, as compared to a case where the photodiode PD and the readout circuit 45 are disposed in the same substrate. This makes it possible to acquire an image having a wide dynamic range. The first substrate 101 may have a color filter CF, for example, on a light incident side of the photodiode PD, i.e., on the opposite side of the photodiode PD to the wiring section 111. In addition, an on-chip lens OCL may be provided on the second surface 11S2 of the first substrate 101. Disposed in the third substrate 103 are, for example, the row driver 220, the timing controller 230, the column signal processor 250, the image signal processor 260, etc. described above. In addition, the inputter 210 and the outputter 270 described above may be disposed in the third substrate 103.

[0044] As schematically illustrated in Fig. 3, the floating diffusion FD of the pixel P of the first substrate 101 is electrically coupled to the amplification transistor AMP and the like of the readout circuit 45 of the second substrate 102 via the wiring layers 11M1 to 11M3 of the wiring section 111 and the wiring layer 22M1 of the wiring section 122. The electric charge subjected to photoelectric conversion by the photodiode PD of the first substrate 101 is output to the floating diffusion FD and the readout circuit 45 of the second substrate 102 via the transfer transistor TR.

[0045] In addition, the second substrate 102 is provided with a through via TSV. In the imaging device 1, the through via TSV is provided for each pixel P or for each multiple pixels P. The through via TSV extends through the semiconducting layer 120 in the Z-axis direction. An upper end of the through via TSV is coupled to the wiring layer 22M1, and a lower end of the through via TSV is coupled to the wiring layer 21M3. Therefore, the wiring layer 22M1 and the wiring layer 21M3 are electrically coupled to each other by the through via TSV. Further, the wiring layer 21M3 is coupled to the gate electrode of the amplification transistor AMP via a via 21V. In the imaging device 1, the through via TSV is disposed for each readout circuit 45 or for each multiple readout circuit 45. The readout circuit 45 provided in the second substrate 102 is electrically coupled to the wiring section 111 and the floating diffusion FD of the light receiving layer 110 via the through via TSV and the wiring section 122. The through via TSV includes, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or the like. It is to be noted that the through via TSV may include any other metal material.Detailed Configuration of Imaging Device 1

[0046] Fig. 4 is a schematic cross-sectional diagram enlarging a part of the second substrate 102 of the imaging device 1 illustrated in Fig. 3. As illustrated in Fig. 4, the first surface 12S1 as the element formation surface of the semiconductor layer 120 is provided with, for example, the amplification transistor AMP and the selection transistor SEL as semiconductor elements. The semiconductor layer 120 has a through hole 23K that extends through the semiconductor layer 120 in the Z-axis direction. The through via TSV is disposed in the through hole 23K in the Z-axis direction. The upper end of the through via TSV is coupled to the electrode pad 25 that is a part of the wiring layer 22M1. The electrode pad 25 is exposed on the second bonding surface 102S2 and is bonded to the wiring layer 11M1 as a part of the first pad exposed on the first bonding surface 101S1. It is to be noted that the electrode pad 25 is one specific example corresponding to one embodiment of each of a "wiring" and a "second pad" of the present disclosure.

[0047] The semiconductor layer 120 includes a semiconductor region 23p of a first conductivity type (e.g., a p-type) and a well region 23nw that is of a second conductivity type (an n-type) and surrounds the through via TSV. The well region 23nw includes a high concentration region 23n+ that is higher in an n-type impurity concentration than a surrounding region thereof. Each of the amplification transistor AMP and the selection transistor SEL includes, for example, an n-type source-drain region S / D in the vicinity of the first surface 12S1. In addition, the amplification transistor AMP and the selection transistor SEL include gate electrodes AMPG and SELG, respectively. The wiring layer 22M2 includes at least a part of a coupling part 24 that electrically couples the high concentration region 23n+ of the well region 23nw and the source-drain region S / D of the amplification transistor AMP.

[0048] More specifically, the coupling part 24 includes a first pillar 24P1, a second pillar 24P2, and a beam 24B. The first pillar 24P1 is coupled to the source-drain region S / D of the amplification transistor AMP, and extends in the Z-axis direction from the source-drain region S / D of the amplification transistor AMP at least to the second surface 12S2 that is the back surface of the semiconductor layer 120 on the opposite side to the first surface 12S1 of the semiconductor layer 120. The second pillar 24P2 is coupled to the high concentration region 23n+ of the well region 23nw and extends in the Z-axis direction from the high concentration region 23n+ of the well region 23nw at least to the second surface 12S2 of the semiconductor layer 120. The wiring layer 22M2 includes, as a part of the coupling part 24, the beam 24B that so extends along the second bonding surface 102S2 as to electrically couple the first pillar 24P1 and the second pillar 24P2 to each other. Therefore, in the second substrate 102 of the embodiment illustrated in Fig. 4, the beam 24B of the coupling part 24 is provided at a layer level that is different from a layer level provided with the wiring layer 22M1.

[0049] In the coupling part 24, a constituent material of the beam 24B, a constituent material of the first pillar 24P1, and a constituent material of the second pillar 24P2 are the same as each other. The constituent material of the beam 24B, the constituent material of the first pillar 24P1, and the constituent material of the second pillar 24P2 is, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or the like, as with the constituent material of the through via TSV, for example. However, the beam 24B, the first pillar 24P1, and the second pillar 24P2 may include any other metal material.

[0050] In addition, it is preferable that the beam 24B, the first pillar 24P1, and the second pillar 24P2 in the coupling part 24 be integrally formed. Specifically, the coupling part 24 may be collectively formed using the same kind of material.

[0051] The second substrate 102 further includes an insulating layer 23Z1, an insulating layer 23Z2, and an insulating layer 23Z3. The insulating layer 23Z1 is interposed in a gap between the first pillar 24P1 and a semiconducting region 23p surrounding the first pillar 24P1. The insulating layer 23Z2 is interposed in a gap between the second pillar 24P2 and the well region 23nw surrounding the second pillar 24P2. In addition, the insulating layer 23Z3 is interposed in a gap between the through via TSV and the well region 23nw surrounding the through via TSV.

[0052] As described above, the second substrate 102 further includes the wiring layer 21M3 on the opposite side of the semiconductor layer 120 to the second bonding surface 102S2. The wiring layer 21M3 electrically couples the through via TSV and the gate electrode AMPG of the amplification transistor AMP. It is to be noted that the wiring layer 21M3 is one specific example corresponding to an embodiment of a "third wiring layer" of the present disclosure.

[0053] In addition, a layout of the imaging device 1 along the XY plane is illustrated in each of Figs. 5A and 5B. Figs. 5A and 5B correspond to horizontal cross-sections at positions Lv1 and Lv2, respectively, in the Z-axis direction illustrated in Fig. 3. However, the configuration example of the stacked cross-section of Fig. 3 and the configuration example of the horizontal cross-section illustrated in each of Figs. 5A and 5B do not exactly coincide with each other. Each of Figs. 5A and 5B illustrates a state in which two pixel sharing units 40 each including the four pixels Pa to Pd are arranged in each of the X-axis direction and the Y-axis direction.

[0054] As illustrated in Fig. 5A, the photodiodes PD1 to PD4 of the respective pixels P are provided in an active region surrounded by a pixel isolator 51. In the active region, the transfer transistors TR1 to TR4 are provided as to respectively overlap with the photodiodes PD1 to PD4 in the Z-axis direction. A contact part FDC is disposed at a middle position of the four pixels Pa to Pd. The contact part FDC is coupled to each of the floating diffusions FD1 to FD4.

[0055] As illustrated in Fig. 5B, the wiring layers 11M1 and 22M1 are provided on the bonding surface between the first substrate 101 and the second substrate 102 as to surround the active region of the four pixels Pa to Pd. The through via TSV is disposed at a middle position of the four pixels Pa to Pd. The through via TSV is electrically coupled to the contact part FDC also illustrated in Fig. 5A via the wiring layer 11M1 and the wiring layer 22M1 (the electrode pad 25). In addition, the well region 23nw is so provided as to surround the through via TSV. In addition, the coupling part 24 (the beam 24B is illustrated in Fig. 5B) is provided that electrically couples the high concentration region 23n+ of the well region 23nw (not illustrated in Fig. 5B) and the source-drain region S / D (not illustrated in Fig. 5B) of the amplification transistor AMP provided in the semiconductor region 23p.Manufacturing Method of Imaging Device 1

[0056] Next, a manufacturing method of the imaging device 1 will be described. Here, in particular, a manufacturing method of the coupling part 24 in the second substrate 102 and a part around the coupling part 24 will be described with reference to Figs. 6A to 6L.

[0057] First, as illustrated in Fig. 6A, a stacked structure including the semiconductor layer 120 and the wiring section 121 is prepared. The semiconductor layer 120 includes the amplification transistor AMP, the selection transistor SEL, and the like that are provided on the first surface 12S1. The wiring section 121 covers the first surface 12S1 and includes the wiring layer 21M3, the via 21V, and the like.

[0058] Thereafter, as illustrated in Fig. 6B, a photoresist pattern PR1 is selectively formed on the insulating layer 22Z. The photoresist pattern PR1 has openings K1 and K2 at locations at which the first pillar 24P1 and the second pillar 24P2 are to be formed, respectively. After the photoresist pattern PR1 is formed, the insulating layer 22Z and the semiconductor region 23p of the semiconductor layer 120 are sequentially and selectively removed by an etching process (e.g., RIE) using the photoresist pattern PR1 as a mask. As a result, holes H1 and H2 reaching the high concentration region 23n+ provided on the first surface 12S1 are formed.

[0059] Thereafter, as illustrated in Fig. 6C, the photoresist pattern PR1 is removed, following which the insulating layers 23Z1 and 23Z2 are respectively formed along inner wall surfaces of the holes H1 and H2. Examples of a method of forming the insulating layers 23Z1 and 23Z2 include an atomic layer deposition (ADL) method. One reason for this is that even in a case where the holes H1 and H2 each have a high-aspect-ratio shape, it is possible to form the insulating layers 23Z1 and 23Z2 having high uniformity in terms of film quality, thickness, and the like, along the inner wall surfaces of the holes H1 and H2, respectively.

[0060] Thereafter, an etching process is performed to remove the insulating layers 23Z1 and 23Z2 deposited on bottom surfaces of the holes H1 and H2, respectively. The high concentration region 23n+ is thereby exposed. Thereafter, as illustrated in Fig. 6D, a metal layer 24M is so formed as to fill each of the holes H1 and H2 and to cover the insulating layer 22Z. The metal layer 24M may be obtained, for example, by forming a barrier layer including at least one of Ta, Ti, W, N, or Co, and thereafter forming an electrically conductive layer including at least one of W, Co, Ru, Cu, Al, or Mo in a consecutive manner.

[0061] Thereafter, as illustrated in Fig. 6E, a photoresist pattern PR2 is selectively formed on the insulating layer 22Z. The photoresist pattern PR2 is formed only in a region in which the coupling part 24 is to be formed.

[0062] Thereafter, the insulating layer 22Z and a part of the metal layer 24M in a region not covered with the photoresist pattern PR2 are sequentially and selectively removed by an etching process (e.g., RIE) using the photoresist pattern PR2 as a mask. Accordingly, as illustrated in Fig. 6F, the beam 24B as the wiring layer 22M2 is formed. As a result, the coupling part 24 is obtained.

[0063] Thereafter, as illustrated in Fig. 6G, a hole H3 is formed at a location at which the through via TSV is to be formed. The hole H3 may be formed, for example, by selectively forming a photoresist pattern having an opening at the location at which the through via TSV is to be formed, and thereafter performing an etching process (e.g., RIE) using the photoresist pattern as a mask. Forming the hole H3 allows for formation of the through hole 23K in the semiconductor region 23P of the semiconductor layer 120.

[0064] Thereafter, as illustrated in Fig. 6H, an impurity layer 23D is so formed as to cover an inner wall surface of the hole H3 and the insulating layer 22Z. The impurity layer 23D includes, for example, P2O5including P (phosphorus), which is an n-type impurity. The impurity layer 23D is formed by, for example, the ALD method. A SiO2film may be so formed as to cover the inner wall surface of the hole H3, following which a P2O5film may be formed. Thereafter, P (phosphorus), which is an n-type impurity, is diffused into the p-type semiconductor region 23p by a heating process, and the well region 23nw of the n-type is formed in a self-aligned manner around the inner wall surface of the hole H3.

[0065] Thereafter, as illustrated in Fig. 6I, the impurity layer 23D is removed by a wet etching process. Thereafter, as illustrated in Fig. 6J, the insulating layer 22Z3 is so formed as to cover the inner wall surface of the hole H3 and the insulating layer 22Z. Examples of a method of forming the insulating layer 23Z3 include the ALD method.

[0066] Thereafter, as illustrated in Fig. 6K, an etching process is performed to sequentially remove the insulating layer 23Z3 deposited on a bottom surface of the hole H3 and the insulating layer 21Z positioned below the hole H3. The wiring layer 21M3 is thereby exposed.

[0067] Thereafter, as illustrated in Fig. 6L, the through via TSV is formed by a CVD method or the like by so providing an electrically conductive material as to fill the hole H3.

[0068] Lastly, the second substrate 102 is completed by forming the wiring layer 22M1.Working and Effects of Imaging Device 1

[0069] In the imaging device 1 of the present embodiment, the wiring layers 22M1 and 22M2 are provided on the opposite side of the semiconductor layer 120 to the first surface 12S1 as the element formation surface in the second substrate 102. Therefore, it is possible to reduce complication of the wiring layers M on the first surface 12S1 side. Accordingly, the degree of freedom of the plan layout of each of the wiring layers M improves, making it easy to achieve higher integration of the readout circuit 45 and the like. In addition, it is possible to electrically couple the high concentration region 23n+ of the well region 23nw around the through via TSV in the semiconductor layer 120, and the amplification transistor AMP to each other, via the beam 24B included in the wiring layer 22M2. Therefore, it is possible to reduce parasitic capacitance between the through via TSV and the well region 23nw around the through via TSV by the Miller effect. As a result, in the imaging device 1, the photodiodes PD1 to PD4 are improved in photoelectric conversion efficiency, and higher photodetection performance is achieved. Therefore, according to the imaging device 1 of the present embodiment, it is possible to achieve both improvement in imaging performance and higher integration. In particular, in the imaging device 1, because the high concentration region 23n+ around the through via TSV and the source-drain region S / D of the amplification transistor AMP are electrically coupled by means of the first pillar 24P1 and the second pillar 24P2 extending in the Z-axis direction, it is possible to prevent an increase in an occupied area in the XY plane, which is advantageous for higher integration.

[0070] In particular, in the imaging device 1, because the insulating layer 23Z1 is provided around the first pillar 24P1, the well region 23nw does not have to be provided around the source-drain region S / D of the amplification transistor AMP. Therefore, the manufacturing process of the second substrate 102 is simpler than, for example, those of a second substrate 102-1 as a first modification example and a second substrate 102-2 as a second modification example both to be described later.

[0071] Further, in the imaging device 1, the coupling part 24 includes a structure in which the first pillar 24P1, the second pillar 24P2, and the beam 24B are integrated. This makes it possible to reduce the number of manufacturing processes, and to improve accuracy of the position to dispose the coupling part 24, dimensional accuracy, and the like of the coupling part 24. Therefore, it is possible to reduce parasitic capacitance formed between the through via TSV and the coupling part 24, as compared with, for example, a second substrate 102-3 as a third modification example to be described later.

[0072] First to Seventh modification examples of the present disclosure will be described below. In each of the following modification examples, the same reference numerals are assigned to the same configurations as those in the above-described embodiments. <2. Modification Examples> (2-1. First Modification Example)

[0073] Fig. 7A is a diagram illustrating a cross-sectional configuration example of the second substrate 102-1 as the first modification example of the present disclosure, corresponding to Fig. 4 of the above-described embodiment. In the second substrate 102 of the above-described embodiment, the insulating layer 23Z1 is provided around the first pillar 24P1, and the insulating layer 23Z2 is provided around the second pillar 24P2. However, in the present disclosure, as in the second substrate 102-1, the well region 23nw may be so provided around each of the first pillar 24P1 and the second pillar 24P2 as to be in contact with each of the first pillar 24P1 and the second pillar 24P2.

[0074] According to the second substrate 102-1 of the present modification example, contact with each of the first pillar 24P1 and the second pillar 24P2 with the well region 23nw makes it possible to reduce electrical resistance between the high concentration region 23n+ around the through via TSV and the source-drain region S / D of the amplification transistor AMP, as compared with the second substrate 102 of the above-described embodiment. (2-2. Second Modification Example)

[0075] Fig. 7B is a diagram illustrating a cross-sectional configuration example of the second substrate 102-2 as the second modification example of the present disclosure, corresponding to Fig. 4 of the above-described embodiment. In the second substrate 102-2 of the present modification example, the high concentration region 23n+ is provided on the second surface 12S2. Specifically, the first pillar 24P1 is coupled to the high concentration region 23n+ coupled to the well region 23nw coupled to the source-drain region S / D of the amplification transistor AMP. The second pillar 24P2 is coupled to the high concentration region 23n+ provided on the second surface 12S2 of the well region 23nw surrounding the through via TSV.

[0076] In the second substrate 102-2 of the present modification example, it is not necessary to provide a hole in the semiconductor layer 120 for providing each of the first pillar 24P1 and the second pillar 24P2. This simplifies the manufacturing process. As a result, it is possible to reduce variations in characteristics between the multiple pixels P and variations in characteristics between the multiple pixel sharing units 40. (2-3 to 2-5. Third to Fifth Modification Examples)

[0077] Figs. 7C to 7E are diagrams respectively illustrating cross-sectional configuration examples of second substrates 102-3 to 102-5 as the third to fifth modification examples of the present disclosure, corresponding to Fig. 4 of the above-described embodiment. In each of the second substrates 102-3 to 102-5 as the third to fifth modification examples, the beam 24B of the coupling part 24 is provided not as the wiring layer 22M2 but as the wiring layer 22M1. The constituent material of the beam 24B is different from each of the constituent material of the first pillar 24P1 and the constituent material of the second pillar 24P2. The electrode pad 25 included in the wiring layer 22M1 is a wiring that is electrically coupled to the upper end part of the through via TSV in the Z-axis direction and is positioned at a layer level that is the same as a layer level of the beam 24B. The constituent material of the beam 24B is preferably the same as the constituent material of the electrode pad 25, for example. Except for these points, the configuration of each of the second substrates 102-3 to 102-5 is substantially the same as the configuration of each of the second substrates 102, 102-1, and 102-2.

[0078] According to the second substrates 102-3 to 102-5 as the third to fifth modification examples of the present disclosure, it is possible to reduce electrical resistance of the coupling part 24, as compared with each of the second substrates 102, 102-1, and 102-2. One reason for this is that it is possible to use a low-resistance material such as copper (Cu) as the constituent material of the beam 24B, and to allow a thickness (a cross-sectional area) of the beam 24B to be relatively large. (2-6. Sixth Modification Example)

[0079] Fig.8 is a diagram illustrating a configuration example of a stack cross-section of an imaging device 1A as the sixth modification example of the present disclosure, corresponding to Fig. 3 of the above-described embodiment. In the imaging device 1A as the sixth modification example, the second substrate 102 further includes a wiring layer 22M3 positioned between the wiring layer 22M2 and the second bonding surface 102S2. Except for this point, the imaging device 1A has a configuration substantially the same as the configuration of the imaging device 1 of the above-described embodiment. According to the imaging device 1A of the present modification example, because the wiring layer 22M3 is also provided in addition to the wiring layers 22M1 and 22M2 on the second surface 12S2 side on the opposite side of the semiconductor layer 120 to the element formation surface, it is possible to further reduce the complication of the wiring layers M on the first surface 12S1 side. Accordingly, the degree of freedom of the plan layout of each of the wiring layers M further improves, making it easier to achieve higher integration of the readout circuit 45 and the like. (2-7. Seventh Modification Example)

[0080] Fig. 9 is a diagram illustrating a configuration example of a stacked cross-section of an imaging device 1B as the seventh modification example of the present disclosure, corresponding to Fig. 3 of the above-described embodiment. The imaging device 1B as the seventh modification example further includes a fourth substrate 104. Specifically, the imaging device 1B includes a structure in which four substrates, i.e., the first substrate 101, the second substrate 102, the third substrate 103, and the fourth substrate 104 are stacked in this order. As with the third substrate 103, the fourth substrate 104 is also a logic substrate provided with a logic circuit. For example, an analog-to-digital (A-D) conversion circuit or the like may be disposed in the third substrate 103, and an Image Signal Processing (ISP) / Digital (Signal Processing (DSP)) circuit or the like may be disposed in the fourth substrate 104. It is to be noted that the circuit provided in the third substrate 103 and the circuit provided in the fourth substrate 104 may be electrically coupled to each other via, for example, a through via TSV2. In this case, a thickness of the through via TSV2 may be larger than a thickness of the through via TSV provided in the second substrate 102.

[0081] In the imaging device 1B, the third substrate 103 includes a bonding surface 103S2 on the opposite side to the second substrate 102. The bonding surface 103S2 is one specific example of a "third bonding surface" as an embodiment of the present disclosure. The bonding surface 103S2 is bonded to a bonding surface 104S1 (to be described later) of the fourth substrate 104. In the imaging device 1B, the third substrate 103 further includes a wiring section 132 in addition to the semiconductor layer 130 and the wiring section 131. The wiring section 132 is positioned on the opposite side of the semiconductor layer 130 to the wiring section 131 and is provided on the second surface 13S2 of the semiconductor layer 130. A surface, of the wiring section 132, on the opposite side to the second surface 13S2 of the semiconductor layer 130 is the bonding surface 103S2. The wiring section 132 has, for example, a configuration in which one or more wiring layers are stacked with an interlayer insulating layer (an interlayer insulating film) interposed therebetween. Specifically, the wiring section 132 includes, for example, a structure in which wiring layers 32M1 and 32M2 stacked in order from the bonding surface 103S2 side are embedded in the interlayer insulating layer 32Z. A part of the wiring layer 32M1 is a third pad exposed on the bonding surface 103S2. The wiring layer 32M1 as the third pad is bonded to a wiring layer 41M1 as a fourth pad to be described later to form a second bonding terminal pair.

[0082] The third substrate 103 is provided with the through via TSV2. The through via TSV2 extends through the semiconducting layer 130 in the Z-axis direction. An upper end of the through via TSV2 is coupled to the wiring layer 31M5, and a lower end of the through via TSV2 is coupled to the wiring layer 32M2. Therefore, the wiring layer 31M5 and the wiring layer 32M2 are electrically coupled to each other by the through via TSV2. The through via TSV2 includes, for example, tungsten (W), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or the like. It is to be noted that the through via TSV2 may include any other metal material.

[0083] In the imaging device 1B, the fourth substrate 104 includes the bonding surface 104S1 that is bonded to the bonding surface 103S2 of the third substrate 103. The bonding surface 104S1 is one specific example of a "fourth bonding surface" as an embodiment of the present disclosure. The fourth substrate 104 includes a semiconductor layer 140 and a wiring section 141. The semiconductor layer 140 includes a first surface 14S1 and a second surface 14S2. The first surface 14S1 and the second surface 14S2 both extend along the XY plane. The first surface 14S1 is an element formation surface on which a semiconductor element such as a transistor is provided. The first surface 14S1 is provided with, for example, a gate electrode, a gate oxide film, a source-drain region, and the like of the transistor. A surface, of the wiring section 141, on the opposite side to the first surface 14S1 of the semiconductor layer 140 is the bonding surface 104S1. The wiring section 141 has, for example, a configuration in which one or more wiring layers are stacked with an interlayer insulating layer (an interlayer insulating film) interposed therebetween. Specifically, the wiring section 141 includes, for example, a structure in which wiring layers 41M1, 41M2, 41M3, 41M4, and 41M5 stacked in this order from the bonding surface 104S1 side are embedded in an interlayer insulating layer 41Z. A part of the wiring layer 41M1 is an electrode pad (referred to as a fourth electrode pad, for convenience) exposed on the bonding surface 104S1. The wiring layer 41M1 as the electrode pad is bonded to the wiring layer 32M1 as the electrode pad to form a bonding terminal pair. It is to be noted that an arrangement pitch of the multiple wiring layers 41M1 as the fourth pads is preferably larger than each of an arrangement pitch of the multiple wiring layers 11M1 as the first pads exposed on the bonding surface 101S1, and an arrangement pitch of the multiple wiring layers 22M1 as the second pads exposed on the bonding surface 102S2. In other words, an arrangement pitch of the multiple second bonding terminal pairs each including the wiring layer 41M1 and the wiring layer 32M1 is larger than an arrangement pitch of the multiple first bonding terminal pairs each including the wiring layer 11M1 and the wiring layer 22M1.

[0084] The third substrate 103 and the fourth substrate 104 may be bonded to each other by what is called hybrid bonding. Specifically, the wiring layer 32M1 as the electrode exposed on the bonding surface 103S2 and the wiring layer 41M1 as the electrode exposed on the bonding surface 104S1 are bonded to each other, and the interlayer insulating layer 32Z exposed on the bonding surface 103S2 and the interlayer insulating layer 41Z exposed on the bonding surface 104S1 are bonded to each other. In a case where both the wiring layer 32M1 and the wiring layer 41M1 include copper (Cu), the bonding between the wiring layer 32M1 and the wiring layer 41M1 is sometimes referred to as Cu-Cu bonding.

[0085] As described above, in the imaging device 1B, because the logic substrate is divided into two and the divided two parts are stacked, it is possible to reduce the occupied area of the third substrate 103 occupying in the XY plane, as compared with the imaging device 1. Therefore, the imaging device 1B is more suitable for achieving both higher definition and higher functionality, and miniaturization.

[0086] It is to be noted that the imaging device 1B is manufacturable, for example, as follows. First, as illustrated in Fig. 10A, the bonding surface 102S1 of the second substrate 102 at a stage prior to formation of the through via TSV and the bonding surface 103S1 of the third substrate 103 at a stage prior to formation of the through via TSV2 are bonded to each other by hybrid bonding. At this stage, the wiring section 132 is not provided yet.

[0087] Thereafter, as illustrated in Fig. 10B, a through hole is formed at a predetermined position of the semiconductor layer 130, following which the interlayer insulating layer 32Z is so formed as to fill the through hole and to cover the second surface 13S2 of the semiconductor layer 130. Further, the through via TSV2 is so formed as to be disposed in the through hole formed in the semiconducting layer 130.

[0088] Thereafter, as illustrated in Fig. 10C, the wiring section 132 including the wiring layers 32M1 and 32M2 embedded in the interlayer insulating layer 32Z is formed on the second surface 13S2 of the semiconductor layer 130. At this time, a part of the wiring layer 32M2 is brought into contact with the lower end of the through via TSV2. Further, the fourth substrate 104 is prepared, following which the bonding surface 103S2 of the third substrate 103 and the bonding surface 104S1 of the fourth substrate 104 are bonded by hybrid bonding.

[0089] Thereafter, as illustrated in Fig. 10D, a through hole is formed at a predetermined position of the semiconductor layer 120, following which the interlayer insulating layer 22Z is so formed as to fill the through hole and to cover the second surface 12S2 of the semiconductor layer 120. Further, the through via TSV is so formed as to be disposed in the through hole formed in the semiconducting layer 120.

[0090] Thereafter, as illustrated in Fig. 10E, the wiring section 122 including the wiring layers 22M1 to 22M3 embedded in the interlayer insulating layer 22Z is formed on the second surface 12S2 of the semiconductor layer 120. At this time, a part of the wiring layer 22M3 is brought into contact with the upper end of the through via TSV.

[0091] Further, the first substrate 101 is prepared, following which the bonding surface 102S2 of the second substrate 102 and the bonding surface 101S1 of the first substrate 101 are bonded by hybrid bonding. Thereafter, the imaging device 1B is completed by, for example, forming the color filter CF, the on-chip lens OCL, and the like. <3. Application Examples> (Application Example 1)

[0092] The imaging device 1 or the like described above is applicable to any type of electronic apparatus having an imaging function. Examples of such an electronic apparatus include a camera system such as a digital still camera or a video camera, a mobile phone having an imaging function, etc. Fig. 11 illustrates a schematic configuration of an electronic apparatus 1000.

[0093] The electronic apparatus 1000 includes, for example, a lens group 1001, the imaging device 1, a (Digital Signal Processor(DSP) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, and the lens group 1001, the imaging device 1, the DSP circuit 1002, the frame memory 1003, the display unit 1004, the recording unit 1005, the operation unit 1006, and the power supply unit 1007 are coupled to each other via a bus line 1008.

[0094] The lens group 1001 takes in incident light (image light) from a subject and forms an image on an imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light imaged on the imaging surface by the lens group 1001 into an electrical signal on a pixel unit basis and supplies the electrical signal to the DSP circuit 1002 as a pixel signal.

[0095] The DSP circuit 1002 is a signal processing circuit that processes a signal supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtainable by processing the signal from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 on a frame unit basis

[0096] The display unit 1004 includes, for example, a panel-type display device such as a liquid crystal panel or an organic Electro Luminescence (EL) panel, and records image data of a moving image or a still image captured by the imaging device 1 on a recording medium such as a semiconductor memory or a hard disk.

[0097] The operation unit 1006 outputs operation signals for various functions owned by the electronic apparatus 1000 in accordance with an operation performed by a user. The power supply unit 1007 appropriately supplies various kinds of power supplies to be used as operation power supplies for the DSP circuit 1002, the frame memory 1003, the display unit 1004, the recording unit 1005, and the operation unit 1006, to these supply targets. (Application Example 2)

[0098] Fig. 12A is a diagram schematically illustrating an example of an overall configuration of a photodetection system 2000 including the imaging device 1. Fig. 12B is a diagram illustrating an example of a circuit configuration of the photodetection system 2000. The photodetection system 2000 includes a light emitting device 2001 as a light source unit that emits light L2, and a photodetector 2002 as a light receiving unit that includes a photoelectric conversion element. As the photodetector 2002, the above-described imaging device 1 is usable. The photodetection system 2000 may further include a system controller 2003, a light source driver 2004, a sensor controller 2005, a light-source-side optical system 2006, and a camera-side optical system 2007.

[0099] The photodetector 2002 is configured to detect light L1 and the light L2. The light L1 is light in which ambient light from an outside is reflected by a subject (an object to be measured) 2100 (Fig. 12A). The light L2 is light emitted by the light emitting device 2001 and thereafter reflected by the subject 2100. The light L1 is, for example, visible light, and the light L2 is, for example, infrared light. The light L1 is detectable by the photoelectric converter in the photodetector 2002, and the light L2 is detectable by a photoelectric conversion region in the photodetector 2002. Image information of the subject 2100 is acquirable from the light L1, and distance information between the subject 2100 and the photodetection system 2000 is acquirable from the light L2. The photodetection system 2000 is mountable on, for example, an electronic apparatus such as a smartphone, or a moving body such as a vehicle. The light emitting device 2001 may include, for example, a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). As a method of detecting the light L2 emitted from the light emitting device 2001 by the photodetector 2002, for example, an iTOF method may be used, but is not limited thereto. In the iTOF method, the photoelectric converter is able to measure the distance to the subject 2100 by, for example, optical time-of-flight (TOF). As a method of detecting the light L2 emitted from the light emitting device 2001 by the photodetector 2002, for example, a structured light system or a stereo vision system may be employed. For example, in the structured light system, the distance between the photodetection system 2000 and the subject 2100 is measurable by projecting light of a predetermined pattern onto the subject 2100 and analyzing a distortion degree of the pattern. Further, in the stereo vision system, for example, the distance between the photodetection system 2000 and the subject 2100 is measurable by using two or more cameras and acquiring two or more images of the subject 2100 viewed from two or more different viewpoints. It is to be noted that it is possible to synchronously control the light emitting device 2001 and the photodetector 2002 by the system controller 2003. <4. Practical Application Examples> <Example of Practical Application to Endoscopic Surgery System>

[0100] The technology (the present technology) according to the present disclosure is applicable to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0101] Fig. 13 is a view depicting an example of a schematic configuration of an endoscopic surgery system to which the technology according to an embodiment of the present disclosure (present technology) can be applied.

[0102] In Fig. 13, a state is illustrated in which a surgeon (medical doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery for a patient 11132 on a patient bed 11133. As depicted, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a supporting arm apparatus 11120 which supports the endoscope 11100 thereon, and a cart 11200 on which various apparatus for endoscopic surgery are mounted.

[0103] The endoscope 11100 includes a lens barrel 11101 having a region of a predetermined length from a distal end thereof to be inserted into a body cavity of the patient 11132, and a camera head 11102 connected to a proximal end of the lens barrel 11101. In the example depicted, the endoscope 11100 is depicted which includes as a rigid endoscope having the lens barrel 11101 of the hard type. However, the endoscope 11100 may otherwise be included as a flexible endoscope having the lens barrel 11101 of the flexible type.

[0104] The lens barrel 11101 has, at a distal end thereof, an opening in which an objective lens is fitted. A light source apparatus 11203 is connected to the endoscope 11100 such that light generated by the light source apparatus 11203 is introduced to a distal end of the lens barrel 11101 by a light guide extending in the inside of the lens barrel 11101 and is irradiated toward an observation target in a body cavity of the patient 11132 through the objective lens. It is to be noted that the endoscope 11100 may be a forward-viewing endoscope or maybe an oblique-viewing endoscope or a side-viewing endoscope.

[0105] An optical system and an image pick-up element are provided in the inside of the camera head 11102 such that reflected light (observation light) from the observation target is condensed on the image pick-up element by the optical system. The observation light is photo-electrically converted by the image pick-up element to generate an electric signal corresponding to the observation light, namely, an image signal corresponding to an observation image. The image signal is transmitted as raw data to a CCU 11201.

[0106] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU) or the like and integrally controls operation of the endoscope 11100 and a display apparatus 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs, for the image signal, various image processes for displaying an image based on the image signal such as, for example, a development process (e.g., demosaic processing).

[0107] The display apparatus 11202 displays thereon an image based on an image signal, for which the image processes have been performed by the CCU 11201, under the control of the CCU 11201.

[0108] The light source apparatus 11203 includes a light source such as, for example, a light emitting diode (LED) and supplies irradiation light upon imaging of a surgical region to the endoscope 11100.

[0109] An inputting apparatus 11204 is an input interface for the endoscopic surgery system 11000. A user can perform inputting of various kinds of information or instruction inputting to the endoscopic surgery system 11000 through the inputting apparatus 11204. For example, the user would input an instruction, or the like, to change an image pick-up condition (type of irradiation light, magnification, focal distance or the like) by the endoscope 11100.

[0110] A treatment tool controlling apparatus 11205 controls driving of the energy device 11112 for cautery or incision of a tissue, sealing of a blood vessel, or the like. A pneumoperitoneum apparatus 11206 feeds gas into a body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to inflate the body cavity to secure the field of view of the endoscope 11100 and secure the working space for the surgeon. A recorder 11207 is an apparatus capable of recording various kinds of information relating to surgery. A printer 11208 is an apparatus capable of printing various kinds of information relating to surgery in various forms such as a text, an image, or a graph.

[0111] It is to be noted that the light source apparatus 11203 which supplies irradiation light when a surgical region is to be imaged to the endoscope 11100 may include a white light source which includes, for example, an LED, a laser light source or a combination of them. Where a white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and the output timing can be controlled with a high degree of accuracy for each color (each wavelength), adjustments to the white balance of a picked-up image can be performed by the light source apparatus 11203. Further, in this case, if laser beams from the respective RGB laser light sources are irradiated time-divisionally on an observation target and driving of the image pick-up elements of the camera head 11102 are controlled in a synchronous manner with the irradiation timings. Then images individually corresponding to the R, G and B colors can be also picked-up time-divisionally. According to this method, a color image can be obtained even if color filters are not provided for the image pick-up element.

[0112] Further, the light source apparatus 11203 may be controlled such that the intensity of light to be output is changed for each predetermined time. By controlling the driving of the image pick-up element of the camera head 11102 in synchronism with the timing of the change of the intensity of light to acquire images time-divisionally and synthesizing the images, an image of a high dynamic range free, from underexposed blocked up shadows and overexposed highlights, can be created.

[0113] Further, the light source apparatus 11203 may be configured to supply light of a predetermined wavelength band ready for special light observation. In special light observation, for example, by utilizing the wavelength dependency of absorption of light in a body tissue to irradiate light of a narrow band in comparison with irradiation light upon ordinary observation (namely, white light), narrow band observation (narrow band imaging) of imaging a predetermined tissue such as a blood vessel of a superficial portion of the mucous membrane or the like in a high contrast is performed. Alternatively, in special light observation, fluorescent observation for obtaining an image from fluorescent light generated by irradiation of excitation light may be performed. In fluorescent observations, it is possible to perform observation of fluorescent light from a body tissue by irradiating excitation light on the body tissue (autofluorescence observation) or to obtain a fluorescent light image by locally injecting a reagent such as indocyanine green (ICG) into a body tissue and irradiating excitation light corresponding to a fluorescent light wavelength of the reagent upon the body tissue. The light source apparatus 11203 can be configured to supply such narrow-band light and / or excitation light suitable for special light observation as described above.

[0114] Fig. 14 is a block diagram depicting an example of a functional configuration of the camera head 11102 and the CCU 11201 depicted in Fig. 13.

[0115] The camera head 11102 includes a lens unit 11401, an image pick-up unit 11402, a driving unit 11403, a communication unit 11404 and a camera head controlling unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412 and a control unit 11413. The camera head 11102 and the CCU 11201 are connected for communication to each other by a transmission cable 11400.

[0116] The lens unit 11401 is an optical system, provided at a connecting location to the lens barrel 11101. Observation light taken in from a distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focusing lens.

[0117] The number of image pick-up elements which is included by the image pick-up unit 11402 may be one (single-plate type) or a plural number (multi-plate type). Where the image pick-up unit 11402 is configured as that of the multi-plate type, for example, image signals corresponding to respective R, G and B are generated by the image pick-up elements, and the image signals may be synthesized to obtain a color image. The image pick-up unit 11402 may also be configured to have a pair of image pick-up elements for acquiring respective image signals for the right eye and the left eye ready for three-dimensional (3D) display. If 3D display is performed, then the depth of a living body tissue in a surgical region can be comprehended more accurately by the surgeon 11131. It is to be noted that, where the image pick-up unit 11402 is configured as that of stereoscopic type, a plurality of systems of lens units 11401 are provided corresponding to the individual image pick-up elements.

[0118] Further, the image pick-up unit 11402 may not necessarily be provided on the camera head 11102. For example, the image pick-up unit 11402 may be provided immediately behind the objective lens in the inside of the lens barrel 11101.

[0119] The driving unit 11403 includes an actuator and moves the zoom lens and the focusing lens of the lens unit 11401 by a predetermined distance along an optical axis under the control of the camera head controlling unit 11405. Consequently, the magnification and the focal point of a picked-up image by the image pick-up unit 11402 can be suitably adjusted.

[0120] The communication unit 11404 includes a communication apparatus for transmitting and receiving various kinds of information to and from the CCU 11201. The communication unit 11404 transmits an image signal acquired from the image pick-up unit 11402 as raw data to the CCU 11201 through the transmission cable 11400.

[0121] In addition, the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head controlling unit 11405. The control signal includes information relating to image pick-up conditions such as, for example, information that a frame rate of a picked-up image is designated, information that an exposure value upon image pick-up is designated and / or information that a magnification and a focal point of a picked-up image are designated.

[0122] It is to be noted that the image pick-up conditions such as the frame rate, exposure value, magnification or focal point may be designated by the user or may be set automatically by the control unit 11413 of the CCU 11201 based on an acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function and an auto white balance (AWB) function are incorporated in the endoscope 11100.

[0123] The camera head controlling unit 11405 controls driving of the camera head 11102 based on a control signal from the CCU 11201 received through the communication unit 11404.

[0124] The communication unit 11411 includes a communication apparatus for transmitting and receiving various kinds of information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted thereto from the camera head 11102 through the transmission cable 11400.

[0125] Further, the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0126] The image processing unit 11412 performs various image processes for an image signal in the form of raw data transmitted thereto from the camera head 11102.

[0127] The control unit 11413 performs various kinds of control processes relating to image pick-up of a surgical region or the like by the endoscope 11100 and display of a picked-up image, or the like. For example, the control unit 11413 creates a control signal for controlling driving of the camera head 11102.

[0128] Further, the control unit 11413 controls, based on an image signal for which image processes have been performed by the image processing unit 11412, the display apparatus 11202 to display a picked-up image in which the surgical region or the like is imaged. Thereupon, the control unit 11413 may recognize various objects in the picked-up image using various image recognition technologies. For example, the control unit 11413 can recognize a surgical tool such as forceps, a particular living body region, bleeding, mist when the energy device 11112 is used and so forth by detecting the shape, color and so forth of edges of objects included in a picked-up image. The control unit 11413 may cause, when controlling the display apparatus 11202 to display a picked-up image, various kinds of surgery supporting information to be displayed in an overlapping manner with an image of the surgical region using a result of the recognition. Where surgery supporting information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery with certainty.

[0129] The transmission cable 11400 which connects the camera head 11102 and the CCU 11201 to each other is an electrical signal cable ready for communication of an electrical signal, an optical fiber ready for optical communication or a composite cable ready for both electrical and optical communications.

[0130] Here, while, in the example depicted, communication is performed by wired communication using the transmission cable 11400, the communication between the camera head 11102 and the CCU 11201, however, may be performed by wireless communication.

[0131] The description has been given above of one example of the endoscopic surgery system to which the technology according to the present disclosure is applicable. The technology according to the present disclosure is applicable to the image pick-up unit 11402 in the above-described configuration. Applying the technology according to the present disclosure to the image pick-up unit 11402 improves detection accuracy.

[0132] It is to be noted that although the endoscopic surgery system has been described as an example here, the technology according to the present disclosure may be applied to, for example, any other system such as a microscopic surgery system. (Example of Practical Application to Mobile Body)

[0133] The technology, according to the present disclosure, is applicable to various products. For example, the technology according to the present disclosure may be achieved as an apparatus to be mounted to a mobile body of any kind. Examples of the mobile body may include an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, any personal mobility device, an airplane, a drone, a vessel, a robot, construction equipment, and agricultural machinery (a tractor), or the like.

[0134] Fig. 15 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0135] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 15, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0136] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0137] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like, of the vehicle.

[0138] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 instructs the imaging section 12031 to provide an image of the outside of the vehicle and receives the imaged image from the imaging section 12031. Based on the received image, the outside-vehicle information detecting unit 12030 may process the received image to detect objects such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or process the received image to detect distances from the object.

[0139] The imaging section 12031 is an optical sensor that receives light, and outputs an electrical signal corresponding to a received amount of light. The imaging section 12031 can output the electrical signal as an image or can output the electrical signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light or may be invisible light such as infrared rays or the like.

[0140] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. Based on detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing off.

[0141] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040and can output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0142] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, (e.g., operating the vehicle without input from the driver, or the like), by controlling the driving force generating device, the steering mechanism, the braking device, or the like based on the information about the outside or inside of the vehicle obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0143] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0144] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 15, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0145] Fig. 16 is a diagram depicting an example of the installation position of the imaging section 12031.

[0146] In Fig. 16, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0147] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle, obtains mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door, obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0148] Incidentally, Fig. 16 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird’s-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0149] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements or maybe an imaging element having pixels for phase difference detection.

[0150] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that allows the vehicle to operate in an automated manner without input from the driver, or the like.

[0151] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0152] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0153] The description has been given above of one example of the mobile body control system to which the technology according to the present disclosure may be applied. The technology according to the present disclosure may be applied to the imaging section 12031 in the configuration described above. Specifically, the imaging device according to any of the embodiments and Modification examples 1 to 7 thereof described above is applicable to the imaging section 12031. The application of the technology according to the present disclosure to the imaging section 12031 makes it possible to obtain a high-resolution captured image with less noise. It is therefore possible to perform a highly accurate control using the captured image in the mobile body control system.

[0154] Although the present disclosure has been described with reference to the embodiment and the first to seventh modification examples thereof, the application examples, and the practical application examples, the present disclosure is not limited to the above-described embodiment and the like, and various modifications may be made. It is to be noted that the effects described herein are mere examples. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than the effects described herein.

[0155] In addition, for example, the present disclosure may also have any of the following configurations. In the photodetector having any of the following configurations, the wiring layer is provided on the opposite side of the semiconductor layer to the element formation surface in the second substrate. Therefore, it is possible to reduce the complication of the wirings on the element formation surface side. In addition, it is possible to electrically couple, via the first wiring layer, the part, of the semiconductor layer, around the through via that is coupled to the electric charge accumulator and extends through the semiconductor layer, and the semiconductor element. Therefore, it is possible to reduce parasitic capacitance between the through via and the semiconductor around the through via by the Miller effect. As a result, photoelectric conversion efficiency improves. It is therefore possible to achieve both performance improvement and higher integration. <1> A photodetector includes a first substrate including a photoelectric converter, an electric charge accumulator, and a first bonding surface, in which the photoelectric converter generates electric charge by performing photoelectric conversion on light, and in which the electric charge accumulator accumulates the electric charge. The photodetector further includes a second substrate including a semiconductor material including a first semiconductor part and a second semiconductor part, a first through via, a second bonding surface, and a first wiring layer. The semiconductor layer includes a coupling part that electrically couples the first semiconductor part to the second semiconductor part and each of the first semiconductor part and the second semiconductor part includes a semiconductor surface having at least one semiconductor element. The at least one semiconductor element is included in a readout circuit that outputs a first signal based on the electric charge and the first through via is electrically coupled to the electric charge accumulator, the second bonding surface is positioned on an opposite side of the semiconductor material to the semiconductor element formation surface and bonded to the first bonding surface, the first wiring layer is positioned between the semiconductor material and the second bonding surface. <2> The photodetector according to <1>, in which the semiconductor material includes a semiconductor region of a first conductivity type, and a well region that is of a second conductivity type and surrounds the first through via, in which the second conductivity type is different from the first conductivity type, in which the well region includes a semiconductor concentration region that is higher in a concentration of an impurity of the second conductivity type than a surrounding region of the semiconductor concentration region, in which the semiconductor element is provided in the semiconductor region and includes a source-drain region of the second conductivity type, and in which the first wiring layer includes a first part of the coupling part that electrically couples the semiconductor concentration region in the well region and the source-drain region of the semiconductor element. <3> The photodetector according to <2>, in which the coupling part includes a first pillar, the first pillar and in which the first pillar is coupled to the source-drain region of the semiconductor element and extends in the first direction from the source-drain region of the semiconductor element at least to a back surface of the semiconductor material on an opposite side to the element formation surface of the semiconductor material. <4> The photodetector according to <3>, in which the coupling part further includes a second pillar, and in which the second pillar is coupled to the semiconductor concentration region of the well region and extends in the first direction from the semiconductor concentration region of the well region at least to the back surface of the semiconductor material. <5> The photodetector according to <4>, in which the first wiring layer includes, as the first part of the coupling part, a beam that extends along the second bonding surface to electrically couple the first pillar and the second pillar to each other. <6> The photodetector according to <5>, in which a constituent material of the beam, a constituent material of the first pillar, and a constituent material of the second pillar is a same constituent material. <7> The photodetector according to <5> or <6>, in which the beam, the first pillar, and the second pillar are integrally formed. <8> The photodetector according to <5>, in which a constituent material of the beam is different from each of a constituent material of the first pillar and a constituent material of the second pillar. <9> The photodetector according to <8>, in which the first wiring layer further includes a wiring that is electrically coupled to an end part of the first through via in the first direction and is positioned at a layer level same as a layer level of the beam. <10> The photodetector according to any one of <4> to <9>, in which the second substrate further includes a first insulating layer interposed between the first pillar and the semiconductor region, and a second insulating layer interposed between the second pillar and the well region. <11> The photodetector according to any one of <1> to <10>, in which the first substrate further includes a first pad that is electrically coupled to the electric charge accumulator and is exposed on the first bonding surface, and in which the second substrate further includes a second pad that is electrically coupled to the first through via, is exposed on the second bonding surface, and is bonded to the first pad. <12> The photodetector according to any one of <1> to <11>, in which the second substrate further includes a second wiring layer positioned between the first wiring layer and the second bonding surface. <13> The photodetector according to <2>, in which the second substrate further includes a third wiring layer on an opposite side of the semiconductor material to the second bonding surface, and in which the third wiring layer electrically couples the through via and a gate electrode of the semiconductor element to each other. <14> An electronic apparatus including a photodetector, in which the photodetector includes a first substrate including a photoelectric converter, an electric charge accumulator, and a first bonding surface, in which the photoelectric converter generates electric charge by performing photoelectric conversion on light, and in which the electric charge accumulator accumulates the electric charge. The electronic apparatus further includes a second substrate including a semiconductor material including a first semiconductor part and a second semiconductor part, a first through via, a second bonding surface, and a first wiring layer. The semiconductor layer includes a coupling part that electrically couples the first semiconductor part to the second semiconductor part and each of the first semiconductor part and the second semiconductor part includes a semiconductor surface having at least one semiconductor element. The at least one semiconductor element is included in a readout circuit that outputs a first signal based on the electric charge and the first through via is electrically coupled to the electric charge accumulator, the second bonding surface is positioned on an opposite side of the semiconductor material to the semiconductor element formation surface and bonded to the first bonding surface, the first wiring layer is positioned between the semiconductor material and the second bonding surface. <15> The photodetector according to any one of <1> to <13>, further including a third substrate provided on an opposite side of the second substrate to the first substrate, in which the third substrate includes a first signal processor electrically coupled to the semiconductor element. <16> The photodetector according to <15>, further including a fourth substrate provided on an opposite side of the third substrate to the second substrate, in which the fourth substrate includes a second signal processor electrically coupled to the first signal processor, in which the third substrate further includes a second through via, and in which the second through via electrically couples the first signal processor and the second signal processor to each other. <17> The photodetector according to <16>, in which the second through via has a thickness greater than a thickness of the first through via. <18> The photodetector according to <16> or <17>, in which the third substrate includes a third bonding surface, in which the fourth substrate includes a fourth bonding surface bonded to the third bonding surface, and in which an arrangement pitch of multiple second bonding terminal pairs in which multiple third pads exposed on the third bonding surface are bonded to multiple fourth pads exposed on the fourth bonding surface is greater than an arrangement pitch of multiple first bonding terminal pairs in which multiple first pads exposed on the first bonding surface are bonded to multiple second pads exposed on the second bonding surface. <19> The electronic apparatus according to <14>, in which the semiconductor material includes a semiconductor region of a first conductivity type and a well region that is of a second conductivity type and surrounds the first through via, in which the second conductivity type is different than the first conductivity type, in which the well region includes a semiconductor concentration region that is higher in a concentration of an impurity of the second conductivity type than a surrounding region of the semiconductor concentration region, in which the semiconductor element is provided in the semiconductor region and includes a source-drain region of the second conductivity type, and in which the first wiring layer includes a first part of the coupling part that electrically couples the semiconductor concentration region in the well region and the source-drain region of the semiconductor element. <20> The electronic apparatus according to <19>, in which the coupling part includes a first pillar and wherein the first pillar is coupled to the source-drain region of the semiconductor element and extends in the first direction from the source-drain region of the semiconductor element at least to a back surface of the semiconductor material on an opposite side to the element formation surface of the semiconductor material.Reference Numerals List

[0156] 1 imaging device 23p semiconductor region 23nw well region 23n+ high concentration region 24 coupling part 24B beam 24P1 first pillar 24P2 second pillar 40 pixel sharing unit 45 readout circuit 101 first substrate 102 second substrate 103 third substrate 110 light receiving layer 120, 130 semiconductor layer 111, 121, 122, 131 wiring section 101S1, 101S1, 102S2, 103S1 bonding surface 210 inputter 220 row driver 230 timing controller 240 pixel array unit 250 column signal processor 260 image signal processor 270 outputter TR (TR1 to TR4) transfer transistor TG transfer gate RST reset transistor AMP amplification transistor SEL selection transistor FDG FD transfer transistor PD photodiode FD floating diffusion P (Pa to Pd) pixel TSV through via

Claims

1. A photodetector, comprising: a first substrate including: a photoelectric converter; an electric charge accumulator; and a first bonding surface, wherein the photoelectric converter generates electric charge by performing photoelectric conversion on light, and wherein the electric charge accumulator accumulates the electric charge; and a second substrate including: a semiconductor material including a first semiconductor part and a second semiconductor part; a first through via; a second bonding surface; and a first wiring layer, wherein the first wiring layer includes a coupling part that electrically couples the first semiconductor part to the second semiconductor part, wherein each of the first semiconductor part and the second semiconductor part includes a semiconductor element surface, having at least one semiconductor element, wherein the at least one semiconductor element is included in a readout circuit that outputs a first signal based on the electric charge, wherein the first through via is electrically coupled to the electric charge accumulator, wherein the second bonding surface is positioned on an opposite side of the semiconductor material to the semiconductor element formation surface and bonded to the first bonding surface, and wherein the first wiring layer is positioned between the semiconductor material and the second bonding surface.

2. The photodetector according to claim 1, wherein the semiconductor material includes: a semiconductor region of a first conductivity type; and a well region that is of a second conductivity type and surrounds the first through via, wherein the second conductivity type is different than the first conductivity type, wherein the well region includes a semiconductor concentration region that is higher in a concentration of an impurity of the second conductivity type than a surrounding region of the semiconductor concentration region, wherein the semiconductor element is provided in the semiconductor region and includes a source-drain region of the second conductivity type, and wherein the first wiring layer includes a first part of the coupling part that electrically couples the semiconductor concentration region in the well region and the source-drain region of the semiconductor element.

3. The photodetector according to claim 2, wherein the coupling part includes a first pillar and wherein the first pillar is coupled to the source-drain region of the semiconductor element and extends in the first direction from the source-drain region of the semiconductor element at least to a back surface of the semiconductor material on an opposite side to the element formation surface of the semiconductor material.

4. The photodetector according to claim 3, wherein the coupling part further includes a second pillar and wherein the second pillar is coupled to the semiconductor concentration region of the well region and extends in the first direction from the semiconductor concentration region of the well region at least to the back surface of the semiconductor material.

5. The photodetector according to claim 4, wherein the first wiring layer includes, as the first part of the coupling part, a beam that extends along the second bonding surface to electrically couple the first pillar and the second pillar to each other.

6. The photodetector according to claim 5, wherein a constituent material of the beam, a constituent material of the first pillar, and a constituent material of the second pillar is a same constituent material.

7. The photodetector according to claim 5, wherein the beam, the first pillar, and the second pillar are integrally formed.

8. The photodetector according to claim 5, wherein a constituent material of the beam is different from each of a constituent material of the first pillar and a constituent material of the second pillar.

9. The photodetector according to claim 8, wherein the first wiring layer further includes a wiring that is electrically coupled to an end part of the first through via in the first direction and is positioned at a layer level same as a layer level of the beam.

10. The photodetector according to claim 4, wherein the second substrate further includes: a first insulating layer interposed between the first pillar and the semiconductor region, and a second insulating layer interposed between the second pillar and the well region.

11. The photodetector according to claim 1, wherein the first substrate further includes a first pad that is electrically coupled to the electric charge accumulator and is exposed on the first bonding surface and wherein the second substrate further includes a second pad that is electrically coupled to the first through via, is exposed on the second bonding surface, and is bonded to the first pad.

12. The photodetector according to claim 1, wherein the second substrate further includes a second wiring layer positioned between the first wiring layer and the second bonding surface.

13. The photodetector according to claim 2, wherein the second substrate further includes a third wiring layer on an opposite side of the semiconductor material to the second bonding surface and wherein the third wiring layer electrically couples the first through via and a gate electrode of the semiconductor element to each other.

14. An electronic apparatus, comprising: a photodetector, wherein the photodetector comprises: a first substrate including: a photoelectric converter; an electric charge accumulator; and a first bonding surface, wherein the photoelectric converter generates electric charge by performing photoelectric conversion on light, wherein the electric charge accumulator accumulates the electric charge; and a second substrate including: a semiconductor material; a first through via formed through both the first substrate and the second substrate; a second bonding surface; and a first wiring layer, wherein the first wiring layer includes a coupling part, wherein the semiconductor material includes a semiconductor element formation surface, wherein the semiconductor element formation surface is a surface on which a semiconductor element is provided, wherein the semiconductor element is included in a readout circuit that outputs a first signal based on the electric charge, wherein the first through via is electrically coupled to the electric charge accumulator, wherein the second bonding surface is positioned on an opposite side of the semiconductor material to the element formation surface and being to the first bonding surface, and wherein the first wiring layer is positioned between the semiconductor material and the second bonding surface.

15. The photodetector according to claim 1, further comprising a third substrate s provided on an opposite side of the second substrate to the first substrate, wherein the third substrate includes a first signal processor electrically coupled to the semiconductor element.

16. The photodetector according to claim 15, further comprising a fourth substrate provided on an opposite side of the third substrate to the second substrate, wherein the fourth substrate includes a second signal processor electrically coupled to the first signal processor, wherein the third substrate further includes a second through via, and wherein the second through via electrically couples the first signal processor and the second signal processor to each other.

17. The photodetector according to claim 16, wherein the second through via has a thickness greater than a thickness of the first through via.

18. The photodetector according to claim 16, wherein the third substrate includes a third bonding surface, wherein the fourth substrate includes a fourth bonding surface bonded to the third bonding surface and wherein an arrangement pitch of multiple second bonding terminal pairs in which multiple third pads exposed on the third bonding surface are bonded to multiple fourth pads exposed on the fourth bonding surface is greater than an arrangement pitch of multiple first bonding terminal pairs in which multiple first pads exposed on the first bonding surface are bonded to multiple second pads exposed on the second bonding surface.

19. The electronic apparatus according to claim 14, wherein the semiconductor material includes: a semiconductor region of a first conductivity type; and a well region that is of a second conductivity type and surrounds the first through via, wherein the second conductivity type is different than the first conductivity type, wherein the well region includes a semiconductor concentration region that is higher in a concentration of an impurity of the second conductivity type than a surrounding region of the semiconductor concentration region, wherein the semiconductor element is provided in the semiconductor region and includes a source-drain region of the second conductivity type, and wherein the first wiring layer includes a first part of the coupling part that electrically couples the semiconductor concentration region in the well region and the source-drain region of the semiconductor element.

20. The electronic apparatus according to claim 19, wherein the coupling part includes a first pillar and wherein the first pillar is coupled to the source-drain region of the semiconductor element and extends in the first direction from the source-drain region of the semiconductor element at least to a back surface of the semiconductor material on an opposite side to the element formation surface of the semiconductor material.

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