Light detection device and semiconductor device

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a first semiconductor layer having a photoelectric conversion element and a floating diffusion; a second semiconductor layer; a first transistor provided on a first surface side of the second semiconductor layer; a through electrode provided so as to penetrate the second semiconductor layer; and a first insulating film and an insulating region provided around the through electrode. In a direction orthogonal to a stacking direction of the first semiconductor layer and the second semiconductor layer, the thickness of the insulating region provided on a second surface side of the second semiconductor layer is larger than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer.

Description

Optical Detection Device and Semiconductor Device

[0001] The present disclosure relates to an optical detection device and a semiconductor device.

[0002] An imaging device having a structure in which a first substrate having sensor pixels and a second substrate having a readout circuit are laminated has been proposed (Patent Document 1).

[0003] International Publication No. 2020 / 170936

[0004] In a device for detecting light, it is desirable to be able to suppress a decrease in quality.

[0005] It is desired to provide an optical detection device capable of suppressing a decrease in quality.

[0006] A photodetector according to one embodiment of the present disclosure comprises a first semiconductor layer having a photoelectric conversion element for photoelectric conversion of light and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; a second semiconductor layer provided to be stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge stored in the floating diffusion; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; and a first insulating film and an insulating region provided around the through electrode in the second semiconductor layer. The first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode. At least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer. At least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface. In a direction orthogonal to the stacking direction of the first and second semiconductor layers, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer. A photodetector according to one embodiment of the present disclosure comprises a first semiconductor layer having a photoelectric conversion element for photoelectric conversion of light and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; a second semiconductor layer provided stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge stored in the floating diffusion; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; a first insulating film provided around the through electrode in the second semiconductor layer; and a conductive film provided around the first insulating film in the second semiconductor layer. The first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode and a source region provided in the second semiconductor layer. The conductive film is electrically connected to the source region of the first transistor.A semiconductor device according to one embodiment of the present disclosure comprises a first semiconductor layer, a second semiconductor layer provided to be stacked with the first semiconductor layer, a first transistor provided on the first surface side of the second semiconductor layer, a through electrode provided around the first transistor so as to penetrate the second semiconductor layer, and a first insulating film and an insulating region provided around the through electrode in the second semiconductor layer. At least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer. At least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface. In a direction orthogonal to the stacking direction of the first and second semiconductor layers, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer. A photodetector according to one embodiment of the present disclosure comprises a first semiconductor layer having a photoelectric conversion element for photoelectric conversion of light and a floating diffusion capable of storing the charge converted by the photoelectric conversion element, and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge stored in the floating diffusion. The first transistor has a first gate electrode provided in the second semiconductor layer. The first gate electrode of the first transistor is electrically connected to the floating diffusion. A photodetector according to one embodiment of the present disclosure comprises a first semiconductor layer having a photoelectric conversion element for photoelectric conversion of light and a floating diffusion capable of storing the charge converted by the photoelectric conversion element, and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge stored in the floating diffusion. The first transistor has a first gate insulating film and a first gate electrode provided so as to sandwich a part of the second semiconductor layer. The first gate electrode of the first transistor is electrically connected to the floating diffusion.

[0007] Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a photodetector according to the first embodiment of this disclosure. Figure 2 is a diagram showing an example of the pixel section of an imaging device according to the first embodiment of this disclosure. Figure 3 is a diagram showing an example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 4 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 5 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 6 is a diagram showing another example of the circuit configuration of a pixel in an imaging device according to the first embodiment of this disclosure. Figure 7 is a diagram showing an example of the cross-sectional configuration of an imaging device according to the first embodiment of this disclosure. Figure 8A is a diagram illustrating an example of the cross-sectional configuration of an imaging device according to the first embodiment of this disclosure. Figure 8B is a diagram illustrating an example of the cross-sectional configuration of an imaging device according to the first embodiment of this disclosure. Figure 9A is a diagram illustrating an example of the planar configuration of an imaging device according to the first embodiment of this disclosure. Figure 9B is a diagram illustrating an example of the planar configuration of an imaging device according to the first embodiment of this disclosure. Figure 10A is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment of this disclosure. Figure 10B is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment of this disclosure. Figure 11 is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment of this disclosure. Figure 12 is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment of this disclosure. Figure 13 is a diagram illustrating an example of the configuration of an imaging device according to the first embodiment of this disclosure. Figure 14A is a diagram illustrating an example of a method for manufacturing an imaging device according to an embodiment of this disclosure. Figure 14B is a diagram illustrating an example of a method for manufacturing an imaging device according to an embodiment of this disclosure. Figure 14C is a diagram illustrating an example of a method for manufacturing an imaging device according to an embodiment of this disclosure. Figure 14D is a diagram illustrating an example of a method for manufacturing an imaging device according to an embodiment of this disclosure. Figure 14E is a diagram illustrating an example of a method for manufacturing an imaging device according to an embodiment of this disclosure. Figure 14F is a diagram illustrating an example of a method for manufacturing an imaging device according to an embodiment of this disclosure. Figure 14G is a diagram illustrating an example of a method for manufacturing an imaging device according to an embodiment of this disclosure.Figure 15 is a diagram illustrating an example configuration of an imaging device according to Modification 1 of the present disclosure. Figure 16 is a diagram illustrating an example configuration of an imaging device according to Modification 1 of the present disclosure. Figure 17 is a diagram illustrating an example configuration of an imaging device according to Modification 1 of the present disclosure. Figure 18 is a diagram illustrating an example configuration of an imaging device according to Modification 2 of the present disclosure. Figure 19 is a diagram illustrating an example configuration of an imaging device according to Modification 2 of the present disclosure. Figure 20 is a diagram illustrating an example configuration of an imaging device according to Modification 3 of the present disclosure. Figure 21 is a diagram illustrating an example configuration of an imaging device according to Modification 3 of the present disclosure. Figure 22 is a diagram illustrating an example configuration of an imaging device according to Modification 3 of the present disclosure. Figure 23 is a diagram illustrating an example configuration of an imaging device according to Modification 3 of the present disclosure. Figure 24 is a diagram illustrating another example configuration of an imaging device according to Modification 3 of the present disclosure. Figure 25 is a diagram illustrating another example configuration of an imaging device according to Modification 3 of the present disclosure. Figure 26 is a diagram illustrating another example configuration of an imaging device according to Modification 3 of the present disclosure. Figure 27 is a diagram illustrating an example configuration of an imaging device according to Modification 4 of the present disclosure. Figure 28 is a diagram illustrating an example configuration of an imaging device according to Modification 4 of the present disclosure. Figure 29 is a diagram illustrating an example configuration of an imaging device according to Modification 4 of the present disclosure. Figure 30 is a diagram illustrating an example configuration of an imaging device according to Modification 4 of the present disclosure. Figure 31 is a diagram illustrating another example configuration of an imaging device according to Modification 4 of the present disclosure. Figure 32 is a diagram illustrating another example configuration of an imaging device according to Modification 4 of the present disclosure. Figure 33 is a diagram illustrating another example configuration of an imaging device according to Modification 4 of the present disclosure. Figure 34 is a diagram illustrating an example configuration of an imaging device according to the second embodiment of the present disclosure. Figure 35 is a diagram illustrating an example configuration of an imaging device according to the second embodiment of the present disclosure. Figure 36 is a diagram illustrating an example configuration of an imaging device according to Modification 5 of the present disclosure. Figure 37 is a diagram illustrating an example configuration of an imaging device according to Modification 5 of the present disclosure. Figure 38 is a diagram illustrating another example configuration of an imaging device according to Modification 5 of the present disclosure. Figure 39 is a diagram illustrating an example of the cross-sectional configuration of an imaging device according to the third embodiment of the present disclosure. Figure 40 is a diagram illustrating an example of the configuration of an imaging device according to the third embodiment of the present disclosure.Figure 41 is a diagram showing an example of the cross-sectional configuration of an imaging device according to the third embodiment of this disclosure. Figure 42A is a diagram showing an example of the planar configuration of an imaging device according to the third embodiment of this disclosure. Figure 42B is a diagram showing an example of the planar configuration of an imaging device according to the third embodiment of this disclosure. Figure 42C is a diagram showing an example of the planar configuration of an imaging device according to the third embodiment of this disclosure. Figure 43A is a diagram showing another example of the planar configuration of an imaging device according to the third embodiment of this disclosure. Figure 43B is a diagram showing another example of the planar configuration of an imaging device according to the third embodiment of this disclosure. Figure 43C is a diagram showing another example of the planar configuration of an imaging device according to the third embodiment of this disclosure. Figure 44 is a diagram illustrating an example of the configuration of an imaging device according to the third embodiment of this disclosure. Figure 45 is a diagram illustrating an example of the configuration of an imaging device according to the third embodiment of this disclosure. Figure 46A is a diagram showing an example of the manufacturing method of a photodetector according to the third embodiment of this disclosure. Figure 46B is a diagram showing an example of the manufacturing method of a photodetector according to the third embodiment of this disclosure. Figure 46C is a diagram showing an example of the manufacturing method of a photodetector according to the third embodiment of this disclosure. Figure 46D is a diagram showing an example of a method for manufacturing a photodetector according to the third embodiment of this disclosure. Figure 46E is a diagram showing an example of a method for manufacturing a photodetector according to the third embodiment of this disclosure. Figure 46F is a diagram showing an example of a method for manufacturing a photodetector according to the third embodiment of this disclosure. Figure 46G is a diagram showing an example of a method for manufacturing a photodetector according to the third embodiment of this disclosure. Figure 46H is a diagram showing an example of a method for manufacturing a photodetector according to the third embodiment of this disclosure. Figure 46I is a diagram showing an example of a method for manufacturing a photodetector according to the third embodiment of this disclosure. Figure 46J is a diagram showing an example of a method for manufacturing a photodetector according to the third embodiment of this disclosure. Figure 47 is a diagram illustrating an example of a cross-sectional configuration of an imaging device according to the fourth embodiment of this disclosure. Figure 48A is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fourth embodiment of this disclosure. Figure 48B is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fourth embodiment of this disclosure. Figure 48C is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fourth embodiment of this disclosure.Figure 49A is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fourth embodiment of the present disclosure. Figure 49B is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fourth embodiment of the present disclosure. Figure 49C is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fourth embodiment of the present disclosure. Figure 50 is a diagram illustrating an example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 51 is a diagram illustrating an example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 52 is a diagram illustrating another example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 53 is a diagram illustrating another example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 54 is a diagram illustrating another example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 55 is a diagram illustrating another example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 56 is a diagram illustrating another example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 57 is a diagram illustrating another example of the configuration of an imaging device according to Modification 6 of the present disclosure. Figure 58 is a diagram illustrating an example of the cross-sectional configuration of an imaging device according to the eighth embodiment of this disclosure. Figure 59 is a diagram illustrating an example of the configuration of an imaging device according to the eighth embodiment of this disclosure. Figure 60A is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fifth embodiment of this disclosure. Figure 60B is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fifth embodiment of this disclosure. Figure 60C is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fifth embodiment of this disclosure. Figure 61A is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fifth embodiment of this disclosure. Figure 61B is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fifth embodiment of this disclosure. Figure 61C is a diagram illustrating an example of the configuration of a pixel transistor in an imaging device according to the fifth embodiment of this disclosure. Figure 62 is a block diagram showing an example of the configuration of an electronic device having an imaging device. Figure 63 is a block diagram showing an example of the schematic configuration of a vehicle control system. Figure 64 is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit. Figure 65 shows an example of a schematic configuration of an endoscopic surgical system.Figure 66 is a block diagram showing an example of the functional configuration of a camera head and CCU.

[0008] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Fifth Embodiment 6. Application Examples 7. Application Examples

[0009] <1. First Embodiment> Figure 1 is a block diagram showing an example of the schematic configuration of an imaging device, which is an example of a photodetector according to the first embodiment of the present disclosure. Figure 2 is a diagram showing an example of the pixel section of an imaging device according to the first embodiment. A photodetector is a device capable of detecting incident light. An imaging device 1, which is an example of a photodetector, has a plurality of pixels P including a photoelectric conversion section (i.e., a photoelectric conversion region), and is configured to generate a signal by photoelectric conversion of incident light.

[0010] The imaging device 1, for example, receives light transmitted through an optical system (not shown) including an optical lens and generates a signal. The imaging device 1 is constructed using, for example, a semiconductor substrate (Si (silicon) substrate, SOI (Silicon On Insulator) substrate, etc.) on which the photoelectric conversion unit for each pixel P is provided. The imaging device 1 may have a structure (layered structure) composed of multiple semiconductor layers stacked on top of each other.

[0011] The photoelectric conversion unit of a pixel P is, for example, a photodiode (PD) and is configured to convert light into photoelectric energy. The photoelectric conversion unit of each pixel P can also be called a photoelectric conversion element or a photoelectric conversion region. The imaging device 1 has a region (pixel section 100) where a plurality of pixels P are provided, as shown in the example in Figure 1 or Figure 2. The pixel section 100 can also be called a pixel array in which a plurality of pixels P are arranged. The imaging device 1 has, for example, a pixel section 100 in which a plurality of pixels P are arranged in a matrix in two dimensions as an imaging area.

[0012] The imaging device 1 captures incident light (image light) from the subject to be measured through an optical system including an optical lens. The imaging device 1 captures an image of the subject formed by the optical lens. The imaging device 1 can generate pixel signals by photoelectric conversion of the received light (e.g., visible light, infrared light, etc.). The imaging device 1, being a light detection device, is a device capable of receiving light and generating signals, and can also be called a light receiving device.

[0013] The imaging device 1 (light detection device) can be configured as an image sensor, for example. The imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The imaging device 1 can be used in various electronic devices such as digital still cameras, video cameras, and mobile phones.

[0014] As shown in Figure 2, the direction of incidence of light from the subject being measured is defined as the Z-axis direction, the left-right direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the up-down direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction. In subsequent figures, directions may also be indicated based on the direction of the arrows in Figure 2.

[0015] [Outline Configuration of the Imaging Device] The imaging device 1, as an example, includes a pixel section 100, a pixel control unit 110, a signal processing unit 112, a control unit 113, and a processing unit 114, as shown in Figure 1. The imaging device 1 is also provided with, for example, a plurality of control lines Lread and a plurality of signal lines VSL. The number and arrangement of pixels P provided in the pixel section 100 (i.e., pixel array) can be changed as appropriate.

[0016] The control line Lread is a signal line capable of transmitting signals to control pixels P, and is connected to the pixel control unit 110 and the pixels P of the pixel unit 100. In the example shown in Figure 1, multiple control lines Lread are wired to each pixel row of the pixel unit 100, which is composed of multiple pixels P arranged in the row direction (for example, in the X-axis direction). The control line Lread is configured to transmit control signals for reading signals from the pixels P.

[0017] The multiple control lines Lread for each pixel row of the imaging device 1 include, for example, wiring that transmits signals to control the transfer transistor, wiring that transmits signals to control the selection transistor, wiring that transmits signals to control the reset transistor, etc. The control lines Lread can also be called drive lines (or pixel drive lines) that transmit signals to drive the pixels P.

[0018] The signal line VSL is a signal line capable of transmitting signals from pixels P, and is connected to the pixels P of the pixel unit 100 and the signal processing unit 112. In the pixel unit 100, one or more signal lines VSL are wired for each pixel row, which is composed of multiple pixels P arranged in the column direction (for example, in the Y-axis direction). The signal line VSL is electrically connected to the pixels P and is configured to transmit signals output from the pixels P.

[0019] In the imaging device 1, multiple signal lines VSL may be provided for a single pixel row. For example, the imaging device 1 may have multiple signal lines VSL for each pixel row containing multiple pixels P. The number and arrangement of control lines Lread and signal lines VSL in the imaging device 1 are not limited to the illustrated example and can be changed as appropriate.

[0020] The pixel control unit 110 is configured to control each pixel P of the pixel unit 100. The pixel control unit 110 is a control circuit and is composed of multiple circuits, such as a buffer, a shift register, and an address decoder. The pixel control unit 110 generates a signal for controlling the pixels P and outputs it to each pixel P of the pixel unit 100 via the control line Lread. The pixel control unit 110 is controlled by the control unit 113 and controls the pixels P of the pixel unit 100.

[0021] The pixel control unit 110 generates signals for controlling the pixels P, such as signals to control the transfer transistor of the pixel P, signals to control the selection transistor, and signals to control the reset transistor, and supplies these signals to each pixel P via the control line Lread. The pixel control unit 110 can perform control to read out pixel signals from each pixel P. The pixel control unit 110 can also be described as a pixel drive unit (pixel drive circuit) configured to drive each pixel P.

[0022] The signal processing unit 112 is configured to perform signal processing on the input pixel signal. The signal processing unit 112 is a signal processing circuit and includes, for example, a load circuit, an AD (Analog Digital) conversion circuit, a horizontal selection switch, etc. The load circuit is composed of, for example, a current source capable of supplying current to the amplification transistor of the pixel P. As an example, the load circuit together with the amplification transistor of the pixel P constitutes a source follower circuit.

[0023] Furthermore, the signal processing unit 112 may have an amplification circuit configured to amplify the pixel signal read from the pixel P via the signal line VSL. The load circuit, amplification circuit, and AD conversion circuit, etc., are provided, for example, for each of the multiple signal lines VSL. In the imaging device 1, the load circuit, amplification circuit, and AD conversion circuit, etc., may be provided for each pixel row of the pixel section 100.

[0024] The signals output from each pixel P selected and scanned by the pixel control unit 110 are input to the signal processing unit 112 via the signal line VSL. The signal processing unit 112 can perform signal processing such as AD conversion and CDS (Correlated Double Sampling) of the pixel P signals. The signals from each pixel P transmitted via each signal line VSL are processed by the signal processing unit 112 and output to the processing unit 114.

[0025] The processing unit 114 is configured to acquire signals from each pixel P and perform signal processing. The processing unit 114 is a processing circuit and consists of, for example, circuits that perform various signal processing on the input pixel signals. The processing unit 114 is configured to include, as an example, an arithmetic circuit, a memory circuit, and the like.

[0026] The processing unit 114 can perform signal processing on the pixel signals input from the signal processing unit 112 and output the processed pixel signals. The processing unit 114 can perform various signal processing such as noise reduction, interpolation, and gradation correction. The processing unit 114 may include a processor and memory.

[0027] The control unit 113 is configured to control each part of the imaging device 1. The control unit 113 receives data such as a clock and operating mode commands from an external source, and can output data such as internal information of the imaging device 1. The control unit 113 is a control circuit and, for example, has a timing generator configured to generate various timing signals.

[0028] The control unit 113 controls the operation of the pixel control unit 110 and the signal processing unit 112, etc., based on various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. The control unit 113 may include circuits such as a PLL (Phase Locked Loop) and a DAC (Digital to Analog Converter). The control unit 113 and the processing unit 114 may be configured as an integrated unit.

[0029] The pixel unit 100, pixel control unit 110, signal processing unit 112, control unit 113, processing unit 114, etc., described above may be provided on a single substrate or on multiple substrates. The imaging device 1 may have a laminated structure formed by stacking multiple substrates.

[0030] The pixel control unit 110, signal processing unit 112, control unit 113, processing unit 114, etc. of the imaging device 1 may be provided, for example, as peripheral circuits in the peripheral area of ​​the pixel unit 100. Note that some or all of the signal processing unit 112, control unit 113, and processing unit 114 may be configured as a single unit.

[0031] [Pixel Configuration] Figure 3 shows an example of the circuit configuration of a pixel in an imaging device according to the first embodiment. A pixel P has a photoelectric conversion unit 11 (photoelectric conversion element), a transistor TG, a floating diffusion FD, and a readout circuit 20. The photoelectric conversion unit 11 is configured to receive light and generate a signal. The photoelectric conversion unit 11 (i.e., the photoelectric conversion region) is configured to generate electric charge by photoelectric conversion.

[0032] In the example shown in Figure 3, the photoelectric conversion unit 11 is a photodiode (PD) that converts incident light into electric charge. The photoelectric conversion unit 11 can perform photoelectric conversion to generate an electric charge corresponding to the amount of light received. The photoelectric conversion unit 11 can also be called a light receiving unit (light receiving element). The readout circuit 20 is configured to output a signal based on the photoelectrically converted charge.

[0033] The transistor TG is configured to transfer the charge photoelectrically converted in the photoelectric conversion unit 11 to the floating diffusion FD. The transistor TG is controlled by the signal STG to electrically connect or disconnect the photoelectric conversion unit 11 and the floating diffusion FD. The transistor TG is a transfer transistor. The transistor TG can transfer the charge photoelectrically converted and stored in the photoelectric conversion unit 11 to the floating diffusion FD.

[0034] The floating diffusion FD is a storage unit and is configured to store the transferred charge. The floating diffusion FD can store the charge photoelectrically converted by the photoelectric conversion unit 11. The floating diffusion FD stores the transferred charge and converts it into a voltage corresponding to the capacitance of the floating diffusion FD. The floating diffusion FD can also be described as a storage unit capable of holding charge.

[0035] The readout circuit 20 includes, for example, a transistor AMP, a transistor SEL, and a transistor RST. The readout circuit 20 can read out pixel signals based on the charge photoelectrically converted in the photoelectric conversion unit 11 (photoelectric conversion region). The readout circuit 20 may also include a floating diffusion FD.

[0036] The transistor AMP is configured to generate and output a signal based on the charge stored in the floating diffusion FD. The transistor AMP is an amplifying transistor. The transistor AMP can generate and output a signal based on the charge converted by the photoelectric conversion unit 11.

[0037] The gate of the transistor AMP is electrically connected to the floating diffusion diode (FD), and the voltage converted by the floating diffusion diode is input to it. The drain of the transistor AMP is connected to a power line that supplies, for example, the power supply voltage (the power supply voltage VDD in the example shown in Figure 3).

[0038] The source of the transistor AMP is connected to the signal line VSL, for example, via the transistor SEL. The transistor AMP is configured to generate a signal based on the charge stored in the floating diffusion FD, i.e., a signal based on the voltage of the floating diffusion FD, and output it to the signal line VSL.

[0039] The transistor SEL is configured to control the output of the pixel signal. The transistor SEL is electrically connected in series with the transistor AMP, for example, as shown in Figure 3. The transistor SEL is controlled by the signal SSEL and is configured to output the signal from the transistor AMP to the signal line VSL. The transistor SEL is a selection transistor. The transistor SEL can control the timing of the pixel signal output.

[0040] The transistor SEL is configured to output a signal based on the charge converted by the photoelectric conversion unit 11. The transistor SEL can output the pixel signal of pixel P to the signal line VSL. The transistor SEL may also be electrically connected in series between the power line to which the power supply voltage (power supply voltage VDD in Figure 3) is supplied and the transistor AMP. Furthermore, the transistor SEL may be omitted if necessary.

[0041] The transistor RST is configured to reset the voltage of the floating diffusion FD. In the example shown in Figure 3, the transistor RST is electrically connected to a power line to which the power supply voltage VDD is supplied and is configured to perform a reset of the charge of pixel P. The transistor RST is a reset transistor.

[0042] The transistor RST is controlled by the signal SRST, resets the charge accumulated in the floating diffusion FD, and can reset the voltage of the floating diffusion FD. The transistor RST, for example, electrically connects the power supply line and the floating diffusion FD to discharge the charge accumulated in the floating diffusion FD. Note that the transistor RST can reset the charge accumulated in the photoelectric conversion unit 11 via the transistor TG.

[0043] The readout circuit 20 may be configured to be able to change the conversion gain (i.e., conversion efficiency) when converting charge to voltage. The readout circuit 20, for example, as shown in FIG. 4, has a transistor FDG and can be configured to be able to change the conversion gain. The transistor FDG is a switching transistor and can be used for setting the conversion gain.

[0044] The transistor FDG is, for example, electrically connected between the floating diffusion FD and the transistor RST. In the example shown in FIG. 4, the transistor FDG is configured to be able to electrically connect the floating diffusion FD and the transistor RST.

[0045] The transistor FDG is, for example, controlled by the signal SFDG to electrically connect or disconnect the floating diffusion FD and the transistor RST. In the readout circuit 20, when the transistor FDG is turned on, the capacitance added to the floating diffusion FD of the pixel P increases, and the conversion gain (conversion efficiency) when converting charge to voltage is switched.

[0046] The transistor FDG can change the conversion gain by switching the capacitance connected to the gate of the transistor AMP. Note that the transistor FDG may be electrically connected in series or in parallel to the transistor RST.

[0047] The above-described transistor TG (transfer transistor), transistor AMP (amplification transistor), transistor SEL (selection transistor), transistor RST (reset transistor), and transistor FDG (switching transistor) are each, for example, a MOS transistor (MOSFET) having gate, source, and drain terminals.

[0048] In the example shown in FIG. 3 or FIG. 4, the transistor TG, transistor AMP, transistor SEL, transistor RST, and transistor FDG are each constituted by an NMOS transistor. Note that the transistor of the pixel P may be constituted by a PMOS transistor.

[0049] The pixel control unit 110 (see FIG. 1) of the imaging device 1 supplies a control signal to the gates of the transistors TG, SEL, RST, FDG, etc. of each pixel P via the above-described control line Lread, to turn the transistors on (conducting state) or off (non-conducting state).

[0050] As an example, the plurality of control lines Lread for each pixel row of the imaging device 1 include a wiring for transmitting a signal STG for controlling the transistor TG, a wiring for transmitting a signal SSEL for controlling the transistor SEL, a wiring for transmitting a signal SRST for controlling the transistor RST, a wiring for transmitting a signal SFDG for controlling the transistor FDG, and the like.

[0051] The transistors TG, SEL, RST, and FDG, etc. are turned on and off by the pixel control unit 110. The pixel control unit 110 causes a pixel signal to be output from each pixel P to the signal line VSL by controlling the readout circuit 20 of each pixel P. The pixel control unit 110 can perform control to read out the pixel signal of each pixel P to the signal line VSL.

[0052] Figure 5 shows another example of the pixel circuit configuration of the imaging device according to the first embodiment. The imaging device 1 may have a configuration in which a plurality of pixels P share one readout circuit 20. In the imaging device 1, the readout circuit 20 may be provided for a plurality of pixels P. In this case, it is possible to reduce the number of circuit elements (e.g., the number of transistors) per pixel P (or per photoelectric conversion unit 11).

[0053] As an example, as shown in Figure 5, a readout circuit 20 is provided for every four pixels P (referred to as pixels Pa to Pd). Pixels Pa, Pb, Pc, and Pd share one readout circuit 20. For example, a 2x2 pixel array composed of adjacent pixels Pa to Pd shares one readout circuit 20.

[0054] The imaging device 1 can read out the pixel signal of each 2x2 pixel by operating the readout circuit 20 in a time-division manner. The imaging device 1 can also read out a pixel signal which is the sum of the signals of each 2x2 pixel. For example, the imaging device 1 can read out a pixel signal corresponding to the charge obtained by summing the charges converted photoelectrically by each of the 2x2 pixels.

[0055] The photoelectric conversion unit 11 (in the example shown in Figure 5, the photodiode PD of pixel Pa to the photodiode PD of pixel Pd) can perform photoelectric conversion to generate charge according to the amount of light received. The transistors TG (in Figure 5, the transistor TG of pixel Pa to the transistor TG of pixel Pd) are configured to transfer the charge converted photoelectrically by the photoelectric conversion unit 11 to the floating diffusion FD.

[0056] In the example shown in Figure 5, the transistors TG of pixels Pa to Pd are controlled on and off by different signals. The transistor TG of pixel Pa is controlled by signal STG1, and the transistor TG of pixel Pb is controlled by signal STG2. The transistor TG of pixel Pc is controlled by signal STG3, and the transistor TG of pixel Pd is controlled by signal STG4.

[0057] The imaging device 1 may have a configuration in which five or more pixels P, for example eight pixels P, share one readout circuit 20. For example, in the imaging device 1, a readout circuit 20 is provided for every eight pixels P, and the eight pixels P share one readout circuit 20. Alternatively, 2x4 pixels may share one readout circuit 20.

[0058] The transistors AMP and RST may be electrically connected to different power lines. For example, as shown in Figure 6, the drain of transistor AMP is electrically connected to the power line supplying power voltage VDD1, and the drain of transistor RST is electrically connected to the power line supplying power voltage VDD2. The drain potentials of transistor RST and transistor AMP can be controlled individually (independently).

[0059] [Configuration of the Imaging Device] Figure 7 is a diagram showing an example of the cross-sectional configuration of an imaging device according to the first embodiment. The imaging device 1 has, for example, a layer 201, a layer 202, and a layer 203, as shown in the example in Figure 7. The imaging device 1 has a configuration in which layer 201 (first layer), layer 202 (second layer), and layer 203 (third layer) are stacked in the Z-axis direction.

[0060] In the example shown in Figure 7, layer 201 has a semiconductor layer 101 and a wiring layer 111. Layer 202 has a semiconductor layer 102, a wiring layer 121 and a wiring layer 122. Layer 203 has a semiconductor layer 103 and a wiring layer 131. From the side where light is incident, the semiconductor layer 101, wiring layer 111, wiring layer 122, semiconductor layer 102, wiring layer 121, wiring layer 131, and semiconductor layer 103 are provided.

[0061] The semiconductor layers 101, 102, and 103 are composed of semiconductor substrates such as silicon substrates and SOI (Silicon On Insulator) substrates. The semiconductor layers 101, 102, and 103 may also be composed of SiGe (silicon germanium) substrates, SiC (silicon carbide) substrates, or may be formed using other semiconductor materials.

[0062] Furthermore, the semiconductor layer 101 and the wiring layer 111 can be collectively referred to as the first substrate (or first circuit layer). The semiconductor layer 102, the wiring layer 121, and the wiring layer 122 can be collectively referred to as the second substrate (or second circuit layer). In addition, the semiconductor layer 103 and the wiring layer 131 can be collectively referred to as the third substrate (or third circuit layer).

[0063] As shown in Figure 7, the semiconductor layer 101 has opposing surfaces 11S1 and 11S2. Surface 11S2 is the surface opposite to surface 11S1. For example, surface 11S2 of the semiconductor layer 101 is the light-receiving surface (i.e., the light-incident surface). Surface 11S1 of the semiconductor layer 101 is the element-forming surface on which elements such as transistors and capacitive elements are formed. Surface 11S1 may be provided with a thermoelectromagnetic film, a gate insulating film (e.g., a gate oxide film), etc.

[0064] Multiple photoelectric conversion units 11 are provided in the semiconductor layer 101. The photoelectric conversion units 11 are provided between surfaces 11S1 and 11S2 of the semiconductor layer 101. The photoelectric conversion units 11 are photoelectric conversion elements, and can also be called photoelectric conversion regions. For example, multiple photoelectric conversion units 11 are embedded and formed in the semiconductor layer 101.

[0065] The semiconductor layer 102 has opposing surfaces 12S1 and 12S2. Surface 12S2 is the surface opposite to surface 12S1. The semiconductor layer 103 also has opposing surfaces 13S1 and 13S2. Surface 13S2 is the surface opposite to surface 13S1. Surfaces 12S1 and 13S1 are, for example, element formation surfaces on which elements such as transistors are formed. Geothermal electrodes, gate insulating films, etc., may be provided on each of surfaces 12S1 and 13S1.

[0066] On the surface 11S1 side of the semiconductor layer 101, for example, the transistor TG and floating diffusion FD of the aforementioned pixel P are provided. The floating diffusion FD is composed of, for example, an n-type semiconductor region. On the surface 12S1 side of the semiconductor layer 102, each transistor of the readout circuit 20 (transistors AMP, SEL, RST, FDG, etc.) is provided.

[0067] A wiring layer 111 is provided on the surface 11S1 side of the semiconductor layer 101. A wiring layer 121 is provided on the surface 12S1 side of the semiconductor layer 102, and a wiring layer 122 is provided on the surface 12S2 side of the semiconductor layer 102. In addition, a wiring layer 131 is provided on the surface 13S1 side of the semiconductor layer 103. Each of the wiring layers 111, 121, 122, and 131 includes, for example, a conductive film and an insulating film, and has a plurality of wirings and a plurality of vias.

[0068] The wiring layers 111, 121, 122, and 131 each have a configuration in which multiple wirings are stacked with an insulating film acting as an interlayer insulating film. Each of the wiring layers 111, 121, 122, and 131 is configured as a multilayer wiring layer and contains two or more layers, or three or more layers of wiring. Each of the wirings in the wiring layers 111, 121, 122, and 131 is formed using a metallic material such as aluminum (Al), tungsten (W), or copper (Cu).

[0069] Each of the wirings in the wiring layers 111, 121, 122, and 131 may be constructed using polysilicon (Poly-Si) or other conductive materials. The interlayer insulating film is formed using, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. The interlayer insulating film may also be constructed using other insulating materials.

[0070] Multiple electrodes 91 are provided on the wiring layer 111, and multiple electrodes 92 are provided on the wiring layer 122. Furthermore, multiple electrodes 93 are provided on the wiring layer 121, and multiple electrodes 94 are provided on the wiring layer 131. Electrodes 91, 92, 93, and 94 are, for example, electrodes formed using copper (Cu).

[0071] Electrodes 91, 92, 93, and 94 are electrodes used for joining metal electrodes and can be called joining electrodes. For example, semiconductor layer 101 and semiconductor layer 102 are bonded together by joining metal electrodes made of Cu (electrodes 91 and 92), i.e., Cu-Cu joining. Electrodes 91 and 92 electrically connect the circuit provided on the semiconductor layer 101 side and the circuit provided on the semiconductor layer 102 side.

[0072] In the example shown in Figure 7, semiconductor layer 101 and semiconductor layer 102 are laminated by bonding between electrodes such that surfaces 11S1 and 12S2 face each other. That is, semiconductor layer 101 and semiconductor layer 102 are bonded so that the surface of semiconductor layer 101 and the back surface of semiconductor layer 102 face each other. Semiconductor layer 101 and semiconductor layer 102 can be laminated so that the surface 11S1 of semiconductor layer 101 on which the floating diffusion FD is provided faces the surface 12S2 of semiconductor layer 102.

[0073] Furthermore, in the example shown in Figure 7, semiconductor layers 102 and 103 are bonded together by a junction between electrodes 93 and 94 made of Cu, i.e., a Cu-Cu junction. Electrodes 93 and 94 electrically connect the circuit provided on the semiconductor layer 102 side to the circuit provided on the semiconductor layer 103 side.

[0074] The semiconductor layer 102 and the semiconductor layer 103 are stacked, for example, by bonding between electrodes, so that surfaces 12S1 and 13S1 face each other. That is, the semiconductor layer 102 and the semiconductor layer 103 are bonded so that the surface of semiconductor layer 102 and the surface of semiconductor layer 103 face each other. At least some of the above-mentioned pixel control unit 110, signal processing unit 112, control unit 113, processing unit 114 (see Figure 1) are provided on the semiconductor layer 103 and the wiring layer 131.

[0075] The electrodes 91, 92, 93, and 94 may each be made of a metal material other than copper, such as nickel (Ni), cobalt (Co), tin (Sn), gold (Au), etc., or they may be made of other materials. Furthermore, a layer 201 containing the semiconductor layer 101, a layer 202 containing the semiconductor layer 102, and a layer 203 containing the semiconductor layer 103 may be stacked using bumps.

[0076] The imaging device 1 has a lens 14 and a filter 15, as shown in the example in Figure 7. The lens 14 and the filter 15 are provided, for example, on the side of the semiconductor layer 101 facing surface 11S2. The lens 14 and the filter 15 are stacked on the semiconductor layer 101 in the thickness direction (i.e., the Z-axis direction) perpendicular to the surface 11S2 of the semiconductor layer 101. The lens 14 and the filter 15 are provided on the side where light is incident, and the wiring layer 111 is provided on the side opposite to the side where light is incident.

[0077] The lens 14 is a lens that focuses light and is also called an on-chip lens. The lens 14 is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. The lens 14 may also be formed using other light-transmitting materials. The lens 14 is provided, for example, above the photoelectric conversion unit 11 for each pixel P or for each of a group of pixels P.

[0078] Light from the subject to be measured enters the lens 14 through an optical system such as an imaging lens. The lens 14 (lens part) guides the incident light toward the photoelectric conversion unit 11. In the imaging device 1, the photoelectric conversion unit 11 of the pixel P converts the incident light via the lens 14 into photoelectric energy. The photoelectric conversion unit 11 can absorb the incident light and generate an electric charge.

[0079] The filter 15 is configured, for example, to selectively transmit light in a specific wavelength band from the incident light. The filter 15 is, for example, a primary color system (RGB) color filter and is provided between the lens 14 and the semiconductor layer 101. The filter 15 is positioned, for example, above the photoelectric conversion unit 11 for each pixel P or for each of a group of pixels P.

[0080] The filter 15 may be a complementary color filter (CMY), an infrared light-transmitting filter, or the like. The photoelectric conversion unit 11 converts the light incident through the lens 14 and the filter 15 into photoelectric light. In the imaging device 1, the filter 15 may be omitted if necessary. The filter 15 does not need to be provided for some or all of the pixels P of the imaging device 1. For example, the filter 15 does not need to be provided for a pixel P that receives white (W) light and performs photoelectric conversion.

[0081] Furthermore, the imaging device 1 has a separation region 17, as shown in the example in Figure 7. The separation region 17 is a separation region (separation section) provided around a pixel P (or photoelectric conversion unit 11). The separation region 17 is provided in the semiconductor layer 101 between a plurality of adjacent pixels P, separating the pixels P (or photoelectric conversion unit 11). The separation region 17 is constructed, for example, using a trench (groove).

[0082] The isolation region 17 is arranged in a grid pattern, for example, in a plan view (i.e., viewed in the XY plane), so as to surround each photoelectric conversion unit 11 of each pixel P. At least a portion of the isolation region 17 is formed at the boundary between adjacent pixels P (or photoelectric conversion units 11). The isolation region 17 can also be called a pixel isolation region or a pixel isolation wall. The isolation region 17 may be provided so as to penetrate the semiconductor layer 101.

[0083] An insulating film, such as a silicon oxide film, silicon nitride film, or aluminum oxide film, is provided in the trench of the isolation region 17. Polysilicon, a metallic material, or other insulating material may be embedded in the trench of the isolation region 17. The isolation region 17 may be composed of a semiconductor region (p-type or n-type semiconductor region) formed by ion implantation.

[0084] The isolation region 17 may be formed using another insulating material having a low refractive index. A gap (cavity) may be provided within the isolation region 17. By providing the isolation region 17, leakage of charge converted by the photoelectric conversion unit 11 of the pixel P to surrounding pixels P (or photoelectric conversion unit 11) is suppressed. In addition, leakage of unwanted light to surrounding pixels P is suppressed, and for example, color mixing can be suppressed.

[0085] The imaging device 1 has through electrodes 25, for example, as shown in Figure 7. The through electrodes 25 are connecting electrodes (connecting parts) that connect circuits (elements) provided in different layers. For example, multiple through electrodes 25 are provided in the semiconductor layer 102 for each pixel P or for each of a group of pixels P. The through electrodes 25 are provided so as to penetrate the semiconductor layer 102. The through electrodes 25 are, for example, TSVs (Through Silicon Vias).

[0086] The through-electrode 25 is formed using a metallic material such as tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), or silver (Ag). The through-electrode 25 may extend in the stacking direction (Z-axis direction in Figure 7) of the semiconductor layers 101, 102, etc., and reach into the wiring layer 121. The through-electrode 25 may also be formed using cobalt (Co), ruthenium (Ru), etc. The through-electrode 25 may be composed of other conductive materials.

[0087] In the imaging device 1, the floating diffusion FD of the semiconductor layer 101 is electrically connected to a circuit (for example, a transistor of the readout circuit 20) provided on the surface 12S1 side of the semiconductor layer 102 via electrodes 91, 92 and through electrode 25. The readout circuit 20 is electrically connected to a circuit (for example, a signal processing unit 112) provided on the semiconductor layer 103 via electrodes 93, 94.

[0088] The charge photoelectrically converted by the photoelectric conversion unit 11 of the semiconductor layer 101 can be transferred via the transistor TG to the floating diffusion FD of the semiconductor layer 101 and the readout circuit 20 of the semiconductor layer 102. The readout circuit 20 can, for example, generate a pixel signal based on the charge converted by the photoelectric conversion unit 11 and output the pixel signal to the signal processing unit 112 of the semiconductor layer 103 via the signal line VSL.

[0089] The floating diffusion FD of pixel P is electrically connected to transistors AMP, RST, etc. of semiconductor layer 102 via electrodes 91, 92 and through electrodes 25, as shown in the example in Figure 7. The through electrodes 25, which are provided in correspondence with the floating diffusion FD of semiconductor layer 101, can be considered part of the floating diffusion FD. Note that the floating diffusion FD may include electrodes 91, 92.

[0090] The photoelectric conversion unit 11, transistor TG, and floating diffusion FD for each pixel P are provided in layer 201. The transistors (transistors AMP, SEL, RST, etc.) of the readout circuit 20 are provided in layer 202. The photoelectric conversion unit 11 and the transistors of the readout circuit 20 are arranged in separate layers. Therefore, the imaging device 1 can have a structure advantageous for pixel miniaturization.

[0091] Figures 8A and 8B are diagrams illustrating an example of the cross-sectional configuration of the imaging device according to the first embodiment. Figures 9A and 9B are diagrams illustrating an example of the planar configuration of the imaging device. Figure 8A corresponds, for example, to an example of the cross-sectional configuration of the imaging device 1 in the direction of line A-A' shown in Figure 9A. Figure 8B corresponds, for example, to an example of the cross-sectional configuration of the imaging device 1 in the direction of line B-B' shown in Figure 9B.

[0092] The through-electrode 25 is provided, for example, around the transistor AMP so as to penetrate the semiconductor layer 102. The transistor AMP has a gate electrode 45 provided on the surface 12S1 side of the semiconductor layer 102. The gate electrode 45 is made of, for example, polysilicon (Poly-Si). The gate electrode 45 of the transistor AMP is electrically connected to the floating diffusion FD of the semiconductor layer 101 via the through-electrode 25.

[0093] As shown in Figures 8A and 8B, the semiconductor layer 102 has wells 31. The wells 31 are, for example, p-type semiconductor regions, and are p-type wells (p-wells). Wells 31, which are p-type well regions, are provided on the surface 12S1 side of the semiconductor layer 102. The wells 31 may be n-type semiconductor regions, which are n-type well regions, as needed.

[0094] As shown in Figure 8B and the like, the transistor AMP of the readout circuit 20 has the gate electrode 45 described above, a semiconductor region 41, and a semiconductor region 42. The semiconductor region 41 and semiconductor region 42 are provided in the well 31. The semiconductor region 41 and semiconductor region 42 are semiconductor regions of a different conductivity type than the well 31 and are formed on the surface 12S1 side of the semiconductor layer 102.

[0095] Semiconductor regions 41 and 42 are the source and drain regions of the transistor AMP. Semiconductor regions 41 and 42 are regions formed using impurities, for example, n-type semiconductor regions. For example, semiconductor regions 41 and 42 each have an impurity concentration higher than the impurity concentration of well 31 and are configured as n+-type semiconductor regions.

[0096] In the example shown in Figure 8B, the semiconductor region 41 is the source region of the transistor AMP, and the semiconductor region 42 is the drain region of the transistor AMP. The semiconductor region 41, which is the source region of the transistor AMP, is electrically connected to the signal line VSL via the transistor SEL. The semiconductor region 42, which is the drain region of the transistor AMP, is electrically connected to the power line to which the power supply voltage (e.g., power supply voltage VDD) is supplied.

[0097] Furthermore, isolation regions 18 are provided in the semiconductor layer 102. The isolation regions 18 are constructed, for example, using trenches and have an STI (Shallow Trench Isolation) structure. An insulating film, such as a silicon oxide film or a silicon nitride film, is provided within the trenches of the isolation regions 18. The isolation regions 18 are formed on the side of the semiconductor layer 102 surface 12S1, which is the element formation surface, and separate the elements.

[0098] The imaging device 1 has an insulating film 51 and an insulating region 55, as shown in the example in Figure 7. The insulating film 51 and the insulating region 55 are provided around the through electrode 25 in the semiconductor layer 102. At least a portion of the insulating film 51 is provided on the surface 12S1 side of the semiconductor layer 102. At least a portion of the insulating region 55 is provided on the surface 12S2 side of the semiconductor layer 102.

[0099] The insulating film 51 and the insulating region 55 are constructed, for example, using an insulating material and are provided on the side surface (side) of the through electrode 25. The insulating film 51 and the insulating region 55 can each be arranged along the side surface (side wall) of the through electrode 25. The insulating film 51 and the insulating region 55 are provided, for example, to surround the through electrode 25 in a plan view (i.e., viewed in the XY plane).

[0100] The insulating film 51 and the insulating region 55 are provided, for example, to surround all four sides of the through electrode 25. Each of the insulating film 51 and the insulating region 55 may have a predetermined thickness and be formed to cover the periphery of the through electrode 25. A portion of each of the insulating film 51 and the insulating region 55 may be located between the through electrode 25 and the transistor AMP.

[0101] The insulating film 51 and the insulating region 55 are provided, for example, adjacent to the through electrode 25. For example, a portion of the through electrode 25 is provided in contact with the insulating film 51, and another portion of the through electrode 25 is provided in contact with the insulating region 55. A portion of the insulating film 51 may be provided within the wiring layer 121. A portion of the insulating region 55 may be provided within the wiring layer 122.

[0102] As shown in Figure 8A, a portion of the insulating film 51 is provided between the through electrode 25 and the isolation region 18 in the semiconductor layer 102. Also, as shown in Figure 8B, another portion of the insulating film 51 is formed between the through electrode 25 and the semiconductor region 41 of the transistor AMP. The semiconductor region 41 is, for example, the source region of the transistor AMP.

[0103] The insulating film 51 and the insulating region 55 are insulating films (insulators) such as oxide films, nitride films, and oxynitride films. In the example shown in Figure 8A, the insulating region 55 is composed of an insulating film 52. The insulating film 51 and the insulating film 52 may be composed of insulating materials such as silicon oxide (SiO) and silicon nitride (SiN). The insulating film 51 and the insulating film 52 may be composed of insulating materials such as silicon oxynitride (SiON) and aluminum oxide (AlO), or other materials.

[0104] The insulating film 51 and part or all of the insulating region 55 (i.e., insulating film 52) may be formed continuously and provided as a single unit. The insulating film 51 and insulating film 52 may be provided continuously around the through electrode 25, for example. The insulating film 51 and the insulating region 55 can also be collectively referred to as the insulating region (or insulating film). The insulating film 51 and the insulating region 55 (insulating film 52) may be made of different materials.

[0105] The insulating film 51 and the insulating region 55 are provided with different thicknesses in a direction perpendicular to the stacking direction of the semiconductor layer 101 and the semiconductor layer 102. The imaging device 1 is configured such that, for example, the thickness of the insulating region 55 provided on the surface 12S2 side of the semiconductor layer 102 in the X-axis direction (or Y-axis direction) is greater than the thickness of the insulating film 51 provided on the surface 12S1 side in the X-axis direction (or Y-axis direction).

[0106] The insulating region 55 is formed such that, for example, in a direction perpendicular to the thickness direction (Z-axis direction) of the semiconductor layer 102, i.e., in the X-axis direction (or Y-axis direction), it has a thickness greater than the thickness of the insulating film 51 provided within the semiconductor layer 102. In the examples shown in Figures 8A and 8B, the thickness of the insulating region 55 provided in the semiconductor layer 102 is greater than the thickness of the insulating film 51 provided within the semiconductor layer 102.

[0107] As shown in the example in Figure 10A, the thickness t2 (film thickness) of the insulating region 55 (i.e., the insulating film 52) may be greater than the thickness t1 of the insulating film 51. Also, as shown in Figure 10B, the width w2 (diameter) of the insulating region 55 surrounding the through electrode 25 may be set to be greater than the width w1 (diameter) of the insulating film 51 surrounding the through electrode 25. It can also be said that the insulating film 51 and the insulating region 55 are integrally constructed and have a portion that is wider (thicker) on the surface 12S2 side.

[0108] As described above, the imaging device 1 according to this embodiment has an insulating film 51 and an insulating region 55 provided around the through electrode 25. The insulating region 55 is configured to have a thickness greater than the thickness of the insulating film 51 on the surface 12S2 side of the semiconductor layer 102. This makes it possible to reduce the parasitic capacitance formed with respect to the through electrode 25.

[0109] Compared to a case where the imaging device 1 does not have an insulating film 51 and an insulating region 55, the parasitic capacitance added to the through electrode 25, i.e., the parasitic capacitance added to the floating diffusion FD, can be reduced. Therefore, the conversion gain (conversion efficiency) when converting charge to voltage in the floating diffusion FD can be improved.

[0110] In the imaging device 1 according to this embodiment, unwanted parasitic capacitance added to the through-electrode 25, which is part of the floating diffusion FD, can be reduced, thereby suppressing a degradation in the quality of the pixel signal. This makes it possible to suppress a degradation in the image quality of the image generated using the pixel signal.

[0111] Furthermore, in this embodiment, parasitic capacitance can be reduced by the insulating region 55 provided on the surface 12S2 opposite to the element formation surface, and the area for arranging the transistors of the pixel P on the surface 12S1, which is the element formation surface, can be secured. This makes it possible to increase the area for arranging the transistors of the readout circuit 20.

[0112] In the imaging device 1, the area for arranging the transistors of the readout circuit 20, such as the transistor AMP, can be made wider (larger). In particular, even in low light conditions, a decrease in the signal-to-noise ratio can be suppressed, making it possible to obtain pixel signals with less noise. In this embodiment, it is possible to suppress unwanted parasitic capacitance added to the through-electrode 25 while securing the area of ​​the element formation region.

[0113] Furthermore, the imaging device 1 is provided with wells 32 and semiconductor regions 43, as shown in the examples in Figures 8A and 8B. The wells 32 are provided around the insulating film 51 in the semiconductor layer 102. The wells 32 are, for example, n-type semiconductor regions and are n-type wells (n-wells). The wells 32 may be p-type semiconductor regions as p-type well regions as needed.

[0114] The well 32 is provided, for example, in the semiconductor layer 102, along the insulating film 51 adjacent to the through electrode 25. The well 32 may be provided so as to surround the through electrode 25 and the insulating film 51 in a plan view, as in the example shown in Figure 9A or Figure 9B. The well 32 may be formed to cover the insulating film 51. At least a portion of the well 32 is provided between the through electrode 25 and the well 31, and is located between the through electrode 25 and the transistor AMP.

[0115] The well 32 is provided adjacent to the insulating film 51 surrounding the through electrode 25. The well 32 is provided, for example, on the side of the semiconductor layer 102 surface 12S1, in contact with the insulating film 51. At least a portion of the well 32 is provided between the insulating film 51 and the semiconductor region 41 of the transistor AMP (i.e., the source region of the transistor AMP).

[0116] The semiconductor region 43 is a semiconductor region of the same conductivity type as the well 32. The semiconductor region 43 is a well contact region and is provided relative to the well 32. The semiconductor region 43 has, for example, a higher impurity concentration than the well 32 and is configured as an n+ type semiconductor region. The semiconductor region 43 is an n+ type diffusion region and can also be called an n+ type conductive region.

[0117] The semiconductor region 43 is electrically connected to, for example, the source region of the transistor AMP. In the example shown in Figure 8B, the semiconductor region 43 is electrically connected to the semiconductor region 41, which is the source region of the transistor AMP, via vias (also called contacts) and wiring of the wiring layer 121. The well 32 is electrically connected to the source region of the transistor AMP by the semiconductor region 43 and the wiring of the wiring layer 121.

[0118] Thus, the imaging device 1 according to this embodiment may have a well 32 provided around the insulating film 51. The well 32 is electrically connected to the source region of the transistor AMP, i.e., the semiconductor region 41. As a result, as schematically shown by the dotted line in Figure 10A or Figure 10B, the parasitic capacitance Cp formed on the through electrode 25, which is part of the floating diffusion FD, is electrically connected to the semiconductor region 41, which is the source region of the transistor AMP.

[0119] In the imaging device 1, as schematically shown in Figure 11, a parasitic capacitance Cp formed in the through electrode 25 and insulating film 51 can be added between the floating diffusion FD and the source region of the transistor AMP of the source follower circuit. By placing the parasitic capacitance Cp in the feedback path, it becomes possible to reduce the capacitance of the floating diffusion FD by utilizing the Miller effect.

[0120] In imaging device 1, the insulating film 51 and insulating region 55 reduce the capacitance of the floating diffusion FD and improve the conversion gain. In particular, even with fine pixels, it is possible to suppress the inclusion of noise in the pixel signal and improve the quality of the pixel signal. This makes it possible to suppress the deterioration of image quality. It becomes possible to realize an optical detection device (imaging device) that is advantageous for miniaturization.

[0121] Figures 12 and 13 are diagrams illustrating an example of the configuration of an imaging device according to the first embodiment. The insulating film 51 and the insulating region 55 (i.e., the insulating film 52) may be made of the same material or of different materials. The insulating film 51 and the insulating region 55 may be configured, for example, to have different dielectric constants.

[0122] The insulating film 51 may be provided from the surface 12S2 side to the surface 12S1 side of the semiconductor layer 102, for example, as shown in the example in Figure 12. The insulating film 51 may be provided so as to reach the surface 12S2 of the semiconductor layer 102. The insulating film 51 and the insulating region 55 may be configured to include a gap (air). For example, the insulating region 55 may be composed of a gap (cavity).

[0123] Figures 14A to 14G illustrate an example of a method for manufacturing an imaging device according to an embodiment. First, as shown in Figure 14A, wells 31 (i.e., Pwell) and wells 32 (i.e., Nwell) are formed in the semiconductor layer 102. Then, as shown in Figure 14B, transistors, wiring layers 121, etc., of the readout circuit 20 are formed on the surface 12S1 side of the semiconductor layer 102.

[0124] Next, as shown in Figure 14C, the semiconductor layer 102 is partially removed by etching (for example, dry etching or wet etching) the surface 12S2 of the semiconductor layer 102. Then, as shown in Figure 14D, an insulating region 55, for example, an insulating film 52, is formed.

[0125] Next, as shown in Figure 14E, a region for the through electrode 25 is formed by removing a portion of the semiconductor layer 102 and a portion of the well 32 by etching (for example, dry etching). Then, as shown in Figure 14F, an insulating film 51 is formed.

[0126] Next, as shown in Figure 14G, through-electrodes 25 are formed in the semiconductor layer 102. Then, electrodes 92 and insulating films of the wiring layer 122 are formed on the surface 12S2 side of the semiconductor layer 102. By using the above manufacturing method, the imaging device 1 shown in Figure 7 can be manufactured. Note that the above manufacturing method is merely an example, and other manufacturing methods may be used.

[0127] [Function and Effects] The photodetector according to this embodiment comprises a first semiconductor layer (semiconductor layer 101) having a photoelectric conversion element (photoelectric conversion unit 11) that converts light into photoelectric energy and a floating diffusion (floating diffusion FD) capable of accumulating the charge converted by the photoelectric conversion element; a second semiconductor layer (semiconductor layer 102) provided so as to be stacked with the first semiconductor layer; a first transistor (e.g., transistor AMP) provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge accumulated in the floating diffusion; a through electrode (through electrode 25) provided around the first transistor so as to penetrate the second semiconductor layer; and a first insulating film and insulating region (insulating film 51 and insulating region 55) provided around the through electrode in the second semiconductor layer. The first transistor has a gate electrode (gate electrode 45) that is electrically connected to the floating diffusion via the through electrode. At least a part of the first insulating film is provided on the first surface side of the second semiconductor layer. At least a portion of the insulating region is provided on the second surface side of the second semiconductor layer, opposite to the first surface. In a direction perpendicular to the stacking direction of the first and second semiconductor layers, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer.

[0128] The photodetector (imaging device 1) according to this embodiment has an insulating film 51 and an insulating region 55 provided around the through electrode 25 in the semiconductor layer 102. In a direction perpendicular to the stacking direction of the semiconductor layer 101 and the semiconductor layer 102, the thickness of the insulating region 55 provided on the surface 12S2 side of the semiconductor layer 102 is greater than the thickness of the insulating film 51 provided on the surface 12S1 side of the semiconductor layer 102. Therefore, the capacitance of the through electrode 25 can be reduced. This makes it possible to realize a photodetector that can suppress quality degradation.

[0129] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0130] (Modification 1) In the above-described embodiment, an example of the configuration of the imaging device was explained, but the configuration of the imaging device is not limited to the example described above. For example, the shape and arrangement of the well 32 are not limited to the illustrated example and can be changed as appropriate. Figures 15 to 17 are diagrams illustrating an example of the configuration of the imaging device according to Modification 1 of this disclosure.

[0131] In the imaging device 1, as shown in the example in Figure 15, the bottom B2 (lower end) of the well 32 is located below, for example, the bottom B1 (lower end) of the well 31. The bottom B2 of the well 32 is formed in a region where the depth from the surface 12S1 of the semiconductor layer 102 is greater than the bottom B1 of the well 31. Alternatively, the well 32 may be provided such that the bottom B2 of the well 32 is located at the same depth as the bottom B1 of the well 31.

[0132] In the example shown in Figure 15, the well 32 is provided such that its bottom B2 is located above the insulating region 55. At least a portion of the well 32 may be provided around the insulating region 55. The well 32 is provided adjacent to the insulating film 51 and the insulating region 55, for example, as shown in the example in Figure 16. The well 32 may be provided so as to overlap a portion of the insulating region 55 (e.g., the insulating film 52).

[0133] In the imaging device 1, the well 32 may extend to the surface 12S2 side of the semiconductor layer 102. The well 32 is provided so as to reach the surface 12S2 of the semiconductor layer 102, for example, as shown in the example in Figure 17. The well 32 may be formed from the surface 12S1 to the surface 12S2 of the semiconductor layer 102 and may be provided so as to be in contact with the insulating region 55.

[0134] (Modification 2) Figures 18 and 19 are diagrams illustrating an example of the configuration of an imaging device according to Modification 2. In the imaging device 1, a well 32 may not be provided around the through electrode 25. In the example shown in Figure 18 or Figure 19, the imaging device 1 has a configuration without a well 32. By configuring the imaging device 1 in this way, it becomes possible to increase the area of ​​the region in the semiconductor layer 102 where elements such as transistors are arranged.

[0135] For example, the area of ​​the region where the transistors of the pixel P are arranged on the surface 12S1 side of the semiconductor layer 102 can be increased. As an example, the size of the transistors in the readout circuit 20 can be enlarged to improve the characteristics of the transistors. The insulating region 55 may be provided from the surface 12S2 side of the semiconductor layer 102 to the vicinity of the well 31, as shown in the example in Figure 19. This makes it possible to effectively reduce the parasitic capacitance added to the through electrode 25.

[0136] (Modification 3) Figures 20 to 23 are diagrams illustrating an example of the configuration of an imaging device according to Modification 3. The insulating film 51 and the insulating region 55 may be made of different materials. In the example shown in Figures 20 to 23, the insulating region 55 is made of a material having a dielectric constant different from that of the insulating film 51.

[0137] The insulating film 51 may have a dielectric constant lower than that of the insulating region 55 (i.e., the insulating film 52). For example, the insulating film 51 can be made of a material having a dielectric constant lower than that of the insulating region 55. With such an insulating film configuration, the capacitance of the through electrode 25, i.e., the floating diffusion FD, can be reduced by the Miller effect. Alternatively, the insulating film 51 may be made of a material having a dielectric constant higher than that of the insulating film 52.

[0138] The insulating film 51 may be provided so as to reach the surface 12S2 of the semiconductor layer 102, as shown in the example in Figure 20. Alternatively, for example, as shown in the example in Figure 21, the insulating film 51 may be provided so that its lower end (bottom) is in contact with the upper end (tip) of the insulating region 55.

[0139] As shown in the example in Figure 22, the insulating film 51 may be provided such that, for example, the bottom of the insulating film 51 is at the same depth as the bottom of the well 32. Alternatively, as shown in the example in Figure 23, the insulating film 51 may be provided such that the bottom of the insulating film 51 is located above the bottom of the well 32.

[0140] Figures 24 to 26 are diagrams illustrating another configuration example of the imaging device according to Modification 3. The imaging device 1 may have a configuration without a well 32, as shown in the example in Figure 24 or Figure 25. The insulating film 51 may be provided such that the bottom of the insulating film 51 is located above the bottom of the well 31, as shown in the example in Figure 26.

[0141] (Modification 4) Figures 27 to 30 are diagrams illustrating an example of the configuration of an imaging device according to Modification 4. The insulating region 55 may be constructed using voids (cavities). The insulating region 55 may have a hollow structure. The insulating region 55 is constructed by voids 53, for example, as shown in the example in Figures 27 to 30. A part of the voids 53 may be provided within the wiring layer 122.

[0142] The void 53, which serves as an insulating region 55, is formed, for example, around the through electrode 25 on the surface 12S2 side of the semiconductor layer 102. The arrangement and shape of the void 53 can be changed as appropriate. For example, as shown in the example in Figure 30, a portion of the void 53 may be provided between the through electrode 25 and the well 32.

[0143] Figures 31 to 33 illustrate another configuration example of the imaging device according to Modification 4. The imaging device 1 may have a configuration without a well 32, as shown in the examples in Figures 31 to 33. As shown in the example in Figure 33, an insulating region 55, i.e., a part of the gap 53, may be provided between the through electrode 25 and the well 31. In this modification as well, the same effects as in the above-described embodiment can be obtained.

[0144] <2. Second Embodiment> Next, a second embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0145] Figure 34 is a diagram illustrating an example configuration of an imaging device according to a second embodiment of the present disclosure. The imaging device 1 has a conductive film 57, as shown in the example in Figure 34. The conductive film 57 is provided around the insulating film 51 in the semiconductor layer 102. The conductive film 57 is a conductive film and is made of a different material than the semiconductor layer 102. In the imaging device 1, for example, the conductive film 57 is provided instead of the insulating region 55 described above.

[0146] The conductive film 57 is provided, for example, between surfaces 12S1 and 12S2 of the semiconductor layer 102, via the insulating film 51, so as to be along the through electrode 25. As an example, the conductive film 57 is arranged to surround the through electrode 25 and the insulating film 51 in a plan view (i.e., when viewed in the XY plane). There may be an insulating film different from the insulating film 51 between the insulating film 51 and the conductive film 57.

[0147] The conductive film 57 is provided, for example, on the semiconductor layer 102, extending from surface 12S1 to surface 12S2, adjacent to the insulating film 51. The conductive film 57 is formed, for example, to cover the periphery of the insulating film 51 and is provided in contact with the insulating film 51. A portion of the conductive film 57 may be provided within the wiring layer 121. Another portion of the conductive film 57 may be provided within the wiring layer 122.

[0148] The conductive film 57 is a conductive member (conductor), and is composed of, for example, ITO (indium tin oxide). The conductive film 57 may be composed of a transparent conductive member such as ITO or IZO. Alternatively, for example, the conductive film 57 may be composed of titanium nitride (TiN) or tantalum nitride (TaN). The conductive film 57 may be formed using a metallic material such as tungsten, or it may be formed using other conductive materials.

[0149] The conductive film 57 is electrically connected to, for example, the source region of the transistor AMP. The conductive film 57 may be provided so as to be directly connected to the source region of the transistor AMP, or it may be electrically connected to the source region of the transistor AMP via vias (contacts) and wiring of a wiring layer (e.g., wiring layer 121).

[0150] The conductive film 57 is provided, for example, adjacent to the semiconductor region 41 which serves as the source region of the transistor AMP. As an example, the conductive film 57 is positioned between the through electrode 25 and the transistor AMP, in contact with the semiconductor region 41 which serves as the source region of the transistor AMP. In the example shown in Figure 34, the conductive film 57 is provided in contact with the side surface (side portion) of the semiconductor region 41 which serves as the source region.

[0151] As described above, the imaging device 1 according to this embodiment has an insulating film 51 provided around the through electrode 25 and a conductive film 57 provided around the insulating film 51. The conductive film 57 is electrically connected to the source region of the transistor AMP, i.e., the semiconductor region 41. As a result, as schematically shown by the dotted line in Figure 35, the parasitic capacitance Cp formed on the through electrode 25, which is part of the floating diffusion FD, is electrically connected to the semiconductor region 41, which is the source region of the transistor AMP.

[0152] In the imaging device 1, as described above using Figure 11, a parasitic capacitance Cp formed in the through electrode 25 and insulating film 51 can be added between the floating diffusion FD and the source region of the transistor AMP of the source follower circuit. By utilizing the Miller effect, it becomes possible to reduce the capacitance of the floating diffusion FD.

[0153] In the imaging device 1, the presence of a conductive film 57 (conductive material) reduces the capacitance of the floating diffusion FD and improves the conversion gain. In particular, even with fine pixels, it is possible to suppress the inclusion of noise in the pixel signal and improve the quality of the pixel signal. This makes it possible to suppress the deterioration of image quality.

[0154] Furthermore, in this embodiment, a relatively thin conductive film 57 allows for the electrical connection between the through-electrode 25, which is part of the floating diffusion FD, and the source (terminal) of the transistor AMP. This expands the area in the semiconductor layer 102 where elements such as transistors can be placed. This makes it possible to realize a photodetector (imaging device) that is advantageous for miniaturization.

[0155] [Function and Effects] The photodetector according to this embodiment comprises a first semiconductor layer (semiconductor layer 101) having a photoelectric conversion element that converts light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; a second semiconductor layer (semiconductor layer 102) provided to be stacked with the first semiconductor layer; a first transistor (e.g., transistor AMP) provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge stored in the floating diffusion; a through electrode (through electrode 25) provided around the first transistor so as to penetrate the second semiconductor layer; a first insulating film (insulating film 51) provided around the through electrode in the second semiconductor layer; and a conductive film (conductive film 57) provided around the first insulating film in the second semiconductor layer. The first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode and a source region provided in the second semiconductor layer. The conductive film is electrically connected to the source region of the first transistor.

[0156] The photodetector (imaging device 1) according to this embodiment has an insulating film 51 provided around the through-electrode 25 in the semiconductor layer 102, and a conductive film 57 provided around the insulating film 51 in the semiconductor layer 102. The conductive film 57 is electrically connected to the source region of the transistor AMP. Therefore, the capacitance of the through-electrode 25 can be reduced. This makes it possible to realize a photodetector that can suppress quality degradation.

[0157] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0158] (Modification 5) Figures 36 and 37 are diagrams illustrating an example of the configuration of an imaging device according to Modification 5 of the present disclosure. The conductive film 57 may be provided so as to be in contact with the source region of the transistor AMP, for example, the bottom surface (bottom) of the semiconductor region 41. In the example shown in Figure 36, the conductive film 57 is provided in contact with the bottom surface (lower end) of the semiconductor region 41 and is electrically connected to the semiconductor region 41. In addition, as shown in the example in Figure 37, a part of the conductive film 57 may be provided within the wiring layer 122.

[0159] Figure 38 is a diagram illustrating another configuration example of the imaging device according to Modification 5. As shown in the example in Figure 38, the conductive film 57 may be electrically connected to the semiconductor region 41 as the source region of the transistor AMP via vias (contacts) and wiring of the wiring layer 121. In the case of the imaging device 1 according to this modification, the same effects as in the embodiment described above can be obtained.

[0160] <3. Third Embodiment> Next, a third embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0161] Figure 39 is a diagram illustrating an example of a cross-sectional configuration of an imaging device according to a third embodiment of the present disclosure. As shown in the example in Figure 39, the transistor AMP has a gate electrode 45a, a gate insulating film 57a, a semiconductor region 41a, and a semiconductor region 42a. The transistor AMP of each pixel P has a gate electrode 45a and a gate insulating film 57a provided within the semiconductor layer 102.

[0162] The gate electrode 45a of the transistor AMP is provided, for example, so as to penetrate the semiconductor layer 102. A portion of the gate electrode 45a of the transistor AMP is provided on the side 12S2 of the semiconductor layer 102 and is electrically connected to the wiring of the wiring layer 122 and electrodes 91a and 92a, which are part of the plurality of junction electrodes 91 and 92 described above. The gate electrode 45a is electrically connected to the floating diffusion FD of the semiconductor layer 101 via electrodes 91a and 92a, etc.

[0163] The gate insulating film 57a of the transistor AMP is provided around the gate electrode 45a in the semiconductor layer 102. The gate insulating film 57a is formed within the semiconductor layer 102 along the gate electrode 45a. The gate electrode 45a and the gate insulating film 57a are provided, for example, by excavating the semiconductor layer 102.

[0164] Figure 40 is a diagram illustrating an example of the configuration of an imaging device according to a third embodiment. The transistor AMP has a region in which a channel is formed in the vertical direction, as schematically shown by the dotted line in Figure 40, and can be configured as a vertical channel transistor. The gate insulating film 57a is provided, for example, so as to surround the gate electrode 45a in a plan view (i.e., when viewed in the XY plane).

[0165] The gate electrode 45a and gate insulating film 57a of the transistor AMP may be arranged to be embedded in the semiconductor layer 102. Parts of the gate electrode 45a and gate insulating film 57a may extend into the wiring layer 121. Furthermore, parts of the gate electrode 45a and gate insulating film 57a may extend into the wiring layer 122.

[0166] One of the source and drain regions of the transistor AMP is provided, for example, on the side 12S1 of the semiconductor layer 102. The other of the source and drain regions of the transistor AMP is provided on the side 12S2 of the semiconductor layer 102. The transistor AMP has a semiconductor region 41a and a semiconductor region 42a as the source and drain regions, as shown in the example in Figure 39 or Figure 40.

[0167] The semiconductor region 41a is, for example, the source region of the transistor AMP and is provided on the surface 12S1 side of the semiconductor layer 102. The semiconductor region 42a is the drain region of the transistor AMP and is provided on the surface 12S2 side of the semiconductor layer 102. The semiconductor regions 41a and 42a are, for example, n-type semiconductor regions and n+-type semiconductor regions, respectively.

[0168] The semiconductor region 42a, which will be the drain region of the transistor AMP, is provided on the surface 12S2 side of the semiconductor layer 102, around the gate electrode 45a and the gate insulating film 57a. The semiconductor region 42a is arranged, for example, in a plan view, to surround the gate electrode 45a and the gate insulating film 57a. The semiconductor region 42a is electrically connected to wiring (power lines) to which a power supply voltage (e.g., power supply voltage VDD) is supplied, for example, by electrodes 91b, 92b, etc.

[0169] The semiconductor region 41a, which serves as the source region of the transistor AMP, is provided on the surface 12S1 side of the semiconductor layer 102, around the gate electrode 45a and the gate insulating film 57a. For example, in a plan view, the semiconductor region 41a is arranged to surround the gate electrode 45a and the gate insulating film 57a. The semiconductor region 41a is electrically connected to the signal line VSL via the transistor SEL provided on the surface 12S1 side of the semiconductor layer 102.

[0170] Furthermore, in the example shown in Figure 39, the transistor RST has a gate electrode 45b, a gate insulating film 57b, a semiconductor region 41b, and a semiconductor region 42b. The transistor RST of each pixel P has a gate electrode 45b and a gate insulating film 57b provided within the semiconductor layer 102. The transistor RST has a region in which a channel is formed in the vertical direction, and can be configured as a vertical channel transistor.

[0171] The gate electrode 45b of the transistor RST is provided so as to penetrate the semiconductor layer 102, as shown in the example in Figure 39. The gate insulating film 57b is provided around the gate electrode 45b in the semiconductor layer 102. The gate electrode 45b and the gate insulating film 57b are provided, for example, by excavating the semiconductor layer 102.

[0172] The gate insulating film 57b is provided, for example, so as to surround the gate electrode 45b in a plan view. Both the gate electrode 45b and the gate insulating film 57b can be arranged so as to be embedded in the semiconductor layer 102. Parts of both the gate electrode 45a and the gate insulating film 57a may extend into the wiring layer 121 or into the wiring layer 122.

[0173] One of the source and drain regions of transistor RST, semiconductor region 41b, is provided on the surface 12S1 side of semiconductor layer 102, for example. The other of the source and drain regions of transistor RST, semiconductor region 42b, is provided on the surface 12S2 side of semiconductor layer 102. Semiconductor regions 41b and 42b are, for example, n-type semiconductor regions and n+-type semiconductor regions, respectively.

[0174] The semiconductor region 42b is provided on the surface 12S2 side of the semiconductor layer 102, around the gate electrode 45b and the gate insulating film 57b. For example, in a plan view, the semiconductor region 42b is arranged to surround the gate electrode 45b and the gate insulating film 57b. The semiconductor region 42b is electrically connected to the floating diffusion FD of the semiconductor layer 101 via electrodes 91a and 92a, etc., as shown in the example in Figure 39.

[0175] The semiconductor region 41b is provided on the surface 12S1 side of the semiconductor layer 102, around the gate electrode 45b and the gate insulating film 57b. For example, in a plan view, the semiconductor region 41b is arranged to surround the gate electrode 45b and the gate insulating film 57b. The semiconductor region 41b is electrically connected to a power line to which a power supply voltage (e.g., power supply voltage VDD) is supplied.

[0176] The gate electrode 45a of transistor AMP and the gate electrode 45b of transistor RST are, for example, electrodes having a columnar shape. Each of the gate electrodes 45a and 45b may, as an example, have a cylindrical shape. The shapes of the gate electrodes 45a and 45b can be changed as appropriate. The shapes of the gate electrodes 45a and 45b may be elliptical, polygonal, or other shapes in a plan view.

[0177] The gate electrodes 45a and 45b are each constructed using, for example, polysilicon (Poly-Si). Each of the gate electrodes 45a and 45b may also be formed using a metallic material or a metallic compound. The gate electrodes 45a and 45b may be constructed using, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), etc.

[0178] The gate insulating films 57a and 57b are each composed of, for example, a single layer film made of one of the following materials: silicon oxide (SiO), silicon oxynitride (SiON), hafnium oxide (HfO), etc., or a multilayer film made of two or more of these materials. The gate insulating films 57a and 57b may also be formed using a high dielectric constant material having a dielectric constant higher than that of silicon oxide, such as a hafnium-based insulating film.

[0179] Furthermore, isolation regions 18 are provided in the semiconductor layer 102. The isolation regions 18 are constructed, for example, using trenches (grooves) and have an STI (Shallow Trench Isolation) structure. An insulating film, such as a silicon oxide film or a silicon nitride film, is provided within the trenches of the isolation regions 18.

[0180] The isolation region 18 is formed on the surface 12S2 side of the semiconductor layer 102, as shown in the example in Figure 39 or Figure 40, and separates the elements on the surface 12S2 side of the semiconductor layer 102. The isolation region 18 is provided around the transistor AMP (or transistor RST) on the surface 12S2 side of the semiconductor layer 102. For example, the isolation region 18 is provided between transistor AMP and transistor RST, which are vertical channel transistors.

[0181] Furthermore, the isolation region 18 is formed on the surface 12S1 side of the semiconductor layer 102 and separates the elements on the surface 12S1 side of the semiconductor layer 102. The isolation region 18 may be provided around the transistor AMP (or transistor RST) on the surface 12S1 side of the semiconductor layer 102. For example, the isolation region 18 is provided between the transistor AMP (or transistor RST) and the transistor SEL.

[0182] In the imaging device 1 according to this embodiment, as described above, a transistor AMP having a gate electrode 45a provided within the semiconductor layer 102 is provided. Therefore, the transistor AMP is configured as a vertical channel transistor, making it possible to eliminate the need for through electrodes for connecting the floating diffusion FD and the transistor AMP.

[0183] In the imaging device 1, it is possible to prevent the addition of unnecessary parasitic capacitance to the floating diffusion floppy disk (FD), thereby effectively reducing the capacitance of the floating diffusion FD. Furthermore, the gate electrode 45a of the transistor AMP has a columnar shape. Therefore, it is possible to increase the gate area (gate width, gate length, etc.) of the transistor AMP and suppress the intrusion of noise into the pixel signal.

[0184] Furthermore, in this embodiment, the transistor RST may have a gate electrode 45b provided within the semiconductor layer 102. Therefore, the transistor RST can be configured as a vertical channel transistor, eliminating the need for through-electrodes for connecting the floating diffusion FD and the readout circuit 20. This makes it possible to further reduce the capacitance of the floating diffusion FD.

[0185] Figure 41 is a diagram showing an example of the cross-sectional configuration of the imaging device according to the third embodiment. Figures 42A to 42C are diagrams showing an example of the planar configuration of the imaging device according to the third embodiment. Figure 42A shows an example of the planar configuration of the wiring layer 111 and semiconductor layer 101 of the layer 201 shown in Figure 41.

[0186] Figure 42B also shows an example of a planar configuration in the wiring layer 122 and semiconductor layer 102 of layer 202. Figure 42C shows an example of a planar configuration in the wiring layer 121 and semiconductor layer 102 of layer 202. Figures 42A to 42C show an example where four adjacent pixels P share one readout circuit 20.

[0187] In the example shown in Figures 42A to 42C, the imaging device 1 has a configuration in which four pixels P, which are 2x2 pixels in size, share a readout circuit 20 (transistors AMP, RST, SEL, etc.). Note that Figures 42A to 42C illustrate a 4x4 pixel configuration. Other pixels P in the imaging device 1 may also have a configuration similar to that shown in Figure 42A, etc.

[0188] As shown in Figure 42A, layer 201 of the imaging device 1 is provided with a photoelectric conversion unit 11 for the pixel P, a transistor TG, a floating diffusion FD, and the like. In addition, the wiring layer 111 of layer 201 is provided with an electrode 91a that is electrically connected to the floating diffusion FD of the semiconductor layer 101, and an electrode 91b that is electrically connected to the wiring (power line) to which the power supply voltage VDD is supplied, as bonding electrodes, as shown in the example in Figure 42A.

[0189] As shown in Figures 42B and 42C, the layer 202 of the imaging device 1 is provided with transistors such as AMP having a gate electrode 45a and RST having a gate electrode 45b. An isolation region 18 is provided around each transistor of the readout circuit 20. Transistor SEL is provided on the wiring layer 121 side of the semiconductor layer 102, as in the example shown in Figure 42C.

[0190] Furthermore, as shown in Figure 42B, electrodes 92a and 92b are provided as bonding electrodes in the wiring layer 122 of layer 202. Electrode 92a is positioned corresponding to electrode 91a of wiring layer 111 and is bonded to electrode 91a (for example, a Cu-Cu junction). Electrode 92a is electrically connected to the gate electrode 45a of transistor AMP.

[0191] Electrode 92b is positioned corresponding to electrode 91b of wiring layer 111 and is joined to electrode 91b (for example, a Cu-Cu junction). Also, as shown in the example in Figure 42C, the semiconductor layer 102 may have a well contact region to which a voltage VSS (for example, 0V) is applied. The well contact region is, for example, an n+ type semiconductor region.

[0192] The imaging device 1 may have a configuration in which eight adjacent pixels P share one readout circuit 20, as shown in the examples in Figures 43A to 43C. In the examples shown in Figures 43A to 43C, the imaging device 1 has a configuration in which eight pixels P, which are 2x4 pixels, share one readout circuit 20. Other pixels P in the imaging device 1 may also have a configuration similar to that shown in Figure 43A, etc.

[0193] Furthermore, some of the transistors provided for each of the multiple pixels P that share the readout circuit 20 may be dummy transistors, as shown in the examples in Figures 43B and 43C. The readout circuit 20 may include one or more dummy transistors.

[0194] Figures 44 and 45 are diagrams illustrating an example configuration of an imaging device according to a third embodiment. The imaging device 1 may have a region 105 on which pads 95 are provided, as shown in Figures 44 and 45. Region 105 can also be called a pad region. Region 105 is provided, for example, around a pixel unit 100 (pixel array). Region 105 may include a plurality of pads 95 and be provided in the peripheral region (periphery) of the pixel unit 100.

[0195] Region 105 includes, for example, pads (terminals) used for transmitting signals to the outside. Region 105 includes power pads, GND (ground) pads, etc. In the imaging device 1, for example, a pad 95 to which a power supply voltage VDD is supplied is provided, as shown in the example in Figure 45. Region 105 also includes input / output pads to which signals are input and output, input pads to which signals are input from outside the imaging device 1, output pads to which signals are output to the outside of the imaging device 1, etc.

[0196] Figures 46A to 46J show an example of a method for manufacturing a photodetector according to a third embodiment. First, as shown in Figure 46A, a semiconductor layer 102 including semiconductor layers 221 to 223 is prepared. Semiconductor layer 221 is, for example, a p-type semiconductor layer. Semiconductor layer 221 may be a p-type semiconductor substrate, for example, a p-type silicon substrate. Semiconductor layer 222 is, for example, an n-type semiconductor layer.

[0197] The semiconductor layer 223 is, for example, a p-type semiconductor layer. The semiconductor layer 223 may be, for example, an n-type epitaxial growth layer and can be formed on the semiconductor layer 222. As the semiconductor layer 102 including the semiconductor layers 221, 222, and 223, for example, a graded epi substrate (graded epitaxial substrate) may be used.

[0198] As shown in Figure 46B, a transistor SEL and isolation region 18 are formed in the semiconductor layer 223, and a wiring layer 121 having an electrode 93 is formed on the semiconductor layer 223. Next, layer 202, on which the wiring layer 121 having an electrode 93 is provided, and layer 203, on which the wiring layer 131 having an electrode 94 is provided, are placed opposite each other, and as shown in Figure 46C, layer 202 and layer 203 are joined together. Then, as shown in Figure 46D, the semiconductor layer 221 is removed.

[0199] Next, as shown in Figure 46E, a separation region 18 is formed on the surface 12S2 side of the semiconductor layer 102. Then, as shown in Figure 46F, the semiconductor layer 102 is partially removed by etching (for example, dry etching or wet etching) the surface 12S2 of the semiconductor layer 102. Furthermore, as shown in Figure 46G, the gate electrodes and gate insulating films of transistors AMP and RST are formed.

[0200] Next, as shown in Figure 46H, a wiring layer 122 having an electrode 92 is formed on the surface 12S1 side of the semiconductor layer 102. Then, the layer 202 on which the wiring layer 122 having an electrode 92 is provided and the layer 201 on which the wiring layer 111 having an electrode 91 are provided are placed facing each other, and the layer 202 and the layer 201 are joined together as shown in Figure 46I.

[0201] As shown in Figure 46J, the filter 15 and lens 14 are formed on the surface 11S2 side of the semiconductor layer 101. By using the above manufacturing method, the imaging device 1 shown in Figure 41 can be manufactured. Note that the above manufacturing method is merely an example, and other manufacturing methods may be used.

[0202] Although the above describes an example of the configuration of the imaging device 1, the configuration of the imaging device 1 is not limited to the example described above. For example, the configuration of each transistor in the readout circuit 20 is not limited to the illustrated example and can be changed as appropriate. For example, transistor RST may have a planar gate structure. Transistor RST may be configured as a planar type transistor and may be provided on the surface 12S1 side of the semiconductor layer 102.

[0203] [Function and Effects] The photodetector according to this embodiment comprises a first semiconductor layer (semiconductor layer 101) having a photoelectric conversion element that converts light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element, and a second semiconductor layer (semiconductor layer 102) having a first transistor (e.g., transistor AMP) capable of generating a first signal based on the charge stored in the floating diffusion, and provided stacked with the first semiconductor layer. The first transistor has a first gate electrode provided in the second semiconductor layer. The first gate electrode of the first transistor is electrically connected to the floating diffusion.

[0204] In the photodetector (imaging device 1) according to this embodiment, a transistor AMP having a gate electrode 45a provided in the semiconductor layer 102 is provided. The gate electrode 45a of the transistor AMP is electrically connected to the floating diffusion FD. Therefore, it is possible to suppress the addition of unnecessary parasitic capacitance to the floating diffusion FD. This makes it possible to realize a photodetector that can suppress the deterioration of quality.

[0205] <4. Fourth Embodiment> Next, a fourth embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0206] Figure 47 is a diagram illustrating an example of a cross-sectional configuration of an imaging device according to the fourth embodiment of this disclosure. Figures 48A to 48C and 49A to 49C are diagrams illustrating an example of the configuration of the pixel transistors of the imaging device according to the fourth embodiment. Each transistor of the readout circuit 20 (transistor AMP, transistor RST, transistor SEL, or transistor FDG, etc.) may have, for example, the configuration shown in Figures 48A to 48C, or the configuration shown in Figures 49A to 49C.

[0207] The transistor AMP may have, for example, the configuration shown in Figures 48A to 48C. The transistor AMP has a gate electrode 45a, a gate insulating film 57a, a semiconductor region 41a, and a semiconductor region 42a, as shown in the examples in Figures 47 and 48A to 48C. The transistor AMP of each pixel P has a gate electrode 45a and a gate insulating film 57a that are provided so as to sandwich a part of the semiconductor layer 102.

[0208] The transistor AMP has, for example, a gate electrode 45a and a gate insulating film 57a that are provided so as to sandwich a part of the semiconductor layer 102 which serves as a channel region. A part of the gate electrode 45a of the transistor AMP is provided on the side of the semiconductor layer 102 surface 12S2 and is electrically connected to the floating diffusion FD of the semiconductor layer 101 via electrodes 91 and 92, etc.

[0209] At least one of the source region and drain region of the transistor AMP is provided, for example, from the surface 12S2 side to the surface 12S1 side of the semiconductor layer 102. At least one of the source region and drain region of the transistor AMP may be provided so as to reach the surface 12S1 of the semiconductor layer 102. The transistor AMP has a semiconductor region 41a and a semiconductor region 42a as the source region and drain region.

[0210] In the example shown in Figure 47, the semiconductor region 41a is the source region of the transistor AMP and is provided from surface 12S2 to surface 12S1 of the semiconductor layer 102. The semiconductor region 42a is the drain region of the transistor AMP and is provided from surface 12S2 to surface 12S1 of the semiconductor layer 102.

[0211] The gate electrode 45a and gate insulating film 57a of the transistor AMP may be provided, for example, so as to enclose a part of the semiconductor layer 102. The transistor AMP may also be a gate all-around (GAA) transistor having a structure in which the gate (gate electrode 45a, gate insulating film 57a) is provided so as to surround a part of the semiconductor layer 102 which serves as the channel region.

[0212] The transistor RST may have, for example, the configuration shown in Figures 49A to 49C. The transistor RST has a gate electrode 45b, a gate insulating film 57b, a semiconductor region 41b, and a semiconductor region 42b, as shown in the example in Figures 47 and 49A to 49C. The transistor RST of each pixel P may have a gate electrode 45b and a gate insulating film 57b that are provided so as to sandwich a part of the semiconductor layer 102.

[0213] The transistor RST has, for example, a gate electrode 45b and a gate insulating film 57b that are provided so as to sandwich a part of the semiconductor layer 102 which serves as the channel region. The gate electrode 45b and gate insulating film 57b of the transistor RST may be provided so as to enclose a part of the semiconductor layer 102. The transistor RST may also be a GAA type transistor having a structure in which the gate is provided so as to surround a part of the semiconductor layer 102 which serves as the channel region.

[0214] At least one of the source region and drain region of the transistor RST is provided, for example, from the surface 12S2 side to the surface 12S1 side of the semiconductor layer 102. At least one of the source region and drain region of the transistor RST may be provided so as to reach the surface 12S1 of the semiconductor layer 102. The transistor RST has a semiconductor region 41b and a semiconductor region 42b as the source region and drain region.

[0215] In the example shown in Figure 47, the semiconductor region 41b, which is one of the source and drain regions of the transistor RST, is provided from surface 12S2 to surface 12S1 of the semiconductor layer 102. The semiconductor region 42b, which is the other of the source and drain regions of the transistor RST, is also provided from surface 12S2 to surface 12S1 of the semiconductor layer 102.

[0216] In the imaging device 1 according to this embodiment, as described above, a transistor AMP having a gate electrode 45a is provided so as to sandwich a part of the semiconductor layer 102. Therefore, through electrodes for connecting the floating diffusion FD and the transistor AMP can be eliminated.

[0217] In this embodiment, it is possible to prevent the addition of unnecessary parasitic capacitance to the floating diffusion FD, thereby effectively reducing the capacitance of the floating diffusion FD. Furthermore, it is possible to prevent stress caused by through electrodes from adversely affecting the transistors (e.g., transistor AMP) of the readout circuit 20.

[0218] Furthermore, the transistor RST may have a gate electrode 45b provided so as to sandwich a portion of the semiconductor layer 102. Therefore, through electrodes for connecting the floating diffusion FD and the readout circuit 20 can be eliminated. The imaging device 1 can have a structure advantageous for pixel miniaturization. High integration becomes possible with fine spacing.

[0219] [Function and Effects] The photodetector according to this embodiment comprises a first semiconductor layer (semiconductor layer 101) having a photoelectric conversion element that converts light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element, and a second semiconductor layer (semiconductor layer 102) having a first transistor (e.g., transistor AMP) capable of generating a first signal based on the charge stored in the floating diffusion, and provided stacked with the first semiconductor layer. The first transistor has a first gate insulating film and a first gate electrode provided so as to sandwich a part of the second semiconductor layer. The first gate electrode of the first transistor is electrically connected to the floating diffusion.

[0220] In the photodetector (imaging device 1) according to this embodiment, a transistor AMP having a gate electrode 45a is provided so as to sandwich a part of the semiconductor layer 102. Therefore, it is possible to suppress the addition of unnecessary parasitic capacitance to the floating diffusion FD. This makes it possible to realize a photodetector that can suppress the deterioration of quality.

[0221] Next, modified examples of the present disclosure will be described. In the following, components similar to those in the above embodiments will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0222] (Modification 6) In the above-described embodiment, an example of the configuration of the imaging device was explained, but the configuration of the imaging device is not limited to the example described above. For example, the configuration of the transistors (transistors AMP, RST, SEL, FDG, etc.) of the readout circuit 20 is not limited to the illustrated example and can be changed as appropriate.

[0223] Figures 50 and 51 are diagrams illustrating an example configuration of an imaging device according to Modification 6 of the present disclosure. The transistor AMP may have a gate electrode 45a provided to cover a part of the semiconductor layer 102, for example, as shown in the example in Figure 50. Alternatively, the transistor RST may have a gate electrode 45b provided to cover a part of the semiconductor layer 102, for example, as shown in the example in Figure 51.

[0224] Furthermore, the shapes and arrangements of the gate electrode, source region, drain region, contacts (vias) connected to the source region, and contacts connected to the drain region of the transistor in the readout circuit 20 are not limited to the examples described above, and can be changed as appropriate, as shown in the examples in Figures 52 to 55.

[0225] As shown in the example in Figure 56, contacts (vias) may be connected to the side (side) of the source region (or drain region) of the transistor. Transistor AMP (or transistor RST, etc.) may have a side contact structure as shown in the example in Figure 56.

[0226] Figure 57 is a diagram illustrating another configuration example of the imaging device according to Modification 6. The transistors of the readout circuit 20 (transistor AMP or transistor RST, etc.) may have gate electrodes and gate insulating films provided so as to sandwich multiple portions of the semiconductor layer 102, as schematically shown in Figure 57. For example, transistor AMP or transistor RST, etc., may be configured as Fin-type transistors.

[0227] <5. Fifth Embodiment> Next, a fifth embodiment of the present disclosure will be described. In the following, components similar to those in the embodiments described above will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0228] Figure 58 is a diagram illustrating an example of a cross-sectional configuration of an imaging device according to a fifth embodiment of the present disclosure. The imaging device 1 may have a light-shielding member 60, as shown in the example in Figure 58. The light-shielding member 60 is a light-shielding portion composed of a light-blocking member, and is provided, for example, in the same layer as the semiconductor layer 102.

[0229] In the example shown in Figure 58, the light-shielding member 60 is provided around the region of the semiconductor layer 102 where the transistors of the readout circuit 20 are formed. The light-shielding member 60 may be formed between a plurality of adjacent transistors in the semiconductor layer 102. The light-shielding member 60 is composed of, for example, a part of the semiconductor layer 102 (e.g., silicon).

[0230] The light-shielding member 60 may be composed of, for example, a region of the semiconductor layer 102 in which transistors are not arranged (also known as a dummy region). The light-shielding member 60 may also be composed of tungsten (W). The light-shielding member 60 (light-shielding film) may also be composed of other metal materials that block light, such as aluminum (Al) or copper (Cu). The light-shielding member 60 may be composed of a material that absorbs light.

[0231] In the imaging device 1 according to this embodiment, the provision of a light-shielding member 60 makes it possible to suppress unwanted light, such as the example shown by the dashed line in Figure 59, from entering the lower layer region. For example, it is possible to suppress noise caused by stray light from being mixed into the pixel signal and improve the quality of the pixel signal. It is possible to suppress the deterioration of image quality.

[0232] Figures 60A to 60C and 61A to 61C are diagrams illustrating examples of the configuration of the pixel transistors in the imaging device according to the fifth embodiment. Each transistor (transistor AMP, RST, SEL, FDG, etc.) of the readout circuit 20 may have, for example, the configuration shown in Figures 60A to 60C, or the configuration shown in Figures 61A to 61C.

[0233] The imaging device 1 may have a barrier film 65 provided around the semiconductor layer 102. The barrier film 65 is provided so as to cover at least one of the source region and drain region of each transistor AMP, RST, etc. As shown in the examples in Figures 60A to 60C, or Figures 61A to 61C, the barrier film 65 may be provided around each of the source region and drain region.

[0234] The barrier film 65 is constructed using, for example, a material having hydrogen barrier properties. The barrier film 65 is, as an example, Al ２ O ３ It is composed of , or TiAlO. The barrier film 65 may be composed of SiN, TaO, TiO, TiAlO, TaAlN, etc., or may be formed using other materials.

[0235] The barrier film 65 is provided, for example, to cover the semiconductor region 41a of the transistor AMP and to cover the semiconductor region 42a of the transistor AMP. Also, for example, the barrier film 65 is provided to cover the semiconductor region 41b of the transistor RST and to cover the semiconductor region 42b of the transistor RST. A portion of the barrier film 65 may be provided around the gate insulating film and the gate electrode.

[0236] In the imaging device 1 according to this embodiment, the barrier film 65 prevents water (moisture) from mixing with transistors AMP, RST, etc. For example, it is possible to prevent moisture from entering the transistors of the readout circuit 20 from layers other than the semiconductor layer 102. This makes it possible to prevent fluctuations and deterioration of the transistor characteristics.

[0237] [Function and Effects] The photodetector according to this embodiment further includes a light-shielding member (light-shielding member 60) provided in the same layer as the second semiconductor layer (semiconductor layer 102). Therefore, it is possible to suppress the leakage of unwanted light into the surroundings, and for example, it is possible to suppress the deterioration of the quality of the pixel signal. This makes it possible to realize a photodetector that can suppress the deterioration of quality.

[0238] The photodetector according to this embodiment further includes a barrier film (barrier film 65) provided around the second semiconductor layer (semiconductor layer 102). This makes it possible to suppress the intrusion of moisture into the transistors of the semiconductor layer 102. This makes it possible to realize a photodetector that can suppress the deterioration of quality.

[0239] <6. Examples of Application> The above-described imaging device 1 can be applied to any type of electronic device equipped with an imaging function, such as camera systems like digital still cameras and video cameras, or mobile phones with imaging capabilities. Figure 62 shows a schematic configuration of the electronic device 1000.

[0240] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, all of which are interconnected via a bus line 1008.

[0241] The lens group 1001 captures incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies it as a pixel signal to the DSP circuit 1002.

[0242] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

[0243] The display unit 1004 consists of, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records the video or still image data captured by the imaging device 1 onto a recording medium such as a semiconductor memory or a hard disk.

[0244] The operation unit 1006 outputs operation signals for various functions possessed by the electronic device 1000 in accordance with user operations. The power supply unit 1007 appropriately supplies various power sources to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006.

[0245] <7. Application Examples> (Application Examples to Mobile Devices) The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be realized as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0246] Figure 63 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0247] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 63, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0248] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0249] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0250] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0251] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0252] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0253] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0254] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0255] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0256] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 63, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0257] Figure 64 shows an example of the installation position of the imaging unit 12031.

[0258] In Figure 64, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0259] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0260] Figure 64 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0261] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0262] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0263] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0264] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0265] The above describes an example of a mobile control system to which the technology described herein can be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the imaging device 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, it becomes possible to obtain high-definition captured images. This makes it possible to perform high-precision control using captured images in the mobile control system.

[0266] (Examples of application to endoscopic surgical systems) The technology disclosed herein (this technology) can be applied to various products. For example, the technology disclosed herein may be applied to endoscopic surgical systems.

[0267] Figure 65 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0268] Figure 65 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0269] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0270] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0271] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0272] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display the image based on that image signal.

[0273] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0274] The light source device 11203 consists of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0275] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0276] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0277] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0278] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0279] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used in normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0280] Figure 66 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 65.

[0281] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0282] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0283] The imaging unit 11402 is composed of image sensors. The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is composed of multiple chips, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (Dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is composed of multiple chips, multiple lens units 11401 may also be provided corresponding to each image sensor.

[0284] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0285] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0286] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0287] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0288] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 will be equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0289] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0290] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0291] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0292] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0293] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0294] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0295] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0296] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0297] The above describes an example of an endoscopic surgical system to which the technology described herein may be applied. The technology described herein can be suitably applied, for example, to the imaging unit 11402 provided on the camera head 11102 of the endoscope 11100. By applying the technology described herein to the imaging unit 11402, it becomes possible to provide a high-definition endoscope 11100.

[0298] Although the present disclosure has been described above with reference to embodiments, modifications, application examples, and application examples, the present technology is not limited to the above embodiments, and various modifications are possible. For example, although the above modifications were described as modifications of the above embodiments, the configurations of each modification can be combined as appropriate.

[0299] In the embodiments described above, an imaging device was used as an example; however, the light detection device of this disclosure may be any device that receives incident light and converts the light into an electric charge. The output signal may be an image information signal or a distance measurement information signal. The light detection device (imaging device) can be applied to an image sensor, a distance measurement sensor, etc. Furthermore, this disclosure is not limited to back-illuminated image sensors, but is also applicable to front-illuminated image sensors.

[0300] The light detection device relating to this disclosure can also be used as a distance measuring sensor capable of measuring distance using the Time of Flight (TOF) method. The light detection device (imaging device) can also be used as a sensor capable of detecting events, for example, an event-driven sensor (also known as an EVS (Event Vision Sensor), EDS (Event Driven Sensor), DVS (Dynamic Vision Sensor), etc.).

[0301] This disclosure can be applied not only to image sensors but also to various circuits and devices. The structure of the photodetector (imaging device) described above can be applied to various semiconductor devices. Any element (or circuit) can be provided in each layer. For example, a semiconductor layer 101 may have an element or circuit other than a photoelectric conversion element formed on it. A memory, sensor circuit, power supply circuit, amplification circuit, or interface circuit may be provided in semiconductor layers 101, 102, and 103. The configuration of the circuits formed in each layer and the layout of each layer can be changed as appropriate. This disclosure can be applied to various electronic devices as a semiconductor device.

[0302] A photodetector according to one embodiment of the present disclosure comprises a first semiconductor layer having a photoelectric conversion element and a floating diffusion, a second semiconductor layer provided to be stacked with the first semiconductor layer, a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge accumulated in the floating diffusion, a through electrode provided around the first transistor so as to penetrate the second semiconductor layer, and a first insulating film and an insulating region provided around the through electrode in the second semiconductor layer. The first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode. At least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer. At least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface. In a direction orthogonal to the stacking direction of the first and second semiconductor layers, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer. This makes it possible to realize a photodetector that can suppress quality degradation.

[0303] A photodetector according to one embodiment of the present disclosure comprises a first semiconductor layer having a photoelectric conversion element and a floating diffusion, a second semiconductor layer provided stacked with the first semiconductor layer, a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge accumulated in the floating diffusion, a through electrode provided around the first transistor so as to penetrate the second semiconductor layer, a first insulating film provided around the through electrode in the second semiconductor layer, and a conductive film provided around the first insulating film in the second semiconductor layer. The first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode and a source region provided in the second semiconductor layer. The conductive film is electrically connected to the source region of the first transistor. Therefore, it is possible to realize a photodetector that can suppress quality degradation.

[0304] A semiconductor device according to one embodiment of the present disclosure comprises a first semiconductor layer, a second semiconductor layer provided stacked with the first semiconductor layer, a first transistor provided on the first surface side of the second semiconductor layer, a through-electrode provided around the first transistor so as to penetrate the second semiconductor layer, and a first insulating film and an insulating region provided around the through-electrode in the second semiconductor layer. At least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer. At least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface. In a direction orthogonal to the stacking direction of the first and second semiconductor layers, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer. This makes it possible to realize a semiconductor device that can suppress quality degradation.

[0305] An embodiment of the photodetector of this disclosure comprises a first semiconductor layer having a photoelectric conversion element and a floating diffusion, and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge accumulated in the floating diffusion. The first transistor has a first gate electrode provided in the second semiconductor layer. The first gate electrode of the first transistor is electrically connected to the floating diffusion. This makes it possible to realize a photodetector that can suppress quality degradation.

[0306] A photodetector according to one embodiment of the present disclosure comprises a first semiconductor layer having a photoelectric conversion element and a floating diffusion, and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge accumulated in the floating diffusion. The first transistor has a first gate insulating film and a first gate electrode provided so as to sandwich a part of the second semiconductor layer. The first gate electrode of the first transistor is electrically connected to the floating diffusion. This makes it possible to realize a photodetector that can suppress quality degradation.

[0307] Furthermore, the effects described herein are merely illustrative and not limited to those described herein, and other effects may also exist. In addition, this disclosure may take the following configuration: (1) A first semiconductor layer having a photoelectric conversion element that converts light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; a second semiconductor layer provided stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge stored in the floating diffusion; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; and a first insulating film and an insulating region provided around the through electrode in the second semiconductor layer, wherein the first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode, at least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer, and at least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface. (1) A photodetector wherein, in a direction perpendicular to the stacking direction of the first semiconductor layer and the second semiconductor layer, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer. (2) The photodetector according to (1), wherein, in a direction perpendicular to the stacking direction, the thickness of the insulating region provided in the second semiconductor layer is greater than the thickness of the first insulating film provided in the second semiconductor layer. (3) The photodetector according to (1) or (2), wherein the insulating region is composed of a second insulating film provided around the through electrode. (4) The photodetector according to any one of (1) to (3), wherein the insulating region is composed of a void provided around the through electrode.(5) The photodetector according to any one of (1) to (4), further comprising a semiconductor region of a first conductivity type provided around the first insulating film in the second semiconductor layer, wherein the first transistor has a source region of the first conductivity type provided in the second semiconductor layer, and the semiconductor region is electrically connected to the source region of the first transistor. (6) The photodetector according to (5), wherein the semiconductor region is a first well of the first conductivity type provided adjacent to the first insulating film. (7) The photodetector according to (5) or (6), wherein the first transistor has a drain region of the first conductivity type electrically connected to a power line. (8) The photodetector according to (7), further comprising a second well of a second conductivity type provided in the second semiconductor layer, wherein the source region and the drain region of the first transistor are provided in the second well. (9) The photodetector according to any one of (5) to (8), wherein the bottom of the semiconductor region is located above the insulating region. (10) The photodetector according to any one of (5) to (8), wherein at least a portion of the semiconductor region is provided around the insulating region, and the semiconductor region is provided adjacent to the first insulating film and the insulating region. (11) The photodetector according to any one of (5) to (8), wherein the semiconductor region is provided up to the second surface side of the second semiconductor layer. (12) The photodetector according to any one of (1) to (11), wherein the dielectric constant of the first insulating film is lower than the dielectric constant of the insulating region. (13) The photodetector according to any one of (1) to (12), wherein the first insulating film and the insulating region are provided integrally.(14) A photodetector comprising: a first semiconductor layer having a photoelectric conversion element for photoelectric conversion of light and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; a second semiconductor layer provided to be stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge stored in the floating diffusion; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; a first insulating film provided around the through electrode in the second semiconductor layer; and a conductive film provided around the first insulating film in the second semiconductor layer, wherein the first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode and a source region provided in the second semiconductor layer, and the conductive film is electrically connected to the source region of the first transistor. (15) The photodetector according to (14), wherein the conductive film is made of a different material from the second semiconductor layer. (16) The photodetector according to (14) or (15), wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, and the conductive film is provided between the first surface and the second surface of the second semiconductor layer so as to be along the through electrode. (17) The photodetector according to any one of (14) to (16), wherein the conductive film is provided in contact with the source region of the first transistor.(18) A semiconductor device comprising: a first semiconductor layer; a second semiconductor layer provided to be stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; and a first insulating film and an insulating region provided around the through electrode in the second semiconductor layer, wherein at least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer, at least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface, and in a direction perpendicular to the stacking direction of the first semiconductor layer and the second semiconductor layer, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer. (19) A photodetector comprising: a first semiconductor layer having a photoelectric conversion element for photoelectric conversion of light and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge stored in the floating diffusion, wherein the first transistor has a first gate electrode provided in the second semiconductor layer, and the first gate electrode of the first transistor is electrically connected to the floating diffusion. (20) The photodetector according to (19), wherein the first gate electrode of the first transistor is provided so as to penetrate the second semiconductor layer. (21) The photodetector according to (19) or (20), wherein the first transistor has a source region and a drain region provided in the second semiconductor layer, one of the source region and the drain region of the first transistor is provided on the first surface side of the second semiconductor layer, and the other of the source region and the drain region of the first transistor is provided on the second surface side of the second semiconductor layer opposite to the first surface.(22) The photodetector according to any one of (19) to (21), wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, and the first semiconductor layer and the second semiconductor layer are stacked such that the surface of the first semiconductor layer on which the floating diffusion is provided and the second surface of the second semiconductor layer face each other, and the first transistor has a source region provided on the first surface side of the second semiconductor layer and a drain region provided on the second surface side of the second semiconductor layer. (23) The photodetector according to any one of (19) to (22), wherein the first transistor has a gate insulating film provided around the first gate electrode in the second semiconductor layer. (24) The photodetector according to any one of (19) to (23), further comprising an isolation region provided in the second semiconductor layer, wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, and the isolation region is provided around the first transistor on the second surface side of the second semiconductor layer. (25) The photodetector according to any one of (19) to (24), further comprising a second transistor capable of resetting the voltage of the floating diffusion, wherein the second transistor has a second gate electrode provided in the second semiconductor layer. (26) The photodetector according to any one of (19) to (25), further comprising a third transistor electrically connected to the first transistor and capable of outputting the first signal, wherein the third transistor is provided on the first surface side of the second semiconductor layer. (27) A photodetector comprising: a first semiconductor layer having a photoelectric conversion element for converting light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge stored in the floating diffusion, wherein the first transistor has a first gate insulating film and a first gate electrode provided so as to sandwich a part of the second semiconductor layer, and the first gate electrode of the first transistor is electrically connected to the floating diffusion.(28) The photodetector according to (27), wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, and the first transistor has a source region and a drain region, and at least one of the source region and the drain region of the first transistor is provided from the second surface side to the first surface side of the second semiconductor layer. (29) The photodetector according to (28), wherein at least one of the source region and the drain region of the first transistor is provided to reach the first surface of the second semiconductor layer. (30) The photodetector according to any one of (27) to (29), wherein the first gate electrode of the first transistor is provided to enclose a part of the second semiconductor layer. (31) The photodetector according to any one of (27) to (30), wherein the first gate electrode of the first transistor is provided to sandwich a plurality of parts of the second semiconductor layer. (32) The photodetector according to any one of (27) to (31), further comprising a second transistor capable of resetting the voltage of the floating diffusion, wherein the second transistor has a second gate insulating film and a second gate electrode provided so as to sandwich a part of the second semiconductor layer. (33) The photodetector according to any one of (27) to (32), further comprising a light-shielding member provided in the same layer as the second semiconductor layer. (34) The photodetector according to (33), wherein the light-shielding member is composed of another part of the second semiconductor layer. (35) The photodetector according to any one of (27) to (34), further comprising a barrier film provided around the second semiconductor layer. (36) The photodetector according to (35), wherein the first transistor has a source region and a drain region, and the barrier film is provided so as to cover at least one of the source region and the drain region of the first transistor.

[0308] This application claims priority based on Japanese Patent Application No. 2024-196244, filed with the Japan Patent Office on 8 November 2024, and all contents of that application are incorporated herein by reference.

[0309] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A first semiconductor layer having a photoelectric conversion element that converts light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; a second semiconductor layer provided stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge stored in the floating diffusion; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; and a first insulating film and an insulating region provided around the through electrode in the second semiconductor layer, wherein the first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode, at least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer, and at least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface. A photodetector in which, in a direction perpendicular to the stacking direction of the first semiconductor layer and the second semiconductor layer, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer.

2. The photodetector according to claim 1, wherein the thickness of the insulating region provided in the second semiconductor layer in a direction perpendicular to the stacking direction is greater than the thickness of the first insulating film provided in the second semiconductor layer.

3. The photodetector according to claim 1, wherein the insulating region is composed of a second insulating film provided around the through electrode.

4. The photodetector according to claim 1, wherein the insulating region is formed by a gap provided around the through electrode.

5. The photodetector according to claim 1, further comprising a semiconductor region of a first conductivity type provided around the first insulating film in the second semiconductor layer, wherein the first transistor has a source region of the first conductivity type provided in the second semiconductor layer, and the semiconductor region is electrically connected to the source region of the first transistor.

6. The photodetector according to claim 5, wherein the semiconductor region is a first well of the first conductivity type provided adjacent to the first insulating film.

7. The photodetector according to claim 5, wherein the first transistor has a drain region of a first conductivity type that is electrically connected to a power line.

8. The photodetector according to claim 7, further comprising a second well of a second conductivity type provided in the second semiconductor layer, wherein the source region and the drain region of the first transistor are provided in the second well.

9. The photodetector according to claim 5, wherein the bottom of the semiconductor region is located above the insulating region.

10. The photodetector according to claim 5, wherein at least a portion of the semiconductor region is provided around the insulating region, and the semiconductor region is provided adjacent to the first insulating film and the insulating region.

11. The photodetector according to claim 5, wherein the semiconductor region extends to the second surface side of the second semiconductor layer.

12. The photodetector according to claim 1, wherein the dielectric constant of the first insulating film is lower than the dielectric constant of the insulating region.

13. The photodetector according to claim 1, wherein the first insulating film and the insulating region are provided integrally.

14. A photodetector comprising: a first semiconductor layer having a photoelectric conversion element for converting light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; a second semiconductor layer provided stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer and capable of generating a first signal based on the charge stored in the floating diffusion; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; a first insulating film provided around the through electrode in the second semiconductor layer; and a conductive film provided around the first insulating film in the second semiconductor layer, wherein the first transistor has a gate electrode electrically connected to the floating diffusion via the through electrode and a source region provided in the second semiconductor layer, and the conductive film is electrically connected to the source region of the first transistor.

15. The photodetector according to claim 14, wherein the conductive film is made of a material different from the second semiconductor layer.

16. The photodetector according to claim 14, wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, and the conductive film is provided between the first surface and the second surface of the second semiconductor layer so as to be aligned with the through electrode.

17. The photodetector according to claim 14, wherein the conductive film is provided in contact with the source region of the first transistor.

18. A semiconductor device comprising: a first semiconductor layer; a second semiconductor layer provided to be stacked with the first semiconductor layer; a first transistor provided on the first surface side of the second semiconductor layer; a through electrode provided around the first transistor so as to penetrate the second semiconductor layer; and a first insulating film and an insulating region provided around the through electrode in the second semiconductor layer, wherein at least a portion of the first insulating film is provided on the first surface side of the second semiconductor layer, at least a portion of the insulating region is provided on the second surface side of the second semiconductor layer opposite to the first surface, and in a direction perpendicular to the stacking direction of the first semiconductor layer and the second semiconductor layer, the thickness of the insulating region provided on the second surface side of the second semiconductor layer is greater than the thickness of the first insulating film provided on the first surface side of the second semiconductor layer.

19. A photodetector comprising: a first semiconductor layer having a photoelectric conversion element for converting light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge stored in the floating diffusion, wherein the first transistor has a first gate electrode provided in the second semiconductor layer, and the first gate electrode of the first transistor is electrically connected to the floating diffusion.

20. The photodetector according to claim 19, wherein the first gate electrode of the first transistor is provided so as to penetrate the second semiconductor layer.

21. The photodetector according to claim 19, wherein the first transistor has a source region and a drain region provided in the second semiconductor layer, one of the source region and the drain region of the first transistor is provided on the first surface side of the second semiconductor layer, and the other of the source region and the drain region of the first transistor is provided on the second surface side of the second semiconductor layer opposite to the first surface.

22. The photodetector according to claim 19, wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, the first semiconductor layer and the second semiconductor layer are stacked such that the surface of the first semiconductor layer on which the floating diffusion is provided faces the second surface of the second semiconductor layer, and the first transistor has a source region provided on the first surface side of the second semiconductor layer and a drain region provided on the second surface side of the second semiconductor layer.

23. The photodetector according to claim 19, wherein the first transistor has a gate insulating film provided around the first gate electrode in the second semiconductor layer.

24. The photodetector according to claim 19, further comprising an isolation region provided in the second semiconductor layer, wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, and the isolation region is provided around the first transistor on the second surface side of the second semiconductor layer.

25. The photodetector according to claim 19, further comprising a second transistor capable of resetting the voltage of the floating diffusion, wherein the second transistor has a second gate electrode provided in the second semiconductor layer.

26. The photodetector according to claim 19, further comprising a third transistor electrically connected to the first transistor and capable of outputting the first signal, wherein the third transistor is provided on the first surface side of the second semiconductor layer.

27. A photodetector comprising: a first semiconductor layer having a photoelectric conversion element for converting light into photoelectric energy and a floating diffusion capable of storing the charge converted by the photoelectric conversion element; and a second semiconductor layer provided stacked with the first semiconductor layer, having a first transistor capable of generating a first signal based on the charge stored in the floating diffusion, wherein the first transistor has a first gate insulating film and a first gate electrode provided so as to sandwich a part of the second semiconductor layer, and the first gate electrode of the first transistor is electrically connected to the floating diffusion.

28. The photodetector according to claim 27, wherein the second semiconductor layer has a first surface and a second surface opposite to the first surface, the first transistor has a source region and a drain region, and at least one of the source region and the drain region of the first transistor is provided from the second surface side to the first surface side of the second semiconductor layer.

29. The photodetector according to claim 28, wherein at least one of the source region and the drain region of the first transistor is provided to reach the first surface of the second semiconductor layer.

30. The photodetector according to claim 27, wherein the first gate electrode of the first transistor is provided so as to enclose a portion of the second semiconductor layer.

31. The photodetector according to claim 27, wherein the first gate electrode of the first transistor is provided so as to sandwich each of the multiple portions of the second semiconductor layer.

32. The photodetector according to claim 27, further comprising a second transistor capable of resetting the voltage of the floating diffusion, wherein the second transistor has a second gate insulating film and a second gate electrode provided so as to sandwich a portion of the second semiconductor layer.

33. The photodetector according to claim 27, further comprising a light-shielding member provided in the same layer as the second semiconductor layer.

34. The light-shielding member is composed of another part of the second semiconductor layer, as described in claim 33.

35. The photodetector according to claim 27, further comprising a barrier film provided around the second semiconductor layer.

36. The photodetector according to claim 35, wherein the first transistor has a source region and a drain region, and the barrier film is provided so as to cover at least one of the source region and the drain region of the first transistor.

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