Semiconductor device

Abstract

This semiconductor device includes a chip, an insulating film covering the chip, and a shield opening formed in the insulating film at the periphery of the chip and partitioning the insulating film into a region on the inner-side of the chip and a region on the periphery-side of the chip.

Description

Semiconductor device

[0001] This application claims priority based on Patent Application No. 2024-195391 filed with the Japan Patent Office on November 7, 2024, and the entire contents of this application are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2023 / 0387193A1) discloses a semiconductor device including a structure on the central side of a chip and a structure on the end side of the chip.

[0003] U.S. Patent Application Publication No. 2023 / 0387193

[0004] [Summary] The present disclosure provides a semiconductor device that contributes to improving reliability.

[0005] The present disclosure provides a semiconductor device including a chip, an insulating film covering the chip, and a shield opening formed in the insulating film at a peripheral portion of the chip to partition the insulating film into an inner region of the chip and a peripheral region of the chip.

[0006] The above or further other objects, features, and effects will be clarified by a detailed description with reference to the accompanying drawings.

[0007] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a plan view obtained by removing the upper insulating film from Figure 1. Figure 3 is a cross-sectional view taken along the line III-III shown in Figure 1. Figure 4 is a plan view showing an example of the layout of the first main surface. Figure 5 is an enlarged plan view showing a key part of the active region shown in Figure 4. Figure 6 is a cross-sectional view taken along the line VI-VI shown in Figure 5. Figure 7 is an enlarged cross-sectional view of the structure shown in Figure 6. Figure 8 is a cross-sectional view taken along the line VIII-VIII shown in Figure 1. Figure 9 is a cross-sectional view taken along the line IX-IX shown in Figure 1. Figure 10 is a cross-sectional view taken along the line XX shown in Figure 1. Figure 11 is an enlarged cross-sectional view showing a key part of the outer region shown in Figure 9. Figure 12 is a further enlarged cross-sectional view of the outer region shown in Figure 11. Figure 13 is an enlarged cross-sectional view showing the gate via structure shown in Figure 12. Figure 14 is an enlarged cross-sectional view showing the outer via structure shown in Figure 12. Figure 15 is an enlarged cross-sectional view showing the shield structure shown in Figure 12. Figure 16A is an enlarged cross-sectional view showing a first modified example of the source via electrode. Figure 16B is an enlarged cross-sectional view showing a second modified example of the source via electrode. Figure 17A is an enlarged cross-sectional view showing a first modified example of the shield electrode. Figure 17B is an enlarged cross-sectional view showing a second modified example of the shield electrode. Figure 18A is an enlarged cross-sectional view showing a first modified example of the source electrode. Figure 18B is an enlarged cross-sectional view showing a second modified example of the source electrode. Figure 18C is an enlarged cross-sectional view showing a third modified example of the source electrode. Figure 18D is an enlarged cross-sectional view showing a fourth modified example of the source electrode. Figure 18E is an enlarged cross-sectional view showing a fifth modified example of the source electrode. Figure 19 is a plan view showing a semiconductor device according to the second embodiment. Figure 20 is a plan view obtained by removing the upper insulating film from Figure 19. Figure 21 is a cross-sectional view taken along the line XXI-XXI shown in Figure 19. Figure 22 is a plan view showing an example of the layout of the first main surface. Figure 23 is an enlarged plan view showing a key part of the active region shown in Figure 22. Figure 24 is a cross-sectional view taken along the line XXIV-XXIV shown in Figure 23. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 23. Figure 26 is an enlarged cross-sectional view of the structure shown in Figure 24. Figure 27 is a cross-sectional view along the line XXVII-XXVII shown in Figure 19. Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 19. Figure 29 is a cross-sectional view along the line XXIX-XXIX shown in Figure 19.Figure 30 is an enlarged cross-sectional view showing a key part of the outer region shown in Figure 28. Figure 31 is a further enlarged cross-sectional view of the outer region shown in Figure 30. Figure 32 is a plan view showing a semiconductor device according to the third embodiment. Figure 33 is a cross-sectional view along the line XXXIII-XXXIII shown in Figure 32. Figure 34 is an enlarged cross-sectional view showing a key part of the outer region shown in Figure 33. Figure 35 is a further enlarged cross-sectional view of the outer region shown in Figure 34. Figure 36 is an enlarged cross-sectional view showing the outer region of a first modified example of the semiconductor device according to the first to third embodiments. Figure 37 is an enlarged cross-sectional view showing the shield structure shown in Figure 36. Figure 38 is an enlarged cross-sectional view showing the outer region of a second modified example of the semiconductor device according to the first to third embodiments. Figure 39 is an enlarged cross-sectional view showing the shield structure shown in Figure 38. Figure 40 is an enlarged cross-sectional view showing the outer region of a third modified example of the semiconductor device according to the first to third embodiments. Figure 41 is an enlarged cross-sectional view showing the shield structure shown in Figure 40. Figure 42 is an enlarged cross-sectional view showing the outer region of a fourth modified example of the semiconductor device according to the first to third embodiments. Figure 43 is an enlarged cross-sectional view showing the shield structure shown in Figure 42. Figure 44 is an enlarged cross-sectional view showing the outer region of a fifth modified example of the semiconductor device according to the first to third embodiments. Figure 45 is an enlarged cross-sectional view showing the shield structure shown in Figure 44. Figure 46 is an enlarged cross-sectional view showing the outer region of a sixth modified example of the semiconductor device according to the first to third embodiments. Figure 47 is an enlarged cross-sectional view showing the shield structure shown in Figure 46. Figure 48 is an enlarged cross-sectional view showing the outer region of a seventh modified example of the semiconductor device according to the first to third embodiments. Figure 49 is an enlarged cross-sectional view showing the shield structure shown in Figure 48. Figure 50 is an enlarged cross-sectional view showing the outer region of an eighth modified example of the semiconductor device according to the first to third embodiments. Figure 51 is an enlarged cross-sectional view showing the shield structure shown in Figure 50. Figure 52 is an enlarged cross-sectional view showing the outer region of a ninth modified example of the semiconductor device according to the first to third embodiments. Figure 53 is an enlarged cross-sectional view showing the shield structure shown in Figure 52. Figure 54 is an enlarged cross-sectional view showing the outer region of a tenth modified example of the semiconductor device according to the first to third embodiments. Figure 55 is an enlarged cross-sectional view showing the outer region of the 11th modified example of the semiconductor device according to the first to third embodiments. Figure 56 is an enlarged cross-sectional view showing the outer region of the 12th modified example of the semiconductor device according to the first to third embodiments.Figure 57 is a schematic diagram showing a module on which at least one of the semiconductor devices according to the first to third embodiments is mounted.

[0008] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0009] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." In this specification, "substantially" includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) being compared.

[0010] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0011] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0012] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a plan view obtained by removing the upper insulating film 80 from Figure 1. Figure 3 is a cross-sectional view taken along the line III-III shown in Figure 1. Figure 4 is a plan view showing an example of the layout of the first main surface 3. Figure 5 is an enlarged plan view showing a key part of the active region 8 shown in Figure 4.

[0014] Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 5. Figure 7 is an enlarged cross-sectional view of the structure shown in Figure 6. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 1. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 1. Figure 10 is a cross-sectional view along the line XX shown in Figure 1.

[0015] Figure 11 is an enlarged cross-sectional view showing a key part of the outer region 9 shown in Figure 9. Figure 12 is a further enlarged cross-sectional view of the outer region 9 shown in Figure 11. Figure 13 is an enlarged cross-sectional view showing the gate via structure 40 shown in Figure 12. Figure 14 is an enlarged cross-sectional view showing the outer via structure 50 shown in Figure 12. Figure 15 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 12.

[0016] Referring to Figures 1 to 15, semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure T as an example of a device structure (functional device). The transistor structure T has a planar gate type vertical structure.

[0017] The semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0018] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0019] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0020] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed in plan from the thickness direction Z of the chip 2 (hereinafter simply referred to as "plan view"). The thickness direction Z is also the normal direction (vertical direction) to the first main surface 3 and the second main surface 4.

[0021] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0022] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0023] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X may be the a-axis direction and the second direction Y may be the m-axis direction. Alternatively, the first direction X may be a direction that intersects both the a-axis and m-axis directions, and the second direction Y may be a direction that intersects both the a-axis and m-axis directions.

[0024] In the following, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is the direction along the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the thickness direction Z.

[0025] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the amount of the off-angle from the thickness direction Z (vertical line) toward the off-direction. The off-direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The off-direction may also be the m-axis direction of the SiC single crystal.

[0026] The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0027] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0028] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in the region on the second main surface 4 side within the chip 2. The first semiconductor layer 6 may also be referred to as the "first layer (region)," the "drain layer (region)," etc. The first semiconductor layer 6 extends in layers along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0029] The n-type impurity concentration of the first semiconductor layer 6 may be approximately constant in the thickness direction Z. The n-type impurity concentration of the first semiconductor layer 6 may be adjusted by a single pentavalent element. Preferably, the first semiconductor layer 6 contains a pentavalent element other than phosphorus. In this embodiment, the concentration of the first semiconductor layer 6 is adjusted by nitrogen as the pentavalent element.

[0030] The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the first semiconductor layer 6 is a semiconductor substrate (SiC substrate) containing a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. Of course, the first semiconductor layer 6 may be made of other polytypes. The first semiconductor layer 6 may be made of a 3C-SiC polycrystal.

[0031] The first semiconductor layer 6 may have a thickness greater than 0 μm and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: greater than 0 μm and 10 μm or less, 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0032] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in the region on the first main surface 3 side relative to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may also be referred to as the "second layer (region)", "drain layer (region)", "drift layer (region)", etc.

[0033] The second semiconductor layer 7 has a lower n-type impurity concentration than the first semiconductor layer 6. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction Z. The n-type impurity concentration of the second semiconductor layer 7 may increase from the first semiconductor layer 6 side toward the first main surface 3 side.

[0034] The second semiconductor layer 7 is stacked on top of the first semiconductor layer 6. The second semiconductor layer 7 extends in layers along the first main surface 3 (first semiconductor layer 6), forming the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0035] The second semiconductor layer 7 contains a single crystal of a wide-bandgap semiconductor. In this embodiment, the second semiconductor layer 7 is a semiconductor layer (SiC layer) containing a hexagonal SiC single crystal. In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer containing a 4H-SiC single crystal (hexagonal) and has the aforementioned off-direction and off-angle. Of course, the second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0036] The second semiconductor layer 7 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may be a value that falls within at least one of the following ranges: greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0037] The semiconductor device 1A includes an active region 8 provided on the first main surface 3. The active region 8 includes a device structure (transistor structure T) and is a region where an output current (drain current) is generated. The active region 8 is provided in the inner part of the first main surface 3, spaced apart from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 8 is provided in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0038] The ratio of the surface area of ​​the active region 8 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0039] The semiconductor device 1A includes an outer region 9 located outside the active region 8 on the first main surface 3. The outer region 9 is a region that does not include the device structure (transistor structure T) and is located at the periphery of the first main surface 3. The outer region 9 is located in the region between the periphery of the first main surface 3 and the active region 8. In a plan view, the outer region 9 extends in a band shape along the active region 8 and is located in a polygonal ring shape (a quadrilateral ring in this embodiment) that surrounds the active region 8.

[0040] The semiconductor device 1A includes a plurality of p-type body regions 10 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The body regions 10 may also be referred to as "impurity regions," etc. The body regions 10 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0041] Multiple body regions 10 are formed in the active region 8, spaced apart from the periphery of the first main surface 3, but not in the outer region 9. Multiple body regions 10 are formed in the surface layer of the first main surface 3. Multiple body regions 10 are arranged spaced apart in the first direction X in a plan view, and each extends in a strip-like manner in the second direction Y. In other words, multiple body regions 10 are arranged in a stripe-like pattern extending in the second direction Y in a plan view.

[0042] Multiple body regions 10 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7. Multiple body regions 10 are formed at intervals from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0043] Multiple body regions 10 may each have a width greater than 0 μm and less than or equal to 10 μm. The width of a body region 10 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm.

[0044] The plurality of body regions 10 may each have a depth greater than 0 μm and not more than 2 μm. The depth of the body region 10 may have a value belonging to at least one of the ranges of greater than 0 μm and not more than 0.5 μm, not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 1.5 μm, and not less than 1.5 μm and not more than 2 μm.

[0045] The interval between the plurality of body regions 10 may be less than the width of the body region 10. The interval between the body regions 10 may be greater than 0 μm and not more than 3 μm. The interval between the body regions 10 may have a value belonging to at least one of the ranges of greater than 0 μm and not more than 0.5 μm, not less than 0.5 μm and not more than 1 μm, not less than 1 μm and not more than 1.5 μm, not less than 1.5 μm and not more than 2 μm, not less than 2 μm and not more than 2.5 μm, and not less than 2.5 μm and not more than 3 μm.

[0046] The semiconductor device 1A includes a plurality of n-type source regions 11 formed on the surface layer portions of the plurality of body regions 10 respectively. The source region 11 may be referred to as an "impurity region" or the like. The source region 11 has an n-type impurity concentration higher than the p-type impurity concentration of the body region 10. The n-type impurity concentration of the source region 11 is higher than the n-type impurity concentration of the second semiconductor layer 7.

[0047] The plurality of source regions 11 are formed at intervals from both edge portions of the corresponding body region 10 to the inner portion of the corresponding body region 10 with respect to the first direction X, and extend in a strip shape in the second direction Y respectively. The plurality of source regions 11 are formed at intervals from the bottom of the corresponding body region 10 to the first main surface 3 side, and face the second semiconductor layer 7 through a part of the corresponding body region 10.

[0048] The plurality of source regions 11 may be formed at intervals from the intermediate depth position of the corresponding body region 10 to the first main surface 3 side. The plurality of source regions 11 may be formed in a one-to-many correspondence relationship with respect to the corresponding one body region 10. In this case, the plurality of source regions 11 may be formed at intervals in the second direction Y on the surface layer portion of the corresponding one body region 10.

[0049] The semiconductor device 1A includes a plurality of p-type contact regions 12 formed in different regions from the plurality of source regions 11 on the surface of the plurality of body regions 10. The contact regions 12 may also be referred to as "impurity regions," etc. The plurality of contact regions 12 have a higher p-type impurity concentration than the p-type impurity concentration of the plurality of body regions 10.

[0050] Multiple contact regions 12 are interposed in the areas between multiple source regions 11 on the surface of the corresponding body region 10, and each extends in a strip-like shape in the second direction Y. In this embodiment, the contact regions 12 have a width less than the width of the multiple source regions 11. The width of the contact regions 12 may be greater than the width of the multiple source regions 11.

[0051] Multiple contact regions 12 are formed at intervals from the bottom of the corresponding body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a portion of the corresponding body region 10. The multiple contact regions 12 are electrically connected to the corresponding body region 10. The multiple contact regions 12 may also be formed at intervals from an intermediate depth position of the corresponding body region 10 toward the first main surface 3.

[0052] In this embodiment, the multiple contact regions 12 have a depth greater than the depth of the multiple source regions 11 and have bottoms located on the bottom side of the body region 10 than the bottoms of the multiple source regions 11. The bottoms of the multiple contact regions 12 may be located on the first main surface 3 side than the bottoms of the multiple source regions 11.

[0053] Multiple contact regions 12 may be formed in a one-to-many correspondence with respect to a single corresponding body region 10. In this case, the multiple contact regions 12 may be formed at intervals in the second direction Y on the surface of the single corresponding body region 10.

[0054] The semiconductor device 1A includes a plurality of n-type surface drift regions 13 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The plurality of surface drift regions 13 have an n-type impurity concentration lower than the n-type impurity concentration of the plurality of source regions 11.

[0055] In this configuration, each of the multiple surface drift regions 13 consists of a part of the second semiconductor layer 7 and has an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. The n-type impurity concentrations of the multiple surface drift regions 13 may be higher or lower than the n-type impurity concentration of the second semiconductor layer 7.

[0056] Multiple surface drift regions 13 are each demarcated in the surface portion of the first main surface 3, in the areas between the multiple body regions 10, and extend in a stripe-like manner in the second direction Y, following the layout of the multiple body regions 10. In other words, the multiple surface drift regions 13 are demarcated with gaps in the first direction X and extend in a strip-like manner in the second direction Y. The width of the surface drift regions 13 corresponds to the spacing between the multiple body regions 10.

[0057] The semiconductor device 1A includes a plurality of p-type channel regions 14 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The plurality of channel regions 14 have a p-type impurity concentration lower than the p-type impurity concentration of the plurality of contact regions 12.

[0058] In this configuration, each of the multiple channel regions 14 consists of a part of the multiple body regions 10 and has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the multiple body regions 10. The p-type impurity concentration of the channel regions 14 may be higher or lower than the p-type impurity concentration of the body regions 10.

[0059] The multiple channel regions 14 are each demarcated in the surface portion of the multiple body regions 10, between the multiple source regions 11 and the multiple surface drift regions 13 (second semiconductor layer 7), and each extends in a strip shape in the second direction Y. The multiple channel regions 14 form current paths that connect the multiple source regions 11 and the multiple surface drift regions 13 in the horizontal direction.

[0060] The semiconductor device 1A includes a plurality of planar type (planar electrode type) gate structures 15 arranged on the first main surface 3 in the inner portion (active region 8) of the first main surface 3. The plurality of gate structures 15 control the inversion and non-inversion of a plurality of channel regions 14 from above the first main surface 3.

[0061] Multiple gate structures 15 are arranged at intervals in the first direction X and extend in a strip-like manner in the second direction Y. Multiple gate structures 15 are arranged in a stripe-like manner extending in the second direction Y. Multiple gate structures 15 are each positioned on at least one channel region 14 (the peripheral edge of the body region 10).

[0062] Specifically, the multiple gate structures 15 each cover the periphery of at least one body region 10, at least one source region 11, and one surface drift region 13. In this embodiment, the multiple gate structures 15 straddle the peripheries of two adjacent body regions 10 and face two source regions 11, one surface drift region 13, and two channel regions 14.

[0063] Each of the multiple gate structures 15 has a stacked structure including a planar insulating film 16 and a planar electrode 17. The planar insulating film 16 may be referred to as a "gate insulating film," and the planar electrode 17 may be referred to as a "gate electrode," "planar gate electrode," etc.

[0064] The planar insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the planar insulating film 16 has a single-layer structure consisting of a silicon oxide film. The planar insulating film 16 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The planar insulating film 16 may include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0065] The planar insulating film 16 coats the first main surface 3 in a film-like manner. The planar insulating film 16 is positioned on at least one channel region 14 (the peripheral edge of the body region 10) and extends in a strip shape in the second direction Y.

[0066] The planar insulating film 16 covers the periphery of at least one body region 10, at least one source region 11, and one surface drift region 13. In this embodiment, the planar insulating film 16 spans the periphery of two adjacent body regions 10 and covers two source regions 11, one surface drift region 13, and two channel regions 14.

[0067] The planar insulating film 16 may have a width greater than 0 μm and 12 μm or less. The width of the planar electrode 17 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, 8 μm or more and 10 μm or less, and 10 μm or more and 12 μm or less.

[0068] The planar insulating film 16 may have a thickness greater than 0 nm and less than or equal to 250 nm. The thickness of the planar insulating film 16 may have a value that falls within at least one of the following ranges: greater than 0 nm and less than or equal to 10 nm, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0069] The planar electrode 17 may contain a metallic or nonmetallic conductor. The planar electrode 17 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. A gate potential is applied to the planar electrode 17 as a control potential.

[0070] The planar electrode 17 is arranged in a film-like manner on the planar insulating film 16. In this embodiment, the planar electrode 17 is formed with a gap inward from the periphery of the planar insulating film 16, exposing the periphery of the planar insulating film 16. Of course, the planar electrode 17 may also have electrode sidewalls that are connected to the periphery of the planar insulating film 16.

[0071] The planar electrode 17 faces at least one channel region 14 (the peripheral edge of the body region 10) via the planar insulating film 16 and extends in a strip shape in the second direction Y. The planar electrode 17 faces at least one peripheral edge of the body region 10, at least one source region 11, and one surface drift region 13 via the planar insulating film 16.

[0072] In this configuration, the planar electrode 17 spans the periphery of two adjacent body regions 10 and faces two source regions 11, one surface drift region 13, and two channel regions 14.

[0073] The planar electrode 17 may have a width greater than 0 μm and less than or equal to 12 μm. The width of the planar electrode 17 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, 8 μm to 10 μm, and 10 μm to 12 μm.

[0074] The planar electrode 17 may have a thickness greater than 0 μm and less than or equal to 1 μm. The thickness of the planar electrode 17 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0075] The semiconductor device 1A includes a p-type outer well region 18 formed in the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The outer well region 18 may also be referred to as an "impurity region" or the like.

[0076] The outer well region 18 has a p-type impurity concentration lower than that of the contact region 12. The p-type impurity concentration of the outer well region 18 may be approximately equal to that of the body region 10. The p-type impurity concentration of the outer well region 18 may be higher or lower than that of the body region 10.

[0077] The outer well region 18 is formed in the outer region 9 on the surface of the first main surface 3. The outer well region 18 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the inward side (active region 8) of the first main surface 3, and extends in a band shape along the active region 8. In a plan view, the outer well region 18 has a portion extending in a first direction X and a portion extending in a second direction Y, and divides the active region 8 from multiple directions.

[0078] In this embodiment, the outer well region 18 surrounds the active region 8 in a plan view and is formed as an ended or endless polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The outer well region 18 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0079] The outer well region 18 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer well region 18 demarcates the boundary between the active region 8 and the outer region 9 and is connected (electrically connected) to a plurality of body regions 10 in the portion extending in the first direction X. The outer edge of the outer well region 18 extends substantially parallel to the inner edge.

[0080] The outer well region 18 may be exposed from the first main surface 3 and may form the first main surface 3. The outer well region 18 may be formed at a distance from the first main surface 3 in the thickness direction Z and may face the first main surface 3 via a part of the second semiconductor layer 7.

[0081] The outer well region 18 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The outer well region 18 is formed with a gap from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0082] The outer well region 18 has a width greater than the width of the body region 10. The width of the outer well region 18 may be greater than 0 μm and 300 μm or less. The width of the outer well region 18 may have a value that falls within at least one of the following ranges: greater than 0 μm and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less.

[0083] In this configuration, the outer well region 18 has a depth approximately equal to the depth of the body region 10. The depth of the outer well region 18 may be greater or less than the depth of the body region 10.

[0084] The depth of the outer well region 18 may be greater than 0 μm and 2 μm or less. The depth of the outer well region 18 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0085] The semiconductor device 1A includes one or more (one in this embodiment) p-type outer contact regions 19 formed in the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The outer contact region 19 may also be referred to as an "impurity region," etc. The outer contact region 19 has a higher p-type impurity concentration than the p-type impurity concentration of the outer well region 18.

[0086] The p-type impurity concentration in the outer contact region 19 is higher than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the outer contact region 19 may be approximately equal to the p-type impurity concentration in the contact region 12. The p-type impurity concentration in the outer contact region 19 may be higher or lower than the p-type impurity concentration in the contact region 12.

[0087] The outer contact region 19 is formed in the outer region 9 on the surface of the first main surface 3. Specifically, the outer contact region 19 is formed on the surface of the outer well region 18. In this embodiment, the outer contact region 19 has a width less than the width of the outer well region 18 and is formed in the inner part of the outer well region 18, spaced apart from the periphery of the outer well region 18.

[0088] In this configuration, the outer contact region 19 is located towards the outer edge of the outer well region 18 relative to the middle portion of the outer well region 18. The width of the outer contact region 19 may be greater than or less than the width of the contact region 12. The width of the outer contact region 19 may be greater than or less than the width of the body region 10.

[0089] The outer contact region 19 extends in a band shape following the direction of extension of the outer well region 18. The outer contact region 19 has a portion extending in a first direction X and a portion extending in a second direction Y in a plan view.

[0090] In this embodiment, the outer contact region 19 is formed as an ended or endless polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8. The outer contact region 19 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0091] The outer contact region 19 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer contact region 19 is formed with a gap outward from the inner edge of the outer well region 18. The outer edge of the outer contact region 19 is formed with a gap inward from the outer edge of the outer well region 18.

[0092] The outer contact region 19 is exposed from the first main surface 3 and forms the first main surface 3. The outer contact region 19 is formed with a gap from the bottom of the outer well region 18 toward the first main surface 3 and faces the second semiconductor layer 7 via a part of the outer well region 18. The outer contact region 19 may also be formed with a gap from an intermediate depth position in the outer well region 18 toward the first main surface 3.

[0093] In this configuration, the outer contact region 19 has a depth approximately equal to the depth of the contact region 12. The depth of the outer contact region 19 may be greater or less than the depth of the contact region 12.

[0094] The width of the outer contact region 19 is arbitrary. The ratio of the width of the outer contact region 19 to the width of the outer well region 18 (width ratio) may be greater than 0 and less than 1. The width ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.1 or less, 0.1 or more and 0.25 or less, 0.25 or more and 0.5 or less, 0.5 or more and 0.75 or less, and 0.75 or more and less than 1. In this embodiment, the width ratio is 0.5 or less.

[0095] If the semiconductor device 1A includes a plurality of outer contact regions 19, the plurality of outer contact regions 19 may be formed at intervals following the extending direction of the outer well region 18. In this case, the plurality of outer contact regions 19 may extend in a strip shape along the extending direction of the outer well region 18. The plurality of outer contact regions 19 may be formed in a polygonal shape (such as a quadrilateral shape) or a circular shape.

[0096] The semiconductor device 1A includes one or more (in this embodiment, more than one) p-type field regions 20 formed in the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The field regions 20 may also be referred to as "impurity regions," etc. The multiple field regions 20 may be formed in an electrically floating state. Source potentials may be applied to the multiple field regions 20.

[0097] The number of field regions 20 may be between 1 and 20. The number of field regions 20 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 20 is between 1 and 8. In this embodiment, the semiconductor device 1A includes 4 field regions 20.

[0098] Multiple field regions 20 have a lower p-type impurity concentration than the contact region 12. The p-type impurity concentration in the field regions 20 is lower than the p-type impurity concentration in the outer contact region 19.

[0099] The p-type impurity concentration in the field region 20 may be approximately equal to the p-type impurity concentration in the outer well region 18. The p-type impurity concentration in the field region 20 may be higher or lower than the p-type impurity concentration in the outer well region 18.

[0100] The p-type impurity concentration in the field region 20 may be approximately equal to the p-type impurity concentration in the body region 10. The p-type impurity concentration in the field region 20 may be higher or lower than the p-type impurity concentration in the body region 10.

[0101] Multiple field regions 20 are formed on the surface of the first main surface 3, spaced apart from each other in the region between the periphery of the first main surface 3 and the active region 8. Specifically, the multiple field regions 20 are formed spaced apart from the outer well region 18 toward the periphery of the first main surface 3 and extend in a band shape along the outer well region 18.

[0102] In this embodiment, the multiple field regions 20 are formed as ended or endless polygonal rings (in this embodiment, quadrangular rings) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 15). The multiple field regions 20 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape).

[0103] Multiple field regions 20 may be exposed from the first main surface 3 and form the first main surface 3. Multiple field regions 20 may be formed at intervals in the thickness direction Z from the first main surface 3 and may face the first main surface 3 via a part of the second semiconductor layer 7.

[0104] Multiple field regions 20 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 through a portion of the second semiconductor layer 7. Multiple field regions 20 are formed at intervals from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0105] Each of the multiple field regions 20 has a width less than the width of the outer well region 18. The width of the field region 20 may be greater than or less than the width of the body region 10. The width of the field region 20 may be greater than or less than the width of the gate structure 15.

[0106] The width of the field region 20 may be greater than 0 μm and 5 μm or less. The width of the field region 20 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0107] The spacing between multiple field areas 20 may be less than the width of a field area 20. The spacing between field areas 20 may be greater than the width of a field area 20. The spacing between multiple field areas 20 may be less than the spacing between body areas 10. The spacing between multiple field areas 20 may be greater than the spacing between body areas 10.

[0108] The spacing of the field regions 20 may be greater than 0 μm and 5 μm or less. The spacing of the field regions 20 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0109] In this configuration, the multiple field regions 20 have a depth approximately equal to the depth of the outer well region 18. The depth of the field regions 20 may be greater than or less than the depth of the outer well region 18. The depth of the field regions 20 may be approximately equal to the depth of the body region 10. The depth of the field regions 20 may be greater than or less than the depth of the body region 10.

[0110] The depth of the field region 20 may be greater than 0 μm and less than or equal to 2 μm. The depth of the field region 20 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, between 0.5 μm and 1 μm, between 1 μm and 1.5 μm, and between 1.5 μm and 2 μm.

[0111] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 20 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 20 may be approximately constant or non-uniform. The width of the multiple field regions 20 may gradually increase or decrease toward the peripheral edge of the first main surface 3.

[0112] The depths of the multiple field regions 20 may be approximately constant or non-uniform. The depths of the multiple field regions 20 may gradually increase or decrease toward the peripheral edge of the first main surface 3. The multiple field regions 20 may each have a relatively shallow portion and a deeper portion that is deeper than the shallow portion. The shallow portion may be formed on the inner side and the deep portion may be formed on the peripheral side.

[0113] The spacing between the multiple field regions 20 may be approximately constant or non-uniform. The spacing between the multiple field regions 20 may gradually increase or decrease toward the periphery of the first main surface 3. The p-type impurity concentration in the multiple field regions 20 may be approximately constant or non-uniform. The p-type impurity concentration in the multiple field regions 20 may gradually increase or decrease toward the periphery of the first main surface 3.

[0114] The semiconductor device 1A includes a p-type or n-type (p-type in this embodiment) channel stop region 21 formed in the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The channel stop region 21 may also be referred to as an "impurity region," etc. The channel stop region 21 may be formed in an electrically floating state.

[0115] The channel stop region 21 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the channel stop region 21 may be approximately equal to the p-type impurity concentration of the body region 10. The p-type impurity concentration of the channel stop region 21 may be higher or lower than the p-type impurity concentrations of the multiple body regions 10.

[0116] The p-type impurity concentration in the channel stop region 21 may be approximately equal to the p-type impurity concentration in the outer well region 18. The p-type impurity concentration in the channel stop region 21 may be higher or lower than the p-type impurity concentration in the outer well region 18.

[0117] The p-type impurity concentration in the channel stop region 21 may be approximately equal to the p-type impurity concentration in the outer contact region 19 (contact region 12). The p-type impurity concentration in the channel stop region 21 may be higher or lower than the p-type impurity concentration in the outer contact region 19 (contact region 12).

[0118] The p-type impurity concentration in the channel stop region 21 may be approximately equal to the p-type impurity concentrations in the multiple field regions 20. The p-type impurity concentration in the channel stop region 21 may be higher or lower than the p-type impurity concentrations in the multiple field regions 20.

[0119] The channel stop region 21 is formed on the surface of the first main surface 3, spaced apart from the outer well region 18 towards the periphery of the first main surface 3. In this configuration, the channel stop region 21 is formed spaced apart from multiple field regions 20 (the outermost field region 20) towards the periphery of the first main surface 3.

[0120] The channel stop region 21 extends in a band shape along the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. In this embodiment, the channel stop region 21 is formed as an ended or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 15).

[0121] In this embodiment, the channel stop region 21 is exposed from the first to fourth sides 5A to 5D and forms part of the first to fourth sides 5A to 5D. The channel stop region 21 may also be formed with a gap inward from the first to fourth sides 5A to 5D.

[0122] The channel stop region 21 has a width greater than the width of the field region 20. The width of the channel stop region 21 is greater than the width of the body region 10. In this embodiment, the width of the channel stop region 21 is less than the width of the outer well region 18. The width of the channel stop region 21 may be greater than the width of the outer well region 18.

[0123] The width of the channel stop region 21 may be greater than 0 μm and 200 μm or less. The width of the channel stop region 21 may have a value that falls within at least one of the following ranges: greater than 0 μm and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, and 150 μm or more and 200 μm or less.

[0124] The channel stop region 21 may be exposed from the first main surface 3 and may form the first main surface 3. The channel stop region 21 may be formed at a distance from the first main surface 3 in the thickness direction Z and may face the first main surface 3 through a part of the second semiconductor layer 7.

[0125] The channel stop region 21 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The channel stop region 21 is formed with a gap from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0126] The channel stop region 21 may have a depth approximately equal to the depth of the outer well region 18. The depth of the channel stop region 21 may be greater or less than the depth of the outer well region 18.

[0127] The depth of the channel stop region 21 may be approximately equal to the depth of the field region 20. The depth of the channel stop region 21 may be greater than or less than the depth of the field region 20. The depth of the channel stop region 21 may be approximately equal to the depth of the body region 10. The depth of the channel stop region 21 may be greater than or less than the depth of the body region 10.

[0128] The spacing between the outermost field region 20 and the channel stop region 21 (the spacing of the channel stop region 21) is greater than the spacing between multiple field regions 20. The spacing of the channel stop region 21 may also be greater than the total width of multiple field regions 20. The spacing of the channel stop region 21 is greater than the spacing between the innermost field region 20 and the outer well region 18.

[0129] The spacing of the channel stop region 21 may be greater than 0 μm and less than or equal to 100 μm. The spacing of the channel stop region 21 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 10 μm, 10 μm or more and less than or equal to 25 μm, 25 μm or more and less than or equal to 50 μm, 50 μm or more and less than or equal to 75 μm, and 75 μm or more and less than or equal to 100 μm.

[0130] The semiconductor device 1A includes a main surface insulating film 25 that selectively covers the first main surface 3. The main surface insulating film 25 may also be called a "surface insulating film," "external insulating film," etc. The main surface insulating film 25 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0131] The main surface insulating film 25 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The main surface insulating film 25 may also include a silicon oxide film containing oxides other than the oxide of the chip 2. The main surface insulating film 25 may also include an insulator of the same type as the planar insulating film 16.

[0132] The main surface insulating film 25 selectively covers the first main surface 3 in the active region 8 and the outer region 9. The main surface insulating film 25 is connected to a plurality of planar insulating films 16 in the active region 8, exposing a plurality of planar electrodes 17. In this embodiment, the main surface insulating film 25 is formed integrally with the plurality of planar insulating films 16 as a single insulating film.

[0133] The main surface insulating film 25 covers the first main surface 3 in its outer region 9. The main surface insulating film 25 also covers the outer well region 18, the outer contact region 19, a plurality of field regions 20, and the channel stop region 21 in its outer region 9.

[0134] The main surface insulating film 25 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The main surface insulating film 25 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and the periphery of the first main surface 3 (channel stop region 21) may be exposed.

[0135] The main surface insulating film 25 may have a thickness approximately equal to the thickness of the planar insulating film 16. The main surface insulating film 25 may have a thickness greater than 0 nm and 250 nm or less. The thickness of the main surface insulating film 25 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 250 nm or less.

[0136] The semiconductor device 1A includes an insulating interlayer film 26 that selectively covers the first main surface 3. The interlayer film 26 may also be called an "insulating film," "interlayer insulating film," or "intermediate insulating film." The interlayer film 26 selectively covers the first main surface 3 in an active region 8 and an outer region 9.

[0137] The interlayer film 26 covers multiple gate structures 15 in the active region 8. Specifically, the interlayer film 26 covers multiple planar electrodes 17 on multiple planar insulating films 16. In the outer region 9, the interlayer film 26 covers the outer well region 18, the outer contact region 19, multiple field regions 20, and the channel stop region 21 via the main surface insulating film 25.

[0138] The interlayer membrane 26 is connected to the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The interlayer membrane 26 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3 (channel stop region 21).

[0139] The interlayer film 26 may have a thickness greater than 0 μm and less than or equal to 2 μm. The thickness of the interlayer film 26 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, between 0.5 μm and 1 μm, between 1 μm and 1.5 μm, and between 1.5 μm and 2 μm.

[0140] In this embodiment, the interlayer film 26 has a laminated structure including a plurality of insulating films. In this embodiment, the interlayer film 26 has a laminated structure including a first interlayer film 27 and a second interlayer film 28 that are laminated in this order from the first main surface 3 side. The interlayer film 26 does not necessarily have to have a laminated structure including a first interlayer film 27 and a second interlayer film 28, and may have a single-layer structure consisting of either the first interlayer film 27 or the second interlayer film 28.

[0141] The first interlayer membrane 27 may have a single-layer structure made of an NSG film (Nondoped Silicate Glass film). The NSG film is a silicon oxide film without impurities. The first interlayer membrane 27 coats the first main surface 3 in a film-like manner with an active region 8 and an outer region 9.

[0142] The first interlayer film 27 covers multiple gate structures 15 in the active region 8. Specifically, the first interlayer film 27 covers multiple planar electrodes 17 on multiple planar insulating films 16. In the outer region 9, the first interlayer film 27 covers the outer well region 18, the outer contact region 19, multiple field regions 20, and the channel stop region 21 via the main surface insulating film 25.

[0143] The first interlayer film 27 may have a thickness greater than 0 μm and less than or equal to 1 μm. The thickness of the first interlayer film 27 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, and between 0.75 μm and 1 μm.

[0144] The second interlayer film 28 contains an insulator different from the insulator of the first interlayer film 27. In this embodiment, the second interlayer film 28 consists of an insulator to which impurities have been added. The second interlayer film 28 may have a single-layer structure or a multilayer structure containing either or both of a PSG film (Phosphorus Silicon Glass film) and a BPSG film (Boron Phosphorus Silicon Glass film).

[0145] The PSG film is a silicon oxide film containing phosphorus, and the BPSG film is a silicon oxide film containing both phosphorus and boron. In this embodiment, the second interlayer film 28 has a single-layer structure consisting of the PSG film. If the second interlayer film 28 has a laminated structure, the PSG film may be laminated on top of the BPSG film, or the BPSG film may be laminated on top of the PSG film.

[0146] The second interlayer film 28 is laminated in a film-like manner on the first interlayer film 27 in the active region 8 and the outer region 9, and covers the first main surface 3 via the first interlayer film 27. The second interlayer film 28 covers a plurality of gate structures 15 via the first interlayer film 27 in the active region 8. Specifically, the second interlayer film 28 covers a plurality of planar insulating films 16 and a plurality of planar electrodes 17 via the first interlayer film 27.

[0147] The second interlayer film 28 covers the outer well region 18, the outer contact region 19, a plurality of field regions 20, and the channel stop region 21 in the outer region 9 via the main surface insulating film 25 and the first interlayer film 27. The second interlayer film 28 may have a thickness greater than that of the first interlayer film 27. The thickness of the second interlayer film 28 may be less than that of the first interlayer film 27.

[0148] The thickness of the second interlayer film 28 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the second interlayer film 28 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, and between 0.75 μm and 1 μm.

[0149] The semiconductor device 1A includes one or more (one in this embodiment) planar wiring 29 selectively routed along the peripheral edge (outer region 9) of the first main surface 3. The planar wiring 29 may also be referred to as "wiring," "gate wiring," etc. The planar wiring 29 is electrically connected to a plurality of gate structures 15 and provides gate potential to the plurality of gate structures 15.

[0150] The planar wiring 29 may contain a metallic or non-metallic conductor. The planar wiring 29 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the planar wiring 29 contains the same conductive material as the conductive material of the planar electrode 17.

[0151] The planar wiring 29 is located within the interlayer film 26. Specifically, the planar wiring 29 is located on the main surface insulating film 25 and covered by the interlayer film 26. In other words, the planar wiring 29 is covered on the main surface insulating film 25 by a laminate film including a first interlayer film 27 and a second interlayer film 28.

[0152] The planar wiring 29 is arranged at intervals from the periphery of the first main surface 3 inward from the first main surface 3. The planar wiring 29 is arranged at intervals inward from the channel stop region 21. The planar wiring 29 is arranged at intervals inward from multiple field regions 20 (the innermost field region 20).

[0153] The planar wiring 29 is positioned at a distance inward from the inner and outer edges of the outer well region 18 and faces the outer well region 18 in the thickness direction Z. In this embodiment, the planar wiring 29 is positioned at a distance inward from the outer edge of the outer contact region 19 and does not face the outer contact region 19 in the thickness direction Z. The planar wiring 29 may have a portion that faces the outer contact region 19 in the thickness direction Z.

[0154] The planar wiring 29 extends in a strip shape along the active region 8 in a plan view. In this embodiment, the planar wiring 29 is formed as an ended or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The planar wiring 29 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape).

[0155] The planar wiring 29 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the planar wiring 29 is mechanically and electrically connected to the ends of the plurality of gate structures 15. Specifically, the inner edge of the planar wiring 29 is drawn out from above the main surface insulating film 25 onto the plurality of planar insulating films 16 and is mechanically and electrically connected to the plurality of planar electrodes 17 on the plurality of planar insulating films 16.

[0156] In this configuration, the planar wiring 29 is integrally formed with the plurality of planar electrodes 17 as a lead wire (lead electrode). The connection portion of the planar wiring 29 to the plurality of planar electrodes 17 may be considered as part of the plurality of planar electrodes 17, or as part of the planar wiring 29. The outer edge of the planar wiring 29 extends substantially parallel to the inner edge.

[0157] The planar wiring 29 has a width greater than the width of the planar electrode 17. The width of the planar wiring 29 may be greater than 0 μm and less than or equal to 250 μm.

[0158] The width of the planar wiring 29 may be greater than 0 μm and fall within at least one of the following ranges: 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or more and 250 μm or less.

[0159] The planar wiring 29 has a thickness approximately equal to the thickness of the planar electrode 17. The thickness of the planar wiring 29 may be greater than or less than the thickness of the planar electrode 17. The thickness of the planar wiring 29 may be greater than 0 μm and less than or equal to 1 μm.

[0160] The thickness of the planar wiring 29 may be greater than 0 μm and fall within at least one of the following ranges: 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less.

[0161] The semiconductor device 1A includes a plurality of conductive source via structures 30 embedded in the interlayer film 26 in the active region 8. The plurality of source via structures 30 are made of metal and penetrate the main surface insulating film 25 and the interlayer film 26 in the region between the plurality of gate structures 15.

[0162] Multiple source via structures 30 are each formed on multiple body regions 10 and are electrically connected to the multiple body regions 10, multiple source regions 11, and multiple contact regions 12. In this embodiment, the multiple source via structures 30 are formed at intervals in the first direction X in a one-to-one correspondence with respect to the multiple body regions 10, and each extends in a strip shape in the second direction Y.

[0163] Multiple source via structures 30 may be arranged in a one-to-many correspondence with respect to a single corresponding body region 10. In this case, the multiple source via structures 30 may be spaced apart in the second direction Y, following the extending direction of the multiple body regions 10 (gate structures 15).

[0164] Each of the multiple source via structures 30 has a height less than or equal to the thickness of the interlayer film 26 (in this embodiment, less than the thickness of the interlayer film 26). Each of the multiple source via structures 30 has a structural width (first width) less than the width of the multiple body regions 10.

[0165] In this embodiment, the first width is greater than or equal to the thickness of the interlaminar film 26. That is, the source via structure 30 has an aspect ratio that extends laterally in the width direction of the interlaminar film 26. The first width may also be less than the thickness of the interlaminar film 26. That is, the source via structure 30 may have an aspect ratio that extends vertically in the thickness direction Z of the interlaminar film 26.

[0166] The first width may be greater than 0 μm and less than 10 μm. The first width may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and less than 10 μm.

[0167] Each of the multiple source via structures 30 includes a source opening 31 and a source via electrode 32. The source opening 31 forms the wall surface of the source via structure 30 and is partitioned by a first main surface 3, a main surface insulating film 25, and an interlayer film 26.

[0168] Specifically, the source opening 31 has a bottom wall partitioned by the first main surface 3, and side walls partitioned by the main surface insulating film 25 and the interlayer film 26. In this embodiment, the side walls are partitioned by the main surface insulating film 25, the first interlayer film 27, and the second interlayer film 28. The first width corresponds to the opening width of the source opening 31.

[0169] The bottom wall exposes multiple source regions 11 and multiple contact regions 12. In this configuration, the bottom wall is defined by a source recess 33 that is recessed in the thickness direction Z from the height position of the first main surface 3.

[0170] The source recess 33 is formed at a distance from the depth position of the bottom of the multiple source regions 11 and the depth position of the bottom of the multiple contact regions 12 toward the first main surface 3. The source recess 33 is not necessarily required, and a configuration without the source recess 33 may be adopted.

[0171] The source via electrode 32 is embedded in the source opening 31 and is mechanically and electrically connected to the first main surface 3. Specifically, the source via electrode 32 is electrically connected to a plurality of source regions 11 and a plurality of contact regions 12 within the source opening 31. The source via electrode 32 has an electrode surface exposed from the insulating surface of the interlayer film 26. The electrode surface is formed with a gap from the height of the insulating surface of the interlayer film 26 toward the first main surface 3, exposing the insulating surface of the interlayer film 26.

[0172] The source via electrode 32 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The source via electrode 32 may contain a metal film comprising at least one of the following: aluminum (Al)-based metals, titanium (Ti)-based metals, nickel (Ni)-based metals, copper (Cu)-based metals, molybdenum (Mo)-based metals, palladium (Pd)-based metals, silver (Ag)-based metals, tungsten (W)-based metals, and gold (Au)-based metals.

[0173] The source via electrode 32 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The source via electrode 32 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0174] In this embodiment, the source via electrode 32 has a laminated structure including a via base electrode 34 and a via body electrode 35 stacked in this order from the wall side of the source opening 31. The via base electrode 34 and the via body electrode 35 of the source via electrode 32 may be referred to as the "source via base electrode" and the "source via body electrode".

[0175] The via base electrode 34 is formed as a barrier electrode to the chip 2 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films. In this embodiment, the via base electrode 34 has a laminated structure including a first via electrode 34a and a second via electrode 34b. The first via electrode 34a and the second via electrode 34b of the source via electrode 32 may be referred to as the "first source via electrode" and the "second source via electrode".

[0176] The first via electrode 34a consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. In this embodiment, the first via electrode 34a consists of a titanium-based metal film (titanium film).

[0177] The first via electrode 34a coats the wall surface of the source opening 31 in a film-like manner. The first via electrode 34a has a portion that coats the first main surface 3 (source recess 33) in a film-like manner at the bottom wall of the source opening 31, and a portion that coats the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner at the side wall of the source opening 31.

[0178] The first via electrode 34a is electrically connected to multiple source regions 11 and multiple contact regions 12 at the bottom wall of the source opening 31. The first via electrode 34a is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the first main surface 3 on the side wall of the source opening 31, and forms the edge of the electrode surface of the source via electrode 32.

[0179] The first via electrode 34a has a thickness less than the thickness of the interlayer film 26. The thickness of the first via electrode 34a may be greater than 0 nm and 200 nm or less. The thickness of the first via electrode 34a may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, and 150 nm to 200 nm.

[0180] The second via electrode 34b consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second via electrode 34b consists of a different metal film or alloy film than the first via electrode 34a. In this embodiment, the second via electrode 34b consists of a titanium-based metal film (a titanium nitride film as an example of a titanium alloy film).

[0181] The second via electrode 34b coats the wall surface of the source opening 31 in a film-like manner via the first via electrode 34a. The second via electrode 34b has a portion that coats the first main surface 3 (source recess 33) in a film-like manner via the first via electrode 34a at the bottom wall of the source opening 31, and a portion that coats the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner via the first via electrode 34a at the side wall of the source opening 31.

[0182] The second via electrode 34b is electrically connected to a plurality of source regions 11 and a plurality of contact regions 12 via the first via electrode 34a at the bottom wall of the source opening 31. The second via electrode 34b is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the first main surface 3 on the side wall of the source opening 31, and forms the edge of the electrode surface of the source via electrode 32.

[0183] The second via electrode 34b has a thickness less than the thickness of the interlayer film 26. In this embodiment, the thickness of the second via electrode 34b is greater than the thickness of the first via electrode 34a. The thickness of the second via electrode 34b may be less than the thickness of the first via electrode 34a. The thickness of the second via electrode 34b may be greater than 0 nm and 300 nm or less.

[0184] The thickness of the second via electrode 34b may be greater than 0 nm and fall within at least one of the following ranges: 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or more and 300 nm or less.

[0185] The via body electrode 35 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The via body electrode 35 is made of a different conductor than the first via electrode 34a and the second via electrode 34b. In this embodiment, the via body electrode 35 is made of a tungsten-based metal (tungsten or tungsten alloy). Due to its physical properties, the tungsten-based metal can be embedded in the source opening 31 at a relatively high density.

[0186] The via body electrode 35 is embedded in the source opening 31 via a via base electrode 34 as the main body of the source via electrode 32. The via body electrode 35 faces the bottom wall and side wall of the source opening 31 via the via base electrode 34.

[0187] The via body electrode 35 is electrically connected to multiple source regions 11 and multiple contact regions 12 via the via base electrode 34. The via body electrode 35 is formed with a gap from the height of the insulating surface of the interlayer film 26 toward the first main surface 3, and forms the electrode surface of the source via electrode 32.

[0188] The semiconductor device 1A includes one or more (in this embodiment, more than one) conductive gate via structures 40 embedded in the interlayer film 26 in the outer region 9. The number of gate via structures 40 (as determined from a cross-sectional view along the first direction X or the second direction Y) may be between one and 20.

[0189] The number of gate via structures 40 may be a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 15, and 15 to 20. In this embodiment, the semiconductor device 1A includes 3 gate via structures 40.

[0190] In this embodiment, the gate via structures 40 are made of metal and are arranged on the planar wiring 29 at intervals from one another. Multiple gate via structures 40 penetrate the interlayer film 26 and are electrically connected to the planar wiring 29. In this embodiment, multiple gate via structures 40 are formed on the outer edge side of the planar wiring 29 relative to the central part of the planar wiring 29, and are unevenly distributed on the outer edge side of the planar wiring 29 relative to the inner edge of the planar wiring 29.

[0191] In this embodiment, the multiple gate via structures 40 each extend in a strip-like shape following the direction of extension of the planar wiring 29. The multiple gate via structures 40 may be formed at intervals in the direction of extension of the planar wiring 29. In this case, the multiple gate via structures 40 may be formed in a polygonal or circular shape in plan view. The multiple gate via structures 40 may be formed in a square or hexagonal shape in plan view.

[0192] The multiple gate via structures 40 may have portions extending in a first direction X and portions extending in a second direction Y in a plan view. The multiple gate via structures 40 may have corners connecting the portions extending in the first direction X and the portions extending in the second direction Y in an arc shape (for example, a quarter arc shape) in a plan view.

[0193] Each of the multiple gate via structures 40 has a height less than or equal to the thickness of the interlayer film 26 (in this embodiment, less than the thickness of the interlayer film 26). Each of the multiple gate via structures 40 has a structural width (second width) less than the width of the planar wiring 29. The second width may be less than the first width of the source via structure 30. The second width may be greater than the first width.

[0194] In this embodiment, the second width is less than the thickness of the interlaminar film 26. That is, the gate via structure 40 has an aspect ratio that extends vertically in the thickness direction Z of the interlaminar film 26. The second width may be greater than the thickness of the interlaminar film 26. That is, the gate via structure 40 may have an aspect ratio that extends horizontally in the width direction of the interlaminar film 26.

[0195] The second width may be greater than 0 μm and less than or equal to 2 μm. The second width may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.75 μm, 0.75 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.25 μm, 1.25 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 1.75 μm, and 1.75 μm or more and less than or equal to 2 μm.

[0196] The spacing between the multiple gate via structures 40 can take any value within the range of less than the width of the planar wiring 29. The spacing between the gate via structures 40 may be less than the second width. The spacing between the gate via structures 40 may be greater than the second width. The spacing between the gate via structures 40 may be less than the spacing between the source via structures 30. The spacing between the gate via structures 40 may be greater than the spacing between the source via structures 30.

[0197] The spacing of the gate via structures 40 may be greater than 0 μm and less than or equal to 5 μm. The spacing of the gate via structures 40 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to less than or equal to 1 μm, 1 μm to less than or equal to 1.5 μm, 1.5 μm to less than or equal to 2 μm, 2 μm to less than or equal to 2.5 μm, 2.5 μm to less than or equal to 3 μm, 3 μm to less than or equal to 3.5 μm, 3.5 μm to less than or equal to 4 μm, 4 μm to less than or equal to 4.5 μm, and 4.5 μm to less than or equal to 5 μm.

[0198] Each of the gate via structures 40 includes a gate opening 41 and a gate via electrode 42. The gate opening 41 forms the wall surface of the gate via structure 40 and is partitioned by the interlayer film 26 and the wiring surface of the planar wiring 29.

[0199] Specifically, the gate opening 41 has a bottom wall partitioned by the wiring surface of the planar wiring 29 and side walls partitioned by the interlayer membrane 26. In this configuration, the side walls are partitioned by the first interlayer membrane 27 and the second interlayer membrane 28. The second width corresponds to the opening width of the gate opening 41.

[0200] In this configuration, the bottom wall is defined by gate recesses 43 that are recessed in the thickness direction Z from the height position of the wiring surface of the planar wiring 29. The gate recesses 43 are formed at intervals from the depth position of the middle part of the planar wiring 29 toward the wiring surface of the planar wiring 29.

[0201] The gate recess 43 has a depth approximately equal to the depth of the source recess 33. The depth of the gate recess 43 may be greater or less than the depth of the source recess 33. The gate recess 43 does not necessarily need to be formed, and a configuration without a gate recess 43 may be adopted.

[0202] The gate via electrode 42 is embedded in the gate opening 41 and is mechanically and electrically connected to the planar wiring 29. The gate via electrode 42 has an electrode surface exposed from the insulating surface of the interlayer film 26. The electrode surface is formed with a gap from the height of the insulating surface of the interlayer film 26 toward the first main surface 3, exposing the insulating surface of the interlayer film 26.

[0203] The gate via electrode 42 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The gate via electrode 42 may contain a metal film comprising at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0204] The gate via electrode 42 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The gate via electrode 42 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0205] In this embodiment, the gate via electrode 42, like the source via electrode 32, has a laminated structure including a via base electrode 34 and a via body electrode 35 stacked in this order from the wall side of the gate opening 41. The via base electrode 34 and the via body electrode 35 of the gate via electrode 42 may be referred to as the "gate via base electrode" and the "gate via body electrode."

[0206] The via base electrode 34 is formed as a barrier electrode for the planar wiring 29 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films. In this embodiment, the via base electrode 34 has a laminated structure including a first via electrode 34a and a second via electrode 34b, similar to the source via electrode 32. The first via electrode 34a and the second via electrode 34b of the gate via electrode 42 may be referred to as the "first gate via electrode" and the "second gate via electrode".

[0207] The first via electrode 34a covers the wall surface of the gate opening 41 in a film-like manner. The first via electrode 34a has a portion that covers the planar wiring 29 in a film-like manner at the bottom wall (gate recess 43) of the gate opening 41, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner at the side wall of the gate opening 41.

[0208] The first via electrode 34a is electrically connected to the planar wiring 29 at the bottom wall of the gate opening 41. The first via electrode 34a is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the planar wiring 29 on the side wall of the gate opening 41, and forms the edge of the electrode surface of the gate via electrode 42.

[0209] The second via electrode 34b covers the wall surface of the gate opening 41 in a film-like manner via the first via electrode 34a. The second via electrode 34b has a portion that covers the planar wiring 29 in a film-like manner via the first via electrode 34a at the bottom wall of the gate opening 41, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner via the first via electrode 34a at the side wall of the gate opening 41.

[0210] The second via electrode 34b is electrically connected to the planar wiring 29 via the first via electrode 34a at the bottom wall of the gate opening 41. The second via electrode 34b is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the planar wiring 29 on the side wall of the gate opening 41, and forms the edge of the electrode surface of the gate via electrode 42.

[0211] The via body electrode 35 is embedded in the gate opening 41 via the via base electrode 34 as the main body of the gate via electrode 42. The via body electrode 35 faces the bottom wall and side wall of the gate opening 41 via the via base electrode 34. The via body electrode 35 is electrically connected to the planar wiring 29 via the via base electrode 34 and forms the electrode surface of the gate via electrode 42.

[0212] The semiconductor device 1A includes one or more (in this embodiment, more) conductive outer via structures 50 embedded in the interlayer film 26 in the outer region 9. The number of outer via structures 50 (the number as determined from a cross-sectional view along the first direction X or the second direction Y) may be between one and 20.

[0213] The number of outer via structures 50 may be a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 15, and 15 to 20. In this embodiment, semiconductor device 1A includes 3 outer via structures 50. The number of outer via structures 50 is the same as the number of gate via structures 40. The number of outer via structures 50 may be more or less than the number of gate via structures 40.

[0214] In this embodiment, the multiple outer via structures 50 are made of metal. The multiple outer via structures 50 are formed at intervals from the planar wiring 29 toward the periphery of the first main surface 3, and at intervals from the periphery of the first main surface 3 toward the inside of the first main surface 3. The multiple outer via structures 50 are formed at intervals toward the inside of the channel stop region 21.

[0215] Multiple outer via structures 50 are formed with a gap inward from multiple field regions 20 (the innermost field region 20). Multiple outer via structures 50 are formed with a gap inward from the outer edge of the outer well region 18.

[0216] Multiple outer via structures 50 are arranged on the outer contact region 19 with gaps between them. The multiple outer via structures 50 penetrate the main surface insulating film 25 and the interlayer film 26 and are electrically connected to the outer contact region 19.

[0217] In this embodiment, the multiple outer via structures 50 each extend in a strip-like shape following the direction of extension of the outer contact region 19. The multiple outer via structures 50 have a portion extending in a first direction X and a portion extending in a second direction Y.

[0218] In this embodiment, the multiple outer via structures 50 are formed in an ended or endless polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surround the active region 8 (multiple gate structures 15). The multiple outer via structures 50 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0219] Multiple outer via structures 50 may be formed at intervals in the direction of extension of the outer contact region 19. In this case, the multiple outer via structures 50 may be formed in a polygonal or circular shape in plan view. The multiple outer via structures 50 may be formed in a square or hexagonal shape in plan view.

[0220] Each of the multiple outer via structures 50 has a portion located on the first main surface 3 side with respect to the height of the wiring surface of the planar wiring 29, and a portion located on the insulating surface side of the interlayer film 26 with respect to the height of the wiring surface of the planar wiring 29. In other words, each of the multiple outer via structures 50 has a portion facing the planar wiring 29 via a part of the interlayer film 26, and a portion facing the gate via structure 40 via a part of the interlayer film 26, with respect to the horizontal direction.

[0221] Each of the multiple outer via structures 50 has a height less than or equal to the thickness of the interlayer film 26 (in this embodiment, less than the thickness of the interlayer film 26). Each of the multiple outer via structures 50 has a structural width (third width) less than the width of the outer contact region 19.

[0222] The third width may be less than the first width of the source via structure 30. The third width may be greater than the first width. The third width may be approximately equal to the second width of the gate via structure 40. The third width may be greater than or less than the second width.

[0223] In this embodiment, the third width is less than the thickness of the interlaminar film 26. That is, the outer via structure 50 has an aspect ratio that extends vertically in the thickness direction Z of the interlaminar film 26. The third width may be greater than the thickness of the interlaminar film 26. That is, the outer via structure 50 may have an aspect ratio that extends horizontally in the width direction of the interlaminar film 26.

[0224] The third width may be greater than 0 μm and less than or equal to 2 μm. The third width may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.75 μm, 0.75 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.25 μm, 1.25 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 1.75 μm, and 1.75 μm or more and less than or equal to 2 μm.

[0225] The spacing between the multiple outer via structures 50 can take any value within the range less than the width of the outer contact region 19. The spacing between the outer via structures 50 may be less than the third width. The spacing between the outer via structures 50 may be greater than the third width.

[0226] The spacing of the outer via structures 50 may be less than the first width of the source via structure 30. The spacing of the outer via structures 50 may be greater than the first width. The spacing of the outer via structures 50 may be less than the second width of the gate via structure 40. The spacing of the outer via structures 50 may be greater than the second width.

[0227] The spacing of the outer via structures 50 may be less than the spacing of the source via structures 30. The spacing of the outer via structures 50 may be greater than the spacing of the source via structures 30. The spacing of the outer via structures 50 may be approximately equal to the spacing of the gate via structures 40. The spacing of the outer via structures 50 may be greater or less than the spacing of the gate via structures 40.

[0228] The spacing of the outer via structures 50 may be greater than 0 μm and less than or equal to 2 μm. The spacing of the outer via structures 50 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.75 μm, 0.75 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.25 μm, 1.25 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 1.75 μm, and 1.75 μm or more and less than or equal to 2 μm.

[0229] Each of the multiple outer via structures 50 includes an outer opening 51 and an outer via electrode 52. The outer opening 51 forms the wall surface of the outer via structure 50 and is partitioned by the main surface insulating film 25, the interlayer film 26, and the first main surface 3.

[0230] Specifically, the outer opening 51 has a bottom wall partitioned by the first main surface 3, and side walls partitioned by the main surface insulating film 25 and the interlayer film 26. In this embodiment, the side walls are partitioned by the main surface insulating film 25, the first interlayer film 27, and the second interlayer film 28. The third width corresponds to the opening width of the outer opening 51.

[0231] The bottom wall exposes the outer contact region 19. In this configuration, the bottom wall is defined by an outer recess 53 that is recessed in the thickness direction Z from the height position of the first main surface 3. The outer recess 53 is formed with a gap from the depth position of the bottom of the outer well region 18 toward the first main surface 3. The outer recess 53 is formed with a gap from the depth position of the middle part of the outer well region 18 toward the first main surface 3.

[0232] The outer recess 53 is formed with a gap from the bottom depth position of the outer contact region 19 toward the first main surface 3. The outer recess 53 is formed with a gap from the middle depth position of the outer contact region 19 toward the first main surface 3. The outer recess 53 may have a depth approximately equal to the depth of the source recess 33. The depth of the outer recess 53 may be greater or less than the depth of the source recess 33.

[0233] The outer recess 53 may have a depth approximately equal to the depth of the gate recess 43. The depth of the outer recess 53 may be greater or less than the depth of the gate recess 43. The outer recess 53 is not necessarily required to be formed, and a configuration without the outer recess 53 may be adopted.

[0234] The outer via electrode 52 is embedded in the outer opening 51 and is mechanically and electrically connected to the outer contact region 19. The outer via electrode 52 has an electrode surface exposed from the insulating surface of the interlayer film 26. The electrode surface is formed with a gap from the height of the insulating surface of the interlayer film 26 toward the first main surface 3, exposing the insulating surface of the interlayer film 26.

[0235] The outer via electrode 52 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The outer via electrode 52 may contain a metal film comprising at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0236] The outer via electrode 52 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The outer via electrode 52 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0237] In this embodiment, the outer via electrode 52, like the source via electrode 32, has a laminated structure including a via base electrode 34 and a via body electrode 35 stacked in this order from the wall side of the outer opening 51. The via base electrode 34 and the via body electrode 35 of the outer via electrode 52 may be referred to as the "outer via base electrode" and the "outer via body electrode."

[0238] The via base electrode 34 is formed as a barrier electrode to the tip 2 and has a single-layer structure consisting of a single metal film or a multilayer structure consisting of multiple metal films. In this embodiment, the via base electrode 34 has a multilayer structure including a first via electrode 34a and a second via electrode 34b, similar to the source via electrode 32. The first via electrode 34a and the second via electrode 34b of the outer via electrode 52 may be referred to as the "first outer via electrode" and the "second outer via electrode."

[0239] The first via electrode 34a covers the wall surface of the outer opening 51 in a film-like manner. The first via electrode 34a has a portion that covers the outer contact region 19 in a film-like manner at the bottom wall (outer recess 53) of the outer opening 51, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner at the side wall of the outer opening 51.

[0240] The first via electrode 34a is electrically connected to the outer contact region 19 at the bottom wall of the outer opening 51. The first via electrode 34a is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the outer contact region 19 on the side wall of the outer opening 51, and forms the edge of the electrode surface of the outer via electrode 52.

[0241] The second via electrode 34b covers the wall surface of the outer opening 51 in a film-like manner via the first via electrode 34a. The second via electrode 34b has a portion that covers the outer contact region 19 in a film-like manner via the first via electrode 34a at the bottom wall of the outer opening 51, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner via the first via electrode 34a at the side wall of the outer opening 51.

[0242] The second via electrode 34b is electrically connected to the outer contact region 19 via the first via electrode 34a at the bottom wall of the outer opening 51. The second via electrode 34b is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the outer contact region 19 at the side wall of the outer opening 51, and forms the edge of the electrode surface of the outer via electrode 52.

[0243] The via body electrode 35 is embedded in the outer opening 51 via a via base electrode 34 as the main body of the outer via electrode 52. The via body electrode 35 faces the bottom wall and side wall of the outer opening 51 via the via base electrode 34. The via body electrode 35 is electrically connected to the outer contact region 19 via the via base electrode 34 and forms the electrode surface of the outer via electrode 52.

[0244] The semiconductor device 1A includes one or more (in this embodiment, more) shield structures 60 embedded in the interlayer film 26 in the outer region 9. In this embodiment, the shield structures 60 are conductive (specifically metallic).

[0245] The number of shield structures 60 (as determined from a cross-sectional view along the first direction X or the second direction Y) may be between 1 and 20. The number of shield structures 60 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20.

[0246] In this embodiment, semiconductor device 1A includes three shield structures 60. That is, the number of shield structures 60 is the same as the number of gate via structures 40. The number of shield structures 60 may be more or less than the number of gate via structures 40. The number of shield structures 60 is the same as the number of outer via structures 50. The number of shield structures 60 may be more or less than the number of outer via structures 50.

[0247] In this embodiment, the multiple shield structures 60 are formed in an electrically floating state. A source potential may be applied to the multiple shield structures 60. The multiple shield structures 60 are formed at a distance from the planar wiring 29 (multiple gate via structures 40) toward the periphery of the first main surface 3, and at a distance from the periphery of the first main surface 3 toward the interior of the first main surface 3.

[0248] Multiple shield structures 60 are formed with a gap between them and the peripheral edge of the multiple outer via structures 50. Multiple shield structures 60 are formed with a gap between them and the peripheral edge of the outer contact region 19. Multiple shield structures 60 are formed with a gap between them and the peripheral edge of the outer well region 18. Multiple shield structures 60 are formed with a gap between them and the peripheral edge of the multiple field regions 20 (the outermost field region 20).

[0249] In this embodiment, the multiple shield structures 60 are formed at intervals from each other, extending from the inner edge side of the channel stop region 21 to the peripheral edge side of the first main surface 3. The multiple shield structures 60 penetrate the main surface insulating film 25 and the interlayer film 26 and are electrically connected to the channel stop region 21. In this embodiment, the multiple shield structures 60 are formed in an electrically floating state together with the channel stop region 21.

[0250] In this configuration, the multiple shield structures 60 are formed on the inner edge side of the channel stop region 21 relative to the central part of the channel stop region 21, and are unevenly distributed on the inner edge side of the channel stop region 21 relative to the periphery of the first main surface 3.

[0251] In this embodiment, the multiple shield structures 60 each extend in a strip-like shape, following the periphery of the first main surface 3 (the inner edge of the channel stop region 21). The multiple shield structures 60 have portions extending in a first direction X and portions extending in a second direction Y.

[0252] In this embodiment, the multiple shield structures 60 are formed in the shape of an ended or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surround the active region 8 (multiple gate structures 15). The multiple shield structures 60 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0253] The multiple shield structures 60 may be formed at intervals in the extending direction of the channel stop region 21. In other words, the multiple shield structures 60 may be formed at intervals along an annular virtual line surrounding the inner part of the first main surface 3. In this case, the multiple shield structures 60 may be formed in the shape of a strip, polygon, circle, etc., in a plan view. The multiple shield structures 60 may be formed in the shape of a square or hexagon in a plan view.

[0254] The multiple shield structures 60 face the outer via structure 50 in the horizontal direction via a portion of the interlayer film 26. The multiple shield structures 60 have a portion located on the first main surface 3 side with respect to the height of the wiring surface of the planar wiring 29, and a portion located on the insulating surface side of the interlayer film 26 with respect to the height of the wiring surface of the planar wiring 29.

[0255] In other words, the multiple shield structures 60 have portions that face the planar wiring 29 via a portion of the interlayer film 26 in the horizontal direction, and portions that face the gate via structure 40 via a portion of the interlayer film 26.

[0256] The shield structure 60 (in this embodiment, a group of multiple shield structures 60) horizontally divides the interlayer membrane 26 into an inner region 26a (first region) on the inner side of the first main surface 3 (chip 2) and a peripheral region 26b (second region) on the peripheral side of the first main surface 3 (chip 2) in both cross-sectional and plan views. Specifically, the shield structure 60 (in this embodiment, a group of multiple shield structures 60) penetrates the interlayer membrane 26 and horizontally divides the interlayer membrane 26 into an inner region 26a and a peripheral region 26b.

[0257] The multiple shielding structures 60 suppress the transmission of external force from the peripheral region 26b to the inner region 26a when an external force is applied to the periphery of the interlayer film 26 (the periphery of the chip 2). In other words, the multiple shielding structures 60 suppress cracks in the chip 2 and the interlayer film 26 caused by external force from reaching the active region 8. This suppresses electrical fluctuations in the transistor structure T (device structure) caused by cracks.

[0258] The multiple shielding structures 60 are also effective in protecting structures inside and outside the chip 2 from external forces (for example, external forces caused by dicing blades, etc.) that occur when cutting multiple semiconductor devices 1A from a single wafer during the manufacturing process of the semiconductor device 1A.

[0259] The multiple shielding structures 60 suppress the intrusion of moisture (humidity) from the outside when the semiconductor device 1A is used in a high-humidity environment. This suppresses oxidation of the chip 2 and metal structures caused by moisture. As a result, electrical fluctuations of the transistor structure T (device structure) caused by moisture are suppressed.

[0260] Each of the multiple shield structures 60 has a height less than or equal to the thickness of the interlayer film 26 (in this embodiment, less than the thickness of the interlayer film 26). Each of the multiple shield structures 60 has a structural width (fourth width) less than the width of the channel stop region 21.

[0261] The fourth width may be less than the first width of the source via structure 30. The fourth width may be greater than the first width. The fourth width may be approximately equal to the second width of the gate via structure 40. The fourth width may be greater than or less than the second width. The fourth width may be approximately equal to the third width of the outer via structure 50. The fourth width may be greater than or less than the third width.

[0262] In this embodiment, the fourth width is less than the thickness of the interlayer film 26. That is, the shield structure 60 has an aspect ratio that extends vertically in the thickness direction Z of the interlayer film 26. The fourth width may be greater than the thickness of the interlayer film 26. That is, the shield structure 60 may have an aspect ratio that extends horizontally in the width direction of the interlayer film 26.

[0263] The fourth width may be greater than 0 μm and less than or equal to 2 μm. The fourth width may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.75 μm, 0.75 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.25 μm, 1.25 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 1.75 μm, and 1.75 μm or more and less than or equal to 2 μm.

[0264] The spacing between the multiple shield structures 60 can take any value within a range less than the width of the channel stop region 21. The spacing between the shield structures 60 may be less than the fourth width. The spacing between the shield structures 60 may be greater than the fourth width. The spacing between the shield structures 60 may be less than the first width of the source via structure 30. The spacing between the shield structures 60 may be greater than the first width.

[0265] The spacing of the shield structures 60 may be less than the second width of the gate via structures 40. The spacing of the shield structures 60 may be greater than the second width. The spacing of the shield structures 60 may be less than the third width of the outer via structures 50. The spacing of the shield structures 60 may be greater than the third width.

[0266] The spacing between the multiple shield structures 60 may be less than the spacing between the source via structures 30. The spacing between the shield structures 60 may be greater than the spacing between the source via structures 30. The spacing between the shield structures 60 may be approximately equal to the spacing between the gate via structures 40. The spacing between the shield structures 60 may be greater or less than the spacing between the gate via structures 40.

[0267] The spacing of the shield structure 60 may be approximately equal to that of the outer via structure 50. The spacing of the shield structure 60 may be greater than or less than the spacing of the outer via structure 50. The spacing of the shield structure 60 may be greater than 0 μm and less than or equal to 2 μm.

[0268] The spacing of the shield structure 60 may be greater than 0 μm and fall within at least one of the following ranges: 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0269] Each of the multiple shield structures 60 includes a shield opening 61 and a conductive (metallic in this embodiment) shield electrode 62 as an example of a shielding member. The shield opening 61 forms the wall surface of the shield structure 60 and is partitioned by the interlayer film 26 and the first main surface 3.

[0270] Specifically, the shield opening 61 has a bottom wall partitioned by the first main surface 3, and side walls partitioned by the main surface insulating film 25 and the interlayer film 26. In this embodiment, the side walls are partitioned by the main surface insulating film 25, the first interlayer film 27, and the second interlayer film 28. The fourth width corresponds to the opening width of the shield opening 61.

[0271] The bottom wall exposes the channel stop region 21. In this configuration, the bottom wall is demarcated by a shield recess 63 that is recessed in the thickness direction Z from the height position of the first main surface 3. The shield recess 63 is formed with a gap from the depth position of the bottom of the channel stop region 21 toward the first main surface 3. The shield recess 63 is formed with a gap from the depth position of the middle part of the channel stop region 21 toward the first main surface 3.

[0272] The shield recess 63 may have a depth approximately equal to the depth of the source recess 33. The depth of the shield recess 63 may be greater or less than the depth of the source recess 33. The shield recess 63 may have a depth approximately equal to the depth of the gate recess 43. The depth of the shield recess 63 may be greater or less than the depth of the gate recess 43.

[0273] The shield recess 63 may have a depth approximately equal to the depth of the outer recess 53. The depth of the shield recess 63 may be greater or less than the depth of the outer recess 53. The shield recess 63 is not necessarily required to be formed, and a configuration without the shield recess 63 may be adopted.

[0274] The shield openings 61 (or in this embodiment, a group of multiple shield openings 61) horizontally divide the interlayer membrane 26 into an inner region 26a on the inner side of the first main surface 3 (chip 2) and a peripheral region 26b on the peripheral side of the first main surface 3 (chip 2) in both cross-sectional and plan views. Specifically, the shield openings 61 (or in this embodiment, a group of multiple shield openings 61) penetrate the interlayer membrane 26 and horizontally divide the interlayer membrane 26 into an inner region 26a and a peripheral region 26b.

[0275] In this configuration, the multiple shield openings 61 reliably penetrate the interlayer film 26 through the multiple shield recesses 63, appropriately dividing the interlayer film 26 into an inner region 26a and a peripheral region 26b. The multiple shield openings 61 function as stoppers (crack endpoints) that prevent cracks in the interlayer film 26 (cracks in the chip 2) from reaching the active region 8 when an external force is applied to the periphery of the interlayer film 26 (periphery of the chip 2).

[0276] The shield electrode 62 is electrically suspended and embedded in the shield opening 61, and is mechanically and electrically connected to the channel stop region 21. The shield electrode 62 has an electrode surface exposed from the insulating surface of the interlayer film 26. The electrode surface is formed with a gap from the height of the insulating surface of the interlayer film 26 toward the first main surface 3, exposing the insulating surface of the interlayer film 26.

[0277] The multiple shield electrodes 62 (shielding members) suppress the intrusion of moisture (humidity) into the multiple shield openings 61 from the outside when the semiconductor device 1A is used in a high-humidity environment. In other words, the multiple shield electrodes 62 (shielding members) suppress the intrusion of moisture (humidity) into other areas through the multiple shield openings 61.

[0278] This suppresses oxidation of the chip 2 and metal structures caused by moisture. The multiple electrically floating shield electrodes 62 appropriately reduce the electrical influence on the transistor structure T (device structure). Therefore, even if oxides are formed on the shield electrodes 62, the electrical influence caused by these oxides is appropriately reduced.

[0279] The shield electrode 62 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The shield electrode 62 may also contain a metal film comprising at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0280] The shield electrode 62 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The shield electrode 62 may also include an alloy film (metal film) containing at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0281] In this embodiment, the shield electrode 62 has a laminated structure including a shield base electrode 64 and a shield body electrode 65, which are stacked in this order from the wall side of the shield opening 61. The shield base electrode 64 is formed as a barrier electrode for the chip 2 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0282] In this embodiment, the shield base electrode 64 has a laminated structure including a first shield electrode 64a and a second shield electrode 64b. The first shield electrode 64a consists of a metal film containing any one of the aforementioned metals, or an alloy film containing any one of the aforementioned alloys.

[0283] In this embodiment, the first shield electrode 64a is made of a titanium-based metal film (titanium film). In other words, the first shield electrode 64a is formed of the same metal material as the first via electrode 34a, such as the source via structure 30.

[0284] The first shield electrode 64a covers the wall surface of the shield opening 61 in a film-like manner. The first shield electrode 64a has a portion that covers the channel stop region 21 in a film-like manner at the bottom wall (shield recess 63) of the shield opening 61, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner at the side wall of the shield opening 61.

[0285] The first shield electrode 64a is electrically connected to the channel stop region 21 at the bottom wall of the shield opening 61. The first shield electrode 64a is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the channel stop region 21 on the side wall of the shield opening 61, and forms the edge of the electrode surface of the shield electrode 62.

[0286] The first shield electrode 64a has a thickness less than the thickness of the interlayer film 26. In this embodiment, the thickness of the first shield electrode 64a is approximately equal to the thickness of the first via electrode 34a. The thickness of the first shield electrode 64a may be greater or less than the thickness of the first via electrode 34a.

[0287] The thickness of the first shield electrode 64a may be greater than 0 nm and 200 nm or less. The thickness of the first via electrode 34a may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, and 150 nm to 200 nm.

[0288] The second shield electrode 64b consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second shield electrode 64b consists of a different metal film or alloy film than the first shield electrode 64a.

[0289] In this configuration, the second shield electrode 64b is made of a titanium-based metal film (a titanium nitride film as an example of a titanium alloy film). In other words, the second shield electrode 64b is made of a different metal material than the first via electrode 34a, such as the source via structure 30, and is made of the same metal material as the second via electrode 34b, such as the source via structure 30.

[0290] The second shield electrode 64b covers the wall surface of the shield opening 61 in a film-like manner via the first shield electrode 64a. The second shield electrode 64b has a portion that covers the channel stop region 21 in a film-like manner via the first shield electrode 64a at the bottom wall of the shield opening 61, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner via the first shield electrode 64a at the side wall of the shield opening 61.

[0291] The second shield electrode 64b is electrically connected to the channel stop region 21 via the first shield electrode 64a at the bottom wall of the shield opening 61. The second shield electrode 64b is formed at a distance from the height of the insulating surface of the interlayer film 26 toward the channel stop region 21 on the side wall of the shield opening 61, and forms the edge of the electrode surface of the shield electrode 62.

[0292] The second shield electrode 64b has a thickness less than the thickness of the interlayer film 26. In this embodiment, the thickness of the second shield electrode 64b is greater than the thickness of the first shield electrode 64a. The thickness of the second shield electrode 64b may be less than the thickness of the first shield electrode 64a.

[0293] The thickness of the second shield electrode 64b is greater than the thickness of the first via electrode 34a. The thickness of the second shield electrode 64b may be less than the thickness of the first via electrode 34a. The thickness of the second shield electrode 64b is approximately equal to the thickness of the second via electrode 34b. The thickness of the second shield electrode 64b may be greater than or less than the thickness of the second via electrode 34b.

[0294] The thickness of the second shield electrode 64b may be greater than 0 nm and 300 nm or less. The thickness of the second shield electrode 64b may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0295] The shield body electrode 65 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The shield body electrode 65 is made of a different metal material than the metal material of the first shield electrode 64a and the metal material of the second shield electrode 64b.

[0296] In this configuration, the shield body electrode 65 is made of a tungsten-based metal (tungsten or tungsten alloy). In other words, the shield body electrode 65 is made of a different metal material than the metal material of the first via electrode 34a and the second via electrode 34b of the source via structure 30, and is made of the same metal material as the via body electrode 35 of the source via structure 30.

[0297] The shield body electrode 65 is embedded in the shield opening 61 via the shield base electrode 64 as the main body portion of the shield electrode 62. The shield body electrode 65 faces the bottom wall and side wall of the shield opening 61 via the shield base electrode 64. The shield body electrode 65 is electrically connected to the channel stop region 21 via the shield base electrode 64 and forms the electrode surface of the shield electrode 62.

[0298] The shield body electrode 65, which contains a tungsten-based metal, can be embedded in the shield opening 61 at a relatively high density due to the physical properties of the tungsten-based metal. This enhances the airtightness of the shield opening 61 and effectively suppresses the intrusion of moisture into the shield opening 61.

[0299] The semiconductor device 1A includes a source electrode 70 disposed in the inner portion (active region 8) of the first main surface 3. The source electrode 70 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," "source pad (electrode)," etc. The source electrode 70 is made of metal and is disposed in a film-like manner on the interlayer film 26.

[0300] In this embodiment, the source electrode 70 has a first pad portion 70a, a second pad portion 70b, and a third pad portion 70c. The first pad portion 70a has a relatively large surface area and forms the main body of the source electrode 70. In this embodiment, the first pad portion 70a is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the first main surface 3 in a plan view, and is offset towards the second side surface 5B side relative to the central part of the first main surface 3.

[0301] The second pad portion 70b has a flat area less than that of the first pad portion 70a, and extends in a strip-like (square-shaped) manner from one end of the first pad portion 70a in the second direction Y (the end on the first side surface 5A side) toward the fourth side surface 5D.

[0302] The third pad portion 70c has a flat area less than the flat area of ​​the first pad portion 70a, extends in a strip shape (square shape) from the other end of the first pad portion 70a in the second direction Y (the end on the third side surface 5C side) toward the fourth side surface 5D, and faces the second pad portion 70b in the second direction Y. The flat area of ​​the third pad portion 70c may be approximately equal to the flat area of ​​the second pad portion 70b. The flat area of ​​the third pad portion 70c may be larger or smaller than the flat area of ​​the second pad portion 70b.

[0303] Either the second pad portion 70b or the third pad portion 70c, or both, may be used as terminal portions for current monitoring. The source electrode 70 may have only one of the second pad portion 70b or the third pad portion 70c. The source electrode 70 may consist only of the first pad portion 70a and may not have both the second pad portion 70b and the third pad portion 70c.

[0304] The source electrode 70 is drawn out in a film-like manner from above the interlayer film 26 onto a plurality of source via structures 30, and is mechanically and electrically connected to the plurality of source via structures 30. The source electrode 70 forms a connection boundary with the plurality of source via structures 30 and is electrically connected to a plurality of source regions 11 and a plurality of contact regions 12 via the plurality of source via structures 30.

[0305] Specifically, in this configuration, the source electrode 70 enters the multiple source openings 31 from above the interlayer film 26 and coats the multiple source via electrodes 32 in a film-like manner within the multiple source openings 31. The source electrode 70 forms connection boundaries with the electrode surfaces of the multiple source via electrodes 32 within the multiple source openings 31 and is electrically connected to the multiple source regions 11 and the multiple contact regions 12 via the multiple source via electrodes 32.

[0306] The source electrode 70 is drawn out from the active region 8 to the outer region 9 and has a peripheral portion that faces the ends of the multiple gate structures 15 via the interlayer film 26. The peripheral portion of the source electrode 70 is formed with a gap between it and the multiple shield structures 60 (the innermost shield structure 60) on the inward side (active region 8) of the first main surface 3. The peripheral portion of the source electrode 70 is formed with a gap between it and the channel stop region 21.

[0307] The peripheral edge of the source electrode 70 is formed with a gap inward from multiple field regions 20 (the innermost field region 20). The peripheral edge of the source electrode 70 is formed with a gap inward from the outer edge of the outer well region 18. The peripheral edge of the source electrode 70 is formed with a gap inward from multiple outer via structures 50.

[0308] The peripheral edge of the source electrode 70 is formed with a gap inward from the outer edge of the planar wiring 29. The peripheral edge of the source electrode 70 is formed with a gap inward from the multiple gate via structures 40. In this configuration, the peripheral edge of the source electrode 70 is drawn outward from the inner edge of the planar wiring 29 and faces the planar wiring 29 via the interlayer film 26.

[0309] In this configuration, the peripheral edge of the source electrode 70 faces the outer well region 18 in the thickness direction Z. In this configuration, the peripheral edge of the source electrode 70 is formed at a distance inward from the inner edge of the outer contact region 19 and does not face the outer contact region 19 in the thickness direction Z. The peripheral edge of the source electrode 70 may face the outer contact region 19 in the thickness direction Z.

[0310] The source electrode 70 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The source electrode 70 may include a metal film comprising at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0311] The source electrode 70 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The source electrode 70 may also include an alloy film (metal film) containing at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0312] In this embodiment, the source electrode 70 has a single-layer structure consisting of a main electrode 71. The main electrode 71 may contain a different conductor than the source via structure 30. The main electrode 71 may contain a different conductor than either or both of the via base electrode 34 and the via main electrode 35. The main electrode 71 may contain a different conductor than either or both of the first via electrode 34a and the second via electrode 34b.

[0313] The main electrode 71 may contain a different conductor than the shield structure 60. The main electrode 71 may contain a different conductor than either or both of the shield base electrode 64 and the shield main electrode 65. The main electrode 71 may contain a different conductor than either or both of the first shield electrode 64a and the second shield electrode 64b.

[0314] In this embodiment, the main electrode 71 includes a conductor different from the first shield electrode 64a, the second shield electrode 64b, and the shield main electrode 65. In this embodiment, the main electrode 71 has a single-layer structure made of an aluminum-based metal (aluminum or an aluminum alloy). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0315] The source electrode 70 (main electrode 71) has a thickness greater than the thickness of the via base electrode 34 (the total thickness of the first via electrode 34a and the second via electrode 34b). The source electrode 70 (main electrode 71) has a thickness greater than the thickness of the shield base electrode 64 (the total thickness of the first shield electrode 64a and the second shield electrode 64b).

[0316] In this configuration, the thickness of the source electrode 70 (main electrode 71) is greater than the thickness of the interlayer film 26. The thickness of the source electrode 70 (main electrode 71) may be less than the thickness of the interlayer film 26. The thickness of the source electrode 70 (main electrode 71) may be greater than 0 μm and 5 μm or less.

[0317] The thickness of the main electrode 71 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0318] The semiconductor device 1A includes source wiring 72 arranged on the peripheral edge (outer region 9) of the first main surface 3. The source wiring 72 may also be called a "source electrode," "source finger (electrode)," etc. The source wiring 72 is made of metal and is drawn out in a film-like manner from the source electrode 70 onto the interlayer film 26. The source wiring 72 transmits the source potential applied to the source electrode 70 to other regions.

[0319] The source wiring 72 is routed from the source electrode 70 to the area between the periphery of the first main surface 3 and the source electrode 70. In this embodiment, the source wiring 72 is drawn out from the side of the first pad portion 70a on the second side surface 5B side onto the plurality of outer via structures 50 and extends in a strip shape following the direction of extension of the plurality of outer via structures 50. In a plan view, the source wiring 72 has a portion that extends in a first direction X and a portion that extends in a second direction Y.

[0320] In this embodiment, the source wiring 72 is formed as an ended or endless polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (source electrode 70). The source wiring 72 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape).

[0321] The source wiring 72 is mechanically and electrically connected to a plurality of outer via structures 50, forming connection boundaries with the plurality of outer via structures 50. The source wiring 72 is electrically connected to the outer contact region 19 via the plurality of outer via structures 50.

[0322] Specifically, in this configuration, the source wiring 72 enters the multiple outer openings 51 from above the interlayer film 26 and coats the multiple outer via electrodes 52 in a film-like manner within the multiple outer openings 51. The source wiring 72 forms connection boundaries with the electrode surfaces of the multiple outer via electrodes 52 within the multiple outer openings 51 and is electrically connected to the outer contact region 19 via the multiple outer via electrodes 52.

[0323] The source wiring 72 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source wiring 72 is formed at intervals from a plurality of gate structures 15 on the peripheral side of the first main surface 3 and faces the outer well region 18 in the thickness direction Z.

[0324] In this configuration, the inner edge of the source wiring 72 is located on the inward side of the first main surface 3 than the inner edge of the outer contact region 19, and does not face the outer contact region 19 in the thickness direction Z. The inner edge of the source wiring 72 may face the outer contact region 19 in the thickness direction Z.

[0325] In this configuration, the inner edge of the source wiring 72 is drawn out onto the planar wiring 29 and faces the planar wiring 29 via the interlayer film 26. The inner edge of the source wiring 72 may be formed at an outward distance from the outer edge of the planar wiring 29.

[0326] The outer edge of the source wiring 72 is formed at a distance from the multiple shield structures 60 toward the inward side (active region 8) of the first main surface 3, and extends substantially parallel to the inner edge of the source wiring 72. The outer edge of the source wiring 72 is formed at a distance inward from the channel stop region 21.

[0327] The outer edge of the source wiring 72 is formed with a gap inward from the multiple field regions 20 (the innermost field region 20). This prevents the source wiring 72 from shielding the electric field dispersion path, and allows the electric field (electric field lines) to be appropriately dispersed by the multiple field regions 20.

[0328] The outer edge of the source wiring 72 is formed with a gap inward from the outer edge of the outer well region 18. The peripheral edge of the source electrode 70 is formed with a gap inward from the multiple outer via structures 50.

[0329] In this configuration, the outer edge of the source wiring 72 is located above the outer well region 18. The outer edge of the source wiring 72 is formed with a gap between the outer edge of the outer contact region 19 and the outer edge of the outer well region 18, and does not face the outer contact region 19 in the thickness direction Z.

[0330] The outer edge of the source wiring 72 may face the outer contact region 19 in the thickness direction Z. The outer edge of the source wiring 72 may be formed with a gap from the outer edge of the outer well region 18 toward the periphery of the first main surface 3, and may face the second semiconductor layer 7 in the thickness direction Z.

[0331] The source wiring 72, like the source electrode 70, may have a single-layer structure including a single metal film, or a laminated structure including multiple metal films. In this embodiment, the source wiring 72, like the source electrode 70, has a single-layer structure consisting of the main electrode 71.

[0332] The semiconductor device 1A includes a gate electrode 73 disposed on the first main surface 3. The gate electrode 73 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," or "gate pad (electrode)." The gate electrode 73 is made of metal and is disposed on the interlayer film 26 at a distance from the source electrode 70 and source wiring 72.

[0333] The gate electrode 73 is positioned in the region on the fourth side surface 5D side relative to the first pad portion 70a, and faces the central portion of the fourth side surface 5D and the first pad portion 70a in the second direction Y. The gate electrode 73 is interposed in the region between the second pad portion 70b and the third pad portion 70c, and faces both the second pad portion 70b and the third pad portion 70c in the second direction Y.

[0334] The gate electrode 73 is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 73 has a planar area less than the planar area of ​​the source electrode 70. The planar area of ​​the gate electrode 73 may be less than the planar area of ​​the first pad portion 70a. The planar area of ​​the gate electrode 73 may be larger or smaller than the planar area of ​​the second pad portion 70b (third pad portion 70c).

[0335] The gate electrode 73 is positioned at a distance from the multiple shield structures 60 (the innermost shield structure 60) inward from the first main surface 3. The gate electrode 73 is positioned at a distance from the channel stop region 21 inward from the channel stop region 21. The gate electrode 73 is positioned at a distance from the multiple field regions 20 (the innermost field region 20) inward from the field region 20. The gate electrode 73 is positioned at a distance from the outer contact region 19 inward from the outer contact region 19.

[0336] In this embodiment, the gate electrode 73 is positioned on the outer well region 18 and faces the outer well region 18 in the thickness direction Z. In this embodiment, the gate electrode 73 has a portion that covers the planar wiring 29 via the interlayer film 26. In this embodiment, the gate electrode 73 does not have a direct electrical connection to the planar wiring 29.

[0337] The gate electrode 73 may be electrically connected to a planar wiring 29 via one or more gate via electrodes 42, and may be electrically connected to a plurality of gate structures 15 via the planar wiring 29. The gate electrode 73 does not necessarily have to cover the planar wiring 29, and some or all of the planar wiring 29 may be removed from the area directly beneath the gate electrode 73.

[0338] The gate electrode 73 may have portions facing the multiple gate structures 15 in the thickness direction Z. The gate electrode 73 may be formed at a distance from the multiple gate structures 15 and may not face the multiple gate structures 15 in the thickness direction Z.

[0339] The gate electrode 73 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The gate electrode 73 may include a metal film comprising at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0340] The gate electrode 73 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The gate electrode 73 may also include an alloy film (metal film) containing at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0341] In this configuration, the gate electrode 73, like the source electrode 70, has a single-layer structure consisting of a main electrode 71. The main electrode 71 of the gate electrode 73 may also be called the "gate main electrode".

[0342] The semiconductor device 1A includes gate wiring 74 arranged on the peripheral edge (outer region 9) of the first main surface 3. The gate wiring 74 may also be called a "gate electrode," "gate finger (electrode)," etc. The gate wiring 74 is made of metal and is drawn out in a film-like manner from the gate electrode 73 onto the interlayer film 26. The gate wiring 74 transmits the gate potential applied to the gate electrode 73 to other regions.

[0343] The gate wiring 74 is routed from the gate electrode 73 to the region between the periphery of the first main surface 3 and the source electrode 70. The gate wiring 74 is drawn over a plurality of gate via structures 40 in the region between the source electrode 70 and the source wiring 72, and extends in a strip shape following the direction of extension of the plurality of gate via structures 40. In a plan view, the gate wiring 74 has a portion that extends in a first direction X and a portion that extends in a second direction Y.

[0344] In this embodiment, the gate wiring 74 is formed as an ended polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (source electrode 70). The gate wiring 74 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape).

[0345] The gate wiring 74 is mechanically and electrically connected to a plurality of gate via structures 40, forming connection boundaries with the plurality of gate via structures 40. The gate wiring 74 is electrically connected to the planar wiring 29 via the plurality of gate via structures 40.

[0346] Specifically, the gate wiring 74 enters a plurality of gate openings 41 from above the interlayer film 26 and coats a plurality of gate via electrodes 42 in a film-like manner within the plurality of gate openings 41. The gate wiring 74 forms connection boundaries with the electrode surfaces of the plurality of gate via electrodes 42 within the plurality of gate openings 41 and is electrically connected to the planar wiring 29 via the plurality of gate via electrodes 42.

[0347] The gate wiring 74 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the gate wiring 74 is spaced apart from the multiple gate structures 15 on the peripheral side. The inner edge of the gate wiring 74 is positioned on the planar wiring 29 and faces the planar wiring 29 in the thickness direction Z. The inner edge of the gate wiring 74 faces the peripheral edge of the source electrode 70 in the horizontal direction on the planar wiring 29.

[0348] The inner edge of the gate wiring 74 faces the outer well region 18 in the thickness direction Z. The inner edge of the gate wiring 74 is located inward from the inner edge of the outer contact region 19 and does not face the outer contact region 19. The inner edge of the gate wiring 74 may face the outer contact region 19 in the thickness direction Z.

[0349] The outer edge of the gate wiring 74 is formed at a distance inward from the first main surface 3 from the multiple shield structures 60 (the innermost shield structure 60) and extends substantially parallel to the inner edge of the gate wiring 74. The outer edge of the gate wiring 74 is formed at a distance inward from the channel stop region 21.

[0350] The outer edge of the gate wiring 74 is formed with a gap inward from the multiple field regions 20 (the innermost field region 20). This prevents the electric field dispersion path from being shielded by the gate wiring 74, and allows the electric field (electric field lines) to be appropriately dispersed by the multiple field regions 20.

[0351] In this configuration, the outer edge of the gate wiring 74 is formed at a distance inward from the outer edge of the outer well region 18 and faces the outer well region 18 in the thickness direction Z. The outer edge of the gate wiring 74 is formed at a distance inward from a plurality of outer via structures 50 (the innermost outer via structure 50).

[0352] In this configuration, the outer edge of the gate wiring 74 is positioned on the planar wiring 29 and faces the planar wiring 29 in the thickness direction Z. The outer edge of the gate wiring 74 faces the inner edge of the source wiring 72 in the horizontal direction on the planar wiring 29.

[0353] The outer edge of the gate wiring 74 is formed with a gap outward from the outer edge of the planar wiring 29 and does not necessarily face the planar wiring 29 in the thickness direction Z. The outer edge of the gate wiring 74 is formed with a gap inward from the inner edge of the outer contact region 19 and does not face the outer contact region 19 in the thickness direction Z. The outer edge of the gate wiring 74 may face the outer contact region 19 in the thickness direction Z.

[0354] The gate wiring 74 may have a single-layer structure including a single metal film, or a multilayer structure including multiple metal films, similar to the source electrode 70 (gate electrode 73). In this embodiment, the gate wiring 74 has a single-layer structure consisting of the main electrode 71, similar to the source electrode 70 (gate electrode 73).

[0355] The semiconductor device 1A includes an upper insulating film 80 that selectively covers the interlayer film 26. The upper insulating film 80 selectively covers a plurality of electrodes on the interlayer film 26. Specifically, the upper insulating film 80 selectively covers the source electrode 70, source wiring 72, gate electrode 73, and gate wiring 74 on the interlayer film 26.

[0356] The upper insulating film 80 has a portion that covers multiple shield structures 60 collectively on the interlayer film 26. The upper insulating film 80 protects the multiple shield structures 60, source electrode 70, source wiring 72, gate electrode 73, and gate wiring 74 from external forces and moisture (humidity).

[0357] The upper insulating film 80 has one or more (one in this embodiment) source pad openings 81 that cover the peripheral edge of the source electrode 70 in a film-like manner and expose the inner portion of the source electrode 70. In this embodiment, the source pad opening 81 exposes the first pad portion 70a, the second pad portion 70b, and the third pad portion 70c together.

[0358] If the upper insulating film 80 has a plurality of source pad openings 81, the plurality of source pad openings 81 may include a source pad opening 81 that exposes a first pad portion 70a, a source pad opening 81 that exposes a second pad portion 70b, and a source pad opening 81 that exposes a third pad portion 70c.

[0359] The upper insulating film 80 covers the periphery of the gate electrode 73 in a film-like manner and has one or more (one in this embodiment) gate pad openings 82 that expose the inner portion of the gate electrode 73. In this embodiment, the upper insulating film 80 covers the entire area of ​​the source wiring 72 and the entire area of ​​the gate wiring 74.

[0360] The upper insulating film 80 coats the interlayer film 26 in a film-like manner in the outer region 9. The upper insulating film 80 is drawn out in a film-like manner from above the interlayer film 26 onto the multiple shield structures 60. The upper insulating film 80 is mechanically connected to the multiple shield structures 60 and forms connection boundaries with the multiple shield structures 60. The upper insulating film 80 electrically insulates the multiple shield structures 60 from the outside.

[0361] Specifically, in this configuration, the upper insulating film 80 penetrates the interlayer film 26 into a plurality of shielding openings 61 and coats the plurality of shielding electrodes 62 in a film-like manner within the plurality of shielding openings 61. The upper insulating film 80 forms connection boundaries with the electrode surfaces of the plurality of shielding electrodes 62 within the plurality of shielding openings 61, electrically insulating the plurality of shielding electrodes 62 from the outside.

[0362] The upper insulating film 80 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 83 between itself and the periphery of the chip 2. The dicing street 83 is demarcated in the region between the periphery of the chip 2 and the plurality of shield structures 60 (the outermost shield structure 60).

[0363] The dicing street 83 exposes the interlayer film 26 and faces the channel stop region 21 in the thickness direction Z. If the main surface insulating film 25 and the interlayer film 26 are formed with a gap inward from the periphery of the first main surface 3, the dicing street 83 may expose the first main surface 3. In this case, the upper insulating film 80 may have a portion that directly covers the first main surface 3.

[0364] In this configuration, the dicing street 83 (the outer wall portion of the upper insulating film 80) is formed with a gap between the inner edge of the channel stop region 21 and the peripheral edge of the chip 2. In other words, the entire area of ​​the dicing street 83 faces the channel stop region 21 in the thickness direction Z.

[0365] The dicing street 83 extends in a band-like manner along the periphery of the chip 2 in a plan view. In this embodiment, the dicing street 83 is formed as an ended or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the inner part of the chip 2 (the multiple shield structures 60).

[0366] The dicing street 83 has a width less than the width of the channel stop region 21. The width of the dicing street 83 may be greater than 0 μm and less than 200 μm. The width of the dicing street 83 may have a value that falls within at least one of the following ranges: greater than 0 μm and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, and 150 μm or more and less than 200 μm.

[0367] The upper insulating film 80 has a thickness less than the thickness of the chip 2. In this embodiment, the thickness of the upper insulating film 80 is greater than the thickness of the interlayer film 26 (the height of the multiple shielding structures 60). The thickness of the upper insulating film 80 may be less than the thickness of the interlayer film 26.

[0368] In this embodiment, the thickness of the upper insulating film 80 is greater than the thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74). The thickness of the upper insulating film 80 may also be less than the thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74).

[0369] In this embodiment, the thickness of the upper insulating film 80 is greater than the combined thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74). The thickness of the upper insulating film 80 may also be less than the combined thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74).

[0370] The thickness of the upper insulating film 80 may be greater than 0 μm and 50 μm or less. The thickness of the upper insulating film 80 may have a value that falls within at least one of the following ranges: greater than 0 μm and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less.

[0371] In this embodiment, the upper insulating film 80 has a laminated structure including an insulating inorganic film 84 and an insulating organic film 85, which are laminated in this order from the chip 2 side (interlayer film 26 side). The upper insulating film 80 only needs to include at least one of the inorganic film 84 and the organic film 85, and does not necessarily need to include both the inorganic film 84 and the organic film 85 at the same time. The inorganic film 84 may be referred to as the "first insulating film," "inorganic insulating film," etc., and the organic film 85 may be referred to as the "second insulating film," "organic insulating film," "resin film," etc.

[0372] The inorganic film 84 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the inorganic film 84 contains an insulating material different from the interlayer film 26. Preferably, the inorganic film 84 contains a silicon nitride film.

[0373] The inorganic film 84 selectively covers multiple electrodes on the interlayer film 26. Specifically, the inorganic film 84 selectively covers the source electrode 70, source wiring 72, gate electrode 73, and gate wiring 74 on the interlayer film 26. The inorganic film 84 has a portion that collectively covers multiple shield structures 60 on the interlayer film 26.

[0374] The inorganic film 84 covers the periphery of the source electrode 70 in a film-like manner, and demarcates one or more (one in this embodiment) source pad openings 81 that expose the inner portion of the source electrode 70. The inorganic film 84 covers the periphery of the gate electrode 73 in a film-like manner, and demarcates one or more (one in this embodiment) gate pad openings 82 that expose the inner portion of the gate electrode 73. In this embodiment, the inorganic film 84 covers the entire area of ​​the source wiring 72 and the entire area of ​​the gate wiring 74 in a film-like manner.

[0375] The inorganic film 84 coats the interlayer film 26 in a film-like manner in the outer region 9. The inorganic film 84 extends in a film-like manner from above the interlayer film 26 onto the multiple shield structures 60. The inorganic film 84 is mechanically connected to the multiple shield structures 60 and forms connection boundaries with the multiple shield structures 60. The inorganic film 84 electrically insulates the multiple shield structures 60 from the outside.

[0376] Specifically, in this configuration, the inorganic film 84 penetrates the interlayer film 26 through multiple shielding openings 61 and coats the multiple shielding electrodes 62 within the multiple shielding openings 61 in a film-like manner. The inorganic film 84 forms connection boundaries with the electrode surfaces of the multiple shielding electrodes 62 within the multiple shielding openings 61, electrically insulating the multiple shielding electrodes 62 from the outside.

[0377] The inorganic film 84 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 83 between itself and the periphery of the chip 2. The inorganic film 84 may have a thickness less than the thickness of the interlayer film 26. The thickness of the inorganic film 84 may also be less than the thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74).

[0378] The thickness of the inorganic film 84 may be greater than 0 μm and less than or equal to 2 μm. The thickness of the inorganic film 84 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.75 μm, 0.75 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.25 μm, 1.25 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 1.75 μm, and 1.75 μm or more and less than or equal to 2 μm.

[0379] The organic film 85 may consist of a resin film other than a thermosetting resin. The organic film 85 may consist of a light-transmitting resin or a transparent resin. The organic film 85 may contain a negative-type or positive-type photosensitive resin film. The organic film 85 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0380] The organic film 85 coats the inorganic film 84 in a film-like manner. The organic film 85 selectively coats multiple electrodes on the interlayer film 26 via the inorganic film 84. Specifically, the organic film 85 selectively coats the source electrode 70, source wiring 72, gate electrode 73, and gate wiring 74 via the inorganic film 84. The organic film 85 has a portion that collectively coats multiple shield structures 60 via the inorganic film 84.

[0381] The organic film 85 covers the periphery of the source electrode 70 via the inorganic film 84, and demarcates one or more (one in this embodiment) source pad openings 81 that expose the inner portion of the source electrode 70. The organic film 85 may expose the end of the inorganic film 84 on the wall surface of the source pad opening 81. The organic film 85 may cover the end of the inorganic film 84 on the wall surface of the source pad opening 81.

[0382] The organic film 85 covers the periphery of the gate electrode 73 via the inorganic film 84, and opens one or more (one in this embodiment) gate pad openings 82 that expose the inner portion of the gate electrode 73. The organic film 85 may expose the end of the inorganic film 84 at the wall surface of the gate pad opening 82. The organic film 85 may cover the end of the inorganic film 84 at the wall surface of the gate pad opening 82. In this embodiment, the organic film 85 covers the entire area of ​​the source wiring 72 and the entire area of ​​the gate wiring 74 via the inorganic film 84.

[0383] The organic film 85 coats the interlayer film 26 in a film-like manner in the outer region 9 via the inorganic film 84. The organic film 85 extends in a film-like manner onto the multiple shield structures 60 via the inorganic film 84 and faces the multiple shield structures 60 via the inorganic film 84. In other words, the organic film 85 enhances the insulating and protective effects of the inorganic film 84 on the multiple shield structures 60.

[0384] The organic film 85 may cover the multiple shield electrodes 62 in a film-like manner via the inorganic film 84 above the multiple shield openings 61. The organic film 85 may also cover the multiple shield electrodes 62 in a film-like manner via the inorganic film 84 within the multiple shield openings 61.

[0385] The organic film 85 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 83 between itself and the periphery of the chip 2. The organic film 85 may expose the end of the inorganic film 84 at the wall surface of the dicing street 83. The organic film 85 may cover the end of the inorganic film 84 at the wall surface of the dicing street 83.

[0386] The organic film 85 has a thickness less than the thickness of the chip 2. The thickness of the organic film 85 is greater than the thickness of the inorganic film 84. In this embodiment, the thickness of the organic film 85 is greater than the thickness of the interlayer film 26 (the height of the multiple shield structures 60). The thickness of the organic film 85 may be less than the thickness of the interlayer film 26.

[0387] In this embodiment, the thickness of the organic film 85 is greater than the thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74). The thickness of the organic film 85 may also be less than the thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74).

[0388] In this embodiment, the thickness of the organic film 85 is greater than the combined thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74). The thickness of the organic film 85 may also be less than the combined thickness of the source electrode 70 (source wiring 72) and the gate electrode 73 (gate wiring 74).

[0389] The thickness of the organic film 85 may be greater than 0 μm and 50 μm or less. The thickness of the organic film 85 may have a value that falls within at least one of the following ranges: greater than 0 μm and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less.

[0390] The inorganic film 84 does not necessarily need to cover the source wiring 72 and the gate wiring 74, and may have a removal portion that exposes either or both of the source wiring 72 and the gate wiring 74. In this case, the organic film 85 may have a portion that directly covers the source wiring 72 and a portion that directly covers the gate wiring 74, or both of these.

[0391] The inorganic film 84 may have a removal portion that exposes the corners (electrode sidewalls) of the source electrode 70 and may cover the peripheral edge of the source electrode 70. In this case, the organic film 85 may have a portion that directly covers the corners (electrode sidewalls) of the source electrode 70.

[0392] The inorganic film 84 may have a removal portion that exposes the corner (electrode side wall) of the gate electrode 73 and may cover the peripheral edge of the gate electrode 73. In this case, the organic film 85 may have a portion that directly covers the corner (electrode side wall) of the gate electrode 73.

[0393] The semiconductor device 1A includes a drain electrode 86 that covers the second main surface 4. The drain electrode 86 may also be referred to as the "third main electrode," "third terminal (electrode)," "third pad (electrode)," or "drain pad (electrode)." The drain electrode 86 is mechanically and electrically connected to the first semiconductor layer 6 on the second main surface 4. The drain electrode 86 forms ohmic contact with the first semiconductor layer 6.

[0394] The drain electrode 86 faces the structure of the active region 8 and the structure of the outer region 9 via the tip 2. In the active region 8, the drain electrode 86 faces the transistor structure T and the source electrode 70 in the thickness direction Z.

[0395] The drain electrode 86 faces the outer well region 18, outer contact region 19, multiple field regions 20, channel stop region 21, planar wiring 29, multiple outer via structures 50, multiple gate via structures 40, multiple shield structures 60, source wiring 72, gate electrode 73, and gate wiring 74 in the thickness direction Z of the outer region 9.

[0396] The drain electrode 86 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 86 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0397] The breakdown voltage that can be applied between the source electrode 70 and the drain electrode 86 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0398] Other configurations of the source via electrode 32 (source via structure 30) are shown below. Figures 16A and 16B are enlarged cross-sectional views showing a first and second modified example of the source via electrode 32.

[0399] Referring to Figure 16A (First Modified Example), the source via electrode 32 may include a via base electrode 34 having a single-layer structure. The via base electrode 34 may be a first via electrode 34a or a second via electrode 34b. In this case, the via body electrode 35 may be electrically connected to a plurality of source regions 11 and a plurality of contact regions 12 within the source opening 31 via the single-layer via base electrode 34.

[0400] Referring to Figure 16B (second modified example), the source via electrode 32 may have a single-layer structure consisting of a via body electrode 35. That is, the via body electrode 35 may be embedded as a single unit in the source opening 31 and may be in direct contact with the first main surface 3 and the interlayer film 26 within the source opening 31. The via body electrode 35 may be mechanically and electrically connected to a plurality of source regions 11 and a plurality of contact regions 12.

[0401] Although specific illustrations are omitted, the gate via structure 40 described above may have a configuration similar to the source via structure 30 according to the first and second modified examples (see Figures 16A and 16B). The specific configuration in this case can be obtained by replacing "source via structure 30" with "gate via structure 40" and replacing the connection target with "planar wiring 29" in the explanation of Figures 16A and 16B.

[0402] The aforementioned outer via structure 50 may have the same configuration as the source via structure 30 according to the first and second modified examples (see Figures 16A and 16B). The specific configuration in this case can be obtained by replacing "source via structure 30" with "outer via structure 50" and replacing the connection target with "outer contact region 19" in the explanation of Figures 16A and 16B.

[0403] Other configurations of the shield electrode 62 (shield structure 60) are shown below. Figures 17A and 17B are enlarged cross-sectional views showing a first and second modified example of the shield electrode 62.

[0404] Referring to Figure 17A (First Modified Example), the shield electrode 62 may include a single-layer shield base electrode 64. The shield base electrode 64 may be a first shield electrode 64a or a second shield electrode 64b. In this case, the shield body electrode 65 may be mechanically and electrically connected to the single-layer shield base electrode 64 within the shield opening 61.

[0405] Referring to Figure 17B (second modified example), the shield electrode 62 may have a single-layer structure consisting of a shield body electrode 65. That is, the shield body electrode 65 may be embedded as a single unit in the shield opening 61 and be in direct contact with the first main surface 3 and the interlayer film 26 within the shield opening 61. In this embodiment, the shield body electrode 65 is mechanically and electrically connected to the channel stop region 21.

[0406] The shield structure 60 according to the first and second modified examples may be used simultaneously with at least one of the source via structure 30, gate via structure 40, and outer via structure 50 according to the first modified example (see Figure 16A).

[0407] The shield structure 60 according to the first and second modifications may be used simultaneously with at least one of the source via structure 30, gate via structure 40, and outer via structure 50 according to the second modification (see Figure 16B).

[0408] Other configurations of the source electrode 70 are shown below. Figures 18A to 18E are enlarged cross-sectional views showing the first to fifth modified examples of the source electrode 70.

[0409] Referring to Figure 18A (First Modified Example), the source electrode 70 may have a laminated structure including a plurality of metal films. In this embodiment, the source electrode 70 has a laminated structure including a base electrode 87 and a main electrode 71 that are laminated in this order from the interlayer film 26 side.

[0410] In this embodiment, the base electrode 87 has a laminated structure including a first electrode 87a and a second electrode 87b. The first electrode 87a consists of a metal film containing any one of the aforementioned metals, or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first electrode 87a consists of a titanium-based metal film (titanium film).

[0411] The first electrode 87a coats the insulating surface of the interlayer film 26 in a film-like manner and is electrically connected to the source via electrode 32. Specifically, the first electrode 87a enters the source opening 31 from above the interlayer film 26 and is connected to the first via electrode 34a of the source via electrode 32 within the source opening 31. In this configuration, the first electrode 87a is made of the same conductor (titanium film) as the first via electrode 34a and is formed integrally with the first via electrode 34a.

[0412] The first electrode 87a has a thickness less than the thickness of the interlayer film 26. The thickness of the first electrode 87a is approximately equal to the thickness of the first via electrode 34a. The thickness of the first electrode 87a may be greater or less than the thickness of the first via electrode 34a.

[0413] The thickness of the first electrode 87a may be greater than 0 nm and 200 nm or less. The thickness of the first electrode 87a may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or more and 200 nm or less.

[0414] The second electrode 87b consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second electrode 87b consists of a different metal film or alloy film than the first electrode 87a. In this embodiment, the second electrode 87b consists of a titanium-based metal film (a titanium nitride film as an example of a titanium alloy film).

[0415] The second electrode 87b covers the first electrode 87a in a film-like manner and is electrically connected to the source via electrode 32. Specifically, the second electrode 87b enters the source opening 31 from above the first electrode 87a and is connected to the second via electrode 34b within the source opening 31. In this configuration, the second electrode 87b is made of the same conductor (titanium nitride film) as the second via electrode 34b and is formed integrally with the second via electrode 34b.

[0416] The second electrode 87b has a thickness less than the thickness of the interlayer film 26. In this embodiment, the thickness of the second electrode 87b is greater than the thickness of the first electrode 87a. The thickness of the second electrode 87b may be less than the thickness of the first electrode 87a. The thickness of the second electrode 87b is approximately equal to the thickness of the second via electrode 34b. The thickness of the second electrode 87b may be greater than or less than the thickness of the second via electrode 34b.

[0417] The thickness of the second electrode 87b may be greater than 0 nm and 300 nm or less. The thickness of the second electrode 87b may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0418] The main electrode 71 covers the base electrode 87 in a film-like manner and is drawn out from above the base electrode 87 onto the source opening 31. The main electrode 71 is mechanically and electrically connected to the source via electrode 32 (via main electrode 35) within the source opening 31, and forms a connection boundary with the source via electrode 32 (via main electrode 35). The main electrode 71 has a thickness greater than the thickness of the base electrode 87 (the total thickness of the first electrode 87a and the second electrode 87b) (= greater than 0 μm and 5 μm or less).

[0419] Referring to Figure 18B (second modified example), in this embodiment, the source via electrode 32 includes a via base electrode 34 having a single-layer structure. The via base electrode 34 may be a first via electrode 34a or a second via electrode 34b. The via body electrode 35 is mechanically and electrically connected to the single-layer via base electrode 34 within the source opening 31.

[0420] In this embodiment, the source electrode 70 has a laminated structure including a base electrode 87 and a main electrode 71, which are stacked in this order from the interlayer film 26 side. In this embodiment, the base electrode 87 has a single-layer structure. The base electrode 87 may be a first electrode 87a or a second electrode 87b.

[0421] If the via base electrode 34 consists of a first via electrode 34a, the base electrode 87 may consist of a first electrode 87a. If the via base electrode 34 consists of a second via electrode 34b, the base electrode 87 may consist of a second electrode 87b.

[0422] The base electrode 87 coats the insulating surface of the interlayer film 26 in a film-like manner and is electrically connected to the source via electrode 32. Specifically, the base electrode 87 enters the source opening 31 from above the interlayer film 26 and is connected to the via base electrode 34 within the source opening 31. In this configuration, the base electrode 87 is made of the same conductor as the via base electrode 34 and is formed integrally with the via base electrode 34.

[0423] The main electrode 71 covers the base electrode 87 in a film-like manner and extends from above the base electrode 87 onto the source opening 31. The main electrode 71 is mechanically and electrically connected to the source via electrode 32 (via main electrode 35) within the source opening 31, forming a connection boundary with the source via electrode 32 (via main electrode 35).

[0424] Referring to Figure 18C (third modified example), in this embodiment, the source electrode 70 has a laminated structure including a base electrode 87 and a main electrode 71, which are laminated in this order from the interlayer film 26 side, similar to the first modified example. The base electrode 87 has a laminated structure including a first electrode 87a and a second electrode 87b.

[0425] The first electrode 87a coats the insulating surface of the interlayer film 26 in a film-like manner, enters the source opening 31 from above the interlayer film 26, and coats the electrode surface of the source via electrode 32 in a film-like manner within the source opening 31. The first electrode 87a is mechanically and electrically connected to the source via electrode 32 within the source opening 31, forming a connection boundary with the source via electrode 32.

[0426] The second electrode 87b covers the first electrode 87a in a film-like manner and enters the source opening 31 from above the first electrode 87a. Within the source opening 31, the second electrode 87b covers the electrode surface of the source via electrode 32 in a film-like manner via the first electrode 87a and is electrically connected to the source via electrode 32.

[0427] The main electrode 71 covers the base electrode 87 in a film-like manner and enters the source opening 31 from above the base electrode 87. Within the source opening 31, the main electrode 71 covers the electrode surface of the source via electrode 32 in a film-like manner via the base electrode 87 and is electrically connected to the source via electrode 32.

[0428] Referring to Figure 18D (fourth modified example), in this embodiment, the source electrode 70 has a laminated structure including a base electrode 87 and a main electrode 71, which are laminated in this order from the interlayer film 26 side, similar to the second modified example. The base electrode 87 may have a single-layer structure consisting of a first electrode 87a or a second electrode 87b.

[0429] The base electrode 87 covers the insulating surface of the interlayer film 26 in a film-like manner, enters the source opening 31 from above the interlayer film 26, and covers the electrode surface of the source via electrode 32 in a film-like manner within the source opening 31. The base electrode 87 is mechanically and electrically connected to the source via electrode 32 and forms a connection boundary with the source via electrode 32.

[0430] The main electrode 71 covers the base electrode 87 in a film-like manner and enters the source opening 31 from above the base electrode 87. Within the source opening 31, the main electrode 71 covers the electrode surface of the source via electrode 32 in a film-like manner via the base electrode 87 and is electrically connected to the source via electrode 32.

[0431] Referring to Figure 18E (Fifth Modification), the source via electrode 32 has a laminated structure including a via base electrode 34 and a via body electrode 35, similar to the first embodiment. In this embodiment, the via base electrode 34 has a laminated structure including a first via electrode 34a and a second via electrode 34b.

[0432] In this embodiment, the via body electrode 35 includes an aluminum-based metal (aluminum or an aluminum alloy). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0433] In this embodiment, the source electrode 70 has a laminated structure including a base electrode 87 and a main electrode 71, which are stacked in this order from the interlayer film 26 side, similar to the first modified example. The base electrode 87 has a laminated structure including a first electrode 87a and a second electrode 87b.

[0434] The first electrode 87a covers the insulating surface of the interlayer film 26 in a film-like manner and enters the source opening 31 from above the interlayer film 26. The first electrode 87a is connected to the first via electrode 34a of the source via electrode 32 within the source opening 31. In this configuration, the first electrode 87a is made of the same conductor (titanium film) as the first via electrode 34a and is formed integrally with the first via electrode 34a.

[0435] The second electrode 87b covers the first electrode 87a in a film-like manner and enters the source opening 31 from above the first electrode 87a. The second electrode 87b is connected to the second via electrode 34b of the source via electrode 32 within the source opening 31. In this configuration, the second electrode 87b is made of the same conductor (titanium nitride film) as the second via electrode 34b and is formed integrally with the second via electrode 34b.

[0436] The main electrode 71 covers the base electrode 87 in a film-like manner and enters the source opening 31 from above the base electrode 87. The main electrode 71 is connected to the via main electrode 35 of the source via electrode 32 within the source opening 31. In this configuration, the main electrode 71 is made of the same conductive material (aluminum-based metal) as the via main electrode 35 and is formed integrally with the via main electrode 35.

[0437] Although specific illustrations are omitted, the aforementioned source wiring 72 may have a configuration similar to that of the source electrode 70 according to the first to fifth modified examples (see Figures 18A to 18E). In this case, the specific configuration can be obtained by replacing "source electrode 70," "source via structure 30," "source opening 31," and "source via electrode 32" with "source wiring 72," "outer via structure 50," "outer opening 51," and "outer via electrode 52" as described in Figures 18A to 18E.

[0438] The aforementioned gate wiring 74 (gate electrode 73) may have the same configuration as the source electrode 70 according to the first to fifth modified examples (see Figures 18A to 18E). In this case, the specific configuration can be obtained by replacing "source electrode 70", "source via structure 30", "source opening 31", and "source via electrode 32" with "gate wiring 74 (gate electrode 73)", "gate via structure 40", "gate opening 41", and "gate via electrode 42" as described in Figures 18A to 18E.

[0439] The shield structure 60 according to the first and second modified examples described above (see Figures 17A and 17B) may be used simultaneously with at least one of the source electrode 70 according to the first to fifth modified examples, the source wiring 72 according to the first to fifth modified examples, and the gate wiring 74 (gate electrode 73) according to the first to fifth modified examples.

[0440] As described above, the semiconductor device 1A includes a chip 2, an interlayer film 26 (insulating film), and a shielding opening 61. The interlayer film 26 covers the chip 2. The shielding opening 61 is formed in the interlayer film 26 at the periphery of the chip 2. The shielding opening 61 divides the interlayer film 26 into an inner region of the chip 2 (inner region 26a) and a peripheral region of the chip 2 (peripheral region 26b).

[0441] This configuration provides a semiconductor device 1A that contributes to improved reliability. For example, with this configuration, when an external force is applied to the periphery of the interlayer film 26 (the periphery of the chip 2), the shield opening 61 functions as a stopper to suppress the inward expansion of delamination or cracks that may occur at the periphery of the interlayer film 26. This suppresses fluctuations in electrical properties caused by delamination or cracks in the interlayer film 26, thereby improving reliability.

[0442] For example, the shielding aperture 61 is also effective in protecting structures inside and outside the chip 2 from external forces (for example, external forces caused by dicing blades, etc.) that occur when cutting multiple semiconductor devices 1A from a single wafer during the manufacturing process of the semiconductor device 1A.

[0443] Chip 2 may contain SiC. This configuration provides a semiconductor device 1A as a novel SiC semiconductor device. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in harsh environments (high voltage and / or high humidity environments), the effect of suppressing fluctuations in electrical properties by the shielding aperture 61 is effective in improving reliability.

[0444] The shield opening 61 may penetrate the interlayer film 26 and divide the interlayer film 26 into an inner region of the chip 2 and a peripheral region of the chip 2. With this configuration, delamination and crack expansion of the interlayer film 26 are appropriately suppressed by the shield opening 61.

[0445] The shield opening 61 may have an opening width less than the thickness of the interlayer film 26 and may extend longitudinally in the thickness direction Z of the interlayer film 26. According to this configuration, the ratio of the shield opening 61 in the interlayer film 26 is appropriately reduced. Thereby, the increase in size of the semiconductor device 1A due to the shield opening 61 is appropriately suppressed.

[0446] The shield opening 61 may extend in a band shape along the periphery of the chip 2 in a plan view. According to this configuration, the peeling of the interlayer film 26 and the expansion of cracks are appropriately suppressed by the shield opening 61 extending in a band shape.

[0447] The shield opening 61 may be formed in an annular shape surrounding the inner part of the chip 2 in a plan view. According to this configuration, the peeling of the interlayer film 26 and the expansion of cracks are appropriately suppressed by the annular shield opening 61.

[0448] A plurality of shield openings 61 may be formed in the interlayer film 26 at intervals. According to this configuration, the peeling of the interlayer film 26 and the expansion of cracks are appropriately suppressed by the plurality of shield openings 61.

[0449] The semiconductor device 1A may include a conductive shield electrode 62 as an example of a shield member made of a member different from the interlayer film 26. The shield electrode 62 may be embedded in the shield opening 61. According to this configuration, when the semiconductor device 1A is used in a high-humidity environment, the intrusion of moisture (humidity) from the outside into the shield opening 61 is suppressed by the shield electrode 62. Thereby, oxidation due to moisture is suppressed, and electrical variations due to oxides are suppressed.

[0450] In this case, the shield electrode 62 may be formed in an electrically floating state. According to this configuration, the electrical influence of the shield electrode 62 is appropriately reduced. Therefore, even when an oxide of the shield electrode 62 is generated, the electrical influence due to the oxide is also appropriately reduced.

[0451] The shield electrode 62 may be in contact with the chip 2 within the shield opening 61. According to this configuration, the contact of moisture (humidity) with the chip 2 is appropriately suppressed by the shield electrode 62.

[0452] The shield electrode 62 may contain a metal. The shield electrode 62 may contain a tungsten-based metal. The tungsten-based metal has a relatively high density and can be embedded in the shield opening 61. Thereby, the sealing property of the shield opening 61 is appropriately enhanced by the shield electrode 62, and the intrusion of moisture (humidity) through the shield opening 61 is appropriately suppressed.

[0453] The semiconductor device 1A may include an upper insulating film 80. The upper insulating film 80 may cover the shield opening 61 on the interlayer film 26. According to this configuration, the chip 2 and the interlayer film 26 are protected by the upper insulating film 80. Thereby, cracks in the chip 2 and / or cracks in the interlayer film 26 are suppressed by the upper insulating film 80. Further, the intrusion of moisture (humidity) through the shield opening 61 is suppressed by the upper insulating film 80.

[0454] The upper insulating film 80 may contain an insulating material different from the interlayer film 26. The upper insulating film 80 may have a single-layer structure or a laminated structure including either or both of the inorganic film 84 and the organic film 85. The upper insulating film 80 preferably includes at least the organic film 85. In this case, the protective effect of the upper insulating film 80 on the chip 2 and the interlayer film 26 is appropriately enhanced by the elasticity of the organic film 85. The organic film 85 may be made of a photosensitive resin film.

[0455] The semiconductor device 1A may include one or more electrodes disposed on the interlayer film 26. The one or more electrodes may be disposed on the interlayer film 26 at a distance from the shield opening 61 toward the inside of the chip 2. According to this configuration, the one or more electrodes are appropriately protected from peeling and cracking of the interlayer film 26 by the shield opening 61.

[0456] The semiconductor device 1A may include a field region 20. The field region 20 may be formed in the surface layer portion of the chip 2 at the peripheral edge of the chip 2. In this case, the shield opening 61 may be formed at a distance from the field region 20 toward the peripheral side of the chip 2.

[0457] This configuration appropriately reduces the electrical influence on the field region 20 caused by the shielding aperture 61. Furthermore, it appropriately suppresses the imposition of design rule restrictions caused by the shielding aperture 61 on the field region 20, while simultaneously appropriately suppressing the imposition of design rule restrictions caused by the field region 20 on the shielding aperture 61.

[0458] The semiconductor device 1A may include an active region 8, an outer region 9, and a device structure. The active region 8 may be located in the inner part of the chip 2. The outer region 9 may be located at the periphery of the chip 2. The device structure may be formed in the active region 8. In this case, the interlayer film 26 may selectively cover the chip 2 in the outer region 9. The shielding opening 61 may be formed in the interlayer film 26 in the outer region 9.

[0459] With this configuration, the delamination of the interlayer film 26 toward the active region 8 and the expansion of cracks are appropriately suppressed by the shield opening 61. As a result, fluctuations in the electrical properties of the device structure are appropriately suppressed, and the reliability of the device structure is appropriately improved.

[0460] The device structure may include a transistor structure T. This configuration appropriately suppresses variations in the electrical characteristics of the transistor structure T, thereby appropriately improving the reliability of the transistor structure T.

[0461] Figure 19 is a plan view showing a semiconductor device 1B according to the second embodiment. Figure 20 is a plan view obtained by removing the upper insulating film 80 from Figure 19. Figure 21 is a cross-sectional view taken along the line XXI-XXI shown in Figure 19.

[0462] Figure 22 is a plan view showing an example layout of the first main surface 3. Figure 23 is an enlarged plan view showing a key part of the active region 8 shown in Figure 22. Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 23. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 23. Figure 26 is an enlarged cross-sectional view of the structure shown in Figure 24.

[0463] Figure 27 is a cross-sectional view along the line XXVII-XXVII shown in Figure 19. Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 19. Figure 29 is a cross-sectional view along the line XXIX-XXIX shown in Figure 19. Figure 30 is an enlarged cross-sectional view showing a key part of the outer region 9 shown in Figure 28. Figure 31 is a further enlarged cross-sectional view of the outer region 9 shown in Figure 30.

[0464] Referring to Figures 19 to 30, semiconductor device 1B is a semiconductor switching device having an insulated gate type transistor structure T as an example of a device structure (functional device). In this embodiment, the transistor structure T has a trench gate type vertical structure. Similar to semiconductor device 1A, semiconductor device 1B includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and an outer region 9.

[0465] The semiconductor device 1B includes a p-type body region 10 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. In this configuration, the body region 10 is formed on the surface layer of the first main surface 3 over the entire area of ​​the active region 8 and extends in layers along the first main surface 3.

[0466] The semiconductor device 1B includes a plurality of trench-type (trench electrode type) gate structures 90 formed in the inner portion (active region 8) of the first main surface 3. The gate structures 90 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential (gate signal) is applied to the plurality of gate structures 90 as a control potential.

[0467] Multiple gate structures 90 are formed in the active region 8 at intervals from the periphery of the first main surface 3, but not in the outer region 9. The multiple gate structures 90 are arranged at intervals in the first direction X in a plan view, and each extends in a strip-like manner in the second direction Y. The multiple gate structures 90 are arranged in a stripe-like manner extending in the second direction Y in a plan view.

[0468] The longer sides of the multiple gate structures 90 are formed by the m-plane ((1-100) plane) of the SiC single crystal, and the shorter sides of the multiple gate structures 90 are formed by the a-plane ((11-20) plane) of the SiC single crystal. Depending on the extension direction of the multiple gate structures 90, the longer sides may be formed by the m-plane and the shorter sides may be formed by the a-plane.

[0469] The bottom walls of the multiple gate structures 90 are formed by the c-planes (Si planes) of the SiC single crystal. The bottom walls of the multiple gate structures 90 may extend substantially flat along the horizontal direction. The bottom walls of the multiple gate structures 90 may be curved in an arc toward the second main surface 4.

[0470] The gate structure 90 may have a width greater than 0 μm and less than or equal to 3 μm. The width of the gate structure 90 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, between 0.5 μm and 1 μm, between 1 μm and 1.5 μm, between 1.5 μm and 2 μm, between 2 μm and 2.5 μm, and between 2.5 μm and 3 μm.

[0471] The spacing between the multiple gate structures 90 may be greater than the width of the gate structure 90. The spacing between the gate structures 90 may be less than the width of the gate structure 90. The spacing between the gate structures 90 may be greater than 0 μm and 3 μm or less.

[0472] The spacing of the gate structure 90 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0473] The multiple gate structures 90 penetrate the body region 10 and are formed with a gap between them and the bottom of the second semiconductor layer 7 (first semiconductor layer 6) on the first main surface 3 side. The side walls (long sides) of the multiple gate structures 90 are formed substantially perpendicular to the first main surface 3. The side walls of the multiple gate structures 90 may be inclined at an angle with respect to the first main surface 3.

[0474] In other words, the multiple gate structures 90 may be formed in a tapered shape toward the bottom of the second semiconductor layer 7. The side walls of the multiple gate structures 90, together with the first main surface 3, define the obliquely inclined open ends. The open ends of the multiple gate structures 90 may be curved in an arc shape (circular arc shape).

[0475] The inclination angle (absolute value) of the side wall of the gate structure 90 with respect to the first main surface 3 may be 85° or more and 95° or less. The inclination angle may have a value that falls within at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.

[0476] The gate structure 90 may have a depth greater than 0 μm and less than or equal to 3 μm. The depth of the gate structure 90 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0477] The gate structure 90 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 90 is the ratio of the depth of the gate structure 90 to the width of the gate structure 90. The aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0478] The multiple gate structures 90 each include a trench 91, an insulating film 92, and an embedded electrode 93. The trench 91 may be referred to as a "gate trench," the insulating film 92 as a "gate insulating film," and the embedded electrode 93 as a "gate embedded electrode." The trench 91 is formed on the first main surface 3 and demarcates the wall surfaces (side walls and bottom walls) of the gate structure 90.

[0479] The insulating film 92 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 92 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The insulating film 92 may also include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0480] The insulating film 92 coats the walls (side walls and bottom walls) of the trench 91 in a film-like manner. The thickness of the insulating film 92 covering the bottom wall of the trench 91 may be greater than the thickness of the insulating film 92 covering the side walls of the trench 91.

[0481] The thickness of the insulating film 92 may be greater than 0 nm and 250 nm or less. The thickness of the insulating film 92 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0482] The embedded electrode 93 includes either a metallic conductor or a non-metallic conductor, or both. The embedded electrode 93 may also include conductive polysilicon. In this case, the embedded electrode 93 may include either a p-type conductive polysilicon or an n-type conductive polysilicon, or both.

[0483] The embedded electrode 93 is embedded in the trench 91 via an insulating film 92. The embedded electrode 93 has an electrode surface located on the bottom wall side of the trench 91 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 91. The electrode surface may also be located on the bottom wall side of the trench 91 with respect to the depth position of the middle part of the trench 91. The electrode surface may have a recess toward the bottom wall side.

[0484] The semiconductor device 1B includes a plurality of n-type source regions 11 formed in the second semiconductor layer 7 in the inner part (active region 8) of the first main surface 3. In this form, the plurality of source regions 11 are formed in the surface layer portion of the body region 10 in the region between the plurality of gate structures 90, and are formed at intervals in the second direction Y following the extending direction of the plurality of gate structures 90.

[0485] The plurality of source regions 11 each extend in a strip shape in the second direction Y following the extending direction of the plurality of gate structures 90. The plurality of source regions 11 are formed at an interval from the bottom of the body region 10 toward the first main surface 3 side, and face the second semiconductor layer 7 through a part of the body region 10. The plurality of source regions 11 are connected to the plurality of gate structures 90 in the first direction X and face the buried electrode 93 through the insulating film 92.

[0486] The semiconductor device 1B includes a plurality of p-type contact regions 12 formed in the second semiconductor layer 7 in the inner part (active region 8) of the first main surface 3. In this form, the plurality of contact regions 12 are formed in the surface layer portion of the body region 10 in the region between the plurality of gate structures 90, and are formed at intervals in the second direction Y following the extending direction of the plurality of gate structures 90.

[0487] Regarding the plurality of contact regions 12 formed on both sides of one gate structure 90, the other plurality of contact regions 12 face the one plurality of contact regions 12 in the first direction X in plan view. That is, the plurality of contact regions 12 are arranged in a matrix at intervals in the first direction X and the second direction Y in plan view.

[0488] The other plurality of contact regions 12 may face the region (the plurality of source regions 11) between the one plurality of contact regions 12 in the first direction X in plan view. That is, the plurality of contact regions 12 may be arranged in a staggered pattern at intervals in the first direction X and the second direction Y in plan view.

[0489] The multiple contact regions 12 are formed in a rectangular shape in plan view. Each of the multiple contact regions 12 has a length less than the length of the multiple source regions 11 with respect to the second direction Y. The multiple contact regions 12 are formed with a gap between them from the bottom of the body region 10 toward the first main surface 3 and face the second semiconductor layer 7 via a part of the body region 10.

[0490] Multiple contact regions 12 are connected to multiple gate structures 90 in a first direction X and face the embedded electrode 93 via an insulating film 92. The multiple contact regions 12 are formed at intervals from the depth position of the intermediate part of the multiple gate structures 90 toward the first main surface 3.

[0491] In this configuration, the multiple contact regions 12 are formed deeper than the multiple source regions 11 and have bottoms located closer to the bottom of the body region 10 than the bottoms of the multiple source regions 11. The multiple contact regions 12 may be formed shallower than the multiple source regions 11.

[0492] Similar to semiconductor device 1A, semiconductor device 1B has an outer well region 18, an outer contact region 19, a plurality of field regions 20, and a channel stop region 21 in its outer region 9. Similar to semiconductor device 1A, semiconductor device 1B also has a main surface insulating film 25, an interlayer film 26, and planar wiring 29.

[0493] The main surface insulating film 25 selectively coats the first main surface 3 in an active region 8 and an outer region 9. The main surface insulating film 25 covers the first main surface 3 in the active region 8, exposing multiple gate structures 90. Specifically, the main surface insulating film 25 is connected to multiple insulating films 92, exposing multiple embedded electrodes 93. In this embodiment, the main surface insulating film 25 forms a single insulating film integral with the multiple insulating films 92.

[0494] The main surface insulating film 25, as in the case of semiconductor device 1A, covers the outer well region 18, the outer contact region 19, a plurality of field regions 20, and the channel stop region 21 in the outer region 9.

[0495] In this configuration, the interlayer film 26 covers multiple gate structures 90 in the active region 8. Specifically, the interlayer film 26 penetrates multiple trenches 91 from above the main surface insulating film 25 and covers multiple embedded electrodes 93 within the trenches 91. Similar to the semiconductor device 1A, the interlayer film 26 covers the outer well region 18, outer contact region 19, multiple field regions 20, and channel stop region 21 via the main surface insulating film 25 in the outer region 9.

[0496] The interlayer film 26 has a laminated structure including a first interlayer film 27 and a second interlayer film 28, which are stacked in this order from the first main surface 3 side, similar to the semiconductor device 1A. The interlayer film 26 does not necessarily have to have a laminated structure including a first interlayer film 27 and a second interlayer film 28, and may have a single-layer structure consisting of either the first interlayer film 27 or the second interlayer film 28.

[0497] The first interlayer film 27 covers the main surface insulating film 25 in the active region 8 and the outer region 9. In the active region 8, the first interlayer film 27 penetrates into a plurality of trenches 91 from above the main surface insulating film 25 and covers a plurality of embedded electrodes 93 within the plurality of trenches 91. In the outer region 9, the first interlayer film 27 covers the outer well region 18, the outer contact region 19, a plurality of field regions 20 and a channel stop region 21 via the main surface insulating film 25.

[0498] The second interlayer film 28 is laminated on the first interlayer film 27 in the active region 8 and the outer region 9, and covers the first main surface 3 in a film-like manner via the first interlayer film 27. The second interlayer film 28 covers a plurality of embedded electrodes 93 via the first interlayer film 27 in the active region 8. In the outer region 9, the second interlayer film 28 covers the outer well region 18, the outer contact region 19, a plurality of field regions 20, and the channel stop region 21 via the main surface insulating film 25 and the first interlayer film 27.

[0499] The planar wiring 29, as in the semiconductor device 1A, is positioned on the main surface insulating film 25 in the outer region 9 and covered by an interlayer film 26. In this embodiment, the planar wiring 29 is mechanically and electrically connected to the ends of a plurality of gate structures 90. Specifically, the inner edge of the planar wiring 29 enters a plurality of trenches 91 from above the main surface insulating film 25 and is mechanically and electrically connected to a plurality of embedded electrodes 93 within the plurality of trenches 91.

[0500] In this embodiment, the planar wiring 29 is integrally formed with the multiple embedded electrodes 93 as the lead-out portion of the multiple embedded electrodes 93. The connection portion of the planar wiring 29 to the multiple embedded electrodes 93 may be considered as part of the multiple embedded electrodes 93 or as part of the planar wiring 29. Further description of the planar wiring 29 is the same as in the case of semiconductor device 1A and is therefore omitted.

[0501] The semiconductor device 1B, like the semiconductor device 1A, includes a plurality of source via structures 30 embedded in the interlayer film 26 in the active region 8. In this embodiment, the plurality of source via structures 30 penetrate the main surface insulating film 25 and the interlayer film 26 in the region between the plurality of gate structures 90. Each of the plurality of source via structures 30 is formed on the mesa between the plurality of gate structures 90 and is electrically connected to the plurality of body regions 10, the plurality of source regions 11, and the plurality of contact regions 12.

[0502] In this embodiment, the multiple source via structures 30 are formed at intervals in the first direction X in a one-to-one correspondence with respect to the multiple mesa sections, and each extends in a strip-like manner in the second direction Y. The multiple source via structures 30 may be arranged in a one-to-many correspondence with respect to a single mesa section. In this case, the multiple source via structures 30 may be arranged at intervals in the second direction Y, following the extending direction of the multiple gate structures 90.

[0503] The multiple source via structures 30 each include a source opening 31 (source recess 33) and a source via electrode 32, similar to the semiconductor device 1A. The source via electrode 32 has a laminated structure including a via base electrode 34 and a via body electrode 35 stacked in this order from the wall side of the source opening 31.

[0504] Further descriptions of the multiple source via structures 30 are the same as those for semiconductor device 1A and are therefore omitted. The multiple source via structures 30 (source via electrodes 32) may have a configuration similar to that of the source via structure 30 (source via electrodes 32) according to the first or second modified example (see Figures 16A and 16B).

[0505] The semiconductor device 1B, like the semiconductor device 1A, includes one or more (in this embodiment, more) gate via structures 40 embedded in the interlayer film 26 in the outer region 9. The multiple gate via structures 40 penetrate the interlayer film 26 over the planar wiring 29 and are electrically connected to the planar wiring 29.

[0506] The multiple gate via structures 40 each include a gate opening 41 (gate recess 43) and a gate via electrode 42, similar to the case of semiconductor device 1A. The gate via electrode 42 has a stacked structure including a via base electrode 34 and a via body electrode 35 stacked in this order from the wall side of the gate opening 41.

[0507] Further descriptions of the multiple gate via structures 40 are the same as those for semiconductor device 1A and are therefore omitted. The multiple gate via structures 40 (gate via electrodes 42) may have the same configuration as the gate via structure 40 (gate via electrodes 42) according to the first or second modified example (see Figures 16A and 16B).

[0508] The semiconductor device 1B, like the semiconductor device 1A, includes one or more (in this embodiment, more) outer via structures 50 embedded in the interlayer film 26 in the outer region 9. The multiple outer via structures 50 penetrate the main surface insulating film 25 and the interlayer film 26 over the outer contact region 19 and are electrically connected to the outer contact region 19.

[0509] The multiple outer via structures 50 each include an outer opening 51 (outer recess 53) and an outer via electrode 52, similar to the semiconductor device 1A. The outer via electrode 52 has a laminated structure including a via base electrode 34 and a via body electrode 35 stacked in this order from the wall side of the outer opening 51.

[0510] Further descriptions of the multiple outer via structures 50 are the same as those for semiconductor device 1A and are therefore omitted. The multiple outer via structures 50 (outer via electrodes 52) may have the same configuration as the outer via structure 50 (outer via electrodes 52) according to the first or second modified example (see Figures 16A and 16B).

[0511] The semiconductor device 1B, like the semiconductor device 1A, includes one or more (in this embodiment, more) shielding structures 60 embedded in the interlayer film 26 in the outer region 9. The more shielding structures 60, like the semiconductor device 1A, penetrate the main surface insulating film 25 and the interlayer film 26 over the channel stop region 21 and are electrically connected to the channel stop region 21.

[0512] The multiple shield structures 60 each include a shield opening 61 (shield recess 63) and a shield electrode 62, similar to the semiconductor device 1A. The shield electrode 62 has a laminated structure including a first shield electrode 64a and a second shield electrode 64b stacked in this order from the wall side of the shield opening 61.

[0513] The shield structure 60 (in this embodiment, a group of multiple shield structures 60) horizontally divides the interlayer membrane 26 into an inner region 26a on the inner side of the first main surface 3 (chip 2) and a peripheral region 26b on the peripheral side of the first main surface 3 (chip 2) in both cross-sectional and plan views. Specifically, the shield structure 60 (in this embodiment, a group of multiple shield structures 60) penetrates the interlayer membrane 26 and horizontally divides the interlayer membrane 26 into an inner region 26a and a peripheral region 26b.

[0514] Further descriptions of the multiple shield structures 60 are the same as those for semiconductor device 1A and are therefore omitted. The multiple shield structures 60 (shield electrodes 62) may have a configuration similar to that of the shield electrodes 62 according to the first or second modified example (see Figures 17A and 17B).

[0515] The semiconductor device 1B includes a source electrode 70, a source wiring 72, a gate electrode 73, a gate wiring 74, and a drain electrode 86, similar to the semiconductor device 1A. The descriptions of the source electrode 70, source wiring 72, gate electrode 73, gate wiring 74, and drain electrode 86 are the same as those for the semiconductor device 1A and are therefore omitted.

[0516] The source electrode 70 may have the same configuration as the source electrode 70 according to the first to fifth modified examples (see Figures 18A to 18E). The source wiring 72 may have the same configuration as the source electrode 70 according to the first to fifth modified examples (see Figures 18A to 18E). The gate wiring 74 (gate electrode 73) may have the same configuration as the source electrode 70 according to the first to fifth modified examples (see Figures 18A to 18E).

[0517] As described above, unlike semiconductor device 1A, semiconductor device 1B has a trench-type gate structure 90 (transistor structure T) as its device structure. This structure also provides the same effects as those associated with semiconductor device 1A.

[0518] Figure 32 is a plan view showing a semiconductor device 1C according to the third embodiment. Figure 33 is a cross-sectional view along the line XXXIII-XXXIII shown in Figure 32. Figure 34 is an enlarged cross-sectional view showing a key part of the outer region 9 shown in Figure 33. Figure 35 is a further enlarged cross-sectional view of the outer region 9 shown in Figure 34.

[0519] Referring to Figures 32 to 35, semiconductor device 1C is a semiconductor rectifier having a diode structure D as an example of a device structure (functional device). In this embodiment, the diode structure D has a vertical Schottky barrier diode structure. Similar to semiconductor device 1A, semiconductor device 1C includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and an outer region 9.

[0520] The semiconductor device 1C includes an n-type diode region 100 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. In this embodiment, the diode region 100 is formed using the second semiconductor layer 7 and has an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. The n-type impurity concentration of the diode region 100 may be higher or lower than that of the second semiconductor layer 7.

[0521] The diode region 100 is formed in the active region 8, spaced apart from the periphery of the first main surface 3, and is not formed in the outer region 9. In this embodiment, the diode region 100 is formed across the entire area of ​​the active region 8. In a plan view, the diode region 100 is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the first main surface 3.

[0522] The semiconductor device 1C, like the semiconductor device 1A, includes a p-type outer well region 18 formed in the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The outer well region 18 is formed with a gap from the peripheral edge of the first main surface 3 toward the inward side (active region 8) of the first main surface 3 and extends in a strip shape along the diode region 100 (active region 8).

[0523] The outer well region 18 has a portion extending in a first direction X and a portion extending in a second direction Y in a plan view, and divides the diode region 100 (active region 8) from multiple directions. In this embodiment, the outer well region 18 is formed as an ended or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the diode region 100.

[0524] The outer well region 18 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer well region 18 demarcates the boundary between the active region 8 and the outer region 9. Further description of the outer well region 18 is the same as in the case of semiconductor device 1A and is therefore omitted.

[0525] The semiconductor device 1C, like the semiconductor device 1A, includes one or more (in this embodiment, more) p-type field regions 20 formed in the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. In this embodiment, the semiconductor device 1C includes four field regions 20.

[0526] Multiple field regions 20 are formed at intervals from the diode region 100 towards the periphery of the first main surface 3 and extend in a strip shape along the diode region 100. Specifically, the multiple field regions 20 are formed at intervals from the outer well region 18 towards the periphery of the first main surface 3.

[0527] In this embodiment, the multiple field regions 20 are formed in an endless or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the diode region 100. Further description of the multiple field regions 20 is the same as in the case of semiconductor device 1A and is therefore omitted.

[0528] The semiconductor device 1C, like the semiconductor device 1A, includes a p-type or n-type (p-type in this embodiment) channel stop region 21 formed in the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. In this embodiment, the channel stop region 21 is formed on the surface layer of the first main surface 3 with a gap between it and the diode region 100 towards the peripheral edge of the first main surface 3.

[0529] The channel stop region 21 is formed with a gap extending from the outer well region 18 toward the periphery. The channel stop region 21 is formed with a gap extending from the multiple field regions 20 (the outermost field region 20) toward the periphery and extends in a band shape along the periphery of the first main surface 3.

[0530] In this embodiment, the channel stop region 21 is formed as an ended or endless polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the diode region 100. Further description of the channel stop region 21 is the same as in the case of semiconductor device 1A and is therefore omitted.

[0531] The semiconductor device 1C includes a main surface insulating film 25 that selectively covers the first main surface 3. The semiconductor device 1C does not necessarily need to have the main surface insulating film 25 and may be omitted if necessary. The main surface insulating film 25 exposes the diode region 100 in the active region 8 and covers the outer well region 18, the outer contact region 19, a plurality of field regions 20 and the channel stop region 21 in the outer region 9.

[0532] The main surface insulating film 25 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The main surface insulating film 25 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and may expose the periphery of the first main surface 3 (channel stop region 21). Further description of the main surface insulating film 25 is the same as in the case of semiconductor device 1A and is therefore omitted.

[0533] The semiconductor device 1C includes an interlayer film 26 that covers the main surface insulating film 25. In this embodiment, the interlayer film 26 has a laminated structure including a first interlayer film 27 and a second interlayer film 28 that are stacked in this order from the first main surface 3 side. The interlayer film 26 does not necessarily have to have a laminated structure including a first interlayer film 27 and a second interlayer film 28, and may have a single-layer structure consisting of either the first interlayer film 27 or the second interlayer film 28.

[0534] The interlayer film 26 exposes the diode region 100 in the active region 8, and covers the outer well region 18, outer contact region 19, multiple field regions 20, and channel stop region 21 via the main surface insulating film 25 in the outer region 9.

[0535] The interlayer film 26 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The interlayer film 26 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and may expose the periphery of the first main surface 3 (channel stop region 21). Further details of the interlayer film 26 are the same as in the case of semiconductor device 1A and are therefore omitted.

[0536] The semiconductor device 1C includes a diode opening 101 formed in the interlayer film 26. The diode opening 101 penetrates the main surface insulating film 25 and the interlayer film 26, exposing the diode region 100.

[0537] In this configuration, the diode opening 101 has a wall portion located above the outer well region 18, and together with the diode region 100, exposes the inner edge of the outer well region 18. The diode opening 101 is divided into a polygonal shape (a quadrilateral shape in this configuration) with four sides parallel to the periphery of the diode region 100 (the inner edge of the outer well region 18).

[0538] The semiconductor device 1C, like the semiconductor device 1A, includes one or more (in this embodiment, more) shield structures 60 embedded in the interlayer film 26 in the outer region 9. The multiple shield structures 60 are formed with a gap between them from the diode region 100 toward the periphery of the first main surface 3, and with a gap between them from the periphery of the first main surface 3 toward the interior of the first main surface 3.

[0539] The multiple shield structures 60 are formed at intervals from the outer edge of the outer well region 18 toward the periphery. The multiple shield structures 60 are formed at intervals from the multiple field regions 20 (the outermost field region 20 toward the periphery). Similar to the semiconductor device 1A, the multiple shield structures 60 penetrate the main surface insulating film 25 and the interlayer film 26 over the channel stop region 21 and are electrically connected to the channel stop region 21.

[0540] The multiple shield structures 60 each include a shield opening 61 (shield recess 63) and a shield electrode 62, similar to the semiconductor device 1A. The shield electrode 62 has a laminated structure including a first shield electrode 64a and a second shield electrode 64b stacked in this order from the wall side of the shield opening 61.

[0541] The shield structure 60 (in this embodiment, a group of multiple shield structures 60) horizontally divides the interlayer membrane 26 into an inner region 26a on the inner side of the first main surface 3 (chip 2) and a peripheral region 26b on the peripheral side of the first main surface 3 (chip 2) in both cross-sectional and plan views. Specifically, the shield structure 60 (in this embodiment, a group of multiple shield structures 60) penetrates the interlayer membrane 26 and horizontally divides the interlayer membrane 26 into an inner region 26a and a peripheral region 26b.

[0542] Further descriptions of the multiple shield structures 60 are the same as those for semiconductor device 1A and are therefore omitted. The multiple shield structures 60 (shield electrodes 62) may have a configuration similar to that of the shield electrodes 62 according to the first or second modified example (see Figures 17A and 17B).

[0543] The semiconductor device 1C includes an anode electrode 105 positioned in the inner portion (active region 8) of the first main surface 3. The anode electrode 105 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," or "anode pad (electrode)." The anode electrode 105 is made of metal and is positioned on the interlayer film 26.

[0544] The anode electrode 105 is positioned on the interlayer film 26 at an inward spacing from the periphery of the first main surface 3. The anode electrode 105 is formed at an inward spacing from a plurality of shield structures 60 (the innermost shield structure 60) and is surrounded by the plurality of shield structures 60 in a plan view. The anode electrode 105 is formed at an inward spacing from a plurality of field regions 20 (the innermost field region 20) and is surrounded by the plurality of field regions 20 in a plan view.

[0545] The anode electrode 105 is formed at a distance inward from the outer edge of the outer well region 18 and faces the outer well region 18 via the interlayer film 26. The peripheral edge of the anode electrode 105 may be located on the peripheral side of the first main surface 3 than the outer edge of the outer well region 18. In this case, the anode electrode 105 may face one or more field regions 20 in the thickness direction Z.

[0546] The anode electrode 105 is drawn out in a film-like manner from above the interlayer film 26 into the diode opening 101 and is mechanically and electrically connected to the first main surface 3. Specifically, the anode electrode 105 is electrically connected to the outer well region 18 on the first main surface 3 and forms a Schottky junction with the diode region 100. This forms a diode structure D (Schottky barrier diode structure) including the diode region 100 as the cathode region and the anode electrode 105 as the anode region.

[0547] The anode electrode 105 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The anode electrode 105 may contain a metal film comprising at least one of the following: magnesium (Mg) metals, aluminum (Al) metals, titanium (Ti) metals, vanadium (V) metals, chromium (Cr) metals, manganese (Mn) metals, cobalt (Co) metals, nickel (Ni) metals, copper (Cu) metals, zirconium (Zr) metals, niobium (Nb) metals, molybdenum (Mo) metals, palladium (Pd) metals, silver (Ag) metals, indium (In) metals, tin (Sn) metals, tantalum (Ta) metals, tungsten (W) metals, platinum (Pt) metals, and gold (Au) metals.

[0548] The anode electrode 105 may include a metal film containing at least one of magnesium, aluminum, titanium, vanadium, chromium, manganese, cobalt, nickel, copper, zirconium, niobium, molybdenum, palladium, silver, indium, tin, tantalum, tungsten, platinum, and gold.

[0549] The anode electrode 105 may include an alloy film containing at least one of the following: magnesium alloy, aluminum alloy, titanium alloy, vanadium alloy, chromium alloy, manganese alloy, cobalt alloy, nickel alloy, copper alloy, zirconium alloy, niobium alloy, molybdenum alloy, palladium alloy, silver alloy, indium alloy, tin alloy, tantalum alloy, tungsten alloy, platinum alloy, and gold alloy.

[0550] In this embodiment, the anode electrode 105 has a laminated structure including a base electrode 106 and a main electrode 107 stacked in this order from the first main surface 3 side. The base electrode 106 is formed as a barrier electrode for the second semiconductor layer 7 (diode region 100) and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0551] In this embodiment, the base electrode 106 has a laminated structure including a first electrode 106a and a second electrode 106b. The first electrode 106a consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. In this embodiment, the first electrode 106a consists of a titanium film.

[0552] In other words, in this configuration, the first electrode 106a is made of the same conductor as the first shield electrode 64a of the shield electrode 62. Of course, the first electrode 106a may be made of a different conductor than the first shield electrode 64a.

[0553] The first electrode 106a is positioned on the interlayer film 26 with an inward gap from the periphery of the first main surface 3. The first electrode 106a is formed with an inward gap from a plurality of shield structures 60. The first electrode 106a is surrounded by a plurality of field regions 20, which are formed with an inward gap from each other.

[0554] The first electrode 106a is formed at a distance inward from the outer edge of the outer well region 18 and faces the outer well region 18 via the interlayer film 26. The peripheral edge of the first electrode 106a may be located on the peripheral side of the first main surface 3 than the outer edge of the outer well region 18. In this case, the first electrode 106a may face one or more field regions 20 in the thickness direction Z.

[0555] The first electrode 106a is drawn out in a film-like manner from above the interlayer film 26 into the diode opening 101 and is mechanically and electrically connected to the first main surface 3. Specifically, the first electrode 106a is electrically connected to the outer well region 18 on the first main surface 3 and forms a Schottky junction with the diode region 100.

[0556] The first electrode 106a has a thickness less than the thickness of the interlayer film 26. The thickness of the first electrode 106a may be greater than 0 nm and 200 nm or less. The thickness of the first electrode 106a may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, and 150 nm to 200 nm.

[0557] The second electrode 106b consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second electrode 106b consists of a different metal film or alloy film than the first electrode 106a. In this embodiment, the second electrode 106b consists of a titanium nitride film (titanium alloy film).

[0558] In other words, in this configuration, the second electrode 106b is made of the same conductor as the second shield electrode 64b of the shield electrode 62. Of course, the second electrode 106b may be made of a different conductor than the second shield electrode 64b.

[0559] The second electrode 106b covers the first electrode 106a in a film-like manner. The second electrode 106b is formed with an inward gap from the plurality of shield structures 60. The second electrode 106b is formed with an inward gap from the plurality of field regions 20. The second electrode 106b is formed with an inward gap from the outer edge of the outer well region 18 and faces the outer well region 18 via the interlayer film 26.

[0560] The peripheral edge of the second electrode 106b may be located closer to the peripheral edge of the first main surface 3 than the outer edge of the outer well region 18. In this case, the second electrode 106b may face one or more field regions 20 in the thickness direction Z.

[0561] The second electrode 106b is drawn out in a film-like manner from above the interlayer film 26 into the diode opening 101, and is electrically connected to the diode region 100 and the outer well region 18 within the diode opening 101 via the first electrode 106a.

[0562] The second electrode 106b has a thickness less than the thickness of the interlayer film 26. In this embodiment, the thickness of the second electrode 106b is greater than the thickness of the first electrode 106a. The thickness of the second electrode 106b may be less than the thickness of the first electrode 106a. The thickness of the second electrode 106b may be between 10 nm and 300 nm.

[0563] The thickness of the second electrode 106b may be greater than 0 nm and fall within at least one of the following ranges: 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or more and 300 nm or less.

[0564] The main electrode 107 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The main electrode 107 is made of a different conductor than the first electrode 106a and the second electrode 106b.

[0565] The main electrode 107 may contain a different conductor than the shield electrode 62. The main electrode 107 may contain a different conductor than either or both of the shield base electrode 64 and the shield main electrode 65. The main electrode 107 may contain a different conductor than either or both of the first shield electrode 64a and the second shield electrode 64b.

[0566] In this embodiment, the main electrode 107 includes a conductor different from the first shield electrode 64a, the second shield electrode 64b, and the shield main electrode 65. In this embodiment, the main electrode 107 has a single-layer structure made of an aluminum-based metal (aluminum or an aluminum alloy). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0567] The main electrode 107 covers the base electrode 106 in a film-like manner. The main electrode 107 is formed with inward spacing from multiple shield structures 60. The main electrode 107 is formed with inward spacing from multiple field regions 20. The main electrode 107 is formed with inward spacing from the outer edge of the outer well region 18 and faces the outer well region 18 via an interlayer film 26.

[0568] The peripheral edge of the main electrode 107 may be located closer to the peripheral edge of the first main surface 3 than the outer edge of the outer well region 18. In this case, the main electrode 107 may face one or more field regions 20 in the thickness direction Z.

[0569] The main electrode 107 is drawn out in a film-like manner from above the interlayer film 26 into the diode opening 101, and is electrically connected to the diode region 100 and the outer well region 18 within the diode opening 101 via the base electrode 106.

[0570] The main electrode 107 has a thickness greater than the thickness of the base electrode 106 (the total thickness of the first electrode 106a and the second electrode 106b). In this embodiment, the thickness of the main electrode 107 is greater than the thickness of the interlayer film 26. The thickness of the main electrode 107 may be less than the thickness of the interlayer film 26.

[0571] The thickness of the main electrode 107 may be greater than 0 μm and 5 μm or less. The thickness of the main electrode 107 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0572] The semiconductor device 1C, like the semiconductor device 1A, includes an upper insulating film 80 that selectively covers the interlayer film 26. The upper insulating film 80 selectively covers the anode electrode 105 on the interlayer film 26. The upper insulating film 80 has a portion that collectively covers multiple shield structures 60 on the interlayer film 26. The upper insulating film 80 protects the multiple shield structures 60 and the anode electrode 105 from external forces and moisture (humidity).

[0573] The upper insulating film 80 has one or more (one in this embodiment) anode pad openings 108 that cover the periphery of the anode electrode 105 and expose the inner part of the anode electrode 105. In this embodiment, the anode pad openings 108 are formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the anode electrode 105 (the periphery of the first main surface 3).

[0574] Similar to the semiconductor device 1A, the upper insulating film 80 covers the interlayer film 26 in a film-like manner in the outer region 9. The upper insulating film 80 is drawn out in a film-like manner from above the interlayer film 26 onto the multiple shield structures 60 and is mechanically connected to the multiple shield structures 60. In other words, the upper insulating film 80 forms a connection boundary with the multiple shield structures 60 and electrically insulates the multiple shield structures 60 from the outside.

[0575] The upper insulating film 80 is formed at an inward distance from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D), similar to the semiconductor device 1A, and has an outer wall portion that defines the dicing street 83 between itself and the periphery of the chip 2.

[0576] The upper insulating film 80 has a laminated structure including an inorganic film 84 and an organic film 85 stacked in this order from the chip 2 side (interlayer film 26 side), similar to the semiconductor device 1A. The upper insulating film 80 only needs to include at least one of the inorganic film 84 and the organic film 85, and does not necessarily need to include both the inorganic film 84 and the organic film 85 at the same time.

[0577] The inorganic film 84 selectively covers the anode electrode 105 on the interlayer film 26. The inorganic film 84 covers the peripheral portion of the anode electrode 105 and demarcates one or more (one in this embodiment) anode pad openings 108 that expose the inner portion of the anode electrode 105.

[0578] The inorganic film 84, as in the case of semiconductor device 1A, has a portion that covers multiple shielding structures 60 collectively on the interlayer film 26. The inorganic film 84 may have a thickness less than the thickness of the interlayer film 26 (i.e., greater than 0 μm and 2 μm or less). The thickness of the inorganic film 84 may be less than the thickness of the anode electrode 105.

[0579] The organic film 85 selectively coats the anode electrode 105 on the interlayer film 26 via the inorganic film 84. Similar to the semiconductor device 1A, the organic film 85 has a portion that collectively coats multiple shield structures 60 via the inorganic film 84.

[0580] The organic film 85 covers the periphery of the anode electrode 105 via the inorganic film 84, and demarcates one or more (one in this embodiment) anode pad openings 108 that expose the inner portion of the anode electrode 105. The organic film 85 may expose the end of the inorganic film 84 at the wall surface of the anode pad opening 108. The organic film 85 may cover the end of the inorganic film 84 at the wall surface of the anode pad opening 108.

[0581] The organic film 85 has a thickness greater than that of the inorganic film 84 (i.e., greater than 0 μm and 50 μm or less). In this configuration, the thickness of the organic film 85 is greater than the thickness of the anode electrode 105. The thickness of the organic film 85 may also be less than the thickness of the anode electrode 105.

[0582] The inorganic film 84 may have a removal portion that exposes the corner (electrode side wall) of the anode electrode 105 and may cover the peripheral edge of the anode electrode 105. In this case, the organic film 85 may have a portion that directly covers the corner (electrode side wall) of the anode electrode 105. Further descriptions of the inorganic film 84 and the organic film 85 are the same as those for semiconductor device 1A and are therefore omitted.

[0583] The semiconductor device 1C includes a cathode electrode 109 that covers the second main surface 4. The cathode electrode 109 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," or "cathode pad (electrode)." The cathode electrode 109 is mechanically and electrically connected to the first semiconductor layer 6 on the second main surface 4. The cathode electrode 109 forms ohmic contact with the first semiconductor layer 6.

[0584] The cathode electrode 109 faces the structure of the active region 8 and the structure of the outer region 9 via the tip 2. In the active region 8, the cathode electrode 109 faces the diode region 100 and the anode electrode 105 in the thickness direction Z. In the outer region 9, the cathode electrode 109 faces the outer well region 18, a plurality of field regions 20, a channel stop region 21, a plurality of shield structures 60 and the anode electrode 105 in the thickness direction Z.

[0585] The cathode electrode 109 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The cathode electrode 109 may also partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0586] The breakdown voltage that can be applied between the anode electrode 105 and the cathode electrode 109 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0587] As described above, unlike semiconductor device 1A, semiconductor device 1C has a diode structure D as its device structure. This structure also provides the same effects as those associated with semiconductor device 1A.

[0588] The following describes the outer region 9 according to the first to twelfth modifications, which are other forms of the outer region 9. The outer regions 9 according to the first to twelfth modifications can be combined as appropriate. The outer regions 9 according to the first to twelfth modifications may be incorporated into semiconductor devices 1A to 1C as appropriate. The combined structures of the outer regions 9 according to the first to twelfth modifications may be incorporated into semiconductor devices 1A to 1C as appropriate.

[0589] Figure 36 is an enlarged cross-sectional view showing the outer region 9 of the first modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 37 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 36. In Figures 36 and 37, semiconductor device 1A is shown as an example.

[0590] Referring to Figures 36 and 37, the upper insulating film 80 does not necessarily have an organic film 85 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an organic film 85 and may have a single-layer structure consisting of an inorganic film 84.

[0591] Figure 38 is an enlarged cross-sectional view showing the outer region 9 of a second modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 39 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 38. In Figures 38 and 39, semiconductor device 1A is shown as an example.

[0592] Referring to Figures 38 and 39, the upper insulating film 80 does not necessarily have an inorganic film 84 in the covering portion over at least a plurality of shield structures 60. The upper insulating film 80 may not have an inorganic film 84 and may have a single-layer structure consisting of an organic film 85.

[0593] In other words, the organic film 85 may be drawn out in a film-like manner from above the interlayer film 26 in the outer region 9 onto the multiple shield structures 60 and mechanically connected to the multiple shield structures 60. In other words, the organic film 85 may form a connection boundary with the multiple shield structures 60 and electrically insulate the multiple shield structures 60 from the outside.

[0594] Specifically, the organic film 85 may penetrate the multiple shielding openings 61 from above the interlayer film 26 and coat the multiple shielding electrodes 62 in a film-like manner within the multiple shielding openings 61. The organic film 85 may also form connection boundaries with the electrode surfaces of the multiple shielding electrodes 62 within the multiple shielding openings 61, electrically insulating the multiple shielding electrodes 62 from the outside.

[0595] Figure 40 is an enlarged cross-sectional view showing the outer region 9 of a third modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 41 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 40. In Figures 40 and 41, semiconductor device 1A is shown as an example.

[0596] Referring to Figures 40 and 41, the shield structure 60 may include an insulating shield member 110 embedded in the shield opening 61 instead of the conductive shield electrode 62. The shield member 110 may be referred to as a "shielding insulator," "insulator," "insulating embedded object," etc.

[0597] The shielding member 110 may have a single-layer structure consisting of a single insulator, or it may have a laminated structure including multiple insulators. In this embodiment, the shielding member 110 has a laminated structure including multiple insulators. Specifically, the shielding member 110 includes a first insulator 111 and a second insulator 112.

[0598] The first insulator 111 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the first insulator 111 includes an insulating material different from the interlayer film 26. Preferably, the first insulator 111 includes a silicon nitride film.

[0599] The first insulator 111 has a thickness of less than half the opening width of the shield opening 61 and covers the wall surface of the shield opening 61 in a film-like manner. The first insulator 111 has a portion that covers the channel stop region 21 in a film-like manner at the bottom wall (shield recess 63) of the shield opening 61, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner at the side wall of the shield opening 61. The first insulator 111 partitions the insulating recess within the shield opening 61 and electrically insulates the channel stop region 21.

[0600] The second insulator 112 is made of a different insulating material than the first insulator 111. The second insulator 112 may contain an inorganic insulator or an organic insulator. As an inorganic insulator, the second insulator 112 may contain at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0601] In this embodiment, the second insulator 112 includes an organic insulator. The second insulator 112 may include a resin other than a thermosetting resin. The second insulator 112 may include a light-transmitting resin or a transparent resin. The organic film 85 may include a negative-type or positive-type photosensitive resin. The organic film 85 may include at least one of polyimide, polyamide, and polybenzoxazole.

[0602] The second insulator 112 is embedded in the shield opening 61 via the first insulator 111 as the main body of the shield member 110. The second insulator 112 faces the bottom wall and side wall of the shield opening 61 via the first insulator 111, and together with the first insulator 111, electrically insulates the channel stop region 21 from the outside.

[0603] In this embodiment, the upper insulating film 80 has a laminated structure including an inorganic film 84 and an organic film 85. In this embodiment, the inorganic film 84 enters the shield opening 61 from above the interlayer film 26 and is connected to the first insulator 111 within the shield opening 61. In this embodiment, the inorganic film 84 is made of the same insulator as the first insulator 111 and is formed integrally with the inorganic film 84.

[0604] In this configuration, the organic film 85 enters the shield opening 61 from above the interlayer film 26 and is connected to the second insulator 112 within the shield opening 61. In this configuration, the organic film 85 is made of the same insulator as the second insulator 112 and is formed integrally with the organic film 85.

[0605] Figure 42 is an enlarged cross-sectional view showing the outer region 9 of a fourth modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 43 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 42. In Figures 42 and 43, semiconductor device 1A is shown as an example.

[0606] Referring to Figures 42 and 43, the shield structure 60 may include an insulating shield member 110 embedded in the shield opening 61, similar to the third modified example. In this embodiment, the shield member 110 has a single-layer structure consisting of a first insulator 111. The first insulator 111 has a thickness of less than half the opening width of the shield opening 61 and covers the wall surface of the shield opening 61 in a film-like manner.

[0607] The first insulator 111 has a portion that covers the channel stop region 21 in a film-like manner at the bottom wall (shield recess 63) of the shield opening 61, and a portion that covers the interlayer film 26 (first interlayer film 27 and second interlayer film 28) in a film-like manner at the side wall of the shield opening 61. The first insulator 111 partitions the insulating recess within the shield opening 61 and electrically insulates the channel stop region 21.

[0608] The upper insulating film 80 does not necessarily have an organic film 85 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an organic film 85 and may have a single-layer structure consisting of an inorganic film 84.

[0609] In this configuration, the inorganic film 84 enters the shield opening 61 from above the interlayer film 26 and is connected to the first insulator 111 within the shield opening 61. In this configuration, the inorganic film 84 is made of the same insulator as the first insulator 111 and is formed integrally with the inorganic film 84.

[0610] Figure 44 is an enlarged cross-sectional view showing the outer region 9 of a fifth modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 45 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 44. In Figures 44 and 45, semiconductor device 1A is shown as an example.

[0611] Referring to Figures 44 and 45, the shield structure 60 may include an insulating shield member 110 embedded in the shield opening 61, similar to the third modified example. In this embodiment, the shield member 110 has a single-layer structure consisting of a first insulator 111.

[0612] The first insulator 111 is embedded as a single unit in the shield opening 61, backfilling the shield opening 61. Within the shield opening 61, the first insulator 111 is in contact with the channel stop region 21 and the interlayer film 26 (first interlayer film 27 and second interlayer film 28).

[0613] In this embodiment, the upper insulating film 80 has a laminated structure including an inorganic film 84 and an organic film 85. In this embodiment, the inorganic film 84 enters the shield opening 61 from above the interlayer film 26 and is connected to the shield member 110 (first insulator 111) within the shield opening 61.

[0614] In this configuration, the inorganic film 84 is made of the same insulator as the shielding member 110 (first insulator 111) and is integrally formed with the shielding member 110 (first insulator 111). In this configuration, the organic film 85 is drawn out from above the inorganic film 84 onto the shielding member 110 and directly covers the shielding member 110.

[0615] Figure 46 is an enlarged cross-sectional view showing the outer region 9 of the sixth modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 47 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 46. In Figures 46 and 47, semiconductor device 1A is shown as an example.

[0616] Referring to Figures 46 and 47, the shield structure 60 may also include an insulating shield member 110 embedded in the shield opening 61, as in the third modified example. In this embodiment, the shield member 110 has a single-layer structure consisting of a first insulator 111.

[0617] The first insulator 111 is embedded as a single unit in the shield opening 61, backfilling the shield opening 61. Within the shield opening 61, the first insulator 111 is in contact with the channel stop region 21 and the interlayer film 26 (first interlayer film 27 and second interlayer film 28).

[0618] The upper insulating film 80 does not necessarily have an organic film 85 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an organic film 85 and may have a single-layer structure consisting of an inorganic film 84.

[0619] In this configuration, the inorganic film 84 enters the shield opening 61 from above the interlayer film 26 and is connected to the shield member 110 (first insulator 111) within the shield opening 61. In this configuration, the inorganic film 84 is made of the same insulator as the shield member 110 (first insulator 111) and is integrally formed with the shield member 110 (first insulator 111).

[0620] Figure 48 is an enlarged cross-sectional view showing the outer region 9 of the seventh modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 49 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 48. In Figures 48 and 49, semiconductor device 1A is shown as an example.

[0621] Referring to Figures 48 and 49, the shield structure 60 may also include an insulating shield member 110 embedded in the shield opening 61, as in the third modified example. In this embodiment, the shield member 110 has a single-layer structure consisting of a second insulator 112.

[0622] The second insulator 112 is embedded as a single unit in the shield opening 61, backfilling the shield opening 61. Within the shield opening 61, the second insulator 112 is in contact with the channel stop region 21 and the interlayer film 26 (first interlayer film 27 and second interlayer film 28).

[0623] The upper insulating film 80 does not necessarily have an inorganic film 84 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an inorganic film 84 and may have a single-layer structure consisting of an organic film 85.

[0624] In this configuration, the organic film 85 enters the shield opening 61 from above the interlayer film 26 and is connected to the shield member 110 (second insulator 112) within the shield opening 61. In this configuration, the organic film 85 is made of the same insulator as the shield member 110 (second insulator 112) and is integrally formed with the shield member 110 (second insulator 112).

[0625] Figure 50 is an enlarged cross-sectional view showing the outer region 9 of the eighth modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 51 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 50. In Figures 50 and 51, semiconductor device 1A is shown as an example.

[0626] Referring to Figures 50 and 51, the shield structure 60 may include an insulating shielding member 110 embedded in the shield opening 61, as in the third modified example. In this embodiment, the shielding member 110 is embedded in the shield opening 61 as a single unit.

[0627] The shielding member 110 may have a single-layer structure consisting of a single insulator. In this case, the shielding member 110 may include a first insulator 111 or a second insulator 112. The shielding member 110 may have a laminated structure consisting of multiple insulators. In this case, the shielding member 110 may include a first insulator 111 and a second insulator 112.

[0628] In this configuration, the shield member 110 backfills the shield opening 61 and is in contact with the channel stop region 21 and the interlayer membrane 26 (first interlayer membrane 27 and second interlayer membrane 28) within the shield opening 61.

[0629] The shield member 110 has an insulating surface exposed from the shield opening 61. The insulating surface of the shield member 110 is formed with a gap between it and the insulating surface of the interlayer film 26, towards the bottom wall side of the shield opening 61. The insulating surface of the shield member 110 may have a recess toward the bottom wall of the shield opening 61. Of course, the insulating surface of the shield member 110 may be formed flat (flush) with respect to the insulating surface of the interlayer film 26.

[0630] In this embodiment, the upper insulating film 80 has a laminated structure including an inorganic film 84 and an organic film 85. In this embodiment, the inorganic film 84 is drawn out in a film-like manner from above the interlayer film 26 onto a plurality of shield structures 60. The inorganic film 84 is mechanically connected to the plurality of shield structures 60 and forms connection boundaries with the plurality of shield structures 60.

[0631] Specifically, the inorganic film 84 penetrates the multiple shield openings 61 from above the interlayer film 26 and coats the multiple shield members 110 in a film-like manner within the multiple shield openings 61. The inorganic film 84 forms connection boundaries with the insulating surfaces of the multiple shield members 110.

[0632] In this embodiment, the organic film 85 covers the multiple shield members 110 via the inorganic film 84. The organic film 85 may also cover the multiple shield members 110 via the inorganic film 84 within the multiple shield openings 61. The organic film 85 may also cover the multiple shield members 110 via the inorganic film 84 above the multiple shield openings 61.

[0633] The upper insulating film 80 does not necessarily have an inorganic film 84 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an inorganic film 84 and may have a single-layer structure consisting of an organic film 85.

[0634] The upper insulating film 80 does not necessarily have an organic film 85 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an organic film 85 and may have a single-layer structure consisting of an inorganic film 84.

[0635] Figure 52 is an enlarged cross-sectional view showing the outer region 9 of the ninth modified example of semiconductor devices 1A to 1C according to the first to third embodiments. Figure 53 is an enlarged cross-sectional view showing the shield structure 60 shown in Figure 52. In Figures 52 and 53, semiconductor device 1A is shown as an example.

[0636] Referring to Figures 52 and 53, the shield structure 60 does not necessarily have to include a shield electrode 62 and a shield member 110, and may have a hollow shield opening 61.

[0637] In this embodiment, the upper insulating film 80 has a laminated structure including an inorganic film 84 and an organic film 85. In this embodiment, the inorganic film 84 includes one or more (multiple in this embodiment) upper shield openings 115 communicating with a plurality of shield openings 61 on the interlayer film 26.

[0638] In this embodiment, the multiple upper shield openings 115 are formed in a one-to-one correspondence with the multiple shield openings 61, exposing the corresponding shield openings 61. In this embodiment, each of the multiple upper shield openings 115 has a side wall that communicates with the side wall of the corresponding shield opening 61. Of course, the inorganic film 84 may have one or more shield openings 61 that expose multiple (two or more) shield openings 61.

[0639] Multiple upper shield openings 115 extend in a strip-like shape following the extending direction of the corresponding shield opening 61. Each of the multiple upper shield openings 115 has a portion extending in a first direction X and a portion extending in a second direction Y in a plan view.

[0640] In this embodiment, the multiple upper shield openings 115 are formed as ended or endless polygonal rings (in this embodiment, quadrangular rings) having four sides parallel to the periphery of the first main surface 3. The multiple upper shield openings 115 may have corners that connect the portions extending in a first direction X and a second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0641] In this configuration, the organic film 85 conceals the multiple shield openings 61 (multiple upper shield openings 115) on top of the inorganic film 84. The organic film 85 may also penetrate the multiple upper shield openings 115 from above the inorganic film 84 and cover the side walls of the multiple upper shield openings 115.

[0642] In this case, the organic film 85 may be formed at a distance from the bottom walls (first main surface 3) of the multiple shield openings 61, and may partition the space SP between the organic film 85 and the bottom walls of the multiple shield openings 61. In other words, the organic film 85 may maintain the multiple shield openings 61 in a hollow state. The organic film 85 may be formed at a distance from the height of the opening ends of the multiple shield openings 61 toward the insulating surface side of the inorganic film 84, and may expose the entire wall surface of the multiple shield openings 61.

[0643] The organic film 85 has a portion located on the bottom wall side of the multiple shield openings 61 with respect to the height of the opening ends of the multiple shield openings 61, and may cover both the side walls of the multiple shield openings 61 and the side walls of the multiple upper shield openings 115. Of course, the organic film 85 may backfill the entire area of ​​the multiple shield openings 61 and be in contact with the bottom walls and side walls of the multiple shield openings 61.

[0644] The upper insulating film 80 does not necessarily have an inorganic film 84 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an inorganic film 84 and may have a single-layer structure consisting of an organic film 85. In these cases, the organic film 85 may conceal a plurality of shield openings 61 on the interlayer film 26. The organic film 85 may penetrate the plurality of shield openings 61 from above the interlayer film 26 and cover the side walls of the plurality of shield openings 61.

[0645] The organic film 85 may be formed at a distance from the bottom walls (first main surface 3) of the multiple shield openings 61, maintaining the multiple shield openings 61 in a hollow state. Of course, the organic film 85 may backfill the entire area of ​​the multiple shield openings 61 and be in contact with the bottom walls and side walls of the multiple shield openings 61.

[0646] The upper insulating film 80 does not necessarily have an organic film 85 in the covering portion for at least a plurality of shield structures 60. The upper insulating film 80 may not have an organic film 85 and may have a single-layer structure consisting of an inorganic film 84.

[0647] Figure 54 is an enlarged cross-sectional view showing the outer region 9 of the 10th modified example of semiconductor devices 1A to 1C according to the first to third embodiments. In Figure 54, semiconductor device 1A is shown as an example.

[0648] Referring to Figure 54, the channel stop region 21 has an n-type conductivity, and the multiple shield structures 60 may be connected to the n-type channel stop region 21. In this case, the channel stop region 21 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor device. The n-type impurity concentration of the channel stop region 21 may be higher or lower than the n-type impurity concentration of the source region 11.

[0649] Figure 55 is an enlarged cross-sectional view showing the outer region 9 of the 11th modified example of semiconductor devices 1A to 1C according to the first to third embodiments. In Figure 55, semiconductor device 1A is shown as an example.

[0650] Referring to Figure 55, semiconductor devices 1A to 1C do not necessarily have a channel stop region 21. In this case, the multiple shield structures 60 may be connected to the second semiconductor layer 7 in a region closer to the periphery of the first main surface 3 than to the multiple field regions 20.

[0651] Figure 56 is an enlarged cross-sectional view showing the outer region 9 of the 12th modified example of semiconductor devices 1A to 1C according to the first to third embodiments. In Figure 56, semiconductor device 1A is shown as an example.

[0652] Referring to Figure 56, the multiple shielding structures 60 may be formed at intervals from the first main surface 3 (chip 2) to the insulating surface side of the interlayer film 26. In other words, the multiple shielding structures 60 do not necessarily have to penetrate the interlayer film 26, and may be physically and electrically isolated from the chip 2 (channel stop region 21) by at least the main surface insulating film 25.

[0653] Multiple shield structures 60 may be formed at intervals from the main surface insulating film 25 to the insulating surface side of the interlayer film 26, and may face the first main surface 3 via the main surface insulating film 25 and a portion of the interlayer film 26. Multiple shield structures 60 may also penetrate the second interlayer film 28 to reach the first interlayer film 27, and may face the first main surface 3 via the main surface insulating film 25 and a portion of the second interlayer film 28.

[0654] Multiple shield structures 60 may be formed on the second interlayer film 28 at a distance from the first interlayer film 27, and may face the first main surface 3 via the main surface insulating film 25, the first interlayer film 27, and a portion of the second interlayer film 28.

[0655] The multiple shield structures 60 may include shield openings 61 partitioned by the interlayer membrane 26, and shield electrodes 62 embedded in the shield openings 61. The multiple shield structures 60 may also include shield openings 61 partitioned by the interlayer membrane 26, and shield members 110 embedded in the shield openings 61.

[0656] The configuration of the shield structure 60 according to the 12th modified example (a configuration in which the chip 2 is physically separated by at least the main surface insulating film 25) is also applicable to the shield structure 60 according to the first to 11th modified examples described above.

[0657] Figure 57 is a schematic diagram showing a module 121 on which at least one of the semiconductor devices 1A to 1C according to the first to third embodiments is mounted. In Figure 57, semiconductor device 1A is shown as an example. Module 121 may also be called a "semiconductor module" or "semiconductor package".

[0658] Referring to Figure 57, module 121 includes a rectangular parallelepiped package body 122. The package body 122 is made of a mold resin and includes a matrix resin (e.g., epoxy resin), a plurality of fillers, and a plurality of flexible particles (flexible agents). The package body 122 has a first surface 123 on one side, a second surface 124 on the other side, and first to fourth side walls 125A to 125D connecting the first surface 123 and the second surface 124.

[0659] The first surface 123 and the second surface 124 are formed in a rectangular shape in plan view. The first side wall 125A extends in the first direction X. The second side wall 125B extends in the second direction Y and is connected to the first side wall 125A. The third side wall 125C extends in the first direction X and is connected to the second side wall 125B. The fourth side wall 125D extends in the second direction Y and is connected to the first side wall 125A and the third side wall 125C.

[0660] Module 121 includes a conductive die pad 126 disposed within the package body 122. The die pad 126 may also be referred to as a "metal plate" or "conductor plate". The die pad 126 may be exposed from the second surface 124, or it may be positioned at a distance from the second surface 124 toward the first surface 123 and covered by the package body 122.

[0661] The die pad 126 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the first to fourth side walls 125A to 125D in a plan view. The die pad 126 includes a pull-out portion 126a that is pulled out to the outside through the first side wall 125A. The pull-out portion 126a has a circular through hole 126b.

[0662] Module 121 includes a plurality (three in this configuration) of lead terminals 127 that are drawn out from inside the package body 122 to the outside. The plurality of lead terminals 127 are arranged at intervals along the second side wall 125B on the second side wall 125B side, and each extends in a strip-like shape in a direction perpendicular to the second side wall 125B.

[0663] The lead terminals 127 on both sides are spaced apart from the die pad 126, and the central lead terminal 127 is mechanically and electrically connected to the die pad 126. The central lead terminal 127 may be integrally formed with the die pad 126. The number and arrangement of the lead terminals 127 are arbitrary.

[0664] Module 121 includes a semiconductor device 1A disposed on a die pad 126 within a package body 122. The semiconductor device 1A is positioned on the die pad 126 with its second main surface 4 facing the die pad 126 and is covered by the package body 122 (molding resin).

[0665] In other words, the multiple shield structures 60 (shielding electrodes 62 and shielding members 110) are covered by the package body 122 (molded resin) via the upper insulating film 80. If the upper insulating film 80 exposes the multiple shield structures 60, or if the semiconductor device 1A does not have the upper insulating film 80, the multiple shield structures 60 may be directly covered by the package body 122 (molded resin).

[0666] If the shield structure 60 does not include a shield electrode 62 or a shield member 110, the shield opening 61 may be sealed by the package body 122 (molded resin). In other words, the package body 122 (molded resin) may have a portion that enters the shield opening 61 from above the interlayer film 26 and is embedded in part or all of the shield opening 61.

[0667] Module 121 is interposed between the die pad 126 and the semiconductor device 1A and includes a conductive adhesive 128 that electrically connects the die pad 126 and the drain electrode 86. The conductive adhesive 128 may contain either solder or a metal paste, or both. The metal paste may be gold paste, silver paste, copper paste, etc.

[0668] The module 121 includes at least one (or more in this embodiment) conductors 129 that electrically connect the semiconductor device 1A and the lead terminals 127 within the package body 122. In this embodiment, the conductors 129 consist of metal wires (i.e., bonding wires).

[0669] The conductor 129 may include at least one of gold wire, copper wire, and aluminum wire. Of course, the conductor 129 may also be made of a metal plate such as a metal clip instead of a metal wire.

[0670] At least one (one in this embodiment) wire 129 is electrically connected to the gate electrode 73 and the gate lead terminal 127. At least one (four in this embodiment) wire 129 is electrically connected to the source electrode 70 and the source lead terminal 127. If the multiple lead terminals 127 include lead terminals 127 for current monitoring, at least one wire 129 may be electrically connected to the source electrode 70 and the current monitoring lead terminal 127.

[0671] When the semiconductor device 1B according to the second embodiment is mounted on the module 121, the semiconductor device 1B is mounted on the module 121 in the same manner as the semiconductor device 1A. When the semiconductor device 1C according to the third embodiment is mounted on the module 121, the cathode electrode 109 is electrically connected to the die pad 126 via a conductive adhesive 128, and at least one conductor 129 is electrically connected to the anode electrode 105 and the lead terminal 127 for the anode.

[0672] In this embodiment, an example is shown in which one semiconductor device 1A is placed on the die pad 126. However, multiple semiconductor devices 1A may be placed on the die pad 126. Of course, multiple semiconductor devices 1B may be placed on the die pad 126. Also, multiple semiconductor devices 1C may be placed on the die pad 126.

[0673] One or more semiconductor devices 1C may be placed together with one or more semiconductor devices 1A in the package body 122 as a freewheeling diode for one or more semiconductor devices 1A. In this case, one or more semiconductor devices 1C may be placed on the same die pad 126 as one or more semiconductor devices 1A, or they may be placed on a die pad 126 different from the die pad 126 of one or more semiconductor devices 1A.

[0674] One or more semiconductor devices 1C may be placed together with one or more semiconductor devices 1B in the package body 122 as a freewheeling diode for one or more semiconductor devices 1B. In this case, one or more semiconductor devices 1C may be placed on the same die pad 126 as one or more semiconductor devices 1B, or they may be placed on a die pad 126 different from the die pad 126 of one or more semiconductor devices 1B.

[0675] Each of the above-described embodiments (including variations) can be implemented in other forms. For example, the features (including variations) of semiconductor devices 1A to 1C can be combined among them as appropriate. Semiconductor devices 1A to 1C may simultaneously include two or three of the features (including variations) of semiconductor devices 1A to 1C.

[0676] For example, semiconductor devices 1A to 1C may simultaneously include at least two or three of the following in the active region 8: a planar transistor structure T (gate structure 15), a trench-type transistor structure T (gate structure 90), and a diode structure D.

[0677] If the semiconductor devices 1A to 1C include both a transistor structure T and a diode structure D, the diode structure D may be formed as a freewheeling diode for the transistor structure T. In this case, the source electrode 70 also serves as the anode electrode 105 for the diode structure D, and the drain electrode 86 also serves as the cathode electrode 109 for the diode structure D.

[0678] The active region 8 may be divided into a first region for the transistor structure T and a second region for the diode structure D. Of course, the diode structure D may be formed using a portion of the region of the transistor structure T.

[0679] For example, the diode structure D may have a diode region 100 (second semiconductor layer 7) selectively formed in the region between a plurality of adjacent planar gate structures 15 in a cross-sectional view. For example, the diode structure D may have a diode region 100 (second semiconductor layer 7) selectively formed in the region between a plurality of adjacent trench-type gate structures 90 in a cross-sectional view.

[0680] The semiconductor devices 1A to 1C described above had an upper insulating film 80 covering the multiple shield structures 60. However, the upper insulating film 80 may be formed with a gap inward from the multiple shield structures 60, exposing the multiple shield structures 60. Of course, semiconductor devices 1A to 1C without the upper insulating film 80 may also be used.

[0681] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the n-type semiconductor region is inverted to p-type, and the conductivity type of the p-type semiconductor region is inverted to n-type. The specific configuration in this case can be obtained by replacing n-type with p-type and simultaneously replacing p-type with n-type in the above description and attached drawings.

[0682] In the embodiments described above, an n-type first semiconductor layer 6 was shown. However, the conductivity type of the first semiconductor layer 6 may be p-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, as explained above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure.

[0683] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components of the aforementioned forms, but this is not intended to limit the scope of each item (Clause) to the aforementioned forms. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," etc., as needed.

[0684] [A1] A semiconductor device (1A, 1B, 1C) comprising a chip (2), an insulating film (26) covering the chip (2), and a shielding opening (61) formed in the insulating film (26) at the peripheral edge of the chip (2), which divides the insulating film (26) into an inner region (26a) of the chip (2) and a peripheral region (26b) of the chip (2).

[0685] [A2] The chip (2) is a semiconductor device (1A, 1B, 1C) as described in A1, which includes SiC.

[0686] [A3] The semiconductor device (1A, 1B, 1C) according to A1 or A2, wherein the shield opening (61) penetrates the insulating film (26) and divides the insulating film (26) into an inner region (26a) of the chip (2) and a peripheral region (26b) of the chip (2).

[0687] [A4] The semiconductor device (1A, 1B, 1C) according to any one of A1 to A3, wherein the shield opening (61) has an opening width less than the thickness of the insulating film (26) and extends vertically in the thickness direction (Z) of the insulating film (26).

[0688] [A5] The shielding opening (61) extends in a strip shape along the periphery of the chip (2) in a plan view, as described in any one of A1 to A4 (1A, 1B, 1C).

[0689] [A6] The shielding opening (61) is formed in an annular shape surrounding the inner part of the chip (2) in a plan view, as described in any one of A1 to A5 (1A, 1B, 1C).

[0690] [A7] A semiconductor device according to any one of A1 to A6 (1A, 1B, 1C), wherein a plurality of shielding openings (61) are formed in the insulating film (26) at intervals.

[0691] [A8] A semiconductor device according to any one of A1 to A7 (1A, 1B, 1C), further comprising a shield member (62, 110) made of a material different from the insulating film (26) and embedded in the shield opening (61).

[0692] [A9] The semiconductor device (1A, 1B, 1C) described in A8, wherein the shielding member (62, 110) is in contact with the chip (2) within the shielding opening (61).

[0693] [A10] The shielding member (62, 110) is a semiconductor device (1A, 1B, 1C) according to A8 or A9, which includes metal.

[0694] [A11] The shielding member (62, 110) is a semiconductor device (1A, 1B, 1C) according to A10, which includes a tungsten-based metal.

[0695] [A12] A semiconductor device according to any one of A1 to A11 (1A, 1B, 1C), further comprising an upper insulating film (80) that covers the shield opening (61) on the insulating film (26).

[0696] [A13] The semiconductor device (1A, 1B, 1C) according to A12, wherein the upper insulating film (80) contains an insulating material different from the insulating film (26).

[0697] [A14] The semiconductor device (1A, 1B, 1C) according to A12 or A13, wherein the upper insulating film (80) has a single-layer structure or a multilayer structure including either or both of an inorganic film (84) and an organic film (85).

[0698] [A15] The semiconductor device (1A, 1B, 1C) described in A14, wherein the organic film (85) is made of a photosensitive resin film.

[0699] [A16] A semiconductor device according to any one of A1 to A15 (1A, 1B, 1C), further comprising one or more electrodes (70, 72, 73, 74, 105) disposed on the insulating film (26) at a distance from the shield opening (61) inward of the chip (2).

[0700] [A17] A semiconductor device according to any one of A1 to A16 (1A, 1B, 1C), further comprising a field region (20) formed on the surface layer of the chip (2) at the peripheral edge of the chip (2), wherein the shielding opening (61) is formed at a distance from the field region (20) toward the peripheral edge of the chip (2).

[0701] [A18] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A17, further comprising: an active region (8) provided in the inner part of the chip (2); an outer region (9) provided in the peripheral part of the chip (2); and a device structure (T, D) formed in the active region (8), wherein the insulating film (26) selectively covers the chip (2) in the outer region (9); and the shielding opening (61) is formed in the insulating film (26) in the outer region (9).

[0702] [A19] The semiconductor device (1A, 1B, 1C) according to A18, wherein the device structure (T, D) includes either or both of a transistor structure (T) and a diode structure (D).

[0703] [A20] The semiconductor device (1A, 1B, 1C) according to A19, wherein the transistor structure (T) includes either or both of a planar gate structure (15) and a trench gate structure (90).

[0704] Although specific forms have been described in detail above, these are merely examples to illustrate the technical content. The various technical ideas extracted from this specification can be combined as appropriate, without being limited by the order of explanation, the order of the examples of forms, the order of the modifications, etc.

[0705] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 2 Chip 8 Active region 9 Outer region 15 Planar gate structure 20 Field region 26 Interlayer film (insulating film) 26a Inner region 26b Outer region 61 Shield opening 62 Shield electrode (shielding member) 70 Source electrode (electrode) 72 Source wiring (electrode) 73 Gate electrode (electrode) 74 Gate wiring 80 Upper insulating film 84 Inorganic film 85 Organic film 90 Trench gate structure 105 Anode electrode (electrode) 110 Shielding member T Transistor structure (device structure) D Diode structure (device structure)

Claims

1. A semiconductor device comprising: a chip; an insulating film covering the chip; and a shielding aperture formed in the insulating film at the peripheral edge of the chip, which divides the insulating film into an inner region of the chip and a peripheral region of the chip.

2. The semiconductor device according to claim 1, wherein the chip includes SiC.

3. The semiconductor device according to claim 1 or 2, wherein the shielding opening penetrates the insulating film and divides the insulating film into an inner region of the chip and a peripheral region of the chip.

4. The semiconductor device according to any one of claims 1 to 3, wherein the shielding opening has an opening width less than the thickness of the insulating film and extends longitudinally in the thickness direction of the insulating film.

5. The semiconductor device according to any one of claims 1 to 4, wherein the shielding aperture extends in a band shape along the periphery of the chip in a plan view.

6. The semiconductor device according to any one of claims 1 to 5, wherein the shielding aperture is formed in an annular shape surrounding the inner portion of the chip in a plan view.

7. The semiconductor device according to any one of claims 1 to 6, wherein a plurality of shielding openings are formed in the insulating film at intervals.

8. The semiconductor device according to any one of claims 1 to 7, further comprising a shield member made of a material different from the insulating film and embedded in the shield opening.

9. The semiconductor device according to claim 8, wherein the shielding member is in contact with the chip within the shielding opening.

10. The semiconductor device according to claim 8 or 9, wherein the shielding member includes a metal.

11. The semiconductor device according to claim 10, wherein the shielding member includes a tungsten-based metal.

12. The semiconductor device according to any one of claims 1 to 11, further comprising an upper insulating film that covers the shielding opening on the insulating film.

13. The semiconductor device according to claim 12, wherein the upper insulating film comprises an insulating material different from the insulating film.

14. The semiconductor device according to claim 12 or 13, wherein the upper insulating film has a single-layer structure or a multilayer structure comprising either an inorganic film or an organic film or both.

15. The semiconductor device according to claim 14, wherein the organic film is made of a photosensitive resin film.

16. The semiconductor device according to any one of claims 1 to 15, further comprising one or more electrodes disposed on the insulating film at a distance from the shield opening inward from the chip.

17. The semiconductor device according to any one of claims 1 to 16, further comprising a field region formed on the surface layer of the chip at the periphery of the chip, wherein the shielding opening is formed at a distance from the field region toward the periphery of the chip.

18. A semiconductor device according to any one of claims 1 to 17, further comprising: an active region provided in the inner part of the chip; an outer region provided in the peripheral edge of the chip; and a device structure formed in the active region, wherein the insulating film selectively covers the chip in the outer region, and the shielding opening is formed in the insulating film in the outer region.

19. The semiconductor device according to claim 18, wherein the device structure includes either a transistor structure or a diode structure or both.

20. The semiconductor device according to claim 19, wherein the transistor structure includes either a planar gate structure or a trench gate structure or both.

Images