Semiconductor device

Abstract

This semiconductor device includes an object to be connected containing silicon, an insulating interlayer film for covering the object to be connected, a via hole formed in the interlayer film and having a via bottom wall partitioned by the object to be connected, a silicide formed following the via bottom wall in the via hole, and a via electrode electrically connected to the object to be connected via the silicide in the via hole.

Description

Semiconductor device

[0001] This application claims priority based on Patent Application No. 2024-195398 filed with the Japan Patent Office on November 7, 2024, and the entire content of this application is incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US6355553B1) discloses a semiconductor device including a Si substrate, an insulating film, a contact hole, and a metal plug. The insulating film is laminated on the Si substrate. The contact hole is formed in the insulating film. The metal plug includes a metal film and a planarization layer and is connected to the Si substrate within the contact hole.

[0003] U.S. Patent No. 6355553

[0004] [Summary] The present disclosure provides a semiconductor device that contributes to improving electrical characteristics.

[0005] The present disclosure provides a semiconductor device including a connection target including silicon, an insulating interlayer film covering the connection target, a via hole formed in the interlayer film and having a via bottom wall partitioned by the connection target, a silicide formed in the via hole following the via bottom wall, and a via electrode electrically connected to the connection target through the silicide within the via hole.

[0006] The present disclosure provides a semiconductor device including a connection target, an insulating interlayer film covering the connection target, a first hole portion partitioned by a first width on the insulating surface side of the interlayer film, a second hole portion partitioned by a second width less than the first width on the connection target side with respect to the first hole portion, a via bottom wall partitioned by the connection target, and a via hole having a stepped portion partitioned between the first hole portion and the second hole portion, a first covering portion in film form for the first hole portion, a second covering portion in film form for the second hole portion, a third covering portion in film form for the via bottom wall, and a fourth covering portion in film form for the stepped portion, a via bottom electrode, and a via main electrode embedded in the via hole through the via bottom electrode and electrically connected to the connection target through the via bottom electrode.

[0007] This disclosure provides a semiconductor device comprising: a silicon-containing chip; a gate structure formed on the chip; an insulating interlayer film covering the gate structure on the chip; a via hole formed in the interlayer film on the side of the gate structure and having a via bottom wall partitioned by the chip; a silicide formed within the via hole following the via bottom wall; and a via electrode connected to the silicide within the via hole.

[0008] This disclosure provides a semiconductor device comprising: a silicon-containing chip; a planar electrode disposed on the chip; an insulating interlayer film covering the planar electrode on the chip; a via hole formed in the interlayer film on the side of the planar electrode and having a via bottom wall partitioned by the chip; a silicide formed within the via hole following the via bottom wall; and a via electrode connected to the silicide within the via hole.

[0009] This disclosure provides a semiconductor device comprising: a connection target containing polysilicon; an insulating interlayer film covering the connection target; a via hole formed in the interlayer film and having a via bottom wall partitioned by the connection target; a polyside formed within the via hole following the via bottom wall; and a via electrode connected to the polyside within the via hole.

[0010] The aforementioned or any other purposes, features, and effects will be revealed in the detailed description with reference to the attached drawings.

[0011] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface. Figure 4 is an enlarged plan view showing an example of the layout of the active region shown in Figure 3. Figure 5 is an enlarged plan view showing an example of the layout of the body region shown in Figure 4. Figure 6 is an enlarged plan view showing an example of the layout of the gate structure shown in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 4. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 4. Figure 10 is an enlarged cross-sectional view showing the main part of the configuration shown in Figure 6. Figure 11 is a further enlarged cross-sectional view showing the main part of the configuration shown in Figure 10. Figure 12 is a plan view showing an example of the layout of planar wiring. Figure 13 is an enlarged plan view showing the main part of the active region shown in Figure 12. Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 13. Figure 15 is an enlarged cross-sectional view showing the main part of the configuration shown in Figure 14. Figure 16 is a further enlarged cross-sectional view showing the main part of the configuration shown in Figure 15. Figure 17 is an enlarged cross-sectional view showing via holes according to another embodiment. Figure 18 is an enlarged cross-sectional view showing via holes according to the first embodiment. Figure 19 is an enlarged plan view showing the main part of the active region of the semiconductor device according to the second embodiment. Figure 20 is a cross-sectional view along the line XX-XX shown in Figure 19. Figure 21 is a cross-sectional view along the line XXI-XXI shown in Figure 19. Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 19. Figure 23 is a cross-sectional view along the line XXIII-XXIII shown in Figure 19. Figure 24 is an enlarged cross-sectional view showing the main part of the configuration shown in Figure 20. Figure 25 is a cross-sectional view showing a via structure according to a modified example. Figure 26 is a cross-sectional view showing a wiring via structure according to a modified example.

[0012] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0013] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." In this specification, "substantially" includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) being compared.

[0014] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0015] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0016] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0017] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example layout of the first main surface 3. Figure 4 is an enlarged plan view showing an example layout of the active region 8 shown in Figure 3. Figure 5 is an enlarged plan view showing an example layout of the body region 10 shown in Figure 4.

[0018] Figure 6 is an enlarged plan view showing an example layout of the gate structure 16 shown in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 4. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 4.

[0019] Referring to Figures 1 to 9, semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure T as an example of a device structure (functional device). The transistor structure T has a planar gate type vertical structure.

[0020] The semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 2 may include a single crystal of Si (silicon) and / or a single crystal of a wide-bandgap semiconductor. A wide-bandgap semiconductor is a semiconductor having a bandgap greater than that of Si. Examples of wide-bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).

[0021] In this embodiment, chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, semiconductor device 1A is a "wide-bandgap semiconductor device". Chip 2 may also be called a "semiconductor chip", "wide-bandgap semiconductor chip", etc. In this embodiment, chip 2 is a "SiC chip" including a hexagonal SiC single crystal. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0022] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0023] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed in plan from the thickness direction Z of the chip 2 (hereinafter simply referred to as "plan view"). The thickness direction Z is also the normal direction (vertical direction) to the first main surface 3 and the second main surface 4.

[0024] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0025] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0026] The first direction X may be the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y may be the m-axis direction ([1-100] direction) of the SiC single crystal. The first direction X may be the m-axis direction, and the second direction Y may be the a-axis direction. The first direction X may be a direction that intersects both the a-axis direction and the m-axis direction, and the second direction Y may be a direction that intersects both the a-axis direction and the m-axis direction.

[0027] In the following, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is the direction along the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction (thickness direction Z).

[0028] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the amount of the off-angle from the thickness direction Z (vertical line) toward the off-direction. The off-direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The off-direction may also be the m-axis direction of the SiC single crystal.

[0029] The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0030] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0031] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in the region on the second main surface 4 side within the chip 2. The first semiconductor layer 6 may also be referred to as the "first layer (region)," the "drain layer (region)," etc. The first semiconductor layer 6 extends in layers along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0032] The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the first semiconductor layer 6 is a semiconductor substrate (SiC substrate) containing a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. Of course, the first semiconductor layer 6 may be made of other polytypes. The first semiconductor layer 6 may be made of a 3C-SiC polycrystal.

[0033] The first semiconductor layer 6 may have a thickness greater than 0 μm and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: greater than 0 μm and 10 μm or less, 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0034] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in the region on the first main surface 3 side relative to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may also be referred to as the "second layer (region)," "drain layer (region)," "drift layer (region)," etc. The second semiconductor layer 7 has an n-type impurity concentration lower than that of the first semiconductor layer 6.

[0035] The second semiconductor layer 7 is stacked on top of the first semiconductor layer 6. The second semiconductor layer 7 extends in layers along the first main surface 3 (first semiconductor layer 6), forming the first main surface 3 and the first to fourth side surfaces 5A to 5D. The second semiconductor layer 7 contains a single crystal of a wide-bandgap semiconductor. In this embodiment, the second semiconductor layer 7 is a semiconductor layer (SiC layer) containing a hexagonal SiC single crystal.

[0036] In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer containing a 4H-SiC single crystal (hexagonal) and has the aforementioned off-direction and off-angle. Of course, the second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0037] The second semiconductor layer 7 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may be a value that falls within at least one of the following ranges: greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0038] The semiconductor device 1A includes an active region 8 provided on the first main surface 3. The active region 8 includes a device structure (transistor structure T) and is a region where an output current (drain current) is generated. The active region 8 is provided in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.

[0039] The active region 8 is provided in a polygonal shape having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the active region 8 is provided in a polygonal shape having a rectangular recess in the center of the side along the first side surface 5A toward the third side surface 5C.

[0040] The semiconductor device 1A includes a non-active region 9 located outside the active region 8 on the first main surface 3. The non-active region 9 is a region that does not include the device structure (transistor structure T) and is located around the active region 8. In this embodiment, the non-active region 9 includes a pad region 9a and an outer region 9b.

[0041] The pad region 9a is provided in a portion along the central portion of the first side surface 5A, and demarcates the concave portion of the active region 8. The outer region 9b is provided in a region between the periphery of the first main surface 3 and the active region 8. The outer region 9b extends in a strip shape along the active region 8 in plan view, and is provided in a polygonal annular shape (in this form, a square annular shape) surrounding the active region 8. The outer region 9b is connected to the pad region 9a in the region on the first side surface 5A side.

[0042] The semiconductor device 1A includes a plurality of p-type body regions 10 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The body region 10 may be referred to as an "impurity region" or the like. The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0043] The plurality of body regions 10 are formed in the active region 8 at intervals from the periphery of the first main surface 3, and are not formed in the inactive region 9. The plurality of body regions 10 are formed in the surface layer portion of the first main surface 3 at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3 side, and face the first semiconductor layer 6 through a part of the second semiconductor layer 7.

[0044] The plurality of body regions 10 are arranged at intervals in a row in the first direction X, and each extend in a strip shape in the first direction X. With respect to the plurality of body regions 10 on one side and the other side in the second direction Y, the plurality of body regions 10 on the other side are arranged shifted in the first direction X with respect to the plurality of body regions 10 on one side, and face the region between the plurality of body regions 10 on one side in the second direction Y.

[0045] That is, in this form, the plurality of body regions 10 are arranged in a staggered pattern at intervals in the first direction X and the second direction Y in plan view. Of course, the plurality of body regions 10 may be arranged at intervals in a row in the second direction Y. That is, the plurality of body regions 10 may be arranged in a matrix pattern at intervals in the first direction X and the second direction Y in plan view.

[0046] The plurality of body regions 10 are formed with a first interval in the first direction X and a second interval in the second direction Y. The first interval may be larger or smaller than the width of each body region 10. The second interval may be larger or smaller than the width of each body region 10. The second interval may be larger or smaller than the first interval.

[0047] The plurality of body regions 10 form pn junctions with the second semiconductor layer 7. Thereby, a pn junction diode Di1 (bipolar diode) having the second semiconductor layer 7 as a cathode and the plurality of body regions 10 as anodes is formed. The pn junction diode Di1 functions as a reflux diode for the transistor structure T.

[0048] The semiconductor device 1A includes a plurality of n-type surface drift regions 11 formed in a region between the plurality of body regions 10 in the surface layer portion of the first main surface 3. The surface drift regions 11 may be referred to as "impurity regions". The surface drift regions 11 are respectively partitioned in a region between the plurality of body regions 10 adjacent to each other in the second direction Y and extend in a strip shape in the first direction X.

[0049] In this form, the surface drift regions 11 are each formed from a part of the second semiconductor layer 7 and have an n-type impurity concentration substantially equal to the n-type impurity concentration of the second semiconductor layer 7. The n-type impurity concentration of the surface drift regions 11 may be higher or lower than the n-type impurity concentration of the second semiconductor layer 7.

[0050] The semiconductor device 1A includes an n-type diode region 12 formed in a region between the plurality of body regions 10 in the surface layer portion of the first main surface 3. The diode regions 12 may be referred to as "impurity regions". The plurality of diode regions 12 are respectively partitioned in a region between the plurality of body regions 10 adjacent to each other in the first direction X.

[0051] Multiple diode regions 12 are connected in a T-shape to multiple adjacent surface drift regions 11 in the second direction Y. The total surface area of ​​the multiple diode regions 12 is less than the total surface area of ​​the multiple body regions 10. Each diode region 12 has a width less than the width of the body region 10 in the second direction Y with respect to the first direction X, and extends in a strip shape in the second direction Y. The width of the diode regions 12 may be greater than the width of the body region 10.

[0052] In this configuration, each diode region 12 consists of a part of the second semiconductor layer 7 and has an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. In other words, the diode region 12, together with the second surface drift region 11, forms a mesh-like (lattice-like) drift region as a second surface drift region 11. The n-type impurity concentration of the diode region 12 may be higher or lower than that of the second semiconductor layer 7.

[0053] The semiconductor device 1A includes a plurality of n-type source regions 13 formed on the surface of a plurality of body regions 10. The source regions 13 may also be referred to as "impurity regions," etc. The source regions 13 have an n-type impurity concentration higher than the p-type impurity concentration of the body regions 10.

[0054] The n-type impurity concentration in the source region 13 is higher than the n-type impurity concentration in the second semiconductor layer 7. The n-type impurity concentration in the source region 13 is higher than the n-type impurity concentration in the surface drift region 11 and the n-type impurity concentration in the diode region 12.

[0055] In this configuration, the multiple source regions 13 are formed on the surface of the multiple body regions 10 in a one-to-one correspondence. The multiple source regions 13 are formed in the inner part of the corresponding body region 10, spaced apart from the periphery of the corresponding body region 10.

[0056] In this configuration, the multiple source regions 13 each extend in a strip-like manner in the first direction X, following the direction of extension of the multiple body regions 10. The multiple source regions 13 face the surface drift region 11 in the second direction Y via a portion of the corresponding body region 10, and face the diode region 12 in the first direction X via a portion of the corresponding body region 10. The multiple source regions 13 face the multiple body regions 10 and one diode region 12 in the second direction Y.

[0057] Multiple source regions 13 are formed at intervals from the bottom of the corresponding body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a portion of the corresponding body region 10. The multiple source regions 13 may be formed in a one-to-many correspondence with respect to one corresponding body region 10. In this case, the multiple source regions 13 may be formed at intervals in the first direction X on the surface of the corresponding body region 10.

[0058] The semiconductor device 1A includes a plurality of p-type contact regions 14 formed on the surface of each of the plurality of body regions 10. The contact regions 14 may also be referred to as "impurity regions," etc. The plurality of contact regions 14 have a higher p-type impurity concentration than the p-type impurity concentration of the plurality of body regions 10.

[0059] In this configuration, the multiple contact regions 14 are formed on the surface of the multiple body regions 10 in a one-to-one correspondence. The multiple contact regions 14 penetrate the corresponding source region 13 in the thickness direction Z within the inner part of the corresponding body region 10.

[0060] In this configuration, the multiple contact regions 14 are formed in the widthwise middle portion of the corresponding body region 10, spaced inward from the periphery of the corresponding source region 13, and extend in a strip-like manner in the first direction X, following the extending direction of the corresponding body region 10. The multiple contact regions 14 face the multiple body regions 10 and one diode region 12 in the second direction Y.

[0061] Multiple contact regions 14 are formed at intervals from the bottom of the corresponding body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a portion of the corresponding body region 10. In this embodiment, the multiple contact regions 14 have a depth greater than the depth of the multiple source regions 13. The depth of the multiple contact regions 14 may be less than the depth of the multiple source regions 13.

[0062] Multiple contact regions 14 may be formed in a one-to-many correspondence with respect to a single corresponding body region 10. In this case, the multiple contact regions 14 may be formed at intervals in the first direction X on the surface of the single corresponding body region 10. If multiple source regions 13 are formed on the surface of the single corresponding body region 10, the multiple contact regions 14 may be arranged alternately with the multiple source regions 13 in the first direction X.

[0063] The semiconductor device 1A includes a plurality of p-type channel regions 15 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The plurality of channel regions 15 have a p-type impurity concentration lower than the p-type impurity concentration of the plurality of contact regions 14.

[0064] In this configuration, each of the multiple channel regions 15 consists of a part of the multiple body regions 10 and has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the multiple body regions 10. The p-type impurity concentration of the channel region 15 may be higher or lower than the p-type impurity concentration of the body region 10.

[0065] Multiple channel regions 15 are each partitioned in the surface portion of multiple body regions 10, between multiple source regions 13 and multiple surface drift regions 11 (second semiconductor layer 7), forming current paths that connect the multiple source regions 13 and multiple surface drift regions 11 in the horizontal direction.

[0066] In this configuration, the multiple channel regions 15 are each partitioned in the surface layer of the multiple body regions 10 into regions between the multiple source regions 13 and the multiple diode regions 12 (second semiconductor layer 7), forming current paths that connect the multiple source regions 13 and the multiple diode regions 12 in the horizontal direction.

[0067] The semiconductor device 1A includes a planar type (planar electrode type) gate structure 16 disposed on the first main surface 3 in the inner portion (active region 8) of the first main surface 3. The gate structure 16 may also be referred to as a "planar structure," etc.

[0068] The gate structure 16 is positioned on the channel region 15 (the peripheral edge of the body region 10) and controls the inversion and non-inversion of the channel region 15 from above the first main surface 3. The gate structure 16 has a stacked structure including a gate insulating film 17 and a gate electrode 18.

[0069] The gate insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 17 has a single-layer structure made of a silicon oxide film. The gate insulating film 17 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The gate insulating film 17 may include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0070] The gate insulating film 17 may have a thickness greater than 0 nm and less than or equal to 150 nm. The thickness of the gate insulating film 17 may have a value that falls within at least one of the following ranges: greater than 0 nm and less than or equal to 10 nm, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0071] The gate insulating film 17 selectively covers the first main surface 3. Specifically, the gate insulating film 17 forms a film over a plurality of body regions 10, a plurality of source regions 13, a plurality of contact regions 14, a plurality of surface drift regions 11, and a plurality of diode regions 12 on the first main surface 3.

[0072] The gate electrode 18 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. A gate potential is applied to the gate electrode 18 as a control potential. The gate electrode 18 has a thickness greater than the thickness of the gate insulating film 17.

[0073] The thickness of the gate electrode 18 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the gate electrode 18 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0074] The gate electrode 18 is arranged in a film-like manner on the gate insulating film 17 and faces the channel region 15 (the peripheral edge of the body region 10) via the gate insulating film 17. In this embodiment, the gate electrode 18 is laid in a mesh-like (lattice-like) pattern on the gate insulating film 17 and has multiple portions that span the peripheral edges of multiple body regions 10, and multiple portions that intersect multiple body regions 10 in three dimensions.

[0075] Specifically, the gate electrode 18 includes a plurality of first gate electrodes 18A and a plurality of second gate electrodes 18B. The plurality of first gate electrodes 18A each extend in a strip shape in a first direction X and are arranged with intervals in a second direction Y. In other words, the plurality of first gate electrodes 18A extend in a stripe shape in the first direction X, following the layout of the plurality of body regions 10.

[0076] Each of the multiple first gate electrodes 18A is positioned on the region between multiple adjacent body regions 10 in the second direction Y (i.e., multiple surface drift regions 11). Each first gate electrode 18A straddles the periphery of the multiple body regions 10 on one side and the other side in the second direction Y.

[0077] Specifically, each first gate electrode 18A spans multiple source regions 13 on one and the other side of the second direction Y. Each first gate electrode 18A faces the surface drift region 11, multiple channel regions 15 on one side of the second direction Y, and multiple channel regions 15 on the other side of the second direction Y.

[0078] The first gate electrode 18A may have a width greater than 0 μm and less than or equal to 3 μm. The width of the first gate electrode 18A may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0079] The spacing between multiple first gate electrodes 18A may be greater than the width of the first gate electrode 18A. The spacing between the first gate electrodes 18A may be less than the width of the first gate electrode 18A. The spacing between the first gate electrodes 18A may be greater than 0 μm and 3 μm or less.

[0080] The spacing of the first gate electrodes 18A may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0081] Multiple second gate electrodes 18B extend in a strip-like manner in the second direction Y within the inter-gate regions between multiple first gate electrodes 18A, and are connected to two adjacent first gate electrodes 18A in the second direction Y. The number of second gate electrodes 18B arranged in the inter-gate regions is arbitrary. A single second gate electrode 18B may be arranged in the inter-gate regions. In this embodiment, multiple second gate electrodes 18B are arranged in the inter-gate regions at intervals in the first direction X.

[0082] Each of the multiple second gate electrodes 18B has one end connected to the first gate electrode 18A on one side of the second direction Y, and the other end connected to the first gate electrode 18A on the other side of the second direction Y, forming a current path connecting the multiple first gate electrodes 18A in the second direction Y. Together with the multiple first gate electrodes 18A, the multiple second gate electrodes 18B form a single gate electrode 18 that extends in a mesh-like (lattice-like) pattern.

[0083] In this configuration, the multiple second gate electrodes 18B are arranged at intervals in the first direction X from the multiple diode regions 12 and intersect the multiple body regions 10 in a one-to-one correspondence. The multiple second gate electrodes 18B have a width less than the width of the multiple body regions 10 with respect to the first direction X and intersect the corresponding source region 13 in the inner part (central part in this configuration) of the corresponding body region 10.

[0084] In this embodiment, the multiple second gate electrodes 18B are formed in a one-to-one correspondence with the multiple contact regions 14 and are positioned on the corresponding contact regions 14. The multiple second gate electrodes 18B have a width less than the width of the multiple contact regions 14 with respect to the first direction X and intersect three-dimensionally in the inner part (central part in this embodiment) of the corresponding contact region 14.

[0085] Multiple second gate electrodes 18B are positioned spaced apart from the edges (both ends in this embodiment) of the corresponding contact region 14, exposing the edges (both ends) of the contact region 14. Multiple second gate electrodes 18B are located inward from both edges of the corresponding body region 10 with respect to the second direction Y, and do not overlap with multiple surface drift regions 11 in the thickness direction Z.

[0086] With respect to the multiple second gate electrodes 18B on one and the other side of the second direction Y, the multiple second gate electrodes 18B on the other side are offset in the first direction X from the multiple second gate electrodes 18B on the one side.

[0087] In other words, the multiple second gate electrodes 18B on the other side are facing the second direction Y in the region between the multiple second gate electrodes 18B on the one side. As a result, the multiple second gate electrodes 18B are each connected to the multiple first gate electrodes 18A in a T-shape, and together with the multiple first gate electrodes 18A, they form a T-shaped current path.

[0088] The multiple second gate electrodes 18B, together with the multiple first gate electrodes 18A, define multiple electrode openings 19 that partially expose the gate insulating film 17. The multiple electrode openings 19 span multiple (two in this embodiment) adjacent body regions 10 in the first direction X, across one or more (one in this embodiment) diode regions 12 in a plan view. That is, the multiple electrode openings 19 overlap one body region 10 in the first direction X, the other body region 10 in the first direction X, and one diode region 12, respectively.

[0089] In this configuration, the multiple electrode openings 19 span the ends of multiple (two in this configuration) adjacent contact regions 14 in the first direction X. The multiple electrode openings 19 expose one end of the body region 10, source region 13, and contact region 14 on one side in the first direction X, and expose the other end of the body region 10, source region 13, and contact region 14 on the other side in the first direction X.

[0090] Of course, the multiple electrode openings 19 may span across the multiple diode regions 12 and extend to three or more adjacent body regions 10 in the first direction X, exposing the multiple body regions 10, multiple source regions 13, multiple contact regions 14, and multiple diode regions 12.

[0091] When multiple body regions 10 are arranged in a matrix, the multiple second gate electrodes 18B on the other side may face the multiple second gate electrodes 18B on one side in the second direction Y. In this case, the multiple second gate electrodes 18B may be connected to the multiple first gate electrodes 18A in a cross shape, forming a cross-shaped current path. In this case, the multiple electrode openings 19 may be partitioned in a matrix with spacing in the first direction X and the second direction Y.

[0092] The width of the second gate electrode 18B in the first direction X may be greater than or less than the width of the first gate electrode 18A in the second direction Y. The width of the second gate electrode 18B may be approximately equal to the width of the first gate electrode 18A. Preferably, the width of the second gate electrode 18B is not less than the width of the first gate electrode 18A.

[0093] The width ratio of the width of the second gate electrode 18B to the width of the first gate electrode 18A may be 0.5 or more and 3 or less. The width ratio may have a value that belongs to at least one of the following ranges: 0.5 or more and 1 or less, 1 or more and 1.5 or less, 1.5 or more and 2 or less, 2 or more and 2.5 or less, and 2.5 or more and 3 or less.

[0094] The semiconductor device 1A includes a p-type well region 20 formed in the second semiconductor layer 7 at the peripheral edge (inactive region 9) of the first main surface 3. The well region 20 may also be referred to as an "impurity region," etc. The well region 20 has a p-type impurity concentration lower than that of the contact region 14.

[0095] The p-type impurity concentration in the well region 20 may be approximately equal to the p-type impurity concentration in the body region 10. The p-type impurity concentration in the well region 20 may be higher or lower than the p-type impurity concentration in the body region 10.

[0096] The well region 20 is formed in the inactive region 9 on the surface of the first main surface 3. The well region 20 is formed with a gap between the bottom of the second semiconductor layer 7 and the first main surface 3. In this embodiment, the well region 20 has a depth approximately equal to the depth of the body region 10. The depth of the well region 20 may be greater or less than the depth of the body region 10.

[0097] In this embodiment, the well region 20 includes a pad well region 20a and an outer well region 20b. The pad well region 20a is formed in the surface layer of the first main surface 3 in the pad region 9a. The pad well region 20a is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0098] In this embodiment, the pad well region 20a has a planar shape similar to the planar shape of the pad region 9a. The pad well region 20a may be drawn out from the pad region 9a to the active region 8 and connected (electrically connected) to the body region 10 at the surface layer of the first main surface 3.

[0099] The outer well region 20b is formed in the outer region 9b on the surface of the first main surface 3. The outer well region 20b is formed at a distance from the periphery of the first main surface 3 toward the inward side of the first main surface 3, extends in a band shape along the active region 8, and demarcates the active region 8 from the periphery side of the first main surface 3.

[0100] The outer well region 20b has a portion extending in a first direction X and a portion extending in a second direction Y in a plan view, and divides the active region 8 from multiple directions. The outer well region 20b may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter arc shape) in a plan view.

[0101] In this embodiment, the outer well region 20b is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8. The outer well region 20b may be drawn out from the outer region 9b to the active region 8 and connected (electrically connected) to the body region 10. The outer well region 20b may have a width greater than the width of the body region 10.

[0102] The well region 20 forms a pn junction with the second semiconductor layer 7. This forms a pn junction diode Di1 having the second semiconductor layer 7 as the cathode and the well region 20 as the anode. The pn junction diode Di1 on the well region 20 side functions as a freewheeling diode for the transistor structure T together with the pn junction diode Di1 on the body region 10 side.

[0103] The semiconductor device 1A includes a main surface insulating film 21 that selectively covers the first main surface 3. The main surface insulating film 21 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 21 has a single-layer structure made of a silicon oxide film.

[0104] The main surface insulating film 21 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The main surface insulating film 21 may also include a silicon oxide film containing oxides other than the oxide of the chip 2. The main surface insulating film 21 may also include the same insulating material as the gate insulating film 17.

[0105] The main surface insulating film 21 coats the first main surface 3 in an active region 8 and is connected to a plurality of gate insulating films 17. In this embodiment, the main surface insulating film 21 forms a single insulating film integral with the plurality of gate insulating films 17. The main surface insulating film 21 coats the first main surface 3 in an inactive region 9. The main surface insulating film 21 coats the well region 20 on the first main surface 3.

[0106] The main surface insulating film 21 has a thickness approximately equal to the thickness of the gate insulating film 17. The thickness of the main surface insulating film 21 may be greater than or less than the thickness of the gate insulating film 17. The thickness of the main surface insulating film 21 may be greater than 0 nm and 150 nm or less.

[0107] The thickness of the main surface insulating film 21 may be greater than 0 nm and fall within at least one of the following ranges: 10 nm or less, 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0108] The semiconductor device 1A includes gate wiring 22 arranged on the first main surface 3 in an inactive region 9. The gate wiring 22 may also be called "wiring electrode," "planar wiring," etc. The gate wiring 22 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wiring 22 contains the same conductive material as the gate electrode 18.

[0109] The gate wiring 22 has a thickness approximately equal to the thickness of the gate electrode 18. The thickness of the gate wiring 22 may be greater than or less than the thickness of the gate electrode 18. The thickness of the gate wiring 22 may be greater than 0 μm and less than or equal to 1 μm.

[0110] The thickness of the gate wiring 22 may be greater than 0 μm and fall within at least one of the following ranges: 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less.

[0111] The gate wiring 22 is selectively routed over the main surface insulating film 21 in the inactive region 9 and faces the well region 20 via the main surface insulating film 21. The gate wiring 22 is led from the inactive region 9 to the active region 8 and connected to a plurality of gate electrodes 18 in the active region 8. In this embodiment, the gate wiring 22 forms a single electrode film integral with the plurality of gate electrodes 18.

[0112] The gate wiring 22 includes a pad wiring section 22a, a first wiring section 22b, and a second wiring section 22c. The presence or absence of the pad wiring section 22a is optional, and a configuration without the pad wiring section 22a may be adopted. The pad wiring section 22a is positioned on the main surface insulating film 21 in the pad region 9a and faces the pad well region 20a via the main surface insulating film 21.

[0113] The pad wiring section 22a is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the pad wiring section 22a has a planar shape similar to the planar shape of the pad region 9a. The pad wiring section 22a may be led out from the pad region 9a to the active region 8 and connected (electrically connected) to a plurality of gate electrodes 18.

[0114] The first wiring section 22b is positioned on the main surface insulating film 21 in the outer region 9b and faces the outer well region 20b via the main surface insulating film 21. The first wiring section 22b is drawn out from the pad wiring section 22a toward the second side surface 5B and has a portion that extends in a strip shape in a first direction X along the active region 8, and a portion that extends in a strip shape in a second direction Y along the active region 8. The portion of the first wiring section 22b that extends in a strip shape in the second direction Y is connected (electrically connected) to a plurality of gate electrodes 18.

[0115] The second wiring section 22c is positioned on the main surface insulating film 21 in the outer region 9b and faces the well region 20 (outer well region 20b) via the main surface insulating film 21. The second wiring section 22c is drawn out from the pad wiring section 22a toward the fourth side surface 5D and has a portion that extends in a strip shape in a first direction X along the active region 8, and a portion that extends in a strip shape in a second direction Y along the active region 8. The portion of the second wiring section 22c that extends in a strip shape in the second direction Y is connected (electrically connected) to a plurality of gate electrodes 18.

[0116] In this embodiment, the first wiring section 22b (second wiring section 22c) has a width greater than the width of the gate electrode 18. The ratio of the width of the first wiring section 22b (second wiring section 22c) to the width of the gate electrode 18 may be between 1 and 100. The ratio may have a value that falls within at least one of the following ranges: between 1 and 10, between 10 and 25, between 25 and 50, between 50 and 75, and between 75 and 100.

[0117] The semiconductor device 1A includes an insulating interlayer film 23 that covers the first main surface 3. The interlayer film 23 may also be called an "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 23 covers the first main surface 3 collectively via the main surface insulating film 21 in the active region 8 and the inactive region 9.

[0118] The interlayer film 23 covers the gate electrodes 18 in the active region 8 and the gate wiring 22 in the inactive region 9. Specifically, the interlayer film 23 coats a plurality of first gate electrodes 18A and a plurality of second gate electrodes 18B in a film-like manner on the gate insulating film 17, and coats the gate wiring 22 in a film-like manner on the main surface insulating film 21.

[0119] The interlayer film 23 is connected to the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The interlayer film 23 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3 (second semiconductor layer 7).

[0120] In this embodiment, the interlayer film 23 has a laminated structure including a first interlayer film 24 (lower interlayer film) and a second interlayer film 25 (upper interlayer film) stacked in this order from the chip 2 side. The first interlayer film 24 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0121] The first interlayer film 24 is preferably made of a silicon oxide film that does not contain phosphorus. In this embodiment, the first interlayer film 24 is made of a silicon oxide film without impurities. A silicon oxide film without impurities may also be called an NSG film (Nondoped Silicate Glass film).

[0122] The first interlayer film 24 has a first thickness T1. The first thickness T1 is greater than the thickness of the gate insulating film 17. The first thickness T1 is greater than the thickness of the main surface insulating film 21. The first thickness T1 is less than the thickness of the gate electrode 18. The first thickness T1 is less than the thickness of the gate wiring 22. Of course, the first thickness T1 may be greater than the thickness of the gate electrode 18 and the thickness of the gate wiring 22.

[0123] The first thickness T1 may be greater than 0 μm and less than or equal to 1 μm. The first thickness T1 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0124] The first interlayer film 24 coats the first main surface 3 in a film-like manner via the main surface insulating film 21 in the active region 8 and the inactive region 9. The first interlayer film 24 coats the gate electrodes 18 in a film-like manner in the active region 8 and coats the gate wiring 22 in a film-like manner in the inactive region 9. Specifically, the first interlayer film 24 coats a plurality of first gate electrodes 18A and a plurality of second gate electrodes 18B in a film-like manner on the gate insulating film 17, and coats the gate wiring 22 in a film-like manner on the main surface insulating film 21.

[0125] The first interlayer film 24 has a portion that horizontally covers the electrode surface of the gate electrode 18 in a film-like manner in the active region 8, a portion that horizontally covers the electrode sidewall of the gate electrode 18 in a film-like manner in the thickness direction Z, and a portion that horizontally covers the gate insulating film 17 in a film-like manner. The first interlayer film 24 covers the gate insulating film 17 in a film-like manner within a plurality of electrode openings 19.

[0126] The first interlayer film 24 has a portion that horizontally covers the wiring surface of the gate wiring 22 in a film-like manner in the inactive region 9, a portion that horizontally covers the wiring sidewall of the gate wiring 22 in a film-like manner in the thickness direction Z, and a portion that horizontally covers the main surface insulating film 21 in a film-like manner.

[0127] The first interlayer film 24 is connected to the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The first interlayer film 24 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3 (second semiconductor layer 7).

[0128] The second interlayer film 25 contains an insulating material different from the first interlayer film 24. The second interlayer film 25 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0129] The second interlayer film 25 has an etching selectivity ratio different from that of the first interlayer film 24. The second interlayer film 25 has a melting temperature different from that of the first interlayer film 24. The melting temperature of the second interlayer film 25 is lower than that of the first interlayer film 24. In this embodiment, the second interlayer film 25 includes a silicon oxide film containing impurities. The impurities may be either or both phosphorus and boron.

[0130] A silicon oxide film containing phosphorus is called a PSG film (Phosphorus Silicon Glass film), a silicon oxide film containing boron is called a BSG film (Boron Silicon Glass film), and a silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass film).

[0131] The second interlayer membrane 25 may have a single-layer structure consisting of a PSG membrane, a BSG membrane, or a BPSG membrane. The second interlayer membrane 25 may have a laminated structure in which two or three layers selected from the PSG membrane, BSG membrane, and BPSG membrane are laminated on the first interlayer membrane 24 in any order. In this embodiment, the second interlayer membrane 25 has a single-layer structure consisting of a PSG membrane.

[0132] The second interlayer film 25 has a second thickness T2. The second thickness T2 is greater than the thickness of the gate insulating film 17. The second thickness T2 is greater than the thickness of the main surface insulating film 21. The second thickness T2 is greater than the thickness of the gate electrode 18. The second thickness T2 is greater than the thickness of the gate wiring 22. Of course, the second thickness T2 may be less than the thickness of the gate electrode 18 and the thickness of the gate wiring 22.

[0133] The second thickness T2 is different from the first thickness T1 of the first interlayer film 24. In this configuration, the second thickness T2 is greater than the first thickness T1. Of course, the second thickness T2 may also be less than the first thickness T1.

[0134] The second thickness T2 may be greater than 0 μm and less than or equal to 1 μm. The second thickness T2 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0135] The second interlayer film 25 coats the first main surface 3 in a film-like manner via the main surface insulating film 21 and the first interlayer film 24 in the active region 8 and the inactive region 9. The second interlayer film 25 coats the gate electrode 18 in a film-like manner via the first interlayer film 24 in the active region 8, and coats the gate wiring 22 in a film-like manner via the first interlayer film 24 in the inactive region 9.

[0136] Specifically, the second interlayer film 25 covers a plurality of first gate electrodes 18A and a plurality of second gate electrodes 18B in a film-like manner on the gate insulating film 17 via the first interlayer film 24, and covers the gate wiring 22 in a film-like manner on the main surface insulating film 21 via the first interlayer film 24.

[0137] The second interlayer film 25 has a portion that horizontally covers the electrode surface of the gate electrode 18 via the first interlayer film 24 in a film-like manner in the active region 8, a portion that horizontally covers the electrode sidewall of the gate electrode 18 via the first interlayer film 24 in a film-like manner in the thickness direction Z, and a portion that horizontally covers the gate insulating film 17 via the first interlayer film 24. The second interlayer film 25 covers the gate insulating film 17 via the first interlayer film 24 in a film-like manner within a plurality of electrode openings 19.

[0138] The second interlayer film 25 has, in the inactive region 9, a portion that horizontally covers the wiring surface of the gate wiring 22 via the first interlayer film 24, a portion that horizontally covers the wiring sidewall of the gate wiring 22 via the first interlayer film 24 in the thickness direction Z, and a portion that horizontally covers the main surface insulating film 21 via the first interlayer film 24.

[0139] The second interlayer film 25 is connected to the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The second interlayer film 25 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3 (second semiconductor layer 7).

[0140] The second interlayer film 25 has an insulating surface that has been smoothed by a reflow process (heating and melting process) to reduce unevenness. The insulating surface of the second interlayer film 25 forms the insulating surface of the interlayer film 23. The insulating surface of the second interlayer film 25 has a flat portion and an inclined portion. The flat portion extends flatly along the electrode surface of the gate electrode 18, and the inclined portion is obliquely inclined from the flat portion toward the chip 2 side in the region outside the gate electrode 18 (electrode opening 19).

[0141] The diffusion of impurities from the second interlayer film 25 to the gate electrode 18 and gate wiring 22 is suppressed by the first interlayer film 24. This suppresses fluctuations in the electrical characteristics (e.g., resistance) of the gate electrode 18 and gate wiring 22.

[0142] The semiconductor device 1A includes a plurality of via holes 30 formed in the interlayer film 23 in the active region 8. In this embodiment, the plurality of via holes 30 are formed with spacing in the first direction X and the second direction Y. The plurality of via holes 30 are arranged in a row with spacing in the first direction X.

[0143] With respect to the multiple via holes 30 on one and the other side in the second direction Y, the multiple via holes 30 on the other side are offset in the first direction X relative to the multiple via holes 30 on the one side, and face the region between the multiple via holes 30 on the one side in the second direction Y. In other words, in this embodiment, the multiple via holes 30 are arranged in a staggered pattern in a plan view.

[0144] Of course, the multiple via holes 30 on the other side may be arranged in a one-to-one correspondence with the multiple via holes 30 on the one side in the second direction Y. In other words, the multiple via holes 30 may be arranged in a matrix with spacing in the first direction X and the second direction Y.

[0145] In this embodiment, the multiple via holes 30 are formed in a one-to-one correspondence with the multiple electrode openings 19 and extend in a strip shape in the first direction X, following the extending direction of the multiple electrode openings 19 (the extending direction of the multiple first gate electrodes 18A). The multiple via holes 30 are formed with a gap inward from the wall surface of the multiple electrode openings 19.

[0146] In other words, the multiple via holes 30 are formed laterally to the gate electrode 18, spaced apart from the gate electrode 18 in a cross-sectional view. Specifically, the multiple via holes 30 are formed spaced apart from the multiple first gate electrode 18A in the second direction Y, and spaced apart from the multiple second gate electrode 18B in the first direction X.

[0147] The horizontal insulation distance between the via hole 30 and the gate electrode 18 may be greater than the thickness of the gate electrode 18. The insulation distance may be less than the thickness of the gate electrode 18. The insulation distance may be 0 μm or more and 1 μm or less.

[0148] The insulation distance may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less.

[0149] The multiple via holes 30 span across one or more (one in this embodiment) diode regions 12 in a plan view, and across multiple (two in this embodiment) adjacent body regions 10 in the first direction X. As a result, the multiple via holes 30 expose one body region 10 in the first direction X, the other body region 10 in the first direction X, and one diode region 12, respectively.

[0150] In this configuration, the multiple via holes 30 span the ends of multiple (two in this configuration) adjacent contact regions 14 in the first direction X. The multiple via holes 30 expose one end of the body region 10, source region 13, and contact region 14 on one side in the first direction X, and expose the other end of the body region 10, source region 13, and contact region 14 on the other side in the first direction X.

[0151] Of course, the multiple via holes 30 may span across multiple diode regions 12 and extend to three or more adjacent body regions 10 in the first direction X, exposing multiple body regions 10, multiple source regions 13, multiple contact regions 14, and multiple diode regions 12.

[0152] Multiple via holes 30 penetrate the gate insulating film 17 and the interlayer film 23, and each has a via side wall 31 partitioned by the interlayer film 23 and a via bottom wall 32 partitioned by the chip 2 (first main surface 3).

[0153] In this configuration, the via sidewall 31 is demarcated by the gate insulating film 17, the first interlayer film 24, and the second interlayer film 25. In this configuration, the via sidewall 31 is connected to the inclined portion of the insulating surface of the interlayer film 23 in the region between the multiple first gate electrodes 18A in a cross-sectional view.

[0154] In this embodiment, the via bottom wall 32 is formed in a plurality of body regions 10, a plurality of source regions 13, a plurality of contact regions 14, and a single diode region 12. In this embodiment, the via bottom wall 32 is defined in the first main surface 3 by via recesses 33 that are recessed in the thickness direction Z from the height position of the first main surface 3.

[0155] In other words, in this embodiment, the via bottom wall 32 is located on the second main surface 4 side of the height position of the connection interface between the first main surface 3 and the gate insulating film 17. The via recess 33 has an arc-shaped corner that connects to the via side wall 31 and an inward portion (bottom wall portion) that extends along the first main surface 3. The via recess 33 is formed with a gap from the depth position of the bottom of the corresponding body region 10 toward the first main surface 3.

[0156] The via recess 33 is formed at a distance from the depth position of the bottom of the corresponding source region 13 and the depth position of the bottom of the corresponding contact region 14 toward the first main surface 3. The presence or absence of the via recess 33 is optional, and the via bottom wall 32 may be partitioned by the first main surface 3.

[0157] The multiple via holes 30 have a cross-sectional shape in which the opening width on the chip 2 side is narrower than the opening width on the insulating surface side of the interlayer film 23. Specifically, the multiple via holes 30 have a cross-sectional shape in which the opening width narrows in a stepwise manner (downward staircase-like) from the insulating surface side of the interlayer film 23 towards the chip 2 side.

[0158] Each of the multiple via holes 30 includes a first hole portion 34, a second hole portion 35, and a stepped portion 36, respectively. The first hole portion 34 is demarcated on the insulating surface side of the interlayer film 23 by a first width W1 and a first depth D1. The first width W1 is the maximum width of the first hole portion 34. The first depth D1 is the depth relative to the insulating surface of the interlayer film 23.

[0159] The first width W1 is less than the width of the first gate electrode 18A. The first width W1 is less than the width of the second gate electrode 18B. The first width W1 is less than the thickness of the interlayer film 23 (= T1 + T2). In other words, the via hole 30 has an aspect ratio that extends in a vertically elongated columnar shape in cross-sectional view. The first width W1 may be greater than or equal to the thickness of the interlayer film 23. In other words, the via hole 30 may have an aspect ratio that extends in a horizontally elongated columnar shape in cross-sectional view.

[0160] The first width W1 may be 0 μm or more and 1 μm or less. The first width W1 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less.

[0161] The first depth D1 is at least half the thickness of the interlaminar film 23. In other words, the first hole 34 crosses the depth position of the intermediate part of the interlaminar film 23. The first depth ratio of the first depth D1 to the thickness of the interlaminar film 23 may be 0.5 or more and 0.9 or less.

[0162] The first depth ratio may have a value that falls within at least one of the following ranges: 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, and 0.8 to 0.9. Preferably, the first depth ratio is 0.7 or greater.

[0163] The first hole 34 is formed in the second interlayer membrane 25. Specifically, the first hole 34 is formed by excavating the second interlayer membrane 25 down to the first interlayer membrane 24, and has a first bottom wall portion 34a partitioned by the first interlayer membrane 24, and a first side wall portion 34b partitioned by the second interlayer membrane 25. In other words, the first depth D1 of the first hole 34 is greater than or equal to the second thickness T2 of the second interlayer membrane 25. The first bottom wall portion 34a and the first side wall portion 34b each form a part of the via side wall 31.

[0164] In this configuration, the first hole 34 crosses the height of the electrode surface of the gate electrode 18. Therefore, the first side wall portion 34b has a portion located on the insulating surface side of the interlayer film 23 relative to the electrode surface of the gate electrode 18, and a portion located on the tip 2 side relative to the electrode surface of the gate electrode 18. In this configuration, the first bottom wall portion 34a faces the gate electrode 18 in the horizontal direction.

[0165] The first side wall portion 34b is inclined obliquely with respect to the normal (vertical line) of the first main surface 3 in a cross-sectional view and is connected to the first bottom wall portion 34a in an arc shape. In other words, the first hole portion 34 is formed in a tapered shape that narrows toward the tip 2 in a cross-sectional view. Of course, the first side wall portion 34b may be approximately coincident with the normal in a cross-sectional view. In other words, the first hole portion 34 may be formed in a vertical shape in a cross-sectional view.

[0166] The inclination angle of the first side wall portion 34b with respect to the normal may be 0° or more and 30° or less. The inclination angle of the first side wall portion 34b may have a value that falls within at least one of the following ranges: 0° or more and 5° or less, 5° or more and 10° or less, 10° or more and 15° or less, 15° or more and 20° or less, 20° or more and 25° or more and 30° or less.

[0167] The second hole 35 is separated from the first hole 34 by a second width W2 and a second depth D2 on the tip 2 side. The second width W2 is the maximum width of the second hole 35. The second depth D2 is the depth of the first hole 34 relative to the first bottom wall portion 34a. The second width W2 is different from the first width W1, and the second depth D2 is different from the first depth D1.

[0168] The second width W2 is less than the width of the first gate electrode 18A. The second width W2 is less than the width of the second gate electrode 18B. The second width W2 is less than the first width W1. The second width W2 is less than the thickness of the interlaminar film 23 (= T1 + T2). The first width W1 may be greater than the thickness of the interlaminar film 23, while the second width W2 may be less than the thickness of the interlaminar film 23. Of course, both the first width W1 and the second width W2 may be greater than the thickness of the interlaminar film 23.

[0169] The width ratio W2 / W1 of the second width W2 to the first width W1 may be 0.5 or more and less than 1. The width ratio W2 / W1 may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0170] The second width W2 may be 0 μm or more and less than 1 μm. The second width W2 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and less than 1 μm.

[0171] The second depth D2 is less than the first depth D1. The second depth D2 is less than half the thickness of the interlayer film 23. In other words, the second hole 35 is partitioned in the region on the tip 2 side relative to the depth position of the intermediate part of the interlayer film 23. The ratio of the second depth D2 to the thickness of the interlayer film 23 may be greater than 0 and less than 0.5.

[0172] The second depth ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, and 0.4 or more and less than 0.5. Preferably, the second depth ratio is 0.3 or less.

[0173] The second hole 35 is formed in the first interlayer film 24. Specifically, the second hole 35 is formed by excavating the first interlayer film 24 down to the chip 2, starting from the first bottom wall portion 34a of the first hole 34. The second depth D2 of the second hole 35 is greater than or equal to the first thickness T1 of the first interlayer film 24.

[0174] The second hole 35 has a second bottom wall portion 35a partitioned by the tip 2, and a second side wall portion 35b partitioned by the main surface insulating film 21 and the first interlayer film 24. The second bottom wall portion 35a is formed as a via bottom wall 32 and is partitioned by a via recess 33. The second side wall portion 35b forms a part of the via side wall 31.

[0175] In this embodiment, the second hole 35 is formed at a distance from the height of the electrode surface of the gate electrode 18 toward the tip 2. Therefore, the second sidewall portion 35b is located toward the tip 2 with respect to the electrode surface of the gate electrode 18. Of course, the second hole 35 may also have a portion located toward the insulating surface side of the interlayer film 23 with respect to the electrode surface of the gate electrode 18, depending on the depth of the first hole 34.

[0176] The second side wall portion 35b is inclined at an angle with respect to the normal (vertical line) of the first main surface 3 in a cross-sectional view. In other words, the second hole portion 35 is formed in a tapered shape that narrows towards the tip 2 in a cross-sectional view. Of course, the second side wall portion 35b may also be approximately aligned with the normal in a cross-sectional view. In other words, the second hole portion 35 may be formed in a vertical shape in a cross-sectional view.

[0177] The inclination angle of the second side wall portion 35b with respect to the normal may be greater than or less than the inclination angle of the first side wall portion 34b. The inclination angle of the second side wall portion 35b may be 0° or more and 30° or less. The inclination angle of the second side wall portion 35b may have a value that falls within at least one of the following ranges: 0° or more and 5° or less, 5° or more and 10° or less, 10° or more and 15° or less, 15° or more and 20° or less, 20° or more and 25° or more and 30° or less.

[0178] The stepped portion 36 is located between the first hole portion 34 and the second hole portion 35. Specifically, the stepped portion 36 is formed by the first bottom wall portion 34a of the first hole portion 34 as a connection between the first side wall portion 34b and the second side wall portion 35b, and defines the step that protrudes inward.

[0179] In this configuration, the stepped portion 36 is located on the tip 2 side relative to the electrode surface of the gate electrode 18. Of course, the stepped portion 36 may also be located on the insulating surface side of the interlayer film 23 relative to the electrode surface of the gate electrode 18, depending on the depth of the first hole 34 (the depth of the second hole 35).

[0180] The stepped portion 36 may have a step width greater than 0 nm and less than or equal to 500 nm. The step width is defined by the horizontal distance between the first side wall portion 34b and the second side wall portion 35b at the first bottom wall portion 34a.

[0181] The step width may have a value greater than 0 μm and belonging to at least one of the following ranges: 10 nm or less, 10 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0182] The semiconductor device 1A includes a silicide 37 formed within a plurality of via holes 30, following the contour of the via bottom wall 32. The silicide 37 is formed by depositing a metal film onto the chip 2 (SiC) using methods such as CVD, PVD, sputtering, or vapor deposition, and then reacting the metal film with the silicon component of the SiC in an annealing process.

[0183] Silicide 37 is a self-aligned silicide formed in a manner consistent with the via bottom wall 32. In other words, silicide 37 is an alloy layer in which the silicon component of the chip 2 is alloyed with metal at the via bottom wall 32.

[0184] Silicide 37 may include at least one of tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, cobalt silicide, nickel silicide, and platinum silicide.

[0185] Tungsten, molybdenum, tantalum, titanium, and cobalt tend to react with the carbon component of SiC under high-temperature conditions, forming carbides. Since carbides have high resistance, they can be a factor in increasing contact resistance.

[0186] Therefore, when using tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, and cobalt silicide instead of SiC, it is necessary to be aware of the increase in power consumption (increase in heat generation temperature) caused by the carbides.

[0187] On the other hand, nickel forms carbides with the carbon component of SiC, but the carbonization reaction proceeds less readily compared to the aforementioned metals. Furthermore, nickel carbides are unstable as a substance and tend to decompose under high temperatures (annealing processes). Therefore, nickel stably forms nickel silicide together with the silicon component of SiC.

[0188] On the other hand, platinum is a chemically stable precious metal and has an extremely low tendency to form carbides. Therefore, platinum stably forms platinum silicides together with the silicon component of SiC.

[0189] In light of the above, it is preferable that the silicide 37 consists of a metal silicide other than tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, and cobalt silicide.

[0190] In this case, with respect to the fine via structure (via holes 30), an increase in contact resistance caused by tungsten carbide, molybdenum carbide, tantalum carbide, titanium carbide, and cobalt carbide is reliably avoided. In particular, since SiC is used in high-voltage environments, such a configuration is effective in avoiding electrical problems caused by poor connections in the fine via structure.

[0191] In this embodiment, silicide 37 consists of nickel silicide. The term "nickel silicide" as used herein conceptually includes silicides composed of high-purity nickel and silicon, as well as silicides composed of high-purity nickel and silicon containing metallic impurities. In this specification, "high-purity" means a pure metal with a purity of 99% or higher. The metallic impurities may, for example, be at least one of platinum, iridium, palladium, and ruthenium.

[0192] Of course, silicide 37 may consist of platinum silicide. The term "platinum silicide" as used herein conceptually includes silicides composed of high-purity platinum and silicon, as well as silicides composed of high-purity platinum and silicon containing metallic impurities. The metallic impurities may include, for example, at least one of nickel, iridium, palladium, and ruthenium.

[0193] In this embodiment, the silicide 37 is formed in the second hole 35 following the via bottom wall 32. The silicide 37 is formed at a distance from the stepped portion 36 toward the tip 2 and is not located within the first hole 34. In this embodiment, the silicide 37 is formed following the via recess 33 and is located below the height of the first main surface 3. Specifically, the silicide 37 is located below the connection interface between the first main surface 3 and the gate insulating film 17.

[0194] In this embodiment, the silicide 37 is formed with a gap between it and the bottom wall portion of the via recess 33, extending from the height position of the first main surface 3. Of course, the silicide 37 may have a portion (a raised portion) that protrudes above the height position of the first main surface 3. In this case, the silicide 37 may be located above the insulating surface of the gate insulating film 17, or it may be located below the insulating surface of the gate insulating film 17.

[0195] The silicide 37 is formed with a gap between it and the first main surface 3, extending from the depth position at the bottom of the multiple body regions 10. The silicide 37 is formed with a gap between it and the first main surface 3, extending from the depth position at the bottom of the multiple source regions 13 and the depth position at the bottom of the multiple contact regions 14.

[0196] The silicide 37 coats the corners and inner parts of the via recess 33 in a film-like manner. The silicide 37 may also coat the inner parts of the via recess 33 in a film-like manner, leaving the corners of the via recess 33 exposed.

[0197] The silicide 37 has a width less than or equal to the first width W1 of the first hole 34. Preferably, the width of the silicide 37 is 3 / 4 or more of the second width W2 of the second hole 35. The width of the silicide 37 may be greater than or equal to the second width W2. Preferably, the silicide 37 has a width ratio of 0.9 to 1.1 with respect to the second width W2.

[0198] The width of the silicide 37 is preferably 3 / 4 or more of the width of the via bottom wall 32. The width of the silicide 37 may be greater than or equal to the width of the via bottom wall 32. The silicide 37 is preferably having a width ratio of 0.9 to 1.1 with respect to the width of the via bottom wall 32.

[0199] Silicide 37 may have a thickness greater than 0 nm and less than or equal to 150 nm. Silicide 37 may have a value that is greater than 0 μm and less than or equal to 10 nm, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0200] The silicide 37 extends in a strip-like manner in a first direction X, following the direction of extension of the via bottom wall 32 (via recess 33). In a plan view, the silicide 37 spans multiple (two in this embodiment) body regions 10 adjacent to one or more (one in this embodiment) diode regions 12 in the first direction X. The silicide 37 is electrically connected to one body region 10 in the first direction X, the other body region 10 in the first direction X, and one diode region 12.

[0201] In this embodiment, the silicide 37 spans the ends of multiple (two in this embodiment) adjacent contact regions 14 in the first direction X. The silicide 37 is electrically connected to one end (one end) of the body region 10, source region 13, and contact region 14 on one side in the first direction X, and to the other end (the other end) of the body region 10, source region 13, and contact region 14 on the other side in the first direction X.

[0202] Depending on the layout of the via holes 30, the silicide 37 may span across a plurality of diode regions 12 and three or more adjacent body regions 10 in the first direction X, and may be electrically connected to the plurality of body regions 10, a plurality of source regions 13, a plurality of contact regions 14, and a plurality of diode regions 12.

[0203] The silicide 37 forms ohmic contact with multiple source regions 13 and multiple contact regions 14. On the other hand, the silicide 37 forms a Schottky junction with the diode region 12. This forms a Schottky barrier diode Di2 (unipolar diode) having the diode region 12 as the cathode and the silicide 37 as the anode.

[0204] The Schottky barrier diode Di2 functions as a freewheeling diode for the transistor structure T together with the pn junction diode Di1 (bipolar diode). The Schottky barrier diode Di2 has a threshold voltage lower than that of the pn junction diode Di1. Therefore, the Schottky barrier diode Di2 turns on before the pn junction diode Di1 turns on, allowing a forward current to flow as freewheeling current. This reduces forward energy loss.

[0205] During normal freewheeling operation, the pn junction diode Di1 may be kept in the off state while the Schottky barrier diode Di2 is in the on state. In other words, during normal freewheeling operation, the freewheeling current may be predominantly handled by the Schottky barrier diode Di2.

[0206] The first semiconductor layer 6 may have basal plane dislocation (BPD) defects. Basal plane dislocation defects are dislocations located on the c-plane, which is the basal plane of a SiC single crystal. If the first semiconductor layer 6 has an off-direction and an off-angle, the basal plane dislocation defects extend in the off-direction at an angle equal to the off-angle. Basal plane dislocation defects typically have a density of 1 cm⁻² to 10,000 cm⁻².

[0207] When holes, acting as minority carriers, are supplied to the second semiconductor layer 7 during reflux operation, the holes recombine with electrons, acting as majority carriers, within the second semiconductor layer 7 and release energy. The majority of holes recombine with electrons in the second semiconductor layer 7, but a small number of holes may reach the first semiconductor layer 6.

[0208] If a hole recombines with an electron at or near a basal plane dislocation defect, the atom of the basal plane dislocation defect may migrate from the first semiconductor layer 6 to the second semiconductor layer 7 due to the energy generated by the recombination.

[0209] In this case, atom migration resulting from a basal plane dislocation defect may extend to the second semiconductor layer 7 as a single Shockley stacking fault (1SSF). A single Shockley stacking fault traps conduction carriers during freewheeling, causing an increase in on-voltage and on-resistance. This type of problem is known as bipolar degradation.

[0210] When the operation of the pn junction diode Di1 as a bipolar device is restricted during freewheeling, and the Schottky barrier diode Di2 as a unipolar device is predominantly driven, the supply of holes as minority carriers to the second semiconductor layer 7 is suppressed. As a result, the number of holes reaching the first semiconductor layer 6 is reduced, and bipolar degradation is suppressed.

[0211] On the other hand, if a surge current occurs during freewheeling, the design may ensure that both the Schottky barrier diode Di2 and the unipolar device are turned on, and the surge current can be handled by both the Schottky barrier diode Di2 and the pn junction diode Di1. In this case, since the total surface area of ​​the pn junction diode Di1 is larger than the total surface area of ​​the Schottky barrier diode Di2, current concentration is suppressed, and at the same time, the on-delay of the pn junction diode Di1 is suppressed.

[0212] The semiconductor device 1A includes a plurality of via electrodes 40 embedded in a plurality of via holes 30. The plurality of via electrodes 40 are conductive embedded objects to which the chip 2 is connected. The plurality of via electrodes 40 are each embedded in the plurality of via holes 30 with a gap between them and the chip 2 side from the insulating surface of the interlayer film 23, exposing the insulating surface of the interlayer film 23. The plurality of via electrodes 40 include portions embedded in the first hole 34 and portions embedded in the second hole 35, respectively.

[0213] Multiple via electrodes 40 are mechanically and electrically connected to corresponding silicides 37 within multiple via holes 30, and electrically connected to the chip 2 via the corresponding silicides 37. Specifically, the multiple via electrodes 40 are electrically connected to multiple body regions 10, multiple source regions 13, multiple contact regions 14, and diode regions 12 via the corresponding silicides 37.

[0214] Each of the multiple via electrodes 40 has an electrode surface formed at a distance from the height of the insulating surface of the interlayer film 23 toward the via bottom wall 32. The electrode surfaces of the multiple via electrodes 40 have recesses that are indented toward the via bottom wall 32. In this configuration, the recesses are V-shaped in cross-section.

[0215] The via electrode 40 may contain at least one metal from among tungsten-based metals, molybdenum-based metals, tantalum-based metals, titanium-based metals, cobalt-based metals, nickel-based metals, platinum-based metals, aluminum-based metals, and copper-based metals.

[0216] Tungsten-based metals conceptually include high-purity tungsten or tungsten alloys. Molybdenum-based metals conceptually include high-purity molybdenum or molybdenum alloys. Tantalum-based metals conceptually include high-purity tantalum or tantalum alloys. Titanium-based metals conceptually include high-purity titanium or titanium alloys.

[0217] Cobalt-based metals conceptually include high-purity cobalt or cobalt alloys. Nickel-based metals conceptually include high-purity nickel or nickel alloys. Platinum-based metals conceptually include high-purity platinum or platinum alloys. Aluminum-based metals conceptually include high-purity aluminum or aluminum alloys. Copper-based metals conceptually include high-purity copper or copper alloys.

[0218] The via electrode 40 preferably contains a metal species different from the metal species that constitutes the silicide 37. In other words, in this embodiment, the via electrode 40 preferably contains a metal species other than nickel-based metals.

[0219] In this embodiment, the multiple via electrodes 40 each include a via under electrode 41 and a via main electrode 42. The via under electrode 41 is formed as a barrier electrode for the object to be coated. The via under electrode 41 has a single-layer structure including a metal film made of any one of the aforementioned metals, or a laminated structure including multiple metal films each made of any one of the aforementioned metals. In this embodiment, the via under electrode 41 includes metal species other than nickel-based metals.

[0220] The via base electrode 41 coats the wall surface of the via hole 30 in a film-like manner. Specifically, the via base electrode 41 has a film-like first coating portion 41a over the first hole portion 34. The first coating portion 41a coats the first side wall portion 34b of the first hole portion 34 in a film-like manner. The first coating portion 41a coats the first side wall portion 34b with an uneven film thickness.

[0221] Specifically, the first coating portion 41a has a film thickness that gradually decreases toward the second hole portion 35. In other words, the first coating portion 41a has an upper end on the insulating surface side of the interlayer film 23 and a lower end on the first bottom wall portion 34a side of the first hole portion 34, and has a film thickness that gradually decreases from the upper end to the lower end. The film thickness at the lower end is smaller than the film thickness at the upper end.

[0222] In this configuration, the film thickness at the upper end of the first coating portion 41a is greater than the thickness of the silicide 37. The film thickness at the upper end of the first coating portion 41a may be less than the thickness of the silicide 37. In this configuration, the film thickness at the lower end of the first coating portion 41a is less than the thickness of the silicide 37. The film thickness at the lower end of the first coating portion 41a may be greater than the thickness of the silicide 37.

[0223] The via-based electrode 41 has a film-like second coating portion 41b over the second hole portion 35. The second coating portion 41b coats the second side wall portion 35b of the second hole portion 35 in a film-like manner. The second coating portion 41b coats the second side wall portion 35b with an uneven film thickness.

[0224] Specifically, the second coating portion 41b has a film thickness that gradually decreases toward the second bottom wall portion 35a (via bottom wall 32). In other words, the second coating portion 41b has an upper end on the first bottom wall portion 34a side of the first hole portion 34 and a lower end on the second bottom wall portion 35a (via bottom wall 32) side of the second hole portion 35, and has a film thickness that gradually decreases from the upper end to the lower end. The film thickness at the lower end is smaller than the film thickness at the upper end.

[0225] The second coating portion 41b has a portion that is thicker than the first coating portion 41a. Specifically, the film thickness at the upper end of the second coating portion 41b is greater than the film thickness at the lower end of the first coating portion 41a. In this embodiment, the film thickness at the upper end of the second coating portion 41b is smaller than the film thickness at the upper end of the first coating portion 41a. The film thickness at the upper end of the second coating portion 41b may be greater than the film thickness at the upper end of the first coating portion 41a.

[0226] In this embodiment, the film thickness at the upper end of the second coating portion 41b is greater than the thickness of the silicide 37. The film thickness at the upper end of the second coating portion 41b may be less than the thickness of the silicide 37. In this embodiment, the film thickness at the lower end of the second coating portion 41b is less than the thickness of the silicide 37. The film thickness at the lower end of the second coating portion 41b may be greater than the thickness of the silicide 37.

[0227] The via base electrode 41 has a film-like third coating portion 41c on the via bottom wall 32. The third coating portion 41c coats the second bottom wall portion 35a (via bottom wall 32) of the second hole portion 35 in a film-like manner. Specifically, the third coating portion 41c coats the silicide 37 in a film-like manner on the via bottom wall 32. In other words, the third coating portion 41c is mechanically and electrically connected to the silicide 37 and coats the via bottom wall 32 in a film-like manner via the silicide 37.

[0228] The third coating portion 41c covers the via bottom wall 32 (silicide 37) with an uneven film thickness. Specifically, the third coating portion 41c rises from the periphery of the via bottom wall 32 toward the inside of the via bottom wall 32.

[0229] The third coating portion 41c has a portion that is thicker than the first coating portion 41a. Specifically, the film thickness of the inner portion of the third coating portion 41c is greater than the film thickness at the lower end of the first coating portion 41a. The film thickness of the inner portion of the third coating portion 41c may be greater than or less than the film thickness at the upper end of the first coating portion 41a.

[0230] The third coating portion 41c has a portion that is thicker than the second coating portion 41b. Specifically, the film thickness of the inner portion of the third coating portion 41c is greater than the film thickness of the lower end of the second coating portion 41b. The film thickness of the inner portion of the third coating portion 41c may be greater than or less than the film thickness of the upper end of the second coating portion 41b. In this embodiment, the film thickness of the third coating portion 41c is greater than the thickness of the silicide 37. The film thickness of the third coating portion 41c may be less than the thickness of the silicide 37.

[0231] The via base electrode 41 has a film-like fourth coating portion 41d over the stepped portion 36. The fourth coating portion 41d covers the stepped portion 36 in a film-like manner and is connected to the lower end of the first coating portion 41a and the upper end of the second coating portion 41b.

[0232] The fourth coating portion 41d has a portion that is thicker than the first coating portion 41a. Specifically, the film thickness of the fourth coating portion 41d is greater than the film thickness at the lower end of the first coating portion 41a. The film thickness of the fourth coating portion 41d may be greater than or less than the film thickness at the upper end of the first coating portion 41a.

[0233] The fourth coating portion 41d has a portion that is thicker than the second coating portion 41b. Specifically, the film thickness of the fourth coating portion 41d is greater than the film thickness at the lower end of the second coating portion 41b. The film thickness of the fourth coating portion 41d may be greater than or less than the film thickness at the upper end of the second coating portion 41b. In this embodiment, the film thickness of the fourth coating portion 41d is greater than the thickness of the silicide 37. The film thickness of the fourth coating portion 41d may be less than the thickness of the silicide 37.

[0234] In this embodiment, the via base electrode 41 has a laminated structure including a first via base electrode 43 and a second via base electrode 44, which are stacked in that order from the wall surface of the via hole 30 (via side wall 31 and via bottom wall 32). The via base electrode 41 does not necessarily have to have a laminated structure and may have a single-layer structure consisting of the first via base electrode 43 or the second via base electrode 44.

[0235] The first via under electrode 43 consists of a metal film containing one of the aforementioned metals. In this embodiment, the first via under electrode 43 consists of a high-purity titanium film, which is an example of a titanium-based metal film. The first via under electrode 43 has a thickness less than the thickness of the interlayer film 23.

[0236] The thickness of the first via substrate electrode 43 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. In this embodiment, the thickness of the first via substrate electrode 43 is less than the thickness of the silicide 37. The thickness of the first via substrate electrode 43 may be greater than the thickness of the silicide 37.

[0237] The thickness of the first via base electrode 43 may be greater than 0 nm and 100 nm or less. The thickness of the first via base electrode 43 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, and 75 nm to 100 nm.

[0238] The first via base electrode 43 coats the via side wall 31 and via bottom wall 32 in a film-like manner as the lowest base layer of the via base electrode 41. In other words, the first via base electrode 43 coats the first hole 34, the second hole 35, the via bottom wall 32 (silicide 37), and the stepped portion 36 in a film-like manner as the base layer for the first coating portion 41a, the second coating portion 41b, the third coating portion 41c, and the fourth coating portion 41d.

[0239] The second via under electrode 44 consists of a metal film containing one of the aforementioned metals. The second via under electrode 44 consists of a metal film containing a different metal species than the first via under electrode 43. In this embodiment, the second via under electrode 44 consists of a titanium nitride film (titanium alloy film) as an example of a titanium-based metal film.

[0240] The second via-based electrode 44 has a thickness less than the thickness of the interlayer film 23. The thickness of the second via-based electrode 44 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. The thickness of the second via-based electrode 44 is greater than the thickness of the first via-based electrode 43.

[0241] The thickness of the second via base electrode 44 may be less than the thickness of the first via base electrode 43. In this embodiment, the thickness of the second via base electrode 44 is greater than the thickness of the silicide 37. The thickness of the second via base electrode 44 may be less than the thickness of the silicide 37.

[0242] The thickness of the second via base electrode 44 may be greater than 0 nm and 300 nm or less. The thickness of the second via base electrode 44 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 200 nm or more and 250 nm or more and 300 nm or less.

[0243] The second via base electrode 44 is laminated in a film-like manner on the first via base electrode 43 as the main body of the via base electrode 41, and covers the via side wall 31 and via bottom wall 32 via the first via base electrode 43.

[0244] In other words, the second via base electrode 44, as the main body of the first coating portion 41a, the main body of the second coating portion 41b, the main body of the third coating portion 41c, and the main body of the fourth coating portion 41d, coats the first hole portion 34, the second hole portion 35, the via bottom wall 32 (silicide 37), and the stepped portion 36 in a film-like manner via the first via base electrode 43.

[0245] The via main electrode 42 consists of a metal film containing one of the aforementioned metals. The via main electrode 42 is made of a different metal species than the first via base electrode 43 and the second via base electrode 44. In this embodiment, the via main electrode 42 is made of a tungsten-based metal (high-purity tungsten or tungsten alloy). Due to its physical properties, the tungsten-based metal can be embedded in the via hole 30 at a relatively high density.

[0246] The via main electrode 42 is embedded in the via hole 30 via the via base electrode 41 as the main body of the via electrode 40, and is electrically connected to the silicide 37 via the via base electrode 41. The via main electrode 42 is formed with a gap from the height of the insulating surface of the interlayer film 23 toward the via bottom wall 32, and forms the electrode surface of the via electrode 40.

[0247] The via main electrode 42 has a portion that covers the first side wall portion 34b via a first covering portion 41a, a portion that covers the second side wall portion 35b via a second covering portion 41b, a portion that covers the via bottom wall 32 (silicide 37) via a third covering portion 41c, and a portion that covers the stepped portion 36 via a fourth covering portion 41d.

[0248] The semiconductor device 1A includes a source terminal 45 located in the inner portion (active region 8) of the first main surface 3. The source terminal 45 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," "source electrode," etc. The source terminal 45 is made of metal and is arranged in a film-like manner on the interlayer film 23.

[0249] In this configuration, the source terminal 45 has a first source pad portion 45a, a second source pad portion 45b, and a third source pad portion 45c. The first source pad portion 45a has a relatively large surface area and forms the main body of the source terminal 45.

[0250] In this configuration, the first source pad portion 45a is formed in a polygonal shape (a quadrilateral shape in this configuration) having four sides parallel to the periphery of the first main surface 3 in a plan view, and is offset towards the third side surface 5C relative to the central part of the first main surface 3.

[0251] The second source pad portion 45b has a planar area less than that of the first source pad portion 45a, and extends in a strip-like (rectangular) shape from one end of the first source pad portion 45a in the first direction X (the end on the second side surface 5B side) toward the first side surface 5A. In a plan view, the second source pad portion 45b is adjacent to the pad region 9a in the first direction X.

[0252] The third source pad portion 45c has a planar area less than that of the first source pad portion 45a, and extends in a strip-like (square-shaped) manner from the other end of the first source pad portion 45a in the first direction X (the end on the fourth side surface 5D side) toward the first side surface 5A. In a plan view, the third source pad portion 45c is adjacent to the pad area 9a in the first direction X and faces the second source pad portion 45b in the first direction X via the pad area 9a.

[0253] The planar area of ​​the third source pad portion 45c may be approximately equal to the planar area of ​​the second source pad portion 45b. The planar area of ​​the third source pad portion 45c may be larger or smaller than the planar area of ​​the second source pad portion 45b. Either or both of the second source pad portion 45b and the third source pad portion 45c may be used as terminal portions for current monitoring.

[0254] The source terminal 45 may have only one of the second source pad portion 45b and the third source pad portion 45c. The source terminal 45 may consist only of the first source pad portion 45a and may not have both the second source pad portion 45b and the third source pad portion 45c.

[0255] The source terminal 45 is formed by covering multiple via electrodes 40 collectively in a film-like manner on the interlayer film 23, and is mechanically and electrically connected to the multiple via electrodes 40. The source terminal 45 forms a connection boundary with the multiple via electrodes 40 and is electrically connected to multiple body regions 10, multiple source regions 13, multiple contact regions 14, and multiple diode regions 12 via the multiple via electrodes 40.

[0256] The source terminal 45 may contain at least one of the following metals: tungsten-based metals, molybdenum-based metals, tantalum-based metals, titanium-based metals, cobalt-based metals, nickel-based metals, platinum-based metals, aluminum-based metals, copper-based metals, palladium-based metals, gold-based metals, and silver-based metals.

[0257] Palladium-based metals conceptually include high-purity palladium or palladium alloys. Gold-based metals conceptually include high-purity gold or gold alloys. Silver-based metals conceptually include high-purity silver or silver alloys.

[0258] The source terminal 45 may have a single-layer structure consisting of a single metal film, or a laminated structure including multiple metal films. In this embodiment, the source terminal 45 has a laminated structure including a source base electrode 46 and a source main electrode 47.

[0259] The source substrate electrode 46 is formed as a barrier electrode for the material to be coated. The source substrate electrode 46 has a single-layer structure containing a metal film made of one of the aforementioned metals, or a laminated structure containing multiple metal films, each made of one of the aforementioned metals. In this embodiment, the source substrate electrode 46 contains metal species other than nickel-based metals.

[0260] The source base electrode 46 coats the insulating surface of the interlayer film 23 in a film-like manner and is mechanically and electrically connected to the multiple via electrodes 40. Specifically, the source base electrode 46 enters the multiple via holes 30 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to the via base electrodes 41 of the multiple via electrodes 40 within the multiple via holes 30. In this embodiment, the source base electrode 46 forms a single electrode film integrated with the multiple via base electrodes 41.

[0261] The source base electrode 46 has a film thickness greater than that of the via base electrode 41. Specifically, the film thickness of the source base electrode 46 is greater than the film thickness at the upper end of the first coating portion 41a. The film thickness of the source base electrode 46 is greater than the film thickness at the upper end of the second coating portion 41b. The film thickness of the source base electrode 46 is greater than the film thickness at the inner part of the third coating portion 41c. The film thickness of the source base electrode 46 is greater than the film thickness of the fourth coating portion 41d.

[0262] In this embodiment, the source base electrode 46 has a laminated structure including a first source base electrode 48 and a second source base electrode 49, which are laminated in this order from the insulating surface side of the interlayer film 23. The source base electrode 46 does not necessarily have to have a laminated structure and may have a single-layer structure consisting of the first source base electrode 48 or the second source base electrode 49.

[0263] The first source substrate electrode 48 consists of a metal film containing one of the aforementioned metals. In this embodiment, the first source substrate electrode 48 consists of a high-purity titanium film, which is an example of a titanium-based metal film. In other words, the first source substrate electrode 48 consists of the same type of metal film as the first via substrate electrode 43.

[0264] The first source substrate electrode 48 has a thickness less than the thickness of the interlayer film 23. The thickness of the first source substrate electrode 48 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. In this embodiment, the thickness of the first source substrate electrode 48 is less than the thickness of the silicide 37. The thickness of the first source substrate electrode 48 may be greater than the thickness of the silicide 37.

[0265] The thickness of the first source substrate electrode 48 may be greater than 0 nm and 100 nm or less. The thickness of the first source substrate electrode 48 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0266] The first source base electrode 48 coats the insulating surface of the interlayer film 23 in a film-like manner as the lowest base layer of the source base electrode 46. The first source base electrode 48 enters a plurality of via holes 30 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to a plurality of first via base electrodes 43 within the plurality of via holes 30. In this embodiment, the first source base electrode 48 forms a single electrode film integral with the plurality of first via base electrodes 43.

[0267] The second source substrate electrode 49 consists of a metal film containing one of the aforementioned metals. The second source substrate electrode 49 consists of a metal film containing a different metal species than the first source substrate electrode 48. In this embodiment, the second source substrate electrode 49 consists of a titanium nitride film (titanium alloy film) as an example of a titanium-based metal film. In other words, the second source substrate electrode 49 consists of the same type of metal film as the second via substrate electrode 44.

[0268] The second source substrate electrode 49 has a thickness less than the thickness of the interlayer film 23. The thickness of the second source substrate electrode 49 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. The thickness of the second source substrate electrode 49 is greater than the thickness of the first via substrate electrode 43.

[0269] The thickness of the second source substrate electrode 49 may be less than the thickness of the first source substrate electrode 48. In this embodiment, the thickness of the second source substrate electrode 49 is greater than the thickness of the silicide 37. The thickness of the second source substrate electrode 49 may be less than the thickness of the silicide 37.

[0270] The thickness of the second source substrate electrode 49 may be greater than 0 nm and 300 nm or less. The thickness of the second source substrate electrode 49 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 200 nm or more and 250 nm or more and 300 nm or less.

[0271] The second source base electrode 49 is laminated in a film-like manner on the first source base electrode 48 as the main body of the source base electrode 46, and covers the insulating surface of the interlayer film 23 via the first source base electrode 48. The second source base electrode 49 enters a plurality of via holes 30 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to a plurality of second via base electrodes 44 within the plurality of via holes 30. In this embodiment, the second source base electrode 49 forms a single electrode film integral with the plurality of second via base electrodes 44.

[0272] The source main electrode 47 consists of a metal film containing one of the aforementioned metals. The source main electrode 47 is made of a different metal species than the first source base electrode 48 and the second source base electrode 49.

[0273] In this embodiment, the source main electrode 47 is made of an aluminum-based metal (high-purity aluminum or aluminum alloy). In other words, the source main electrode 47 is made of a different metal species than the via main electrode 42. The aluminum alloy may be an AlSi alloy, an AlCu alloy, or an AlSiCu alloy.

[0274] The source main electrode 47 has a thickness greater than the thickness of the gate electrode 18. The thickness of the source main electrode 47 is greater than the thickness of the interlayer film 23. The thickness of the source main electrode 47 may be less than the thickness of the interlayer film 23. The thickness of the source main electrode 47 may be greater than 0 μm and 5 μm or less.

[0275] The thickness of the source main electrode 47 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0276] The source main electrode 47 is laminated in a film-like manner on the source base electrode 46 as the main body of the source terminal 45, and covers the insulating surface of the interlayer film 23 via the source base electrode 46. The source main electrode 47 enters a plurality of via holes 30 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to a plurality of via main electrodes 42 within the plurality of via holes 30. The source main electrode 47 forms a connection interface with the electrode surfaces of the plurality of via main electrodes 42.

[0277] The semiconductor device 1A includes one or more (one in this embodiment) wiring via holes 50 formed in the interlayer film 23 in an inactive region 9. The wiring via holes 50 are formed in the interlayer film 23 above the gate wiring 22 and extend in a strip shape following the direction of extension of the gate wiring 22.

[0278] The semiconductor device 1A may include a plurality of wiring via holes 50. In this case, the plurality of wiring via holes 50 may be formed at intervals following the extending direction of the gate wiring 22. Alternatively, the plurality of wiring via holes 50 may be formed at intervals in a direction perpendicular to the extending direction of the gate wiring 22.

[0279] The wiring via hole 50 penetrates the interlayer membrane 23 and has a wiring via side wall 51 partitioned by the interlayer membrane 23 and a wiring via bottom wall 52 partitioned by the gate wiring 22. In this configuration, the wiring via side wall 51 is partitioned by the first interlayer membrane 24 and the second interlayer membrane 25.

[0280] In this configuration, the wiring via bottom wall 52 is defined by a wiring via recess 53 that is recessed in the thickness direction Z from the height position of the wiring surface of the gate wiring 22. In other words, the wiring via bottom wall 52 is located on the first main surface 3 side of the height position of the connection interface between the wiring surface of the gate wiring 22 and the interlayer film 23 (first interlayer film 24).

[0281] The wiring via recess 53 has an arc-shaped corner that connects to the wiring via side wall 51 and an inward portion (bottom wall portion) that extends along the wiring surface of the gate wiring 22. The wiring via recess 53 is formed at a distance from the thickness position of the middle portion of the gate wiring 22 toward the wiring surface of the gate wiring 22. The presence or absence of the wiring via recess 53 is optional, and the wiring via bottom wall 52 may be demarcated by the wiring surface of the gate wiring 22.

[0282] Multiple wiring via holes 50 have a cross-sectional shape in which the opening width on the gate wiring 22 side is narrower than the opening width on the insulating surface side of the interlayer film 23. Specifically, multiple wiring via holes 50 have a cross-sectional shape in which the opening width narrows in a stepwise manner (downward staircase-like) from the insulating surface side of the interlayer film 23 toward the chip 2 side.

[0283] Each of the multiple wiring via holes 50 includes a first wiring hole section 54, a second wiring hole section 55, and a wiring step section 56, respectively. The first wiring hole section 54 is demarcated by a third width W3 and a third depth D3 on the insulating surface side of the interlayer film 23. The third width W3 is the maximum width of the first wiring hole section 54. The third depth D3 is the depth relative to the insulating surface of the interlayer film 23.

[0284] The third width W3 is less than the width of the first gate electrode 18A. The third width W3 is less than the width of the second gate electrode 18B. The third width W3 is less than the thickness of the interlayer film 23 (= T1 + T2). In other words, the wiring via hole 50 has an aspect ratio that extends in a vertically elongated columnar shape when viewed in cross-section.

[0285] The third width W3 may be greater than or equal to the thickness of the interlayer film 23. In other words, the wiring via hole 50 may have an aspect ratio that extends in a horizontal columnar shape in cross-sectional view. The third width W3 may be approximately equal to or different from the first width W1 of the first hole portion 34. The third width W3 may be larger or smaller than the first width W1.

[0286] The third width W3 may be 0 μm or more and 1 μm or less. The third width W3 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less.

[0287] The third depth D3 is at least half the thickness of the interlayer film 23. In other words, the first wiring hole 54 crosses the intermediate depth position of the interlayer film 23. The third depth D3 may be approximately equal to or different from the first depth D1 of the first hole 34. The third depth D3 may be greater or less than the first depth D1. The ratio of the third depth D3 to the thickness of the interlayer film 23 may be between 0.5 and 0.9.

[0288] The third depth ratio may have a value that falls within at least one of the following ranges: 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, and 0.8 to 0.9. Preferably, the third depth ratio is 0.7 or greater.

[0289] The first wiring hole 54 is formed in the second interlayer membrane 25. Specifically, the first wiring hole 54 is formed by excavating the second interlayer membrane 25 down to the first interlayer membrane 24, and has a first wiring bottom wall portion 54a partitioned by the first interlayer membrane 24, and a first wiring side wall portion 54b partitioned by the second interlayer membrane 25. In other words, the third depth D3 of the first wiring hole 54 is greater than or equal to the second thickness T2 of the second interlayer membrane 25. The first wiring bottom wall portion 54a and the first wiring side wall portion 54b each form a part of the wiring via side wall 51.

[0290] The first wiring side wall portion 54b is inclined diagonally with respect to the normal (vertical line) to the wiring surface of the gate wiring 22 in a cross-sectional view, and is connected in an arc to the first wiring bottom wall portion 54a. In other words, the first wiring hole portion 54 is formed in a tapered shape that narrows towards the wiring surface side of the gate wiring 22 in a cross-sectional view. Of course, the first wiring side wall portion 54b may be approximately coincident with the normal in a cross-sectional view. In other words, the first wiring hole portion 54 may be formed in a vertical shape in a cross-sectional view.

[0291] The inclination angle of the first wiring side wall portion 54b with respect to the normal may be 0° or more and 30° or less. The inclination angle of the first wiring side wall portion 54b may have a value that falls within at least one of the following ranges: 0° or more and 5° or less, 5° or more and 10° or less, 10° or more and 15° or less, 15° or more and 20° or less, 20° or more and 25° or more and 30° or less.

[0292] The second wiring hole 55 is separated from the first wiring hole 54 by a fourth width W4 and a fourth depth D4 on the gate wiring 22 side. The fourth width W4 is the maximum width of the second wiring hole 55. The fourth depth D4 is the depth of the first wiring bottom wall 54a of the first wiring hole 54. The fourth width W4 is different from the third width W3, and the fourth depth D4 is different from the third depth D3.

[0293] The fourth width W4 is less than the width of the first gate electrode 18A. The fourth width W4 is less than the width of the second gate electrode 18B. The fourth width W4 is less than the third width W3. The fourth width W4 is less than the thickness of the interlaminar film 23 (= T1 + T2). The third width W3 may be greater than the thickness of the interlaminar film 23, while the fourth width W4 may be less than the thickness of the interlaminar film 23.

[0294] Of course, both the third width W3 and the fourth width W4 may be greater than the thickness of the interlayer film 23. The fourth width W4 may be approximately equal to or different from the second width W2 of the second hole 35. The fourth width W4 may be greater than or less than the second width W2.

[0295] The width ratio W4 / W3 of the fourth width W4 to the third width W3 may be 0.5 or more and less than 1. The width ratio W4 / W3 may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0296] The fourth width W4 may be 0 μm or more and less than 1 μm. The fourth width W4 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and less than 1 μm.

[0297] The fourth depth D4 is less than the third depth D3. The fourth depth D4 is less than half the thickness of the interlayer film 23. In other words, the second wiring hole 55 is partitioned in the region on the gate wiring 22 side relative to the depth position of the intermediate part of the interlayer film 23. The fourth depth D4 may be approximately equal to or different from the second depth D2 of the second hole 35. The fourth width W4 may be greater or less than the second depth D2.

[0298] The fourth depth ratio of the fourth depth D4 to the thickness of the interlaminar film 23 may be greater than 0 and less than 0.5. The fourth depth ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, and 0.4 or more and less than 0.5. Preferably, the fourth depth ratio is 0.3 or less.

[0299] The second wiring hole 55 is formed in the first interlayer film 24. Specifically, the second wiring hole 55 is formed by excavating the first interlayer film 24 down to the gate wiring 22, starting from the first wiring bottom wall portion 54a of the first wiring hole 54. The fourth depth D4 of the second wiring hole 55 is greater than or equal to the first thickness T1 of the first interlayer film 24.

[0300] The second wiring hole 55 has a second wiring bottom wall portion 55a partitioned by the gate wiring 22, and a second wiring side wall portion 55b partitioned by the first interlayer film 24. The second wiring bottom wall portion 55a is formed as a wiring via bottom wall 52 and is partitioned by a wiring via recess 53. The second wiring side wall portion 55b forms a part of the wiring via side wall 51.

[0301] The second wiring side wall portion 55b is inclined at an angle with respect to the normal (vertical line) of the first main surface 3 in a cross-sectional view. In other words, the second wiring hole portion 55 is formed in a tapered shape that narrows towards the gate wiring 22 in a cross-sectional view. Of course, the second wiring side wall portion 55b may also be approximately aligned with the normal in a cross-sectional view. In other words, the second wiring hole portion 55 may be formed in a vertical shape in a cross-sectional view.

[0302] The inclination angle of the second wiring side wall portion 55b with respect to the normal may be greater than or less than the inclination angle of the first wiring side wall portion 54b. The inclination angle of the second wiring side wall portion 55b may be 0° or more and 30° or less. The inclination angle of the second wiring side wall portion 55b may have a value that falls within at least one of the following ranges: 0° or more and 5° or less, 5° or more and 10° or less, 10° or more and 15° or less, 15° or more and 20° or less, 20° or more and 25° or more and 30° or less.

[0303] The wiring step 56 is partitioned between the first wiring hole 54 and the second wiring hole 55. Specifically, the wiring step 56 is formed by the first wiring bottom wall 54a of the first wiring hole 54 as a connection point between the first wiring side wall 54b and the second wiring side wall 55b, and partitions the step that protrudes inward. The wiring step 56 is located above the height of the step 36.

[0304] The wiring step portion 56 may have a step width greater than 0 nm and less than or equal to 500 nm. The step width is defined by the horizontal distance between the first wiring side wall portion 54b and the second wiring side wall portion 55b at the first wiring bottom wall portion 54a. The step width of the wiring step portion 56 may be approximately equal to or different from the step width of the step portion 36 of the via hole 30. The step width of the wiring step portion 56 may be greater or less than the step width of the step portion 36.

[0305] The width of the wiring step portion 56 may be greater than 0 μm and fall within at least one of the following ranges: 10 nm or less, 10 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0306] Unlike the configuration on the side of the multiple via holes 30, semiconductor device 1A does not include silicide 37 within the multiple wiring via holes 50. In this embodiment, semiconductor device 1A includes wiring via electrodes 60 embedded in the wiring via holes 50 without the silicide 37. The wiring via electrodes 60 are conductive embedded objects to which the gate wiring 22 is connected.

[0307] In this embodiment, the semiconductor device 1A includes one wiring via electrode 60. If the semiconductor device 1A includes a plurality of wiring via holes 50, the semiconductor device 1A may include a plurality of wiring via electrodes 60 embedded in the plurality of wiring via holes 50.

[0308] The wiring via electrode 60 is mechanically and electrically connected to the gate wiring 22 within the wiring via hole 50. The wiring via electrode 60 includes a portion embedded in the first wiring hole 54 and a portion embedded in the second wiring hole 55, respectively.

[0309] The wiring via electrode 60 has an electrode surface formed at a distance from the height of the insulating surface of the interlayer film 23 toward the wiring via bottom wall 52. The electrode surface of the wiring via electrode 60 has a recess that is indented toward the wiring via bottom wall 52. In this configuration, the recess is V-shaped in cross-section.

[0310] The wiring via electrode 60, like the via electrode 40, may contain at least one metal from among tungsten-based metals, molybdenum-based metals, tantalum-based metals, titanium-based metals, cobalt-based metals, nickel-based metals, platinum-based metals, aluminum-based metals, and copper-based metals.

[0311] It is preferable that the wiring via electrode 60 contains a metal species different from the metal species that constitutes the silicide 37. In other words, it is preferable that the wiring via electrode 60 contains a metal species other than nickel-based metals. It is preferable that the wiring via electrode 60 contains the same metal species as the via electrode 40.

[0312] In this embodiment, the wiring via electrode 60 includes a wiring via under electrode 61 and a wiring via main electrode 62. The wiring via under electrode 61 is formed as a barrier electrode for the material to be covered.

[0313] The wiring via under electrode 61 has a single-layer structure including a metal film made of one of the aforementioned metals, or a laminated structure including multiple metal films, each made of one of the aforementioned metals. In this embodiment, the wiring via under electrode 61 includes metal species other than nickel-based metals.

[0314] The wiring via base electrode 61 coats the wall surface of the wiring via hole 50 in a film-like manner. Specifically, the wiring via base electrode 61 has a film-like first wiring coating portion 61a over the first wiring hole portion 54. The first wiring coating portion 61a coats the first wiring side wall portion 54b of the first wiring hole portion 54 in a film-like manner. The first wiring coating portion 61a coats the first wiring side wall portion 54b with an uneven film thickness.

[0315] Specifically, the first wiring covering portion 61a has a film thickness that gradually decreases toward the second wiring hole portion 55. In other words, the first wiring covering portion 61a has an upper end on the insulating surface side of the interlayer film 23 and a lower end on the first wiring bottom wall portion 54a side of the first wiring hole portion 54, and has a film thickness that gradually decreases from the upper end to the lower end. The film thickness at the lower end is smaller than the film thickness at the upper end.

[0316] In this configuration, the film thickness at the upper end of the first wiring coating 61a is greater than the thickness of the silicide 37. The film thickness at the upper end of the first wiring coating 61a may be less than the thickness of the silicide 37. In this configuration, the film thickness at the lower end of the first wiring coating 61a is less than the thickness of the silicide 37. The film thickness at the lower end of the first wiring coating 61a may be greater than the thickness of the silicide 37.

[0317] The wiring via base electrode 61 has a film-like second wiring covering portion 61b over the second wiring hole portion 55. The second wiring covering portion 61b covers the second wiring side wall portion 55b of the second wiring hole portion 55 in a film-like manner. The second wiring covering portion 61b covers the second wiring side wall portion 55b with an uneven film thickness.

[0318] Specifically, the second wiring covering portion 61b has a film thickness that gradually decreases toward the second wiring bottom wall portion 55a (wiring via bottom wall 52). In other words, the second wiring covering portion 61b has an upper end on the first wiring bottom wall portion 54a side of the first wiring hole portion 54 and a lower end on the second wiring bottom wall portion 55a (wiring via bottom wall 52) side of the second wiring hole portion 55, and has a film thickness that gradually decreases from the upper end to the lower end. The film thickness at the lower end is smaller than the film thickness at the upper end.

[0319] The second wiring coating portion 61b has a thicker portion than the first wiring coating portion 61a. Specifically, the film thickness at the upper end of the second wiring coating portion 61b is greater than the film thickness at the lower end of the first wiring coating portion 61a. In this configuration, the film thickness at the upper end of the second wiring coating portion 61b is smaller than the film thickness at the upper end of the first wiring coating portion 61a.

[0320] The film thickness at the upper end of the second wiring coating portion 61b may be greater than the film thickness at the upper end of the first wiring coating portion 61a. The film thickness at the upper end of the second wiring coating portion 61b may be greater than or less than the film thickness at the upper end of the second coating portion 41b of the via electrode 40.

[0321] In this configuration, the film thickness at the upper end of the second wiring coating 61b is greater than the thickness of the silicide 37. The film thickness at the upper end of the second wiring coating 61b may be less than the thickness of the silicide 37. In this configuration, the film thickness at the lower end of the second wiring coating 61b is less than the thickness of the silicide 37. The film thickness at the lower end of the second wiring coating 61b may be greater than the thickness of the silicide 37.

[0322] The wiring via base electrode 61 has a film-like third wiring covering portion 61c on the wiring via bottom wall 52. The third wiring covering portion 61c covers the second wiring bottom wall portion 55a (wiring via bottom wall 52) of the second wiring hole portion 55 in a film-like manner. In this configuration, the third wiring covering portion 61c is mechanically and electrically connected to the gate wiring 22 at the wiring via bottom wall 52.

[0323] The third wiring insulation portion 61c covers the wiring via bottom wall 52 with an uneven film thickness. Specifically, the third wiring insulation portion 61c rises from the periphery of the wiring via bottom wall 52 toward the inside of the wiring via bottom wall 52.

[0324] The third wiring covering portion 61c has a thicker portion than the first wiring covering portion 61a. Specifically, the film thickness of the inner portion of the third wiring covering portion 61c is greater than the film thickness at the lower end of the first wiring covering portion 61a. The film thickness of the inner portion of the third wiring covering portion 61c may be greater or less than the film thickness at the upper end of the first wiring covering portion 61a.

[0325] The third wiring coating portion 61c has a thicker portion than the second wiring coating portion 61b. Specifically, the film thickness of the inner portion of the third wiring coating portion 61c is greater than the film thickness at the lower end of the second wiring coating portion 61b. The film thickness of the inner portion of the third wiring coating portion 61c may be greater or less than the film thickness at the upper end of the second wiring coating portion 61b.

[0326] The film thickness of the inner portion of the third wiring coating 61c may be greater than or less than the film thickness of the inner portion of the third coating 41c of the via electrode 40. In this embodiment, the film thickness of the third wiring coating 61c is greater than the thickness of the silicide 37. The film thickness of the third wiring coating 61c may also be less than the thickness of the silicide 37.

[0327] The wiring via base electrode 61 has a film-like fourth wiring covering portion 61d over the wiring step portion 56. The fourth wiring covering portion 61d covers the wiring step portion 56 in a film-like manner and is connected to the lower end of the first wiring covering portion 61a and the upper end of the second wiring covering portion 61b. The fourth wiring covering portion 61d has a portion that is thicker than the first wiring covering portion 61a.

[0328] The fourth wiring coating portion 61d has a portion that is thicker than the first wiring coating portion 61a. Specifically, the film thickness of the fourth wiring coating portion 61d is greater than the film thickness at the lower end of the first wiring coating portion 61a. The film thickness of the fourth wiring coating portion 61d may be greater or less than the film thickness at the upper end of the first wiring coating portion 61a.

[0329] The fourth wiring coating portion 61d has a portion that is thicker than the second wiring coating portion 61b. Specifically, the film thickness of the fourth wiring coating portion 61d is greater than the film thickness at the lower end of the second wiring coating portion 61b. The film thickness of the fourth wiring coating portion 61d may be greater than or less than the film thickness at the upper end of the second wiring coating portion 61b. In this embodiment, the film thickness of the fourth wiring coating portion 61d is greater than the thickness of the silicide 37. The film thickness of the fourth wiring coating portion 61d may be less than the thickness of the silicide 37.

[0330] In this embodiment, the wiring via base electrode 61 has a laminated structure including a first wiring via base electrode 63 and a second wiring via base electrode 64, which are stacked in that order from the wall surface of the wiring via hole 50 (wiring via side wall 51 and wiring via bottom wall 52). The wiring via base electrode 61 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of the first wiring via base electrode 63 or the second wiring via base electrode 64.

[0331] The first wiring via under electrode 63 consists of a metal film containing one of the aforementioned metals. In this embodiment, the first wiring via under electrode 63 consists of a high-purity titanium film, which is an example of a titanium-based metal film. In other words, the first wiring via under electrode 63 contains the same type of metal as the first via under electrode 43 of the via electrode 40.

[0332] The first wiring via underlay electrode 63 has a thickness less than the thickness of the interlayer film 23. The thickness of the first wiring via underlay electrode 63 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. The thickness of the first wiring via underlay electrode 63 is approximately equal to the thickness of the first via underlay electrode 43. The thickness of the first wiring via underlay electrode 63 may be greater or less than the thickness of the first via underlay electrode 43.

[0333] The thickness of the first wiring via base electrode 63 may be greater than 0 nm and 100 nm or less. The thickness of the first wiring via base electrode 63 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, and 75 nm to 100 nm.

[0334] The first wiring via base electrode 63 serves as the lowest base layer of the wiring via base electrode 61, covering the wiring via sidewall 51 and wiring via bottom wall 52 in a film-like manner. In other words, the first wiring via base electrode 63 serves as the base layer for the first wiring covering portion 61a, the second wiring covering portion 61b, the third wiring covering portion 61c, and the fourth wiring covering portion 61d, covering the first wiring hole portion 54, the second wiring hole portion 55, the wiring via bottom wall 52, and the wiring step portion 56 in a film-like manner.

[0335] The second wiring via under electrode 64 consists of a metal film containing one of the aforementioned metals. The second wiring via under electrode 64 consists of a metal film containing a different metal species than the first wiring via under electrode 63. In this embodiment, the second wiring via under electrode 64 consists of a titanium nitride film (titanium alloy film) as an example of a titanium-based metal film. In other words, the second wiring via under electrode 64 contains the same metal species as the second via under electrode 44 of the via electrode 40.

[0336] The second wiring via underlay electrode 64 has a thickness less than the thickness of the interlayer film 23. The thickness of the second wiring via underlay electrode 64 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. The thickness of the second wiring via underlay electrode 64 is greater than the thickness of the first wiring via underlay electrode 63. The thickness of the second wiring via underlay electrode 64 may be less than the thickness of the first wiring via underlay electrode 63.

[0337] The thickness of the second wiring via base electrode 64 is approximately equal to the thickness of the second via base electrode 44. The thickness of the second wiring via base electrode 64 may be greater or less than the thickness of the second via base electrode 44.

[0338] The thickness of the second wiring via base electrode 64 may be greater than 0 nm and 300 nm or less. The thickness of the second wiring via base electrode 64 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0339] The second wiring via base electrode 64 is laminated in a film-like manner on the first wiring via base electrode 63 as the main body of the wiring via base electrode 61, and covers the wiring via side wall 51 and wiring via bottom wall 52 via the first wiring via base electrode 63.

[0340] In other words, the second wiring via base electrode 64 serves as the main body of the first wiring covering portion 61a, the main body of the second wiring covering portion 61b, the main body of the third wiring covering portion 61c, and the main body of the fourth wiring covering portion 61d, and covers the first wiring hole portion 54, the second wiring hole portion 55, the wiring via bottom wall 52, and the wiring step portion 56 in a film-like manner via the first wiring via base electrode 63.

[0341] The main electrode 62 of the wiring via is made of a metal film containing one of the metals described above. The main electrode 62 of the wiring via is made of a different metal species than the first wiring via base electrode 63 and the second wiring via base electrode 64. In this embodiment, the main electrode 62 of the wiring via is made of a tungsten-based metal (high-purity tungsten or tungsten alloy). In other words, the main electrode 62 of the wiring via is made of the same metal species as the main electrode 42 of the via electrode 40.

[0342] The main via electrode 62 is embedded in the via hole 50 as the main body of the via electrode 60 via the via base electrode 61, and is electrically connected to the gate wiring 22 via the via base electrode 61. The main via electrode 42 is formed at a distance from the height of the insulating surface of the interlayer film 23 toward the bottom wall 52 of the via, and forms the electrode surface of the via electrode 60.

[0343] The main electrode 62 of the wiring via has a portion that covers the first wiring side wall portion 54b of the first wiring hole portion 54 via the first wiring covering portion 61a, a portion that covers the second wiring side wall portion 55b of the second wiring hole portion 55 via the second wiring covering portion 61b, a portion that covers the bottom wall 52 of the wiring via via the third wiring covering portion 61c, and a portion that covers the wiring step portion 56 via the fourth wiring covering portion 61d.

[0344] The semiconductor device 1A includes a gate terminal 65 located in the inner portion (inactive region 9) of the first main surface 3. The gate terminal 65 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," "gate electrode," etc. The gate terminal 65 is made of metal and is arranged in a film-like manner on the interlayer film 23 at a distance from the source terminal 45.

[0345] The gate terminal 65 includes a gate pad portion 65a, a first finger portion 65b, and a second finger portion 65c. The gate pad portion 65a is positioned on the interlayer film 23 in the pad region 9a as the main body of the gate terminal 65, and faces the pad well region 20a of the well region 20 and the pad wiring portion 22a of the gate wiring 22 in the thickness direction Z.

[0346] The gate pad portion 65a is interposed in the region between the second source pad portion 45b and the third source pad portion 45c, and faces both the second source pad portion 45b and the third source pad portion 45c in the first direction X. The gate pad portion 65a is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0347] The gate pad portion 65a has a flat area less than the flat area of ​​the source terminal 45. The flat area of ​​the gate terminal 65 may be less than the flat area of ​​the first source pad portion 45a. The flat area of ​​the gate terminal 65 may be larger or smaller than the flat area of ​​the second source pad portion 45b (third source pad portion 45c).

[0348] The first finger portion 65b is extended from the gate pad portion 65a towards the second side surface 5B in the outer region 9b and is positioned on the first wiring portion 22b of the gate wiring 22 via the interlayer film 23.

[0349] The first finger portion 65b has a portion that extends in a strip shape in a first direction X following the extending direction of the first wiring portion 22b, and a portion that extends in a strip shape in a second direction Y following the extending direction of the first wiring portion 22b. The first finger portion 65b faces the outer well region 20b of the well region 20 in the thickness direction Z.

[0350] The second finger portion 65c is extended from the gate pad portion 65a towards the fourth side surface 5D in the outer region 9b and is positioned on the second wiring portion 22c of the gate wiring 22 via the interlayer film 23.

[0351] The second finger portion 65c has a portion that extends in a strip shape in a first direction X following the extending direction of the second wiring portion 22c, and a portion that extends in a strip shape in a second direction Y following the extending direction of the second wiring portion 22c. The second finger portion 65c faces the outer well region 20b of the well region 20 in the thickness direction Z.

[0352] The gate terminal 65 is mechanically and electrically connected to the wiring via electrode 60 at least by the first finger portion 65b and the second finger portion 65c, and is electrically connected to the gate wiring 22 (first wiring portion 22b and second wiring portion 22c) via the wiring via electrode 60.

[0353] The gate terminal 65 has a portion that is mechanically and electrically connected to the wiring via electrode 60 at the gate pad portion 65a, and may also be electrically connected to the gate wiring 22 (pad wiring portion 22a) via the wiring via electrode 60. The gate terminal 65 forms a connection boundary with the wiring via electrode 60 and is electrically connected to the gate wiring 22 via the wiring via electrode 60.

[0354] The gate terminal 65, like the source terminal 45, may contain at least one metal from among tungsten-based metals, molybdenum-based metals, tantalum-based metals, titanium-based metals, cobalt-based metals, nickel-based metals, platinum-based metals, aluminum-based metals, copper-based metals, palladium-based metals, gold-based metals, and silver-based metals.

[0355] The gate terminal 65 may have a single-layer structure including a metal film, or a laminated structure including multiple metal films. In this embodiment, the gate terminal 65 has a laminated structure including a gate under electrode 66 and a gate main electrode 67, similar to the source terminal 45.

[0356] The gate substrate electrode 66 is formed as a barrier electrode for the material to be coated. The gate substrate electrode 66 has a single-layer structure containing a metal film made of one of the aforementioned metals, or a laminated structure containing multiple metal films, each made of one of the aforementioned metals. In this embodiment, the gate substrate electrode 66 contains metal species other than nickel-based metals.

[0357] The gate base electrode 66 covers the insulating surface of the interlayer film 23 in a film-like manner and is mechanically and electrically connected to the wiring via electrode 60. Specifically, the gate base electrode 66 enters the wiring via hole 50 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to the wiring via base electrode 61 of the wiring via electrode 60 within the wiring via hole 50. In this configuration, the gate base electrode 66 forms a single electrode film integrated with multiple wiring via base electrodes 61.

[0358] The gate base electrode 66 has a film thickness greater than that of the wiring via base electrode 61. Specifically, the film thickness of the gate base electrode 66 is greater than that of the upper end of the first wiring coating portion 61a. The film thickness of the gate base electrode 66 is greater than that of the upper end of the second wiring coating portion 61b. The film thickness of the gate base electrode 66 is greater than that of the inner part of the third wiring coating portion 61c. The film thickness of the gate base electrode 66 is greater than that of the fourth wiring coating portion 61d.

[0359] In this embodiment, the gate base electrode 66 has a laminated structure including a first gate base electrode 68 and a second gate base electrode 69, which are laminated in this order from the insulating surface side of the interlayer film 23. The gate base electrode 66 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of the first gate base electrode 68 or the second gate base electrode 69.

[0360] The first gate base electrode 68 consists of a metal film containing one of the aforementioned metals. In this embodiment, the first gate base electrode 68 consists of a high-purity titanium film, which is an example of a titanium-based metal film. In other words, the first gate base electrode 68 consists of the same type of metal film as the first via base electrode 43, the first source base electrode 48, and the first wiring via base electrode 63.

[0361] The first gate base electrode 68 has a thickness less than the thickness of the interlayer film 23. The thickness of the first gate base electrode 68 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. The thickness of the first gate base electrode 68 is approximately equal to the thickness of the first source base electrode 48. The thickness of the first gate base electrode 68 may be greater or less than the thickness of the first source base electrode 48.

[0362] The thickness of the first gate substrate electrode 68 may be greater than 0 nm and 100 nm or less. The thickness of the first gate substrate electrode 68 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0363] The first gate base electrode 68 forms a film covering the insulating surface of the interlayer film 23 as the lowest base layer of the gate base electrode 66. The first gate base electrode 68 enters the wiring via hole 50 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to the first wiring via base electrode 63 within the wiring via hole 50. In this configuration, the first gate base electrode 68 forms a single electrode film integrated with the first wiring via base electrode 63.

[0364] The second gate base electrode 69 consists of a metal film containing one of the aforementioned metals. The second gate base electrode 69 consists of a metal film containing a different metal species than the first gate base electrode 68. In this embodiment, the second gate base electrode 69 consists of a titanium nitride film (titanium alloy film) as an example of a titanium-based metal film. In other words, the second gate base electrode 69 consists of the same type of metal film as the second via base electrode 44, the second source base electrode 49, and the second wiring via base electrode 64.

[0365] The second gate base electrode 69 has a thickness less than the thickness of the interlayer film 23. The thickness of the second gate base electrode 69 is less than the thickness of the first interlayer film 24 and the second interlayer film 25. The thickness of the second gate base electrode 69 is greater than the thickness of the first wiring via base electrode 63.

[0366] The thickness of the second gate substrate electrode 69 may be less than the thickness of the first gate substrate electrode 68. The thickness of the second gate substrate electrode 69 is approximately equal to the thickness of the second source substrate electrode 49. The thickness of the second gate substrate electrode 69 may be greater than or less than the thickness of the second source substrate electrode 49.

[0367] The thickness of the second gate substrate electrode 69 may be greater than 0 nm and 300 nm or less. The thickness of the second gate substrate electrode 69 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 200 nm or more and 250 nm or more and 300 nm or less.

[0368] The second gate base electrode 69 is laminated in a film-like manner on the first gate base electrode 68 as the main body of the gate base electrode 66, and covers the insulating surface of the interlayer film 23 via the first gate base electrode 68.

[0369] The second gate substrate electrode 69 enters the wiring via hole 50 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to a plurality of second wiring via substrate electrodes 64 within the wiring via hole 50. In this embodiment, the second gate substrate electrode 69 forms a single electrode film integral with the plurality of second wiring via substrate electrodes 64.

[0370] The gate main electrode 67 is made of a metal film containing one of the metals described above. The gate main electrode 67 is made of a different metal species than the first gate base electrode 68 and the second gate base electrode 69. In this embodiment, the via main electrode 42 is made of an aluminum-based metal (high-purity aluminum or aluminum alloy).

[0371] In other words, the gate main electrode 67 is made of a different metal species than the via main electrode 42 and the wiring via main electrode 62. The gate main electrode 67 is made of the same type of metal film as the source main electrode 47. The aluminum alloy may be an AlSi alloy, an AlCu alloy, or an AlSiCu alloy.

[0372] The gate main electrode 67 has a thickness greater than the thickness of the gate electrode 18. The thickness of the gate main electrode 67 is greater than the thickness of the interlayer film 23. The thickness of the gate main electrode 67 may be less than the thickness of the interlayer film 23.

[0373] The thickness of the gate main electrode 67 is approximately equal to the thickness of the source main electrode 47. The thickness of the gate main electrode 67 may be greater than or less than the thickness of the source main electrode 47. The thickness of the gate main electrode 67 may be greater than 0 μm and 5 μm or less.

[0374] The thickness of the gate main electrode 67 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0375] The gate main electrode 67 is laminated in a film-like manner on the gate base electrode 66 as the main body of the gate terminal 65, and covers the insulating surface of the interlayer film 23 via the gate base electrode 66. The gate main electrode 67 enters the wiring via hole 50 from above the insulating surface of the interlayer film 23 and is mechanically and electrically connected to the wiring via main electrode 62 within the wiring via hole 50. The gate main electrode 67 forms a connection interface with the electrode surface of the wiring via main electrode 62.

[0376] The semiconductor device 1A includes a drain terminal 70 covering the second main surface 4. The drain terminal 70 may also be referred to as the "third main electrode," "third terminal (electrode)," "third pad (electrode)," "drain electrode," etc. The drain terminal 70 is mechanically and electrically connected to the first semiconductor layer 6 on the second main surface 4.

[0377] The drain terminal 70 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain terminal 70 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0378] The breakdown voltage that can be applied between the source terminal 45 and the drain terminal 70 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more, 2250V or more and 2500V or more and 3000V or less.

[0379] As described above, the semiconductor device 1A includes a silicon-containing chip 2 (to be connected), an insulating interlayer film 23, a via hole 30, a silicide 37, and a via electrode 40. The interlayer film 23 covers the chip 2. The via hole 30 is formed in the interlayer film 23 and has a via bottom wall 32 partitioned by the chip 2. The silicide 37 is formed within the via hole 30 following the via bottom wall 32. The via electrode 40 is electrically connected to the chip 2 within the via hole 30 via the silicide 37.

[0380] This configuration provides a semiconductor device 1A that contributes to improved electrical characteristics. For example, with this semiconductor device 1A, the alignment margin of the silicide 37 with respect to the via electrode 40 is reduced, and at the same time, the via electrode 40 is properly connected to the silicide 37. As a result, miniaturization and performance improvements of the semiconductor device 1A are achieved through the via electrode 40.

[0381] Chip 2 may contain SiC (silicon carbide). This configuration provides a semiconductor device 1A as a SiC semiconductor device. With a SiC semiconductor device, the electrical characteristics are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in high-voltage environments, miniaturization and performance improvement through via structures including silicide 37 and via electrodes 40 are also effective in reducing power consumption.

[0382] The via bottom wall 32 may be defined by a via recess 33 recessed in the thickness direction Z of the tip 2. In this case, the silicide 37 may be formed following the via recess 33. With this configuration, the silicide 37 is properly connected to the tip 2. As a result, the via electrode 40 is properly electrically connected to the tip 2 via the silicide 37.

[0383] The silicide 37 may consist of a metal silicide other than titanium silicide. Such a configuration is effective in avoiding an increase in contact resistance caused by titanium carbide when the tip 2 contains SiC. In this case, the via electrode 40 may contain a titanium-based metal.

[0384] The via electrode 40 may include a film-like via under electrode 41 for the silicide 37, and a via main electrode 42 electrically connected to the silicide 37 via the via under electrode 41 within the via hole 30. In this case, the silicide 37 may be made of a metal silicide other than titanium silicide. The via under electrode 41 may contain a titanium-based metal. The via main electrode 42 may contain a tungsten-based metal.

[0385] This configuration is effective in avoiding an increase in contact resistance caused by titanium carbides when the chip 2 contains SiC. The titanium-based metal is effective as a barrier film that shields against the diffusion of tungsten into the silicide 37 and SiC. Due to its physical properties, the tungsten-based metal has high conformability to the outer surface of the interlayer film 23 and the walls of the via holes 30, and is embedded in the via holes 30 at high density.

[0386] The via hole 30 may include a first hole portion 34 and a second hole portion 35. The first hole portion 34 may be demarcated by a first width W1 on the insulating surface side of the interlayer film 23. The second hole portion 35 may be demarcated by a second width W2 less than the first width W1 on the chip 2 side.

[0387] In this case, the silicide 37 may be formed within the second hole 35. With this configuration, since the location where the silicide 37 is formed is limited to within the second hole 35, the area occupied by the silicide 37 on the tip 2 (formation area) is appropriately reduced. Therefore, the miniaturization of the via structure is appropriately achieved.

[0388] The via hole 30 may have the configuration shown in Figure 17 or the configuration shown in Figure 18. Figure 17 is an enlarged cross-sectional view showing a via hole 30 according to another embodiment. Figure 18 is an enlarged cross-sectional view showing a via hole 30 according to the first embodiment. Figures 17 and 18 show the state of the wafer (2) used as a base member for the chip 2 in the manufacturing process of the semiconductor device 1A.

[0389] Referring to Figure 17, the via hole 30 in the other embodiment does not have a stepped portion 36, and has a configuration in which the second hole portion 35 is smoothly connected to the first hole portion 34. In other words, the via hole 30 in the other embodiment has an opening width that gradually (continuously) narrows from the first hole portion 34 to the second hole portion 35.

[0390] In this configuration, the area occupied (formed area) of the silicide 37 on the chip 2 is appropriately reduced, but when the seed metal film 71 of the silicide 37 is formed, the seed metal film 71 may become thicker near the opening end of the via hole 30, and an overhang portion 71a may be formed on the via side wall 31.

[0391] In this case, the film formation ability of the seed metal film 71 on the via bottom wall 32 and via side wall 31 decreases, which can result in a decrease in the conformability of the silicide 37 on the via bottom wall 32 and an increase in contact resistance. In order to resolve such problems, relatively strict process conditions are imposed during the seed metal film 71 (silicide 37) formation process.

[0392] If the via electrode 40 includes a via base electrode 41 and a via main electrode 42, such an overhang portion 71a may also occur in the via base electrode 41. In this case, the film-forming ability of the via base electrode 41 against the via bottom wall 32 and via side wall 31 is reduced, and the embedding of the via main electrode 42 into the via hole 30 may be hindered by the overhang portion 71a. Therefore, relatively strict process conditions are imposed even in the formation process of the via base electrode 41.

[0393] Referring to Figure 18, the via hole 30 according to the first embodiment has a first hole portion 34, a second hole portion 35, and a stepped portion 36 partitioned between the first hole portion 34 and the second hole portion 35. In this configuration, the relatively wide first hole portion 34 enhances the film formation of the seed metal film 71 and suppresses the formation of an overhang portion 71a.

[0394] Furthermore, since the seed metal film 71 is thickened starting from the stepped portion 36, the film formation properties of the seed metal film 71 on the relatively narrow second hole portion 35 are improved. As a result, the process conditions imposed on the seed metal film 71 (silicide 37) formation process are relaxed, and at the same time, the conformability of the silicide 37 to the via bottom wall 32 is appropriately improved.

[0395] As a result, contact resistance is suppressed. In addition, since the silicide 37 is formed in the relatively narrow second hole 35, the alignment margin of the silicide 37 with respect to the via electrode 40 is appropriately reduced.

[0396] For example, with this configuration, the silicide 37 may have a width less than the first width W1. For example, the silicide 37 may have a width ratio of 0.9 to 1.1 with respect to the second width W2 (width of the via bottom wall 32). For example, the width of the silicide 37 may be greater than or equal to the second width W2. The silicide 37 may be formed with a gap between the stepped portion 36 and the tip 2 side.

[0397] When the via electrode 40 includes a via base electrode 41 and a via main electrode 42, the formation of an overhang portion 71a is suppressed for the via base electrode 41 as well. Furthermore, since the via base electrode 41 is thickened starting from the stepped portion 36, the film formation performance of the via base electrode 41 on the relatively narrow second hole portion 35 is improved.

[0398] As a result, the via main electrode 42 is properly embedded in the via hole 30 via the via base electrode 41. Consequently, the via electrode 40 is properly connected to the silicide 37. Furthermore, the process conditions imposed on the via electrode 40 formation process are relaxed. In addition, miniaturization and performance improvement of the semiconductor device 1A are achieved through the via electrode 40.

[0399] The first hole 34 may have a first depth D1. The second hole 35 may have a second depth D2 which is less than the first depth D1. With this configuration, the covering area of ​​the seed metal film 71 on the second hole 35 is reduced, so that the decrease in the film-forming ability of the seed metal film 71 on the second hole 35 is appropriately suppressed. As a result, the conformability of the silicide 37 on the via bottom wall 32 is appropriately improved.

[0400] Furthermore, when the via electrode 40 includes a via base electrode 41 and a via main electrode 42, the covering area of ​​the via base electrode 41 on the second hole 35 is reduced, thereby appropriately suppressing the decrease in the film-forming ability of the via base electrode 41 on the second hole 35. As a result, the conformability of the via base electrode 41 on the via bottom wall 32 is appropriately improved.

[0401] The interlayer film 23 may have a laminated structure including a first interlayer film 24 and a second interlayer film 25 stacked in this order from the chip 2 side. In this case, the first hole 34 may be partitioned on the second interlayer film 25 side, and the second hole 35 may be partitioned on the first interlayer film 24 side.

[0402] In this configuration, the first hole 34 is formed targeting the second interlayer membrane 25, and the second hole 35 is formed targeting the first interlayer membrane 24. Therefore, the accuracy of the width and depth of the first hole 34 is improved by utilizing the second interlayer membrane 25, and the accuracy of the width and depth of the second hole 35 is improved by utilizing the first interlayer membrane 24.

[0403] For example, the second interlayer film 25 may contain an insulating material different from the first interlayer film 24. With this configuration, the precision of the first hole 34 is improved by utilizing the etching selectivity ratio of the second interlayer film 25 to that of the first interlayer film 24, and the precision of the second hole 35 is improved by utilizing the etching selectivity ratio of the first interlayer film 24 to that of the second interlayer film 25.

[0404] From an alternative perspective, the semiconductor device 1A may include a chip 2 to be connected, an insulating interlayer film 23, via holes 30, a via base electrode 41, and a via main electrode 42. The interlayer film 23 may cover the chip 2. The via holes 30 may have a first hole portion 34, a second hole portion 35, a via bottom wall 32, and a stepped portion 36.

[0405] The first hole 34 may be demarcated by a first width W1 on the insulating surface side of the interlayer film 23. The second hole 35 may be demarcated by a second width W2 less than the first width W1 on the tip 2 side relative to the first hole 34. The via bottom wall 32 may be demarcated by the tip 2. The stepped portion 36 may be demarcated between the first hole 34 and the second hole 35.

[0406] The via base electrode 41 may have a film-like first coating portion 41a over the first hole portion 34, a film-like second coating portion 41b over the second hole portion 35, a film-like third coating portion 41c over the via bottom wall 32, and a film-like fourth coating portion 41d over the stepped portion 36. The via main electrode 42 may be embedded in the via hole 30 via the via base electrode 41 and electrically connected to the tip 2 via the via base electrode 41.

[0407] This configuration provides a semiconductor device 1A that contributes to improved electrical characteristics. For example, with this semiconductor device 1A, the first hole 34, the second hole 35, the via bottom wall 32, and the stepped portion 36 improve the film formation of the via under electrode 41 on the via hole 30. As a result, the via under electrode 41 is properly connected to the via bottom wall 32, and the via main electrode 42 is properly electrically connected to the chip 2 via the via under electrode 41. Consequently, contact resistance is suppressed.

[0408] The first coating portion 41a may have a film thickness that gradually decreases toward the second hole portion 35. The second coating portion 41b may have a portion that is thicker than the first coating portion 41a. The second coating portion 41b may have a film thickness that gradually decreases toward the via bottom wall 32.

[0409] The third coating portion 41c may have a portion that is thicker than the first coating portion 41a. The third coating portion 41c may have a portion that is thicker than the second coating portion 41b. The fourth coating portion 41d may have a portion that is thicker than the first coating portion 41a. The fourth coating portion 41d may have a portion that is thicker than the second coating portion 41b.

[0410] The chip 2 may contain silicon. In this case, the semiconductor device 1A may include a silicide 37 formed in the via hole 30 following the via bottom wall 32. In this case, the via under electrode 41 may have a film-like third coating portion 41c on the silicide 37. The via main electrode 42 may be electrically connected to the chip 2 via the silicide 37 and the via under electrode 41.

[0411] With this configuration, when the seed metal film 71 of the silicide 37 is formed to conform to the wall surface of the via hole 30, the first hole portion 34, the second hole portion 35, the via bottom wall 32, and the stepped portion 36 improve the film formation of the seed metal film 71 on the via hole 30. As a result, the conformability of the silicide 37 to the via bottom wall 32 is appropriately improved, and contact resistance is suppressed.

[0412] Furthermore, since the silicide 37 is formed in the relatively narrow second hole 35, the alignment margin of the silicide 37 with respect to the via electrode 40 is appropriately reduced. Also, the via electrode 40 is appropriately connected to the silicide 37 in the second hole 35. As a result, miniaturization and performance improvement of the semiconductor device 1A are achieved through the via electrode 40.

[0413] Chip 2 may contain SiC (silicon carbide). This configuration provides a semiconductor device 1A as a SiC semiconductor device. With a SiC semiconductor device, the electrical characteristics are appropriately improved due to the physical properties of SiC. In particular, in the case of a SiC semiconductor device, the effect of suppressing contact resistance is also effective in reducing power consumption.

[0414] From a different perspective, the semiconductor device 1A may include gate wiring 22 (wiring electrodes) to be connected, an insulating interlayer film 23, wiring via holes 50, wiring via base electrodes 61, and wiring via main electrodes 62. The interlayer film 23 covers the gate wiring 22. The wiring via holes 50 may have a wiring via bottom wall 52, a first wiring hole portion 54, a second wiring hole portion 55, and a wiring step portion 56.

[0415] The first wiring hole 54 may be partitioned by a third width W3 on the insulating surface side of the interlayer film 23. The second wiring hole 55 may be partitioned by a fourth width W4 less than the third width W3 on the gate wiring 22 side relative to the first wiring hole 54. The wiring via bottom wall 52 may be partitioned by the gate wiring 22. The wiring step 56 may be partitioned between the first wiring hole 54 and the second wiring hole 55.

[0416] The wiring via base electrode 61 may have a film-like first wiring covering portion 61a for the first wiring hole portion 54, a film-like second wiring covering portion 61b for the second wiring hole portion 55, a film-like third wiring covering portion 61c for the wiring via bottom wall 52, and a film-like fourth wiring covering portion 61d for the wiring step portion 56. The wiring via main electrode 62 may be embedded in the wiring via hole 50 via the wiring via base electrode 61 and electrically connected to the gate wiring 22 via the wiring via base electrode 61.

[0417] This configuration provides a semiconductor device 1A that contributes to improving electrical characteristics. For example, with this semiconductor device 1A, the film formation properties of the wiring via base electrode 61 on the wiring via hole 50 are improved by the first wiring hole portion 54, the second wiring hole portion 55, the wiring via bottom wall 52, and the wiring step portion 56.

[0418] As a result, the wiring via base electrode 61 is properly connected to the wiring via bottom wall 52, and the wiring via main electrode 62 is properly electrically connected to the gate wiring 22 via the wiring via base electrode 61. Consequently, contact resistance is suppressed.

[0419] The first wiring coating portion 61a may have a film thickness that gradually decreases toward the second wiring hole portion 55. The second wiring coating portion 61b may have a portion that is thicker than the first wiring coating portion 61a. The second wiring coating portion 61b may have a film thickness that gradually decreases toward the wiring via bottom wall 52.

[0420] The third wiring insulation portion 61c may have a portion that is thicker than the first wiring insulation portion 61a. The third wiring insulation portion 61c may have a portion that is thicker than the second wiring insulation portion 61b. The fourth wiring insulation portion 61d may have a portion that is thicker than the first wiring insulation portion 61a. The fourth wiring insulation portion 61d may have a portion that is thicker than the second wiring insulation portion 61b.

[0421] From an alternative perspective, the semiconductor device 1A may include a silicon-containing chip 2, a gate structure 16, an insulating interlayer film 23, via holes 30, a silicide 37, and via electrodes 40. The gate structure 16 may be formed on the chip 2. The interlayer film 23 may cover the gate structure 16 on the chip 2.

[0422] The via holes 30 may be formed in the interlayer film 23 on the side of the gate structure 16. The via holes 30 may have a via bottom wall 32 partitioned by the tip 2. The silicide 37 may be formed within the via holes 30 following the via bottom wall 32. The via electrode 40 may be connected to the silicide 37 within the via holes 30.

[0423] This configuration provides a semiconductor device 1A that contributes to improving electrical characteristics. For example, with this semiconductor device 1A, the alignment margin of the silicide 37 with respect to the via electrode 40 is reduced, and at the same time, the via electrode 40 is properly connected to the silicide 37.

[0424] Furthermore, the reduction in alignment margin caused by the silicide 37 narrows the distance between the silicide 37 and the gate structure 16. This allows for miniaturization and improved performance of the semiconductor device 1A through the via electrode 40.

[0425] The gate structure 16 may be of the planar electrode type. With this configuration, the distance between the silicide 37 and the planar electrode type gate structure 16 is narrowed by reducing the alignment margin caused by the silicide 37.

[0426] The semiconductor device 1A may include an impurity region formed on the surface layer of the chip 2. The impurity region may have an n-type conductivity or a p-type conductivity. In this case, the via hole 30 may be formed in the interlayer film 23 in a region above the impurity region.

[0427] The silicide 37 may be electrically connected to the impurity region. The via electrode 40 may be electrically connected to the impurity region via the silicide 37. This configuration reduces the alignment margin of the silicide 37 with respect to the impurity region, while also ensuring that the via electrode 40 is properly electrically connected to the impurity region via the silicide 37.

[0428] The semiconductor device 1A may include a plurality of impurity regions, namely a first n-type impurity region and a second p-type impurity region. In this case, the via electrode 40 may be electrically connected to both the first and second impurity regions via the silicide 37.

[0429] The n-type impurity region (first impurity region) may be the n-type source region 13. The n-type impurity region (first impurity region) may be the n-type diode region 12. The p-type impurity region (second impurity region) may be the p-type body region 10. The p-type impurity region (second impurity region) may be the p-type contact region 14.

[0430] From an alternative perspective, the semiconductor device 1A may include a silicon-containing chip 2, a gate electrode 18 (planar electrode), an insulating interlayer film 23, via holes 30, a silicide 37, and a via electrode 40. The gate electrode 18 may be placed on top of the chip 2. The interlayer film 23 may cover the gate electrode 18 on top of the chip 2.

[0431] The via hole 30 may be formed in the interlayer film 23 on the side of the gate electrode 18. The via hole 30 may have a via bottom wall 32 partitioned by the tip 2. The silicide 37 may be formed within the via hole 30 following the via bottom wall 32. The via electrode 40 may be connected to the silicide 37 within the via hole 30.

[0432] This configuration provides a semiconductor device 1A that contributes to improving electrical characteristics. For example, with this semiconductor device 1A, the alignment margin of the silicide 37 with respect to the via electrode 40 is reduced, and at the same time, the via electrode 40 is properly connected to the silicide 37.

[0433] Furthermore, the reduction in alignment margin caused by the silicide 37 narrows the distance between the silicide 37 and the gate electrode 18. This allows for miniaturization and performance improvement of the semiconductor device 1A through the via electrode 40.

[0434] The via hole 30 may include a first hole portion 34 and a second hole portion 35. The first hole portion 34 may be demarcated by a first width W1 on the insulating surface side of the interlayer film 23. The second hole portion 35 may be demarcated by a second width W2 less than the first width W1 on the chip 2 side.

[0435] In this case, the silicide 37 may be formed within the second hole 35. With this configuration, since the location where the silicide 37 is formed is limited to within the second hole 35, the area occupied by the silicide 37 on the chip 2 (formation area) is appropriately reduced.

[0436] The first hole 34 may have a first depth D1. The second hole 35 may have a second depth D2 which is less than the first depth D1. With this configuration, the covering area of ​​the seed metal film 71 on the second hole 35 is reduced, so that the decrease in the film-forming ability of the seed metal film 71 on the second hole 35 is appropriately suppressed. As a result, the conformability of the silicide 37 on the via bottom wall 32 is appropriately improved.

[0437] The first hole 34 may be formed on the insulating surface side of the interlayer film 23 with respect to the height of the electrode surface of the gate electrode 18. The second hole 35 may be formed on the tip 2 side with respect to the height of the electrode surface of the gate electrode 18. With this configuration, the location where the silicide 37 is formed is appropriately limited to the tip 2 side with respect to the height of the electrode surface of the gate electrode 18.

[0438] The interlayer membrane 23 may have a laminated structure including a first interlayer membrane 24 and a second interlayer membrane 25. The first interlayer membrane 24 may cover the gate electrode 18. The second interlayer membrane 25 may cover the gate electrode 18 via the first interlayer membrane 24. The first interlayer membrane 24 may be thinner than the gate electrode 18. The second interlayer membrane 25 may be thicker than the first interlayer membrane 24. The second interlayer membrane 25 may be thicker than the gate electrode 18.

[0439] The first hole 34 may be partitioned by the second interlayer membrane 25, and the second hole 35 may be partitioned by the first interlayer membrane 24. With this configuration, the first hole 34 is formed targeting the second interlayer membrane 25, and the second hole 35 is formed targeting the first interlayer membrane 24. Therefore, the accuracy of the width and depth of the first hole 34 is improved by utilizing the second interlayer membrane 25, and the accuracy of the width and depth of the second hole 35 is improved by utilizing the first interlayer membrane 24.

[0440] For example, the second interlayer film 25 may contain an insulating material different from the first interlayer film 24. With this configuration, the precision of the first hole 34 is improved by utilizing the etching selectivity ratio of the second interlayer film 25 to that of the first interlayer film 24, and the precision of the second hole 35 is improved by utilizing the etching selectivity ratio of the first interlayer film 24 to that of the second interlayer film 25.

[0441] The gate electrode 18 may contain polysilicon. The first interlayer film 24 may contain silicon oxide that does not contain phosphorus. The second interlayer film 25 may contain silicon oxide that contains phosphorus. With this configuration, the second interlayer film 25 can be smoothed by a reflow process (heating and melting process) and have an insulating surface.

[0442] This allows the via holes 30 (first holes 34) to be properly formed in the smoothed second interlayer film 25. In this case, the diffusion of phosphorus from the second interlayer film 25 to the gate electrode 18 is blocked by the phosphorus-free first interlayer film 24. This suppresses fluctuations in the electrical properties (e.g., resistance) of the gate electrode 18.

[0443] Figure 19 is an enlarged plan view showing the main part of the active region 8 of the semiconductor device 1B according to the second embodiment. Figure 20 is a cross-sectional view along the line XX-XX shown in Figure 19. Figure 21 is a cross-sectional view along the line XXI-XXI shown in Figure 19. Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 19. Figure 23 is a cross-sectional view along the line XXIII-XXIII shown in Figure 19. Figure 24 is an enlarged cross-sectional view showing the main part of the configuration shown in Figure 20.

[0444] Referring to Figures 19 to 24, semiconductor device 1B has a trench gate type transistor structure T instead of a planar gate type transistor structure T. Similar to semiconductor device 1A, semiconductor device 1B includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and an inactive region 9.

[0445] The semiconductor device 1B includes a plurality of trench-type (trench electrode type) gate structures 76 formed on the first main surface 3 in the inner portion (active region 8) of the first main surface 3. The gate structures 76 may also be referred to as "trench structures," "trench gate structures," etc.

[0446] Multiple gate structures 76 are formed in the active region 8 at intervals from the periphery of the first main surface 3, but not in the inactive region 9. Multiple gate structures 76 are formed at intervals from the bottom of the second semiconductor layer 7 (first semiconductor layer 6) toward the first main surface 3. Multiple gate structures 76 extend in a strip-like manner in the first direction X in a plan view and are arranged at intervals in the second direction Y. Multiple gate structures 76 extend in a stripe-like manner in the first direction X in a plan view.

[0447] The gate structure 76 has a long side (side surface) formed by the m-plane ((1-100) plane) of the SiC single crystal, and a short side (side surface) formed by the a-plane ((11-20) plane) of the SiC single crystal. Depending on the extension direction of the gate structure 76, the long side may be formed by the m-plane and the short side may be formed by the a-plane.

[0448] The side surface of the gate structure 76 may be formed substantially perpendicular to the first main surface 3. The side surface of the gate structure 76 may be inclined at an angle with respect to the first main surface 3. In other words, the gate structure 76 may be formed in a tapered shape toward the second main surface 4. The gate structure 76 may have an inclined open end. The open end of the gate structure 76 may be curved in an arc shape (circular arc shape).

[0449] The bottom surface of the gate structure 76 is formed by the c-plane (Si plane) of the SiC single crystal. The bottom surface of the gate structure 76 may extend in a nearly flat manner. The bottom surface of the gate structure 76 may be curved in an arc towards the second main surface 4.

[0450] The gate structure 76 may have a width greater than 0 μm and not more than 3 μm. The width of the gate structure 76 may have a value belonging to at least one of the ranges of greater than 0 μm and not more than 0.5 μm, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0451] The pitch between the plurality of gate structures 76 may be greater than the width of the gate structure 76. The pitch between the gate structures 76 may be less than the width of the gate structure 76. The pitch between the gate structures 76 may be greater than 0 μm and not more than 3 μm.

[0452] The pitch between the gate structures 76 may have a value belonging to at least one of the ranges of greater than 0 μm and not more than 0.5 μm, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0453] The gate structure 76 may have a depth greater than 0 μm and not more than 3 μm. The depth of the gate structure 76 may have a value belonging to at least one of the ranges of greater than 0 μm and not more than 0.5 μm, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0454] The plurality of gate structures 76 each include a trench 77, an insulating film 78, and a buried electrode 79. The trench 77 may be referred to as a "gate trench", the insulating film 78 may be referred to as a "gate insulating film", and the buried electrode 79 may be referred to as a "gate buried electrode". The trench 77 is formed on the first main surface 3 and demarcates the wall surfaces (side surfaces and bottom surface) of the gate structure 76.

[0455] The insulating film 78 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 78 has a single-layer structure made of a silicon oxide film. The insulating film 78 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The insulating film 78 may include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0456] The insulating film 78 may have a thickness greater than 0 nm and less than or equal to 150 nm. The thickness of the insulating film 78 may have a value that falls within at least one of the following ranges: greater than 0 nm and less than or equal to 10 nm, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0457] The insulating film 78 coats the walls (sides and bottom) of the trench 77 in a film-like manner. The insulating film 78 may cover the walls of the trench 77 with a uniform thickness. The thickness of the insulating film 78 covering the bottom of the trench 77 may be greater than the thickness of the insulating film 78 covering the sides of the trench 77.

[0458] The embedded electrode 79 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon. The embedded electrode 79 is embedded in the trench 77 via an insulating film 78. The embedded electrode 79 has an electrode surface located on the bottom side of the trench 77 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 77. The electrode surface may have a recess toward the bottom side.

[0459] The semiconductor device 1B, like the semiconductor device 1A, includes a plurality of p-type body regions 10 formed in the second semiconductor layer 7 in the inner part of the first main surface 3. In this embodiment, the plurality of body regions 10 are formed in the surface layer of the first main surface 3 in the region between the plurality of gate structures 76.

[0460] Multiple body regions 10 are arranged at intervals in a first direction X, following the extending direction of the multiple gate structures 76, and each extends in a strip-like manner in the first direction X. The interval between the multiple body regions 10 in the first direction X is less than the length of the body region 10 in the first direction X. The interval between the multiple body regions 10 in the first direction X may be greater than the length of the body region 10 in the first direction X.

[0461] With respect to the multiple body regions 10 on one and the other side of the second direction Y, the multiple body regions 10 on the other side are in a one-to-one correspondence with the multiple body regions 10 on the one side. In other words, the multiple body regions 10 are arranged in a matrix in the first direction X and the second direction Y.

[0462] The multiple body regions 10 on the other side may be arranged offset in the first direction X relative to the multiple body regions 10 on the one side, and may face the region between the multiple body regions 10 on the one side in the second direction Y. In other words, the multiple body regions 10 may be arranged in a staggered pattern in the first direction X and the second direction Y.

[0463] The semiconductor device 1B, like the semiconductor device 1A, includes an n-type diode region 12 formed in the region between the multiple body regions 10 on the surface layer of the first main surface 3. The diode region 12 is partitioned into regions between multiple gate structures 76 adjacent in the second direction Y and regions between multiple body regions 10 adjacent in the first direction X. The total plane area of ​​the multiple diode regions 12 is less than the total plane area of ​​the multiple body regions 10.

[0464] In this configuration, each diode region 12 consists of a part of the second semiconductor layer 7 and has an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. The n-type impurity concentration of the diode region 12 may be higher or lower than that of the second semiconductor layer 7.

[0465] The semiconductor device 1B, like the semiconductor device 1A, includes a plurality of n-type source regions 13 formed on the surface of a plurality of body regions 10. In this embodiment, the plurality of source regions 13 are each formed on the surface of a plurality of body regions 10 in the region between a plurality of gate structures 76, and each extends in a strip shape in the first direction X following the extending direction of the plurality of gate structures 76.

[0466] Multiple source regions 13 are formed in the inner part of the corresponding body region 10, spaced apart from the periphery (both ends in the first direction X) of the corresponding body region 10. The multiple source regions 13 face the diode region 12 via a portion of the corresponding body region 10 in the horizontal direction.

[0467] Multiple source regions 13 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a part of the body region 10. Multiple source regions 13 are connected to multiple gate structures 76 in the second direction Y, and face the embedded electrode 79 via an insulating film 78.

[0468] The semiconductor device 1B, like the semiconductor device 1A, includes a plurality of p-type contact regions 14 formed on the surface of a plurality of body regions 10. In this embodiment, the plurality of contact regions 14 are formed on the surface of the plurality of body regions 10 in the regions between the plurality of gate structures 76.

[0469] In this configuration, the multiple contact regions 14 are formed on the surface of the multiple body regions 10 in a one-to-one correspondence. Similar to the semiconductor device 1A, the multiple contact regions 14 penetrate the corresponding source region 13 in the thickness direction Z at the inner (intermediate) portion of the corresponding body region 10.

[0470] The multiple contact regions 14 are formed in a rectangular shape in plan view and each has a length smaller than the length of the multiple source regions 13 in the first direction X. The length of the contact regions 14 may be greater than the length of the source regions 13. The multiple contact regions 14 are connected to the multiple gate structures 76 in the second direction Y and face the embedded electrode 79 via an insulating film 78.

[0471] Multiple contact regions 14 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a portion of the body region 10. In this configuration, the multiple contact regions 14 are formed deeper than the multiple source regions 13. The multiple contact regions 14 may also be formed shallower than the multiple source regions 13.

[0472] With respect to the multiple contact regions 14 on one and the other side of the second direction Y, the multiple contact regions 14 on the other side are in a one-to-one correspondence with the multiple contact regions 14 on the one side. In other words, the multiple contact regions 14 are arranged in a matrix in the first direction X and the second direction Y.

[0473] The multiple contact regions 14 on the other side may be arranged offset in the first direction X relative to the multiple contact regions 14 on the one side, and may face the region between the multiple contact regions 14 on the one side (multiple source regions 13) in the second direction Y. In other words, the multiple contact regions 14 may be arranged in a staggered pattern in the first direction X and the second direction Y.

[0474] The semiconductor device 1B, like the semiconductor device 1A, includes a well region 20, a main surface insulating film 21, gate wiring 22, and an interlayer film 23. In this embodiment, the main surface insulating film 21 covers the first main surface 3 with active regions 8 and inactive regions 9, and is connected to a plurality of insulating films 78 in the active region 8. In this embodiment, the main surface insulating film 21 forms a single insulating film integral with the plurality of insulating films 78.

[0475] The gate wiring 22 may contain the same conductive material as the embedded electrode 79. In this embodiment, the gate wiring 22 enters into a plurality of trenches 77 from above the main surface insulating film 21 and is mechanically and electrically connected to the plurality of embedded electrodes 79 within the plurality of trenches 77. In this embodiment, the gate wiring 22 is formed integrally with the plurality of embedded electrodes 79 as a lead electrode (lead wire).

[0476] In this embodiment, the interlayer film 23 covers a plurality of gate structures 76 in the active region 8. Specifically, the interlayer film 23 has a laminated structure including a first interlayer film 24 and a second interlayer film 25, similar to the semiconductor device 1A.

[0477] In this configuration, the first interlayer membrane 24 coats the main surface insulating film 21 in a film-like manner in the active region 8, penetrates into a plurality of trenches 77 from above the main surface insulating film 21, and coats the plurality of embedded electrodes 79 within the plurality of trenches 77. In this configuration, the second interlayer membrane 25 coats the first interlayer membrane 24 in a film-like manner in the active region 8, and coats the plurality of embedded electrodes 79 via the first interlayer membrane 24.

[0478] The semiconductor device 1B, like the semiconductor device 1A, includes a plurality of via holes 30 formed in the interlayer film 23 in the active region 8. In this embodiment, the plurality of via holes 30 each extend in a strip-like manner in the first direction X and are formed with intervals in the second direction Y. The plurality of via holes 30 extend in a stripe-like manner in the first direction X. The plurality of via holes 30 may be arranged in a matrix or staggered pattern with intervals in the first direction X and the second direction Y, similar to the semiconductor device 1A.

[0479] In this embodiment, the multiple via holes 30 are formed in a one-to-one correspondence with the mesa portion partitioned between the multiple gate structures 76, and extend in a strip shape in the first direction X following the direction of extension of the mesa portion (the direction of extension of the multiple gate structures 76).

[0480] Multiple via holes 30 are formed on the sides of multiple gate structures 76, spaced apart from each other in a cross-sectional view. The horizontal insulation distance between the via holes 30 and the gate structures 76 is smaller than the width of the gate structures 76. The insulation distance may be larger than the width of the gate structures 76. The insulation distance may be 0 μm or more and 1 μm or less.

[0481] The insulation distance may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less.

[0482] The plurality of via holes 30 straddle a plurality (in this form, a plurality) of body regions 10 adjacent to each other in the first direction X across one or a plurality (in this form, a plurality) of diode regions 12 in a plan view. Thereby, the plurality of via holes 30 expose the plurality of body regions 10, the plurality of diode regions 12, the plurality of source regions 13, and the plurality of contact regions 14.

[0483] The plurality of via holes 30 each have a via sidewall 31 partitioned by an interlayer film 23 and a via bottom wall 32 partitioned by the chip 2 (first main surface 3), similar to the case of the semiconductor device 1A. The via sidewall 31 is partitioned by the main surface insulating film 21, the first interlayer film 24, and the second interlayer film 25 in this form.

[0484] The via bottom wall 32 is formed in the plurality of body regions 10, the plurality of source regions 13, the plurality of contact regions 14, and the plurality of diode regions 12 in this form. The via bottom wall 32 is partitioned by a via recess 33, similar to the case of the semiconductor device 1A. That is, the via bottom wall 32 is positioned on the second main surface 4 side rather than the height position of the connection interface portion between the first main surface 3 and the main surface insulating film 21 in this form.

[0485] The via recess 33 has a corner portion that continues in an arc shape with respect to the via sidewall 31 and has an inner portion (bottom wall portion) that extends flatly. The via recess 33 is formed at an interval from the depth position of the bottom wall of the plurality of gate structures 76 toward the first main surface 3 side. The via recess 33 is formed at an interval from the depth position of the bottom of the plurality of body regions 10 toward the first main surface 3 side.

[0486] The via recess 33 is formed at an interval from the depth position of the bottom of the plurality of source regions 13 and the depth position of the bottom of the plurality of contact regions 14 toward the first main surface 3 side. The presence or absence of the via recess 33 is arbitrary, and the via bottom wall 32 may be partitioned by the first main surface 3.

[0487] The multiple via holes 30, as in the semiconductor device 1A, have a cross-sectional shape in which the opening width on the chip 2 side is narrower than the opening width on the insulating surface side of the interlayer film 23. Specifically, the multiple via holes 30 have a cross-sectional shape in which the opening width narrows in a stepwise manner (downward staircase shape) from the insulating surface side of the interlayer film 23 toward the chip 2 side. The multiple via holes 30 each include a first hole portion 34, a second hole portion 35, and a stepped portion 36, respectively.

[0488] Similar to the semiconductor device 1A, the first hole 34 is defined by a first width W1 and a first depth D1 on the insulating surface side of the interlayer film 23, and the second hole 35 is defined by a second width W2 and a second depth D2 on the chip 2 side relative to the first hole 34. The first width W1 and the second width W2 are less than the width of the gate structure 76.

[0489] The first width W1 and the second width W2 may be greater than the width of the gate structure 76. The first width W1 may be greater than the width of the gate structure 76, and the second width W2 may be less than the width of the gate structure 76. For other details of the via hole 30, the description of the via hole 30 of the semiconductor device 1A applies.

[0490] The semiconductor device 1B, like the semiconductor device 1A, includes silicides 37 formed within a plurality of via holes 30 following the via bottom walls 32. In this embodiment, the silicides 37 are formed at a distance from the depth position of the bottom walls of the plurality of gate structures 76 toward the first main surface 3, and are formed at a distance from the plurality of gate structures 76 toward the second direction Y.

[0491] The silicide 37 extends in a strip-like shape in a first direction X, following the direction of extension of the via bottom wall 32 (via recess 33). In a plan view, the silicide 37 crosses multiple body regions 10 and multiple diode regions 12. The silicide 37 is electrically connected to the multiple body regions 10, multiple diode regions 12, multiple source regions 13 and multiple contact regions 14 in the region between the multiple gate structures 76.

[0492] The silicide 37 forms ohmic contact with multiple source regions 13 and multiple contact regions 14. On the other hand, the silicide 37 forms a Schottky junction with the diode region 12. This forms a Schottky barrier diode Di2. Further description of the silicide 37 is provided in the description of the silicide 37 of semiconductor device 1A.

[0493] The semiconductor device 1B, like the semiconductor device 1A, includes a plurality of via electrodes 40 embedded in a plurality of via holes 30. The plurality of via electrodes 40, like the semiconductor device 1A, each include a via base electrode 41 and a via main electrode 42. The via base electrode 41 has a first coating portion 41a, a second coating portion 41b, a third coating portion 41c, and a fourth coating portion 41d.

[0494] The via base electrode 41 has a laminated structure including a first via base electrode 43 and a second via base electrode 44, which are stacked in this order from the walls of the via hole 30 (via side wall 31 and via bottom wall 32). The via main electrode 42 is embedded in the via hole 30 via the via base electrode 41 as the main body of the via electrode 40 and is electrically connected to the silicide 37 via the via base electrode 41. For further details of the via electrode 40, refer to the description of the via electrode 40 of semiconductor device 1A.

[0495] The semiconductor device 1B, like the semiconductor device 1A, includes a source terminal 45 located in the inner portion (active region 8) of the first main surface 3. The description of the source terminal 45 is the same as the description of the source terminal 45 of the semiconductor device 1A.

[0496] The semiconductor device 1B, like the semiconductor device 1A, includes one or more (one in this embodiment) wiring via holes 50, one or more (one in this embodiment) wiring via electrodes 60, and a gate terminal 65 formed in the interlayer film 23 in the inactive region 9. The descriptions of the wiring via holes 50, wiring via electrodes 60, and gate terminal 65 are the same as those for the semiconductor device 1A.

[0497] The semiconductor device 1B, like the semiconductor device 1A, includes a drain terminal 70 that covers the second main surface 4. The description of the drain terminal 70 is the same as the description of the drain terminal 70 of the semiconductor device 1A.

[0498] As described above, semiconductor device 1B also produces the same effects as semiconductor device 1A. In semiconductor device 1B, a trench electrode type gate structure 76 is used instead of a planar electrode type gate structure 16. With this configuration, the distance between the silicide 37 and the gate structure 76 is narrowed by reducing the alignment margin caused by the silicide 37. As a result, miniaturization and performance improvement of semiconductor device 1B are achieved through the via electrode 40.

[0499] The following shows modified via structures and wiring via structures. Figure 25 is a cross-sectional view showing a modified via structure. Figure 26 is a cross-sectional view showing a modified wiring via structure. The modified via structure (see Figure 25) and the modified wiring via structure (see Figure 26) are applicable to semiconductor device 1A and semiconductor device 1B.

[0500] Referring to Figure 25, the modified via structure does not have a silicide 37 in the via hole 30. In this case, the via electrode 40 is mechanically and electrically connected to the via bottom wall 32 (tip 2) within the via hole 30.

[0501] Specifically, the third coating portion 41c of the via base electrode 41 covers the via bottom wall 32 with a film thickness and is mechanically and electrically connected to the via bottom wall 32. The third coating portion 41c is electrically connected to the body region 10, source region 13, contact region 14, and diode region 12 at the via bottom wall 32.

[0502] The via main electrode 42 is electrically connected to the via bottom wall 32 via the via base electrode 41. Specifically, the via main electrode 42 is electrically connected to the body region 10, source region 13, contact region 14, and diode region 12 via the second coating portion 41b at the via bottom wall 32.

[0503] Referring to Figure 26, the modified wiring via structure includes wiring silicides 80 formed within a plurality of wiring via holes 50, following the shape of the wiring via bottom walls 52. The wiring silicides 80 are salicides formed in a self-aligned manner with respect to the wiring via bottom walls 52.

[0504] In other words, the wiring silicide 80 is an alloy layer in which the Si of the gate wiring 22 is alloyed with metal at the wiring via bottom wall 52. Furthermore, the wiring silicide 80 is a polyside in which the polysilicon of the gate wiring 22 is alloyed with metal.

[0505] The wiring silicide 80 may include at least one of tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, cobalt silicide, nickel silicide, and platinum silicide. No particular restrictions are imposed on the type of wiring silicide 80.

[0506] Wiring silicide 80 may be made of a metal silicide other than tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, and cobalt silicide, from the viewpoint of structural identity with silicide 37. In this embodiment, wiring silicide 80 is made of nickel silicide. Wiring silicide 80 may also be made of platinum silicide.

[0507] In this configuration, the wiring silicide 80 is formed within the second wiring hole 55, following the shape of the wiring via bottom wall 52. In other words, the wiring silicide 80 is formed at a distance from the wiring step portion 56 of the wiring via hole 50 toward the gate wiring 22, and is not located within the first wiring hole 54.

[0508] In this embodiment, the wiring silicide 80 is formed to conform to the wiring via recess 53. That is, the wiring silicide 80 is formed below the height of the wiring surface of the gate wiring 22. Specifically, the wiring silicide 80 is formed below the height of the connection interface between the wiring surface of the gate wiring 22 and the interlayer film 23 (first interlayer film 24).

[0509] In this configuration, the wiring silicide 80 is formed with a gap between it and the bottom wall of the wiring via recess 53, from the height of the wiring surface of the gate wiring 22. Of course, the wiring silicide 80 may also have a portion (a raised portion) that protrudes above the height of the wiring surface of the gate wiring 22.

[0510] The wiring silicide 80 covers the corners and inner parts of the wiring via recess 53 in a film-like manner. Alternatively, the wiring silicide 80 may cover the inner parts of the wiring via recess 53 in a film-like manner, leaving the corners of the wiring via recess 53 exposed.

[0511] The wiring silicide 80 has a width less than or equal to the third width W3 of the first wiring hole 54. Preferably, the width of the wiring silicide 80 is 3 / 4 or more of the fourth width W4 of the second wiring hole 55. The width of the wiring silicide 80 may be greater than or equal to the fourth width W4. Preferably, the wiring silicide 80 has a width ratio of 0.9 to 1.1 with respect to the fourth width W4.

[0512] The width of the wiring silicide 80 is preferably 3 / 4 or more of the width of the wiring via bottom wall 52. The width of the wiring silicide 80 may be greater than or equal to the width of the wiring via bottom wall 52. The wiring silicide 80 is preferably having a width ratio of 0.9 to 1.1 with respect to the width of the wiring via bottom wall 52.

[0513] The wiring silicide 80 may have a thickness greater than the thickness of the silicide 37. The thickness of the wiring silicide 80 may be less than the thickness of the silicide 37. The thickness of the wiring silicide 80 may be greater than 0 nm and 150 nm or less.

[0514] The wiring silicide 80 may have a value greater than 0 μm and belonging to at least one of the following ranges: 10 nm or less, 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0515] The wiring silicide 80 is formed at a distance from the thickness position in the middle of the gate wiring 22 towards the wiring surface side of the gate wiring 22, and extends in a strip shape following the direction of extension of the wiring via bottom wall 52 (wiring via recess 53). The wiring silicide 80 forms ohmic contact with the gate wiring 22.

[0516] The wiring via electrode 60 includes a wiring via base electrode 61 and a wiring via main electrode 62. The wiring via base electrode 61 has a first wiring coating portion 61a, a second wiring coating portion 61b, a third wiring coating portion 61c, and a fourth wiring coating portion 61d.

[0517] In this configuration, the film thickness at the upper end of the first wiring insulation portion 61a is greater than the thickness of the wiring silicide 80. The film thickness at the upper end of the first wiring insulation portion 61a may be less than the thickness of the wiring silicide 80. In this configuration, the film thickness at the lower end of the first wiring insulation portion 61a is less than the thickness of the wiring silicide 80. The film thickness at the lower end of the first wiring insulation portion 61a may be greater than the thickness of the wiring silicide 80.

[0518] In this configuration, the film thickness at the upper end of the second wiring insulation portion 61b is greater than the thickness of the wiring silicide 80. The film thickness at the upper end of the second wiring insulation portion 61b may be less than the thickness of the wiring silicide 80. In this configuration, the film thickness at the lower end of the second wiring insulation portion 61b is less than the thickness of the wiring silicide 80. The film thickness at the lower end of the second wiring insulation portion 61b may be greater than the thickness of the wiring silicide 80.

[0519] In this configuration, the third wiring covering portion 61c coats the wiring silicide 80 in a film-like manner at the wiring via bottom wall 52. In other words, the third wiring covering portion 61c is mechanically and electrically connected to the wiring silicide 80 at the wiring via bottom wall 52, and coats the gate wiring 22 in a film-like manner via the wiring silicide 80.

[0520] The third wiring insulation portion 61c covers the wiring via bottom wall 52 (wiring silicide 80) with an uneven film thickness. Specifically, the third wiring insulation portion 61c bulges inward from the wiring via side wall 51 towards the wiring via bottom wall 52.

[0521] In this configuration, the film thickness of the third wiring insulation portion 61c is greater than the thickness of the wiring silicide 80. The film thickness of the third wiring insulation portion 61c may be less than the thickness of the wiring silicide 80. In this configuration, the film thickness of the fourth wiring insulation portion 61d is greater than the thickness of the wiring silicide 80. The film thickness of the fourth wiring insulation portion 61d may be less than the thickness of the wiring silicide 80.

[0522] As described above, the semiconductor device 1A (semiconductor device 1B) may include a gate wiring 22 (to be connected) containing polysilicon, an insulating interlayer film 23, wiring via holes 50, wiring silicide 80 as polyside, and wiring via electrodes 60. The interlayer film 23 may cover the gate wiring 22.

[0523] The wiring via hole 50 may have a wiring via bottom wall 52 formed in the interlayer film 23 and partitioned by gate wiring 22. The wiring silicide 80 may be formed within the wiring via hole 50 following the shape of the wiring via bottom wall 52. The wiring via electrode 60 may be connected to the wiring silicide 80 within the wiring via hole 50.

[0524] This configuration provides a semiconductor device 1A that contributes to improved electrical characteristics. For example, with this semiconductor device 1A, the alignment margin of the wiring silicide 80 with respect to the wiring via electrode 60 is reduced, and at the same time, the wiring via electrode 60 is properly connected to the wiring silicide 80. As a result, miniaturization and performance improvement of the semiconductor device 1A (semiconductor device 1B) are achieved through the wiring via electrode 60.

[0525] The wiring via hole 50 may have a first wiring hole portion 54 and a second wiring hole portion 55. The first wiring hole portion 54 may be partitioned by a third width W3 on the insulating surface side of the interlayer film 23. The second wiring hole portion 55 may be partitioned by a fourth width W4 less than the third width W3 on the gate wiring 22 side relative to the first wiring hole portion 54. The wiring via bottom wall 52 may be partitioned by the gate wiring 22.

[0526] In this case, the wiring silicide 80 may be formed in the second wiring hole 55. With this configuration, the location where the wiring silicide 80 is formed is limited to within the second wiring hole 55, so the area occupied by the wiring silicide 80 relative to the gate wiring 22 (formation area) is appropriately reduced. Therefore, the miniaturization of the gate wiring 22 and the wiring via structure is appropriately achieved.

[0527] The wiring via hole 50 may have a wiring step portion 56 partitioned between the first wiring hole portion 54 and the second wiring hole portion 55. With this configuration, when the seed metal film 71 of the wiring silicide 80 is formed following the wall surface of the wiring via hole 50, the first wiring hole portion 54, the second wiring hole portion 55, the wiring via bottom wall 52, and the wiring step portion 56 improve the film formation of the seed metal film 71 on the wiring via hole 50. As a result, the conformability of the wiring silicide 80 with respect to the wiring via bottom wall 52 is appropriately improved, and contact resistance is suppressed.

[0528] The wiring via electrode 60 may include a wiring via base electrode 61 and a wiring via main electrode 62. The wiring via base electrode 61 may have a film-like first wiring coating portion 61a for the first wiring hole portion 54, a film-like second wiring coating portion 61b for the second wiring hole portion 55, a film-like third wiring coating portion 61c for the wiring silicide 80, and a film-like fourth wiring coating portion 61d for the wiring step portion 56.

[0529] The main electrode 62 of the wiring via may be embedded in the wiring via hole 50 via the wiring via base electrode 61 and electrically connected to the gate wiring 22 via the wiring via base electrode 61 and the wiring silicide 80. With this configuration, the film formation properties of the wiring via base electrode 61 on the wiring via hole 50 are improved by the first wiring hole portion 54, the second wiring hole portion 55, the wiring via bottom wall 52 and the wiring step portion 56.

[0530] As a result, the wiring via base electrode 61 is properly connected to the wiring via bottom wall 52, and the wiring via main electrode 62 is properly electrically connected to the gate wiring 22 via the wiring via base electrode 61. Consequently, contact resistance is suppressed.

[0531] Each of the above-described embodiments (including variations) can be implemented in other forms. For example, the features (including variations) of semiconductor device 1A and semiconductor device 1B can be combined with each other as appropriate. Semiconductor device 1A and semiconductor device 1B may simultaneously include at least two of the features (including variations) of semiconductor device 1A and semiconductor device 1B.

[0532] The semiconductor device 1A (semiconductor device 1B) may simultaneously include a trench-type transistor structure T (gate structure 16) and a planar-type transistor structure T (gate structure 76) in the active region 8.

[0533] In the first embodiment described above, the semiconductor device 1A does not necessarily need to include the diode region 12. In this case, the multiple body regions 10 may each extend in a strip-like manner in the first direction X and be formed with gaps in the second direction Y. In other words, the multiple body regions 10 may extend in a stripe-like manner in the first direction X.

[0534] In this case, the multiple source regions 13 may extend in a strip-like manner in the first direction X on the surface of the corresponding body region 10. The multiple contact regions 14 may extend in a strip-like manner in the first direction X on the surface of the corresponding body region 10.

[0535] In the second embodiment described above, the semiconductor device 1B does not necessarily need to include the diode region 12. In this case, the multiple body regions 10 may each extend in a strip-like manner in the first direction X in the region between the multiple gate structures 76.

[0536] In this case, the multiple source regions 13 may be spaced apart in the first direction X on the surface of the corresponding body region 10 and each may extend in a strip shape in the first direction X. The multiple contact regions 14 may be spaced apart in the first direction X on the surface of the corresponding body region 10.

[0537] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the n-type semiconductor region is inverted to p-type, and the conductivity type of the p-type semiconductor region is inverted to n-type. The specific configuration in this case can be obtained by replacing n-type with p-type and simultaneously replacing p-type with n-type in the above description and attached drawings.

[0538] In each of the above-described embodiments, a p-type first semiconductor layer 6 may be used. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure.

[0539] In the embodiments described above, examples were shown in which wiring via holes 50 and wiring via electrodes 60 were applied to the gate wiring 22. However, wiring via holes 50 and wiring via electrodes 60 are applicable to various types of electrical wiring.

[0540] For example, the wiring via holes 50 and wiring via electrodes 60 can be applied to electrical wiring to which any potential (voltage) is applied, which is incorporated into an integrated circuit such as an LSI. The electrical wiring may be polysilicon wiring. In this case, the modified wiring silicide 80 (see Figure 26) may be installed alongside the wiring via holes 50 and wiring via electrodes 60 in various types of electrical wiring (polysilicon wiring).

[0541] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components of the aforementioned forms, but this is not intended to limit the scope of each item (Clause) to the aforementioned forms. The term "semiconductor device" in the following items may be replaced with "wide-bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "semiconductor integrated circuit device," etc.

[0542] [A1] A semiconductor device (1A, 1B) comprising: a silicon-containing connection target (2, 22); an insulating interlayer film (23) covering the connection target (2, 22); via holes (30, 50) formed in the interlayer film (23) and having via bottom walls (32, 52) partitioned by the connection target (2, 22); silicides (37, 80) formed within the via holes (30, 50) in accordance with the via bottom walls (32, 52); and via electrodes (40, 60) electrically connected to the connection target (2, 22) within the via holes (30, 50) via the silicides (37, 80).

[0543] [A2] The connection targets (2, 22) are semiconductor devices (1A, 1B) as described in A1, which include silicon carbide.

[0544] [A3] The semiconductor device (1A, 1B) according to A1 or A2, wherein the via bottom walls (32, 52) are defined by via recesses (33, 53) recessed in the thickness direction (Z) at the connection target (2, 22), and the silicide (37, 80) is formed following the via recesses (33, 53).

[0545] [A4] The semiconductor device (1A, 1B) according to any one of A1 to A3, wherein the silicide (37, 80) includes a metal silicide other than titanium silicide, and the via electrodes (40, 60) include a titanium-based metal.

[0546] [A5] The semiconductor device (1A, 1B) according to any one of A1 to A4, wherein the via electrodes (40, 60) include film-like via under electrodes (41, 61) for the silicide (37, 80), and via main electrodes (42, 62) electrically connected to the silicide (37, 80) via the via under electrodes (41, 61) within the via holes (30, 50).

[0547] [A6] The semiconductor device (1A, 1B) according to A5, wherein the silicide (37, 80) includes a metal silicide other than titanium silicide, the via under electrode (41, 61) includes a titanium-based metal, and the via main electrode (42, 62) includes a tungsten-based metal.

[0548] [A7] The via holes (30, 50) include first holes (34, 54) demarcated by a first width (W1, W3) on the insulating surface side of the interlayer film (23), second holes (35, 55) demarcated by a second width (W2, W4) less than the first width (W1, W3) on the connection target (2, 22) side, and stepped portions (36, 56) demarcated between the first holes (34, 54) and the second holes (35, 55), and the silicide (37, 80) is formed within the second holes (35, 55), wherein the semiconductor device (1A, 1B) is described in any one of A1 to A6.

[0549] [A8] The semiconductor device (1A, 1B) according to A7, wherein the silicide (37, 80) has a width less than the first width (W1, W3).

[0550] [A9] The semiconductor device (1A, 1B) according to A7 or A8, wherein the first holes (34, 54) have a first depth (D1, D3) with respect to the insulating surface of the interlayer film (23), and the second holes (35, 55) have a second depth (D2, D4) less than the first depth (D1, D3) with respect to the stepped portions (36, 56).

[0551] [A10] The silicide (37, 80) is formed with a gap between the stepped portion (36, 56) and the connection target (2, 22), as described in any one of A7 to A9, semiconductor device (1A, 1B).

[0552] [A11] The semiconductor device (1A, 1B) according to any one of A7 to A10, wherein the interlayer film (23) has a laminated structure including a first interlayer film (24) and a second interlayer film (25), the first holes (34, 54) are partitioned on the second interlayer film (25) side, and the second holes (35, 55) are partitioned on the first interlayer film (24) side.

[0553] [A12] A via hole (30, 50) having a stepped portion (36, 56) partitioned between the first hole (34, 54) and the second hole (35, 55) on the insulating surface side of the interlayer film (23) with a first width (W1, W3), a second hole (35, 55) on the connection target (2, 22) side relative to the first hole (34, 54) with a second width (W2, W4) less than the first width (W1, W3), a via bottom wall (32, 52) partitioned by the connection target (2, 22), and the first hole (34, 54) and the second hole (35, 55), and the A semiconductor device (1A, 1B) includes via base electrodes (41, 61) having a film-like first coating portion (41a, 61a) over a first hole portion (34, 54), a film-like second coating portion (41b, 61b) over a second hole portion (35, 55), a film-like third coating portion (41c, 61c) over the via bottom wall (32, 52), and a film-like fourth coating portion (41d, 61d) over the stepped portion (36, 56); and via main electrodes (42, 62) embedded in the via holes (30, 50) via the via base electrodes (41, 61) and electrically connected to the connection target (2, 22) via the via base electrodes (41, 61).

[0554] [A13] The semiconductor device (1A, 1B) according to A12, wherein the first coating portion (41a, 61a) has a film thickness that gradually decreases toward the second hole portion (35, 55).

[0555] [A14] The semiconductor device (1A, 1B) according to A12 or A13, wherein the second covering portion (41b, 61b) has a portion that is thicker than the first covering portion (41a, 61a).

[0556] [A15] The semiconductor device (1A, 1B) according to any one of A12 to A14, wherein the second coating portion (41b, 61b) has a film thickness that gradually decreases toward the via bottom wall (32, 52) side.

[0557] [A16] The semiconductor device (1A, 1B) according to any one of A12 to A15, wherein the third covering portion (41c, 61c) has a portion that is thicker than the first covering portion (41a, 61a).

[0558] [A17] The semiconductor device (1A, 1B) according to any one of A12 to A16, wherein the third covering portion (41c, 61c) has a portion that is thicker than the second covering portion (41b, 61b).

[0559] [A18] The semiconductor device (1A, 1B) according to any one of A12 to A17, wherein the fourth covering portion (41d, 61d) has a portion that is thicker than the first covering portion (41a, 61a).

[0560] [A19] The semiconductor device (1A, 1B) according to any one of A12 to A18, wherein the fourth covering portion (41d, 61d) has a portion that is thicker than the second covering portion (41b, 61b).

[0561] [A20] A semiconductor device (1A, 1B) according to any one of A12 to A19, further comprising: a connection target (2, 22) containing silicon; and a silicide (37, 80) formed in the via hole (30, 50) following the via bottom wall (32, 52); wherein the via base electrode (41, 61) has a film-like third coating portion (41c, 61c) over the silicide (37, 80); and the via main electrode (42, 62) is electrically connected to the connection target (2, 22) via the via base electrode (41, 61) and the silicide (37, 80).

[0562] [B1] A semiconductor device (1A, 1B) comprising a silicon-containing chip (2), gate structures (16, 76) formed on the chip (2), an insulating interlayer film (23) covering the gate structures (16, 76) on the chip (2), a via hole (30) formed in the interlayer film (23) on the side of the gate structures (16, 76) and having a via bottom wall (32) partitioned by the chip (2), a silicide (37) formed within the via hole (30) following the via bottom wall (32), and a via electrode (40) connected to the silicide (37) within the via hole (30).

[0563] [B2] The chip (2) is a semiconductor device (1A, 1B) according to B1, which contains silicon carbide.

[0564] [B3] The semiconductor device (1A, 1B) according to B1 or B2, wherein the gate structure (16, 76) is of the planar type.

[0565] [B4] The semiconductor device (1A, 1B) according to B1 or B2, wherein the gate structure (16, 76) is of the trench type.

[0566] [B5] A semiconductor device (1A, 1B) according to any one of B1 to B4, further comprising impurity regions (10 to 14) formed on the surface layer of the chip (2), wherein the via holes (30) are formed in the interlayer film (23) in a region above the impurity regions (10 to 14), the silicide (37) is electrically connected to the impurity regions (10 to 14), and the via electrode (40) is electrically connected to the impurity regions (10 to 14) via the silicide (37).

[0567] [B6] The semiconductor device (1A, 1B) according to B5, wherein the impurity region (10-14) has an n-type conductivity.

[0568] [B7] The semiconductor device (1A, 1B) according to B5, wherein the impurity region (10-14) has a p-type conductivity.

[0569] [B8] The semiconductor device (1A, 1B) according to B5, further comprising a plurality of impurity regions (10-14) formed on the surface of the chip (2), namely n-type first impurity regions (11-13) and p-type second impurity regions (10, 14), wherein the via electrode (40) is electrically connected to both the first impurity regions (11-13) and the second impurity regions (10, 14) via the silicide (37).

[0570] [B9] A semiconductor device (1A, 1B) comprising: a silicon-containing chip (2); a planar electrode (18) disposed on the chip (2); an insulating interlayer film (23) covering the planar electrode (18) on the chip (2); a via hole (30) formed in the interlayer film (23) on the side of the planar electrode (18) and having a via bottom wall (32) partitioned by the chip (2); a silicide (37) formed within the via hole (30) following the via bottom wall (32); and a via electrode (40) connected to the silicide (37) within the via hole (30).

[0571] [B10] The via hole (30) includes a first hole portion (34) demarcated by a first width (W1) on the insulating surface side of the interlayer film (23), and a second hole portion (35) demarcated by a second width (W2) less than the first width (W1) on the chip (2) side, and the silicide (37) is formed within the second hole portion (35), as described in B9 (1A, 1B).

[0572] [B11] The semiconductor device (1A, 1B) according to B10, wherein the first hole (34) has a first depth (D1) and the second hole (35) has a second depth (D2) less than the first depth (D1).

[0573] [B12] The semiconductor device (1A, 1B) according to B10 or B11, wherein the first hole (34) is formed on the insulating surface side of the interlayer film (23) with respect to the height position of the electrode surface of the planar electrode (18), and the second hole (35) is formed on the chip (2) side with respect to the height position of the electrode surface of the planar electrode (18).

[0574] [B13] The semiconductor device (1A, 1B) according to B9, wherein the interlayer film (23) has a laminated structure including a first interlayer film (24) that covers the planar electrode (18) and a second interlayer film (25) that covers the planar electrode (18) via the first interlayer film (24).

[0575] [B14] The semiconductor device (1A, 1B) according to B13, wherein the first interlayer film (24) is thinner than the planar electrode (18) and the second interlayer film (25) is thicker than the first interlayer film (24).

[0576] [B15] The semiconductor device (1A, 1B) described in B14, wherein the second interlayer film (25) is thicker than the planar electrode (18).

[0577] [B16] The via hole (30) includes a first hole portion (34) partitioned by a first width (W1) on the second interlayer film (25) side, and a second hole portion (35) partitioned by a second width (W2) less than the first width (W1) on the first interlayer film (24) side, and the silicide (37) is formed within the second hole portion (35), wherein the semiconductor device (1A, 1B) is as described in any one of B13 to B15.

[0578] [B17] A semiconductor device (1A, 1B) according to any one of B13 to B16, wherein the planar electrode (18) contains polysilicon, the first interlayer film (24) contains phosphorus-free silicon oxide, and the second interlayer film (25) contains phosphorus-containing silicon oxide.

[0579] [B18] A semiconductor device (1A, 1B) comprising: a connection target (22) containing polysilicon; an insulating interlayer film (23) covering the connection target (22); a via hole (50) formed in the interlayer film (23) and having a via bottom wall (52) partitioned by the connection target (22); a polyside (80) formed within the via hole (50) following the via bottom wall (52); and a via electrode (60) connected to the polyside (80) within the via hole (50).

[0580] [B19] The via hole (50) includes a first hole portion (54) partitioned by a first width (W3) on the insulating surface side of the interlayer film (23), a second hole portion (55) partitioned by a second width (W4) less than the first width (W3) on the connection target (22) side, and a stepped portion (56) partitioned between the first hole portion (54) and the second hole portion (55), and the polyside (80) is formed in the second hole portion (55), as described in B18 (1A, 1B).

[0581] [B20] The semiconductor device (1A, 1B) according to B19, wherein the via electrode (60) includes a base electrode (61) having a film-like first coating portion (61a) over the first hole (54), a film-like second coating portion (61b) over the second hole (55), and a film-like third coating portion (61c) over the polyside (80), and a via main electrode (62) embedded in the via hole (50) via the base electrode (61) and electrically connected to the connection target (22) via the base electrode (61) and the polyside (80).

[0582] Although specific forms have been described in detail above, these are merely examples to illustrate the technical content. The various technical ideas extracted from this specification can be combined as appropriate, without being limited by the order of explanation, the order of the examples of forms, the order of the modifications, etc.

[0583] 1A Semiconductor device 1B Semiconductor device 2 Chip (to be connected) 10 Body region (impurity region) 11 Surface drift region (impurity region) 12 Diode region (impurity region) 13 Source region (impurity region) 14 Contact region (impurity region) 16 Gate structure 18 Gate electrode (planar electrode) 22 Gate wiring (to be connected) 23 Interlayer film 24 First interlayer film 25 Second interlayer film 30 Via hole 32 Via bottom wall 33 Via recess 34 First hole portion 35 Second hole portion 36 Step portion 37 Silicide 40 Via electrode 41 Via under electrode 41a First coating portion 41b Second coating portion 41c Third coating portion 41d Fourth coating portion 42 Via main electrode 50 Wiring via hole (via hole) 52 Wiring via bottom wall (via bottom wall) 53 54 Wiring via recess (via recess) 55 First wiring hole (first hole) 56 Second wiring hole (second hole) 60 Wiring step (step) 61 Wiring via electrode (via electrode) 61 Wiring via base electrode (via base electrode) 61a First wiring coating (first coating) 61b Second wiring coating (second coating) 61c Third wiring coating (third coating) 61d Fourth wiring coating (fourth coating) 62 Wiring via main electrode (via main electrode) 76 Gate structure 80 Wiring silicide (polycide) D1 First depth D2 Second depth D3 Third depth (first depth) D4 Fourth depth (second depth) W1 First width W2 Second width W3 Third width (first width) W4 Fourth width (second width) Z Thickness direction

Claims

1. A semiconductor device comprising: a connection target containing silicon; an insulating interlayer film covering the connection target; a via hole formed in the interlayer film and having a via bottom wall partitioned by the connection target; a silicide formed within the via hole following the via bottom wall; and a via electrode electrically connected to the connection target via the silicide within the via hole.

2. The semiconductor device according to claim 1, wherein the connection target includes silicon carbide.

3. The semiconductor device according to claim 1 or 2, wherein the via bottom wall is defined by via recesses that are recessed in the thickness direction at the connection target, and the silicide is formed following the via recesses.

4. The semiconductor device according to any one of claims 1 to 3, wherein the silicide includes a metal silicide other than titanium silicide, and the via electrode includes a titanium-based metal.

5. The semiconductor device according to any one of claims 1 to 4, wherein the via electrode includes a film-like via under electrode relative to the silicide, and a via main electrode electrically connected to the silicide via the via under electrode within the via pore.

6. The semiconductor device according to claim 5, wherein the silicide includes a metal silicide other than titanium silicide, the via under electrode includes a titanium-based metal, and the via main electrode includes a tungsten-based metal.

7. The semiconductor device according to any one of claims 1 to 6, wherein the via hole includes a first hole portion partitioned by a first width on the insulating surface side of the interlayer film, a second hole portion partitioned by a second width less than the first width on the connection target side, and a stepped portion partitioned between the first hole portion and the second hole portion, and the silicide is formed in the second hole portion.

8. The semiconductor device according to claim 7, wherein the silicide has a width less than the first width.

9. The semiconductor device according to claim 7 or 8, wherein the first hole has a first depth with respect to the insulating surface of the interlayer film, and the second hole has a second depth less than the first depth with respect to the stepped portion.

10. The semiconductor device according to any one of claims 7 to 9, wherein the silicide is formed with a gap between the stepped portion and the connection target side.

11. The semiconductor device according to any one of claims 7 to 10, wherein the interlayer film has a laminated structure including a first interlayer film and a second interlayer film, the first pore portion is partitioned on the second interlayer film side, and the second pore portion is partitioned on the first interlayer film side.

12. A semiconductor device comprising: a connection target; an insulating interlayer film covering the connection target; a via hole having a first hole portion partitioned by a first width on the insulating surface side of the interlayer film, a second hole portion partitioned by a second width less than the first width on the connection target side relative to the first hole portion, a via bottom wall partitioned by the connection target portion, and a stepped portion partitioned between the first hole portion and the second hole portion; a via base electrode having a film-like first covering portion over the first hole portion, a film-like second covering portion over the second hole portion, a film-like third covering portion over the via bottom wall, and a film-like fourth covering portion over the stepped portion; and a via main electrode embedded in the via hole via the via base electrode and electrically connected to the connection target via the via base electrode.

13. The semiconductor device according to claim 12, wherein the first coating portion has a film thickness that gradually decreases toward the second hole portion.

14. The semiconductor device according to claim 12 or 13, wherein the second coating portion has a portion that is thicker than the first coating portion.

15. The semiconductor device according to any one of claims 12 to 14, wherein the second coating portion has a film thickness that gradually decreases toward the via bottom wall side.

16. The semiconductor device according to any one of claims 12 to 15, wherein the third coating portion has a portion that is thicker than the first coating portion.

17. The semiconductor device according to any one of claims 12 to 16, wherein the third coating portion has a portion that is thicker than the second coating portion.

18. The semiconductor device according to any one of claims 12 to 17, wherein the fourth coating portion has a portion that is thicker than the first coating portion.

19. The semiconductor device according to any one of claims 12 to 18, wherein the fourth coating portion has a portion that is thicker than the second coating portion.

20. The semiconductor device according to any one of claims 12 to 19, further comprising: a connection target containing silicon; and a silicide formed in the via hole following the via bottom wall, wherein the via under electrode has the film-like third coating portion over the silicide; and the via main electrode is electrically connected to the connection target via the via under electrode and the silicide.

Images