Photodetection device and electronic equipment

Abstract

A photodetection device according to one embodiment of the present invention comprises a substrate, an insulating layer which is layered on the substrate, a photoelectric conversion unit which is provided on the substrate and generates electric charges by photoelectric conversion, and a shield wiring which is provided on the insulating layer and extends in the thickness direction of the insulating layer. The shield wiring includes a shield film which extends in the thickness direction.

Description

Optical Detection Device and Electronic Device

[0001] The present disclosure relates to an optical detection device and an electronic device.

[0002] In an optical detection device such as an imaging device (e.g., a CMOS (complementary metal oxide semiconductor) image sensor), for example, a shield may be required between a wiring connected to a photodiode and a driving line such as a control line. Therefore, a method has been proposed in which by arranging a wiring serving as a shield layer around the wiring connected to the photodiode, deterioration of characteristics such as crosstalk due to coupling is suppressed (see, for example, Patent Document 1).

[0003] Japanese Unexamined Patent Application Publication No. 2023-84462

[0004] However, in the above method, for example, when the wiring capacitance is increased, the number of layers of the wiring serving as the shield layer increases, and the planar area of the wiring serving as the shield layer increases, making it difficult to miniaturize the pixel, that is, the device.

[0005] Therefore, the present disclosure provides an optical detection device and an electronic device capable of realizing miniaturization of the device.

[0006] The optical detection device according to the embodiment includes a substrate, an insulating layer laminated on the substrate, a photoelectric conversion unit provided on the substrate that generates charges by photoelectric conversion, and a shield wiring provided in the insulating layer that extends in the thickness direction of the insulating layer. The shield wiring includes a shield film that extends in the thickness direction.

[0007] The electronic device according to the embodiment includes an optical detection device. The optical detection device includes a substrate, an insulating layer laminated on the substrate, a photoelectric conversion unit provided on the substrate that generates charges by photoelectric conversion, and a shield wiring provided in the insulating layer that extends in the thickness direction of the insulating layer. The shield wiring includes a shield film that extends in the thickness direction.

[0008] This figure shows an example configuration of a light detection device according to the first embodiment. This figure shows an example configuration of a pixel circuit for a pixel according to the first embodiment. This is a cross-sectional view showing an example configuration of a pixel according to the first embodiment. This figure shows the plane of a pixel at the position of line A1-A1 in Figure 3. This figure shows the plane of a pixel at the position of line A2-A2 in Figure 3. This figure shows the plane of a pixel at the position of line A3-A3 in Figure 3. This figure shows the plane of a pixel at the position of line A4-A4 in Figure 3. This figure shows the plane of the first layer of a pixel according to the first embodiment. This figure shows the plane of the second layer of a pixel according to the first embodiment. This figure shows the plane of the third layer of a pixel according to the first embodiment. This figure shows the plane of the fourth layer of a pixel according to the first embodiment. This figure shows the plane of the fifth layer of a pixel according to the first embodiment. This figure shows an example of the manufacturing process of a shielded wiring according to the first embodiment. This figure shows an example of the manufacturing process of a shielded wiring according to the first embodiment. This is a cross-sectional view showing an example configuration of a pixel according to a first modified example of the first embodiment. This is a cross-sectional view showing an example configuration of a pixel according to a second modified example of the first embodiment. This is a cross-sectional view showing an example configuration of a pixel according to a third modified example of the first embodiment. This is a cross-sectional view showing an example configuration of a pixel according to a fourth modified example of the first embodiment. This figure shows an example configuration of a pixel circuit for a pixel according to the second embodiment. This figure shows another example of the pixel circuit configuration of a pixel according to the second embodiment. This is a cross-sectional view showing an example of the pixel configuration according to the second embodiment. This figure shows the plane of the first layer of the pixel according to the second embodiment. This figure shows the plane of the second layer of the pixel according to the second embodiment. This figure shows the plane of the third layer of the pixel according to the second embodiment. This figure shows the plane of the fourth layer of the pixel according to the second embodiment. This figure shows the plane of the fifth layer of the pixel according to the second embodiment. This figure shows the plane of the sixth layer of the pixel according to the second embodiment. This is a cross-sectional view showing an example of the pixel configuration according to the first modified example of the second embodiment. This is a cross-sectional view showing an example of the pixel configuration according to the second modified example of the second embodiment. This figure shows an example of the configuration of a light detection device according to an application example. This figure shows an example of the configuration of a sensor pixel and readout circuit according to an application example. This figure shows various application examples of the light detection device. This figure shows an example of the configuration of an imaging device according to an application example. This figure shows an example of the configuration of a distance measuring device according to an application example.

[0009] Embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments include examples and modifications. However, the technology relating to this disclosure is not limited by the embodiments. In addition, in the following embodiments, the same reference numerals are used for essentially the same parts to omit redundant explanations.

[0010] This disclosure will be described in the following order of items: 1. First Embodiment 1-1. Example of the configuration of a light detection device 1-2. Example of the configuration of a pixel circuit 1-3. Example of the configuration of a pixel 1-4. Example of a stacked structure of a pixel 1-5. Example of the manufacturing process of shielded wiring 1-6. Modifications 1-6-1. First modification 1-6-2. Second modification 1-6-3. Third modification 1-6-4. Fourth modification 2. Second Embodiment 2-1. Example of the configuration of a pixel circuit 2-2. Example of the configuration of a pixel 2-3. Example of a stacked structure of a pixel 2-4. Modifications 2-4-1. First modification 2-4-2. Second modification 3. Overview of each embodiment 4. Other embodiments 5. Application examples 5-1. Light detection device 5-2. Various devices 5-3. Imaging device 5-4. Distancing device 6. Notes

[0011] <1. First Embodiment> <1-1. Example of Light Detection Device Configuration> The light detection device 101 according to the first embodiment will be described with reference to Figure 1. Figure 1 is a diagram showing an example of the configuration of the light detection device 101 according to the first embodiment. The light detection device 101 is an example of an image sensor (solid-state imaging device).

[0012] As shown in Figure 1, the light detection device 101 according to the first embodiment is configured to have a pixel section (so-called imaging area) 103 and a peripheral circuit section. The pixel section 103 is configured in which a plurality of pixels 102, each containing a photoelectric conversion element, are arranged in a matrix on a semiconductor substrate 111, such as a silicon substrate. The pixels 102 include, for example, a photodiode (PD), which is an example of a photoelectric conversion element, and a plurality of pixel transistors (so-called MOS transistors).

[0013] The peripheral circuit section comprises a vertical drive circuit 104, a column signal processing circuit 105, a horizontal drive circuit 106, an output circuit 107, and a control circuit 108.

[0014] The vertical drive circuit 104 is composed of, for example, a shift register, which selects a pixel drive line and supplies pulses to the selected pixel drive line to drive the pixels 102, driving the pixels 102 row by row. That is, the vertical drive circuit 104 sequentially selects and scans each pixel 102 of the pixel section 103 vertically row by row, and supplies a pixel signal based on the signal charge generated in the PD of each pixel 102 according to the amount of light received, through the vertical signal line 109 to the column signal processing circuit 105.

[0015] The column signal processing circuit 105 is arranged, for example, for each pixel column, and performs signal processing such as noise reduction on the signal output from one row of pixels 102 for each pixel column. That is, the column signal processing circuit 105 performs signal processing such as CDS (correlated double sampling) to remove fixed pattern noise specific to the pixels 102, signal amplification, and AD (analog-to-digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 105, connected to the horizontal signal line 110.

[0016] The horizontal drive circuit 106 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 105 in order, causing each of the column signal processing circuits 105 to output a pixel signal to the horizontal signal line 110.

[0017] The output circuit 107 processes the signals supplied sequentially from each column signal processing circuit 105 through the horizontal signal line 110 and outputs them. Signal processing may include, for example, only buffering, or it may include black level adjustment, column variation correction, and various digital signal processing. The input / output terminal 112 exchanges signals with the outside world.

[0018] The control circuit 108 receives an input clock and data that commands the operating mode, and outputs data such as internal information of the light detection device 101. In other words, the control circuit 108 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 104, column signal processing circuit 105, and horizontal drive circuit 106, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 108 then inputs these signals to the vertical drive circuit 104, column signal processing circuit 105, and horizontal drive circuit 106, etc.

[0019] <1-2. Example of Pixel Circuit Configuration> An example of the pixel circuit configuration of pixel 102 according to the first embodiment will be described with reference to Figure 2. Figure 2 is a diagram showing an example of the pixel circuit configuration of pixel 102 according to the first embodiment. Note that the pixel circuit shown in Figure 2 is merely one example of a pixel circuit. For example, various known circuit configurations may be used as the pixel circuit.

[0020] As shown in Figure 2, the pixel 102 includes a photoelectric conversion unit (PD) 11, a transfer transistor (TRG) 12, a first charge storage unit (FD1) 13, a reset transistor (RST) 14, an amplification transistor (AMP) 15, a selection transistor (SEL) 16, a second charge storage unit (FD2) 17, and a switching transistor (FDG) 18. The first charge storage unit 13 includes a capacitor (C1) 13a. The second charge storage unit 17 includes a capacitor (C2) 17a and a capacitor (C3) 17b. Each of the capacitors 13a, 17a, and 17b functions as an additional charge storage unit (Sub-FD). Capacitor 17a is an example of wiring capacitance, and capacitor 17b is an example of shielding capacitance.

[0021] For example, a PN junction photodiode is used as the photoelectric conversion unit 11. A CMOS (Complementary Metal Oxide Semiconductor) transistor is used as the transfer transistor 12. The transfer transistor 12 is an example of a charge transmission unit. For example, floating diffusion is used as the first charge storage unit 13 and the second charge storage unit 17. Similar to the transfer transistor 12, CMOS transistors are used as the reset transistor 14, amplification transistor 15, selection transistor 16, and switching transistor 18.

[0022] The photoelectric conversion unit 11 performs photoelectric conversion on incident light and generates an electric charge corresponding to the amount of light received. The cathode of the photoelectric conversion unit 11 is electrically connected to the source of the transfer transistor 12, and the anode of the photoelectric conversion unit 11 is electrically connected to a reference potential line (for example, ground). The drain of the transfer transistor 12 is electrically connected to the first charge storage unit 13, and the gate of the transfer transistor 12 is electrically connected to the pixel drive line. When the transfer transistor 12 is turned on, it transfers the charge generated by the photoelectric conversion unit 11 to the first charge storage unit 13. The first charge storage unit 13 temporarily stores the charge output from the photoelectric conversion unit 11 via the transfer transistor 12. This first charge storage unit 13 can, for example, convert the stored charge into an electrical signal (for example, a voltage signal) and output it.

[0023] The source of the reset transistor 14 is electrically connected to the second charge storage unit 17 and the drain of the switching transistor 18, and the drain of the reset transistor 14 is electrically connected to the power line VDD and the drain of the amplification transistor 15. The gate of the reset transistor 14 is electrically connected to the pixel drive line. The source of the amplification transistor 15 is electrically connected to the drain of the selection transistor 16, and the gate of the amplification transistor 15 is electrically connected to the source of the switching transistor 18 and the first charge storage unit 13. The source of the selection transistor 16 is electrically connected to the vertical signal line 109, and the gate of the selection transistor 16 is electrically connected to the pixel drive line. The source of the switching transistor 18 is electrically connected to the first charge storage unit 13, and the drain of the switching transistor 18 is electrically connected to the second charge storage unit 17. The gate of the switching transistor 18 is electrically connected to the pixel drive line.

[0024] The reset transistor 14 resets the potentials of the first charge storage unit 13 and the second charge storage unit 17 to a predetermined potential. When the reset transistor 14 is turned on, it resets the potentials of the first charge storage unit 13 and the second charge storage unit 17 to the potential of the power line VDD. The selection transistor 16 controls the output timing of the voltage signal (pixel signal). The amplification transistor 15 generates a voltage signal (pixel signal) corresponding to the amount of charge stored in, for example, the first charge storage unit 13 (capacitor 13a) and the second charge storage unit 17 (capacitor 17a or capacitor 17b). When the selection transistor 16 is turned on, the amplification transistor 15 amplifies the potentials of the first charge storage unit 13 (capacitor 13a) and the second charge storage unit 17 (capacitor 17a or capacitor 17b) and outputs a voltage signal corresponding to that potential to the vertical signal line 109.

[0025] The switching transistor 18 is used to switch the conversion efficiency. Generally, when shooting in a dark place, the amount of charge generated by the photoelectric conversion unit 11 is small. In such cases, when converting the charge into a voltage signal based on Q=CV, if the capacitance 13a of the first charge storage unit 13 is large, the voltage V when converted to voltage will be small. On the other hand, when shooting in a bright place, the amount of charge generated by the photoelectric conversion unit 11 is large. In this case, because the amount of charge is large, if the capacitance 13a of the first charge storage unit 13 is not large, the first charge storage unit 13 will not be able to accept the charge generated by the photoelectric conversion unit 11. In this case, it is preferable to increase the capacitance 13a of the first charge storage unit 13 so that the converted voltage V does not become too large.

[0026] When the switching transistor 18 is turned ON, the capacitances 17a and 17b of the second charge storage unit 17 are added to the capacitance 13a of the first charge storage unit 13, thus increasing the capacity that can store charge (high capacity = low conversion efficiency). On the other hand, when the switching transistor 18 is turned OFF, the second charge storage unit 17 is disconnected from the first charge storage unit 13, thus decreasing the capacity that can store charge (low capacity = high conversion efficiency). In this way, by switching the switching transistor 18 ON or OFF according to the brightness during shooting, the capacity that can store charge can be varied, and the sensitivity of the voltage signal to the change in charge generated in the photoelectric conversion unit 11 (conversion efficiency) can be switched.

[0027] Furthermore, for each capacitance 13a, 17a, and 17b, in addition to wiring capacitance using parasitic capacitance between wirings, various other capacitances such as MIM capacitance (Metal-Insulator-Metal Capacitor), diffusion layer (capacitance of PN junction), and oxide film capacitance may be used.

[0028] <1-3. Example of Pixel Configuration> The pixel 102 according to the first embodiment will be described with reference to Figures 3 to 12. Figure 3 is a cross-sectional view showing an example of the configuration of the pixel 102 according to the first embodiment. The pixel 102 is, for example, an example of a back-illuminated type.

[0029] As shown in Figure 3, the pixel 102 according to the first embodiment comprises a substrate 20 and a wiring layer 30. The pixel 102 may also include other components such as a color filter or an on-chip lens.

[0030] The substrate 20 is a semiconductor substrate (semiconductor layer) on which various elements are arranged. This substrate 20 is made of, for example, silicon (Si). A photoelectric conversion unit (PD) 11, a first charge storage unit (FD1) 13, a second charge storage unit (FD2) 17, and a power line (VDD) 21 are provided on the surface side of the substrate 20 (the top surface in Figure 3). The photoelectric conversion unit 11 is arranged, for example, in a well region formed in the substrate 20. The first charge storage unit 13 and the second charge storage unit 17 are, for example, diffusion layers.

[0031] The wiring layer 30 is provided on the surface of the substrate 20. This wiring layer 30 is an area where various elements and wiring are arranged, for example. The wiring layer 30 is an example of a multilayer wiring layer. On the back side (bottom side in Figure 3) of the wiring layer 30, a transfer transistor (TRG) 12, a reset transistor (RST) 14, and a switching transistor (FDG) 18 are provided. The wiring layer 30 is also provided with an insulating layer (interlayer insulating layer) 31, multiple wirings 32, multiple control lines 33, a reference potential line 34, a first capacitance wiring 35, and shield wiring 36. The shield wiring 36 is an example of a plug.

[0032] Each wiring 32, each control line 33, the reference potential line 34, and the first capacitance wiring 35 are laminated with an insulating layer 31 in between. The insulating layer 31 is made of, for example, silicon oxide (SiOx) or silicon nitride (SiNx). The wiring 32 transmits signals to elements formed on the substrate 20. The control lines 33 include, for example, pixel drive lines. The reference potential line 34 and the first capacitance wiring 35 are formed, for example, on the surface side of the wiring layer 30 than the position of the control line 33. The reference potential line 34 is connected to, for example, ground. The first capacitance wiring 35 is provided opposite the reference potential line 34 at a predetermined distance apart, with the insulating layer 31 in between. This forms the capacitance 17a of the second charge storage unit 17. Each wiring 32, each control line 33, the reference potential line 34, and the first capacitance wiring 35 are made of, for example, aluminum (Al), copper (Cu), or tungsten (W).

[0033] The transfer transistor 12 and the wiring 32 are electrically connected, for example, via via V1. The reset transistor 14 and the wiring 32 are also electrically connected, for example, via via V1. The switching transistor 18 and the wiring 32 are also electrically connected, for example, via via V1. In addition, each of the wirings 32 and each of the control lines 33 are electrically connected, for example, via via V2. Vias V1 and V2 are examples of connections.

[0034] The second charge storage unit 17 and the first capacitance wiring 35 are electrically connected via shield wiring 36. The shield wiring 36 extends, for example, in the thickness direction (up and down direction in Figure 3) and penetrates the reference potential line 34, electrically connecting the second charge storage unit 17 and the first capacitance wiring 35. The thickness direction is the thickness direction (lamination direction) of the wiring layer 30 (for example, the insulating layer 31). The shield wiring 36 has the function of either or both of the following: electrical shielding (noise countermeasure) and optical shielding (light shielding countermeasure). This reduces the influence of electromagnetic waves and crosstalk generated between each element. For example, the shield wiring 36 suppresses the propagation of coupling between the control lines 33 of the reset transistor 14 and the switching transistor 18 to the second charge storage unit 17.

[0035] The shielded wiring 36 is composed of a shielding film 36a, an insulating film 36b, and a conductor 36c. The shielding film 36a is provided on the inner circumferential surface of the hole H1 formed in the insulating layer 31 and functions as a sidewall shield. This shielding film 36a is electrically connected to the reference potential line 34. The insulating film 36b is provided on the inner circumferential surface of the shielding film 36a within the hole H1. The conductor 36c is provided on the inner circumferential surface of the insulating film 36b within the hole H1 and is electrically connected to the second charge storage section 17 and the first capacitance wiring 35. The shielding film 36a and the conductor 36c are provided via the insulating film 36b. This forms the capacitance 17b of the second charge storage section 17.

[0036] The shielding film 36a is not in contact with the second charge storage unit 17 and the first capacitance wiring 35, but is in contact with the reference potential line 34. The insulating film 36b and the conductor 36c are in contact with the second charge storage unit 17 and the first capacitance wiring 35, but are not in contact with the reference potential line 34. The length of the shielding film 36a in the thickness direction is shorter than the length of one or both of the insulating film 36b and the conductor 36c in the thickness direction. For example, the shielding film 36a may not be provided over the entire surface of the shielding wiring 36, i.e., the entire outer surface of the insulating film 36b, but only on a part of the outer surface of the insulating film 36b.

[0037] The shielding film 36a and the conductor 36c are made of, for example, aluminum (Al), copper (Cu), or tungsten (W). The insulating film 36b is made of, for example, silicon oxide (SiOx) or silicon nitride (SiNx). The insulating film 36b may also be made of a high dielectric material, for example, to increase parasitic capacitance.

[0038] Figure 4 shows the plane of pixel 102 at the position of line A1-A1 in Figure 3. Figure 5 shows the plane of pixel 102 at the position of line A2-A2 in Figure 3. Figure 6 shows the plane of pixel 102 at the position of line A3-A3 in Figure 3. Figure 7 shows the plane of pixel 102 at the position of line A4-A4 in Figure 3.

[0039] As shown in Figures 4 to 6, the shield wiring 36 is formed in a circular shape in plan view. Specifically, the hole H1 is formed in a circular shape in plan view, the shield film 36a is formed in an annular shape in plan view, the insulating film 36b is also formed in an annular shape in plan view, and the conductor 36c is formed in a circular shape in plan view. That is, the planar shapes of the shield film 36a and insulating film 36b are annular, and the planar shape of the conductor 36c is circular. The three-dimensional shapes of the shield film 36a and insulating film 36b are cylindrical, and the planar shape of the conductor 36c is cylindrical.

[0040] As shown in Figure 5, the shield wiring 36 is formed to be non-contact with each control line 33. The shield wiring 36 and each control line 33 are provided via an insulating layer 31. Also, as shown in Figure 6, the planar shape of the reference potential line 34 is formed to be approximately rectangular. The shield wiring 36 penetrates the reference potential line 34, but the shield film 36a of the shield wiring 36 is formed to be in contact with the reference potential line 34. Also, as shown in Figure 7, the planar shape of the first capacitance wiring 35 is formed to be approximately rectangular.

[0041] In the example shown in Figure 4, the planar shape of the shield wiring 36 is circular, but it is not limited to this. The planar shape of the shield wiring 36 may be, for example, elliptical or polygonal. Also, in the example shown in Figure 6, the planar shapes of the reference potential line 34 and the first capacitance wiring 35 are formed in a rectangular shape, for example, but it is not limited to this. The planar shapes of the reference potential line 34 and the first capacitance wiring 35 may be formed in a circular, elliptical, or other polygonal shape, for example.

[0042] <1-4. Example of Pixel Stacking Structure> Details of the stacking structure of the pixel 102 according to the first embodiment will be explained with reference to Figures 8 to 12. In the example shown in Figures 8 to 12, the number of layers (wiring layers) of the pixel 102 is 5, but the number of layers of the pixel 102 is not particularly limited.

[0043] FIG. 8 is a diagram showing a plan view of the first layer of pixel 102 according to the first embodiment. As shown in FIG. 8, pixel 102 is surrounded and separated by pixel isolation portion 22 (the same applies to FIGS. 9 to 12 hereinafter). The first layer of pixel 102 includes transfer transistor 12, reset transistor 14, amplification transistor 15, selection transistor 16, and switching transistor 18. A plurality of vias V1 for electrical connection to the second layer are provided for each of these elements. Note that first charge storage portion 13 and second charge storage portion 17 are formed on substrate 20 side (see FIG. 3). Shield wiring 36 is provided, for example, at one of the four corners of pixel 102 and is electrically connected to second charge storage portion 17.

[0044] FIG. 9 is a diagram showing a plan view of the second layer of pixel 102 according to the first embodiment. As shown in FIG. 9, the second layer of pixel 102 includes a plurality of wirings 32. Each wiring 32 includes, for example, various connection lines. A plurality of vias V2 for electrical connection to the third layer are provided for each of these wirings 32.

[0045] FIG. 10 is a diagram showing a plan view of the third layer of pixel 102 according to the first embodiment. As shown in FIG. 10, the third layer of pixel 102 includes a plurality of control lines 33. Each control line 33 includes, for example, various control lines (drive lines) such as pixel drive lines. The pixel drive line extends, for example, in the row direction of the pixel row.

[0046] FIG. 11 is a diagram showing a plan view of the fourth layer of pixel 102 according to the first embodiment. As shown in FIG. 11, the fourth layer of pixel 102 includes reference potential line 34 and wiring 34a. Shield wiring 36 penetrates reference potential line 34. Note that shield film 36a of shield wiring 36 is in contact with reference potential line 34 and is electrically connected to that reference potential line 34 (see FIG. 3).

[0047] FIG. 12 is a diagram showing the fifth layer plane of the pixel 102 according to the first embodiment. As shown in FIG. 12, the fifth layer of the pixel 102 includes the first capacitor wiring 35. A shield wiring 36 is electrically connected to the first capacitor wiring 35 (see FIG. 11). The conductor 36c of the shield wiring 36 is in contact with the first capacitor wiring 35 and is electrically connected to the first capacitor wiring 35 (see FIG. 3).

[0048] <1-5. Example of manufacturing process of shield wiring> An example of the manufacturing process of the shield wiring 36 according to the first embodiment will be described with reference to FIGS. 13 and 14. Each of FIGS. 13 and 14 is a diagram showing an example of the manufacturing process of the shield wiring 36 according to the first embodiment.

[0049] As shown in FIG. 13, a hole H1 is processed on the upper surface of the insulating layer 31 by an etching technique. The hole H1 extends in the thickness direction from the upper surface of the insulating layer 31 toward the second charge storage portion 17. A stopper layer 31a is laminated on the upper surface of the second charge storage portion 17. As the material of the stopper layer 31a, for example, SiN is used.

[0050] Next, a shield film 36a is formed on the upper surface of the insulating layer 31 including the hole H1 (the inner peripheral surface of the hole H1 and the upper surface of the insulating layer 31) by a thin film forming technique. At this time, the shield film 36a is also formed on the upper surface of the stopper layer 31a which is the bottom surface of the hole H1. As the material of the shield film 36a, for example, a metal such as tungsten is used. As the thin film forming technique, for example, CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) is used.

[0051] Next, an oxide film 31b is laminated on the shield film 36a. This oxide film 31b protects the shield film 36a on the inner peripheral surface (side wall) of the hole H1 during the etching process in the next step. As a result, the shield film 36a on the inner peripheral surface (side wall) of the hole H1 will remain without being etched during the etching process.

[0052] Subsequently, the stopper layer 31a is processed by etching techniques such as anisotropic etching. This forms a connection hole H1a in the stopper layer 31a. At this time, the shield film 36a and oxide film 31b on the bottom surface of the hole H1 are removed. The shield film 36a and oxide film 31b on the upper surface of the insulating layer 31 are also removed. In the case of the shield film 36a and oxide film 31b on the inner circumferential surface of the hole H1, only a predetermined region (a region of a predetermined depth) above them is removed.

[0053] Next, as shown in Figure 14, the oxide film 31b is removed. This oxide film 31b is damaged by the etching process in the previous step. Then, an insulating film 36b is formed on the shield film 36a inside the hole H1. At this time, an insulating film 36b is also formed on the upper surface of the second charge storage portion 17, which is the bottom surface of the connection hole H1a. After that, the insulating film 36b on the bottom surface of the connection hole H1a is removed by etching techniques such as anisotropic etching. At this time, the insulating film 36b on the upper surface of the insulating layer 31 is also removed.

[0054] Finally, a conductor 36c is formed within the hole H1. For example, tungsten (W) is embedded within the hole H1, forming a columnar conductor 36c within the hole H1 (see the upper diagram in Figure 14). Alternatively, for example, a metal material is embedded within the hole H1, forming a tubular conductor 36c within the hole H1 (see the lower diagram in Figure 14). The conductor 36c is provided with respect to the shield film 36a via an insulating film 36b. This completes the shield wiring 36.

[0055] <1-6. Modified Examples> <1-6-1. First Modified Example> An example of the configuration of pixel 102 according to the first modified example of the first embodiment will be described with reference to Figure 15. Figure 15 is a cross-sectional view showing an example of the configuration of pixel 102 according to the first modified example of the first embodiment.

[0056] As shown in Figure 15, the pixel 102 according to the first modified example includes a logic board 40 in addition to the substrate 20 and wiring layer 30. The substrate 20 and wiring layer 30 function as imaging substrates. The logic board 40 and the imaging substrate are stacked. The logic board 40 is an example of a second substrate.

[0057] The logic board 40 includes an insulating layer 41 and a shielding layer 42. The insulating layer 41 is provided with a reference potential line 34 and a first capacitance wiring 35, as well as a reference potential line (GND) 43 and a power line (VSS) 44. The reference potential line 43 is laminated on the shielding layer 42 via the insulating layer 41. The power line 44 is laminated on the reference potential line 34 via the insulating layer 41. This power line 44 is electrically connected to the reference potential line 34 by via V4.

[0058] The shielding layer 42 is provided on the back side of the logic board 40. This shielding layer 42 is electrically connected to the reference potential line 43 by via V4. The shielding layer 42 has one or both functions, for example, electrical shielding (noise reduction) and optical shielding (light reduction). This makes it possible to reduce the effects of electromagnetic waves and crosstalk generated between each element, for example. The shielding layer 42 is made of, for example, aluminum (Al), copper (Cu), or tungsten (W).

[0059] The shielded wiring 36 is provided so as to penetrate the shielding layer 42. The shielding film 36a of the shielded wiring 36 is electrically connected to the shielding layer 42. The surface end of the shielding film 36a is in contact with the shielding layer 42. As a result, the shielding film 36a is electrically connected to the reference potential line 43 via the shielding layer 42 and via V4. The shielding film 36a and the shielding layer 42 are, for example, integrated, but may be separate components.

[0060] Multiple wires 33a are provided in the wiring layer 30. Each wire 33a is provided on each control line 33 via an insulating layer 31. Each control line 33 and each wire 33a are electrically connected, for example, via V3. Each wire 33a is made of, for example, aluminum (Al), copper (Cu), or tungsten (W).

[0061] <1-6-2. Second Modification> An example of the configuration of pixel 102 according to the second modification of the first embodiment will be described with reference to Figure 16. Figure 16 is a cross-sectional view showing an example of the configuration of pixel 102 according to the second modification of the first embodiment.

[0062] As shown in Figure 16, the pixel 102 according to the second modified example comprises a substrate 20 and a wiring layer 30. The wiring layer 30 is provided with a plurality of wirings 33a, a plurality of vias V3, a shielding layer 42, a reference potential line (GND) 43, a power line (VSS) 44, and a plurality of vias V4. These are the same as in the first modified example. The shielding wiring 36 is also the same as in the first modified example.

[0063] <1-6-3. Third Modification> An example of the configuration of pixel 102 according to the third modification of the first embodiment will be described with reference to Figure 17. Figure 17 is a cross-sectional view showing an example of the configuration of pixel 102 according to the third modification of the first embodiment.

[0064] As shown in Figure 17, the pixel 102 in the third modified example has the same configuration as the first modified example. Furthermore, the pixel 102 in the third modified example has a second capacitance wiring 37. This second capacitance wiring 37 extends in the thickness direction (vertical direction in Figure 17) and penetrates the shield layer 42, and is electrically connected to the first capacitance wiring 35 and wiring 33a.

[0065] The second capacitance wiring 37 is composed of an insulating film 37a and a conductor 37b. The insulating film 37a is provided on the inner circumferential surface of the hole H2 formed in the insulating layer 31. The insulating film 37a is in contact with the first capacitance wiring 35 and wiring 33a. The conductor 37b is provided on the inner circumferential surface of the insulating film 37a within the hole H2 and is in contact with the first capacitance wiring 35 and wiring 33a. Wiring 33a connected to the first capacitance wiring 35 and wiring 32 facing wiring 33a at a predetermined distance apart are provided via the insulating layer 31. This forms a capacitance 17c for the second charge storage unit 17. Capacitance 17c is an example of wiring capacitance.

[0066] <1-6-4. Fourth Modification> An example of the configuration of pixel 102 according to the fourth modification of the first embodiment will be described with reference to Figure 18. Figure 18 is a cross-sectional view showing an example of the configuration of pixel 102 according to the fourth modification of the first embodiment.

[0067] As shown in Figure 18, the pixel 102 according to the fourth modified example comprises a substrate 20 and a wiring layer 30. The wiring layer 30 is provided with a plurality of wirings 33a and a plurality of vias V3. These are the same as in the first modified example. The first capacitance wiring 35 is provided in the wiring layer 30. For example, the first capacitance wiring 35 is provided in the same layer as each wiring 32. A shield wiring 36 is provided between this first capacitance wiring 35 and the second charge storage unit 17. The shield wiring 36 is electrically connected to the first capacitance wiring 35 and the second charge storage unit 17.

[0068] <2. Second Embodiment> <2-1. Example of Pixel Circuit Configuration> An example of the pixel circuit configuration of the pixel 102 according to the second embodiment will be described with reference to Figures 19 and 20. Figure 19 is a diagram showing an example of the pixel circuit configuration of the pixel 102 according to the second embodiment. Figure 20 is a diagram showing another example of the pixel circuit configuration of the pixel 102 according to the second embodiment. Note that the pixel circuits shown in Figures 19 and 20 are merely examples of pixel circuits. For example, various known circuit configurations may be used as pixel circuits.

[0069] As shown in Figure 19, the pixel 102 according to the second embodiment has a shielding wire 38A in addition to the parts according to the first embodiment (see Figure 2). This shielding wire 38A connects, for example, the first charge storage unit 13 to the drain of the transfer transistor 12, the gate of the amplification transistor 15, and the source of the switching transistor 18. The gate potential of the amplification transistor 15 is fixed by the connecting wire 32a to the potential between the amplification transistor 15 and the selection transistor 16 (AMP-SEL potential). The AMP-SEL potential is, for example, the ground potential or the power supply potential. The capacitance of the shielding wire 38A connected to the amplification transistor 15 is approximately zero.

[0070] Furthermore, as shown in Figure 20, the pixel 102 may also have a shielding wire 38A. This shielding wire 38A is connected, for example, to the gate of the reset transistor 14. The gate potential of the reset transistor 14 is fixed by the connecting wire 32a to the potential between the reset transistor 14 and the switching transistor 18 (RST-FDG potential). The RST-FDG potential is, for example, the ground potential or the power supply potential. The capacitance of the shielding wire 38A connected to the reset transistor 14 is approximately zero.

[0071] The shield wiring 38 may be provided to the gates of one or both of the amplification transistor 15 and the reset transistor 14, or it may be provided to the gates of other transistors such as the selection transistor 16 and the switching transistor 18.

[0072] <2-2. Example of Pixel Configuration> The pixel 102 according to the second embodiment will be described with reference to Figure 21. Figure 21 is a cross-sectional view showing an example of the configuration of the pixel 102 according to the second embodiment. The pixel 102 is, for example, an example of a back-illuminated type.

[0073] As shown in Figure 21, in the second embodiment, the substrate 20 has, in addition to the parts according to the first embodiment (see Figure 3), a ground line (GND) 23, a power line (VDD) 24, an AMP-SEL line 25, and a signal line (VSL) 26. Note that in the example of Figure 21, the photoelectric conversion unit 11 is omitted.

[0074] The ground line 23, power line 24, AMP-SEL line 25, and signal line 26 are provided on the surface side (top surface in Figure 21) of the substrate 20. The ground line 23 is connected to the reference potential line 34 via vias V1, V2, V3, wiring 32, and control line 33. The AMP-SEL line 25 is connected to via V1. The signal line 26 is connected to wiring 34a via vias V1, V2, V3, wiring 32, and control line 33. The signal line 26 is included, for example, in the aforementioned vertical signal line 109.

[0075] The wiring layer 30 includes, in addition to the parts according to the first embodiment (see Figure 3), an amplifying transistor 15 and a selecting transistor 16. These amplifying transistor 15 and selecting transistor 16 are provided on the back side (bottom side in Figure 21) of the wiring layer 30.

[0076] Furthermore, the wiring layer 30 has a plurality of shielding wires 38. These shielding wires 38 are provided, for example, on the back side (bottom side in Figure 21) of the wiring layer 30 than each wire 32. Each of the shielding wires 38 extends in the thickness direction (up and down direction in Figure 21). Each shielding wire 38 is included, for example, in the aforementioned shielding wire 38A.

[0077] Each shielded wiring 38 is composed of a shielding film 38a, an insulating film 38b, and a conductor 38c. In each shielded wiring 38, the shielding film 38a is provided on the inner circumferential surface of a hole H2 formed in the insulating layer 31. Each shielding film 38a of each shielded wiring 38 is electrically connected by a connecting wire 32a. This connecting wire 32a is electrically connected to via V1 connected to the AMP-SEL line 25, i.e., to the AMP-SEL line 25. As a result, each shielding film 38a of each shielded wiring 38 is fixed at the AMP-SEL potential. For example, the gate potential of the amplifying transistor 15 becomes the same as the AMP-SEL potential, i.e., the source potential of the amplifying transistor 15.

[0078] In each shielded wiring 38, the insulating film 38b is provided on the inner circumferential surface of the shielding film 38a within the hole H2, and the conductor 38c is provided on the inner circumferential surface of the insulating film 38b within the hole H2. In each shielded wiring 38, the shielding film 38a and the conductor 38c are provided via the insulating film 38b. One conductor 38c of each shielded wiring 38 is electrically connected to the first charge storage unit 13, and the other conductor 38c of each shielded wiring 38 is electrically connected to the amplification transistor 15. Each conductor 38c of each shielded wiring 38 is connected by a connecting wire 32b.

[0079] Furthermore, in one of the shielded wirings 38, the shielding film 38a is not in contact with the first charge storage unit 13 and the connecting line 32b, while the insulating film 38b and the conductor 38c are in contact with the first charge storage unit 13 and the connecting line 32b. In the other of the shielded wirings 38, the shielding film 38a is not in contact with the amplifying transistor 15 and the connecting line 32b, while the insulating film 38b and the conductor 38c are in contact with the amplifying transistor 15 and the connecting line 32b. In each shielded wiring 38, the length of the shielding film 38a in the thickness direction is shorter than the length of one or both of the insulating film 38b and the conductor 38c in the thickness direction. For example, the shielding film 38a may not be provided on the entire surface of the shielded wiring 38, i.e., on the entire outer surface of the insulating film 38b, but only on a part of the outer surface of the insulating film 38b.

[0080] With this configuration, the potential of each shield wire 38 is fixed to the potential of the AMP-SEL line 25, that is, the potential between the amplification transistor 15 and the selection transistor 16 (AMP-SEL potential). This suppresses fluctuations in the signal of the first charge storage unit 13 caused by other drive lines, etc. Furthermore, since the potential of each shield wire 38 moves in conjunction with the first charge storage unit 13, no relative potential difference is generated. As a result, almost no additional capacitance is generated due to the potential of the shield wires 38, and high conversion efficiency can be maintained.

[0081] Here, capacitance 17b is generated in the shield wiring 36 connected to the second charge storage unit 17, which corresponds to low conversion efficiency. At low conversion efficiency, this is not a problem because the capacitance is large from the start, but at high conversion efficiency, the capacitance of the shield wiring 38 becomes a problem because it is desirable to reduce the capacitance of the first charge storage unit 13, which corresponds to high conversion efficiency, as much as possible. Therefore, the shield film 38a of the shield wiring 38 is fixed at the AMP-SEL potential. As a result, the AMP-SEL potential fluctuates in conjunction with the output of the amplifying transistor 15 in response to fluctuations in the potential of the first charge storage unit 13 (gate input of the amplifying transistor 15). As a result, the potential between the first charge storage unit 13 and the shield wiring 38 is independent of potential changes, and no capacitance is added to the first charge storage unit 13 by the shield wiring 38. Therefore, it is possible to obtain a shielding effect from other drive lines, etc., while maintaining high conversion efficiency.

[0082] Furthermore, the length of the shield wiring 38 in the thickness direction is shorter than the length of the shield wiring 36 in the thickness direction (low profile). This makes it possible to reduce the capacitance of the shield wiring 38, thereby further improving the high conversion efficiency. On the other hand, by routing the shield wiring 36 to a higher position than the shield wiring 38, it is possible to secure a metal area for wiring capacitance, and at the same time, by making the shield wiring 36 itself longer, it is possible to increase the capacitance of the shield wiring 36, thereby achieving low conversion efficiency.

[0083] Furthermore, in the shield wiring 38 connected to the first charge storage unit 13, it is desirable that the insulating film 38b, such as an oxide film, be made of, for example, a low-k material (low dielectric constant material). A film made of a low-k material is an insulating film with a low dielectric constant, and plays a role in reducing capacitive coupling between wirings, for example. The dielectric constant of a low-k material is, for example, SiO ２ It is lower than the dielectric constant of 4.2. In the source follower (SF) circuit of the amplification transistor 15, for example, the output noise of the amplification transistor 15 may be superimposed as noise on the shield potential, but by using a Low-k film as the insulating film 38b, it is possible to reduce the capacitive coupling of the shield wiring 38 and the first charge storage unit 13, thereby reducing the effect of the noise.

[0084] <2-3. Example of Pixel Stacking Structure> Details of the stacking structure of the pixel 102 according to the second embodiment will be explained with reference to Figures 22 to 27. In the example shown in Figures 22 to 27, the number of layers (wiring layers) of the pixel 102 is 6, but the number of layers of the pixel 102 is not particularly limited.

[0085] Figure 22 is a diagram showing the first layer of a pixel 102 according to the second embodiment. As shown in Figure 22, the pixel 102 is separated by a pixel separation unit 22 (the same applies to Figures 23 to 27 thereafter). The first layer of the pixel 102 includes a transfer transistor 12, a reset transistor 14, an amplification transistor 15, a selection transistor 16, and a switching transistor 18. Each of these elements is provided with, for example, a plurality of vias V1 for electrical connection to the second layer. The first charge storage unit 13 and the second charge storage unit 17 are formed on the substrate 20 side (see Figure 21). The shield wiring 36 is provided, for example, at one of the four corners of the pixel 102 and is electrically connected to the second charge storage unit 17. Also, for example, one of the two shield wirings 38 is electrically connected to the first charge storage unit 13, and the other of the two shield wirings 38 is electrically connected to the amplification transistor 15.

[0086] Figure 23 is a diagram showing the second layer plane of the pixel 102 according to the second embodiment. As shown in Figure 23, the second layer of the pixel 102 includes connecting lines 32a. The connecting lines 32a electrically connect, for example, each shield wiring 38 (each shield film 38a) to the via V1 connected to the AMP-SEL interline 25.

[0087] Figure 24 shows a plan view of the third layer of a pixel 102 according to a second embodiment. As shown in Figure 24, the third layer of the pixel 102 includes a plurality of wirings 32 and connecting lines 32b. Each wiring 32 includes, for example, various connecting lines. Each of these wirings 32 is provided with, for example, a plurality of vias V2 for electrical connection to the third layer. The connecting lines 32b are formed, for example, to run opposite to the connecting lines 32a of the second layer and electrically connect each shield wiring 38 (each conductor 38c).

[0088] Figure 25 is a diagram showing the fourth layer plane of a pixel 102 according to the second embodiment. As shown in Figure 25, the fourth layer of the pixel 102 includes a plurality of control lines 33. Each control line 33 includes various control lines (drive lines), such as pixel drive lines. The pixel drive lines extend, for example, in the row direction of the pixel row.

[0089] Figure 26 shows a plan view of the fifth layer of the pixel 102 according to the second embodiment. As shown in Figure 26, the fifth layer of the pixel 102 includes a reference potential line 34 and wiring 34a. The shield wiring 36 penetrates the reference potential line 34. The shield film 36a of the shield wiring 36 is in contact with the reference potential line 34 and is electrically connected to the reference potential line 34 (see Figure 21).

[0090] Figure 27 shows a plan view of the sixth layer of a pixel 102 according to the second embodiment. As shown in Figure 27, the sixth layer of the pixel 102 includes a first capacitance wiring 35. A shield wiring 36 is electrically connected to this first capacitance wiring 35 (see Figure 26). The conductor 36c of the shield wiring 36 is in contact with the first capacitance wiring 35 and is electrically connected to the first capacitance wiring 35 (see Figure 21).

[0091] <2-4. Modified Examples> <2-4-1. First Modified Example> An example of the configuration of pixel 102 according to the first modified example of the second embodiment will be described with reference to Figure 28. Figure 28 is a cross-sectional view showing an example of the configuration of pixel 102 according to the first modified example of the second embodiment.

[0092] In the example shown in Figure 28, a first chip (substrate 20 and wiring layer 30) and a second chip (second substrate 20A and second wiring layer 30A) are stacked. The first and second chips are connected by via structures such as TSV (Through Silicon Via). Note that the photoelectric conversion unit 11 is omitted in the example shown in Figure 28.

[0093] As shown in Figure 28, the pixel 102 according to the first modified example of the second embodiment includes a second substrate 20A and a second wiring layer 30A, in addition to a substrate (first substrate) 20 and a wiring layer (first wiring layer) 30. The second substrate 20A and the second wiring layer 30A are laminated, with the substrate 20 and wiring layer 30 being laminated on the surface of the second wiring layer 30A (the upper surface in Figure 28).

[0094] The second substrate 20A is a semiconductor substrate (semiconductor layer) on which various elements are arranged. This second substrate 20A is made of, for example, silicon (Si). A ground line (GND) 23A and a first charge storage section 13A are provided on the surface side (top surface in Figure 28) of the second substrate 20A. The ground line 23A is electrically connected to the wiring 32 via via V1.

[0095] The first charge storage unit 13A is electrically connected to the connecting line 32b by a shielding wire 38. The conductor 38c of the shielding wire 38 connected to the first charge storage unit 13A is in contact with the first charge storage unit 13A and the connecting line 32b. The shielding film 38a of this shielding wire 38 is electrically connected to the shielding film 38a of other shielding wires 38 by the connecting line 32a. The shielding wire 38 passes through a hole H2a formed in the substrate 20. An insulating film 20a is provided on the inner circumferential surface of the hole H2a. In the example of Figure 28, a via V1 is connected to the second charge storage unit 17 instead of a shielding wire 36.

[0096] The second wiring layer 30A is provided on the surface of the second substrate 20A. This second wiring layer 30A is an area where various elements and wiring are arranged, for example. The second wiring layer 30A is an example of a multilayer wiring layer. A transfer transistor 12 is provided on the back side (bottom side in Figure 28) of the second wiring layer 30A. The second wiring layer 30A is also provided with an insulating layer (interlayer insulating layer) 31, a plurality of wirings 32, and a plurality of vias V1. The transfer transistor 12 is electrically connected to the wirings 32 via the vias V1.

[0097] Furthermore, in the shield wiring 38 connected to the first charge storage unit 13 or the first charge storage unit 13A, it is desirable that the insulating film 38b, such as an oxide film, be made of, for example, a low-k material (low dielectric constant material).

[0098] <2-4-2. Second Modification> An example of the configuration of the pixel 102 according to the second modification of the second embodiment will be described with reference to Figure 29. Figure 29 is a cross-sectional view showing an example of the configuration of the pixel 102 according to the second modification of the second embodiment.

[0099] In the example shown in Figure 29, a first chip (substrate 20 and wiring layer 30) and a second chip (second substrate 20A and second wiring layer 30A) are stacked. The first and second chips are bonded together by a metal-to-metal bonding such as a Cu-Cu junction. Note that in the example shown in Figure 29, the photoelectric conversion unit 11, reference potential line 34, first capacitance wiring 35, shield wiring 36, etc., are omitted.

[0100] As shown in Figure 29, the pixel 102 according to the second modification of the second embodiment is basically the same as the first modification according to the second embodiment, but in the second modification of the second embodiment, the wiring layer 30 has a plurality of joints 30a, and the second wiring layer 30A has a plurality of joints 30b. Each joint 30a is provided on the lower surface (in Figure 29) side of the wiring layer 30. Each joint 30b is provided on the upper surface (in Figure 29) side of the wiring layer 30. These joints 30a and joints 30b are joined by metal-to-metal joining such as Cu-Cu joining.

[0101] The first charge storage unit 13 and the first charge storage unit 13A are electrically connected via two shield wires 38, a joint 30a, and a joint 30b. One shield film 38a of each shield wire 38 is electrically connected to a joint 32c by a connecting wire 32a. The joint 32c electrically connects the via V2 connected to the AMP-SEL line 25 to the joint 30a. The other shield film 38a of each shield wire 38 is electrically connected to a joint 32d by a connecting wire 32a. The joint 32d is electrically connected to a joint 30b connected to the AMP-SEL line 25. Thus, each shield film 38a of each shield wire 38 is electrically connected to the AMP-SEL line 25.

[0102] <3. Overview of Each Embodiment> As described above, the photodetector 101 according to each embodiment comprises a substrate 20, an insulating layer 31 laminated on the substrate 20, a photoelectric conversion unit 11 provided on the substrate 20 that generates electric charge by photoelectric conversion, and a shield wiring 36 provided on the insulating layer 31 that extends in the thickness direction of the insulating layer 31. The shield wiring 36 includes a shield film 36a that extends in the thickness direction (see Figure 3, etc.). As a result, since the shield film 36a, which is part of the shield wiring 36, extends in the thickness direction, it is possible to reduce the number of layers and planar area of ​​the wiring that forms the shield layer while reducing the effects of electromagnetic waves and crosstalk, thereby enabling miniaturization of the device.

[0103] Furthermore, the shielded wiring 36 may include capacitance 17b (see Figures 2 and 3). This allows the capacitance to be adjusted using the shielded wiring 36.

[0104] Furthermore, the shielded wiring 36 may be electrically connected to the wiring capacitance (for example, capacitance 17a) (see Figures 2 and 3). This allows the capacitance to be adjusted using the shielded wiring 36.

[0105] Furthermore, the shielded wiring 36 may be electrically connected to multiple wiring capacitances (for example, capacitance 17a, capacitance 17c) (see Figures 2, 3, and 17). This allows the capacitance to be adjusted using the shielded wiring 36.

[0106] Furthermore, the light detection device 101 may also include a second charge storage unit 17 provided on the substrate 20 for accumulating electric charge, and the shield wiring 36 may be electrically connected to the second charge storage unit 17 (see Figure 3, etc.). This allows the shield wiring 36 to be used as wiring connected to the second charge storage unit 17.

[0107] Furthermore, multiple charge storage units, for example, a first charge storage unit 13 and a second charge storage unit 17, are provided, and the shield wiring 36 may be electrically connected to the second charge storage unit 17 among the first charge storage unit 13 and the second charge storage unit 17 (see Figure 3, etc.). This allows the shield wiring 36 to be used as wiring connected to the second charge storage unit 17 even when the first charge storage unit 13 and the second charge storage unit 17 are present.

[0108] Furthermore, the shield wiring 36 includes an insulating film 36b and a conductor 36c that are stretched in the thickness direction, and the shield film 36a and the conductor 36c may be provided via the insulating film 36b (see Figure 3, etc.). This makes it easy to form a shield wiring 36 that includes capacitance 17b.

[0109] Furthermore, the shield film 36a is not in contact with the second charge storage unit 17, while the conductor 36c may be in contact with the second charge storage unit 17 (see Figure 3, etc.). This ensures that the shield wiring 36 can be reliably used as wiring connected to the second charge storage unit 17.

[0110] Furthermore, the length of the shield film 36a in the thickness direction may be shorter than the length of one or both of the insulating film 36b and the conductor 36c in the thickness direction (see Figure 3, etc.). This makes it easy to form the shield wiring 36 used as wiring connected to the second charge storage unit 17.

[0111] Furthermore, the photodetector 101 may also include a first capacitance wiring 35 provided in the insulating layer 31, and the conductor 36c may be electrically connected to the first capacitance wiring 35 (see Figure 3, etc.). This allows the shield wiring 36 to be used as wiring connected to the first capacitance wiring 35.

[0112] Furthermore, the shield film 36a is not in contact with the first capacitance wiring 35, while the conductor 36c may be in contact with the first capacitance wiring 35 (see Figure 3, etc.). This ensures that the shield wiring 36 can be reliably used as wiring connected to the first capacitance wiring 35.

[0113] Furthermore, the photodetector 101 may also include a reference potential line 34 provided in the insulating layer 31, and the reference potential line 34 may be provided between the first capacitance wiring 35 and the second charge storage unit 17, on the side of the first capacitance wiring 35 (see Figure 3, etc.). This ensures that the device can be miniaturized.

[0114] Furthermore, the shield wiring 36 may penetrate the reference potential line 34, the shield film 36a may be in contact with the reference potential line 34, and the conductor 36c may not be in contact with the reference potential line 34 (see Figure 3, etc.). This allows the potential of the shield film 36a to be set to the reference potential (for example, ground).

[0115] Furthermore, the photodetector 101 may also include a reference potential line 34 provided in the insulating layer 31, and the reference potential line 34 may be provided on the side opposite to the second charge storage section 17 in the first capacitance wiring 35 (see Figure 15, etc.). This ensures that the device can be miniaturized.

[0116] Furthermore, the photodetector 101 may further include a second capacitance wiring 37 provided in the insulating layer 31 and extending in the thickness direction, and the conductor 36c may be electrically connected to the second capacitance wiring 37 via the first capacitance wiring 35 (see Figure 17). This allows the capacitance to be adjusted using the shield wiring 36.

[0117] Furthermore, the photodetector 101 further comprises a second substrate (for example, a logic substrate 40) laminated on the insulating layer 31, and a shield layer 42 provided on the second substrate, wherein the shield wiring 36 penetrates the shield layer 42, the shield film 36a is in contact with the shield layer 42, and the conductor 36c may not be in contact with the shield layer 42 (see Figure 15, etc.). This makes it possible to reliably reduce the effects of electromagnetic waves and crosstalk.

[0118] Furthermore, the photodetector 101 may also include a shielding layer 42 provided on the insulating layer 31, with the shielding wiring 36 penetrating the shielding layer 42, the shielding film 36a in contact with the shielding layer 42, and the conductor 36c not in contact with the shielding layer 42 (see Figure 16). This ensures a reliable reduction in the effects of electromagnetic waves and crosstalk.

[0119] Furthermore, the photodetector 101 may also include a second capacitance wiring 37 provided in the insulating layer 31 and extending in the thickness direction, and the second capacitance wiring 37 may penetrate the shield layer 42 (see Figure 17). This ensures that the device can be miniaturized.

[0120] Furthermore, the second capacitance wiring 37 includes an insulating film 37a and a conductor 37b that are stretched in the thickness direction, respectively, with the insulating film 37a in contact with the shield layer 42, and the conductor 37b not in contact with the shield layer 42 (see Figure 17). This makes it possible to easily form the second capacitance wiring 37.

[0121] Furthermore, the photodetector 101 includes transistors (for example, an amplifying transistor 15, a reset transistor 14, etc.) provided in the insulating layer 31, and the shielding wiring 38 is connected to the gate of the transistor, and the gate potential of the transistor may be the same as the source potential of the transistor (see, for example, Figures 19 to 21). This makes it possible to suppress the addition of capacitance due to the shielding wiring 38.

[0122] Furthermore, the shield wiring 38 includes an insulating film 38b and a conductor 38c that are stretched in the thickness direction, respectively, and the shield film 38a and the conductor 38c are provided via the insulating film 38b, and the insulating film 38b may be formed of a low dielectric constant material (see, for example, Figures 19 to 21). This ensures that the addition of capacitance by the shield wiring 38 is suppressed.

[0123] <4. Other Embodiments> The configurations and processes described in the above-described embodiments (including examples and modifications) may be implemented in various other forms besides those described above. For example, the configurations and processes may be in various forms, not limited to the examples described above. Also, for example, the configurations, processing procedures, specific names, and information including various data and parameters shown in the above document and drawings may be changed at will unless otherwise specified.

[0124] Furthermore, the configurations and processes described in the above-mentioned embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the figures. In other words, the specific forms of distribution and integration of each configuration and process are not limited to those shown in the figures, and all or part of them may be functionally or physically distributed and integrated in any unit depending on various loads and usage conditions.

[0125] Furthermore, the various configurations and processes described in the above-mentioned embodiments (including examples and modifications) may be combined as appropriate. For example, at least a part of one embodiment may be combined with at least a part of another embodiment as appropriate. Also, the effects described in the embodiments are merely illustrative and not limiting, and other effects may also occur.

[0126] <5. Application Examples> <5-1. Light Detection Device> An example of the application of the pixel 102 described above will be explained with reference to Figures 30 and 31. The light detection device 201 is an example of an image sensor (solid-state imaging device).

[0127] Figure 30 shows an example of the configuration of a photodetector 201 according to an application example. The photodetector 201 comprises three substrates (first substrate 210, second substrate 220, and third substrate 230). The photodetector 201 has a three-dimensional structure formed by bonding the three substrates (first substrate 210, second substrate 220, and third substrate 230). The first substrate 210, second substrate 220, and third substrate 230 are stacked in this order.

[0128] The first substrate 210 has a semiconductor substrate 211 with a plurality of sensor pixels 212 that perform photoelectric conversion. For example, the aforementioned pixel 102 is used as each sensor pixel 212. The plurality of sensor pixels 212 are arranged in a matrix within the pixel region 213 of the first substrate 210.

[0129] The second substrate 220 has a readout circuit 222 for every four sensor pixels 212 on the semiconductor substrate 221, which outputs a pixel signal based on the charge output from the sensor pixels 212. The second substrate 220 has a plurality of pixel drive lines 223 extending in the row direction and a plurality of vertical signal lines 224 extending in the column direction.

[0130] The third substrate 230 has a logic circuit 232 for processing pixel signals on a semiconductor substrate 231. The logic circuit 232 includes, for example, a vertical drive circuit 233, a column signal processing circuit 234, a horizontal drive circuit 235, and a system control circuit 236. The logic circuit 232 (specifically the horizontal drive circuit 235) outputs an output voltage Vout for each sensor pixel 212 to the outside. In the logic circuit 232, for example, CoSi is present on the surface of the impurity diffusion region that is in contact with the source electrode and the drain electrode. ２ A low-resistance region may be formed from silicides, such as NiSi, that are formed using a salicide (Self-Aligned Silicide) process.

[0131] The vertical drive circuit 233, for example, sequentially selects a plurality of sensor pixels 212 row by row. The column signal processing circuit 234, for example, applies correlated double sampling (CDS) processing to the pixel signals output from each sensor pixel 212 in the row selected by the vertical drive circuit 233. The column signal processing circuit 234, for example, extracts the signal level of the pixel signals by applying CDS processing and holds pixel data corresponding to the amount of light received by each sensor pixel 212. The horizontal drive circuit 235, for example, sequentially outputs the pixel data held by the column signal processing circuit 234 to the outside. The system control circuit 236, for example, controls the driving of each block in the logic circuit 232 (vertical drive circuit 233, column signal processing circuit 234, and horizontal drive circuit 235).

[0132] Figure 31 shows an example configuration of a sensor pixel 212 and a readout circuit 222 related to an application example. Below, we will describe the case in which four sensor pixels 212 share one readout circuit 222, as shown in Figure 31. Here, "sharing" means that the outputs of the four sensor pixels 212 are input to a common readout circuit 222.

[0133] Each sensor pixel 212 has components that are common to all of them. In the example in Figure 31, an identification number (1, 2, 3, 4) is added to the end of the code of each sensor pixel 212 component to distinguish them from one another. Hereafter, when it is necessary to distinguish the components of each sensor pixel 212 from one another, an identification number will be added to the end of the code of each sensor pixel 212 component; however, when it is not necessary to distinguish the components of each sensor pixel 212 from one another, the identification number at the end of the code of each sensor pixel 212 component will be omitted.

[0134] Each sensor pixel 212 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to one specific example of the "photoelectric conversion element" of this disclosure. The photodiode PD performs photoelectric conversion to generate a charge corresponding to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 223. The transfer transistor TR is, for example, a CMOS transistor.

[0135] The floating diffusion FDs of each sensor pixel 212 that share a single readout circuit 222 are electrically connected to each other and are also electrically connected to the input terminal of the common readout circuit 222. The readout circuit 222 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted if necessary. The source of the reset transistor RST (the input terminal of the readout circuit 222) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 223 (see Figure 30). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 222) is electrically connected to the vertical signal line 224, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 223 (see Figure 30).

[0136] When the transfer transistor TR is turned ON, it transfers the charge from the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned ON, it resets the potential of the floating diffusion FD to the potential of the power line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 222. The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge held in the floating diffusion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal with a voltage corresponding to the level of charge generated in the photodiode PD. When the selection transistor SEL is turned ON, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to that potential to the column signal processing circuit 234 via the vertical signal line 224. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0137] Furthermore, the pixel 102 may be applied to other light detection devices besides the aforementioned light detection devices 101 and 201. Also, the shield wiring 36 of the pixel 102 may be applied to various semiconductor devices. For example, the light detection devices 101 and 201 can be considered types of semiconductor devices.

[0138] <5-2. Various Devices> Examples of applications of the above-mentioned photodetector 101 or photodetector 201 will be explained with reference to Figure 32. Figure 32 is a diagram showing various application examples of the photodetector 101 or photodetector 201.

[0139] The above-described photodetector 101 or photodetector 201 may be applied to various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. For example, the photodetector 101 or photodetector 201 may be applied to various devices (electronic devices) or electronic devices mounted on various devices, as shown below.

[0140] As shown in Figure 32, the above-mentioned light detection device 101 or light detection device 201 can be used, for example, in: "devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions"; "devices used for traffic, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles"; "devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow for device operation according to those gestures"; "devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography by receiving infrared light"; "devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition"; "devices used for beauty purposes, such as skin measuring devices that capture images of the skin and microscopes that capture images of the scalp"; "devices used for sports, such as action cameras and wearable cameras for sports use"; and "devices used for agriculture, such as cameras for monitoring the condition of fields and crops."

[0141] Furthermore, the technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as electronic equipment mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors). Alternatively, for example, the technology disclosed herein may be implemented as electronic equipment mounted on endoscopic surgical systems or microsurgical systems.

[0142] <5-3. Imaging Device> The imaging device 300 relating to the application example will be described with reference to Figure 33. Figure 33 is a diagram showing an example configuration of the imaging device 300 relating to the application example. This imaging device 300 is an example of an electronic device to which the above-mentioned light detection device 101 or light detection device 201 is applied. Examples of imaging devices 300 include digital still cameras, video cameras, smartphones and mobile phones with imaging functions, and other electronic devices.

[0143] As shown in Figure 33, the imaging device 300 includes an optical system 301, a shutter device 302, an image sensor (solid-state imager) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. This imaging device 300 is capable of capturing both still and moving images.

[0144] The optical system 301 has one or more lenses. This optical system 301 guides light from the subject (incident light) to the image sensor 303 and forms an image on the light-receiving surface of the image sensor 303.

[0145] The shutter device 302 is positioned between the optical system 301 and the image sensor 303. The shutter device 302 controls the light illumination period and the light shielding period for the image sensor 303 according to the control of the control circuit 304.

[0146] The image sensor 303 accumulates signal charge for a certain period of time in response to light that is imaged onto the light-receiving surface via the optical system 301 and shutter device 302. The signal charge accumulated in the image sensor 303 is transferred according to a drive signal (timing signal) supplied from the control circuit 304. As the image sensor 303, for example, the light detection device 101 or the light detection device 201 described above is used.

[0147] The control circuit 304 drives the image sensor 303 and the shutter device 302 by outputting drive signals that control the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302.

[0148] The signal processing circuit 305 performs various signal processing operations on the signal charge output from the image sensor 303. The image (image data) obtained by the signal processing circuit 305 is supplied to the monitor 306 and also to the memory 307.

[0149] The monitor 306 displays video or still images captured by the image sensor 303 based on image data supplied from the signal processing circuit 305. For example, the monitor 306 may be a panel-type display device such as a liquid crystal panel or an organic EL (Electro-Luminescence) panel.

[0150] The memory 307 stores image data supplied from the signal processing circuit 305, that is, image data of moving or still images captured by the image sensor 303. Various types of storage devices can be used as the memory 307.

[0151] Even in the imaging device 300 configured in this way, the same effects as in the above-described embodiment can be obtained by applying the above-described light detection device 101 or light detection device 201 as the image sensor 303.

[0152] <5-4. Distance Measuring Device> The distance measuring device 400 relating to the application example will be described with reference to Figure 34. Figure 34 is a diagram showing an example configuration of the distance measuring device 400 relating to the application example. This distance measuring device 400 is an example of an electronic device to which the above-mentioned optical detection device 101 or optical detection device 201 is applied.

[0153] As shown in Figure 34, the distance measuring device (distance image sensor) 400 comprises a light source unit 401, an optical system 402, an image sensor (solid-state imager) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. This distance measuring device 400 can acquire a distance image corresponding to the distance to the subject by projecting light from the light source unit 401 toward the subject and receiving the light (modulated light or pulsed light) reflected from the surface of the subject.

[0154] The light source unit 401 projects light toward the subject. The light source unit 401 can be, for example, a vertical cavity surface-emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the arrangement of the laser diodes.

[0155] The optical system 402 has one or more lenses. This optical system 402 guides light from the subject (incident light) to the image sensor 403 and forms an image on the light-receiving surface (sensor part) of the image sensor 403.

[0156] The image sensor 403 accumulates signal charge in response to light formed on the light-receiving surface via the optical system 402. A distance signal indicating the distance, determined from the light-receiving signal (APD OUT) output from the image sensor 403, is supplied to the signal processing circuit 405. As the image sensor 403, for example, the light detection device 101 or the light detection device 201 described above can be used.

[0157] The control circuit 404 outputs drive signals (control signals) that control the operation of the light source unit 401 and the image sensor 403, and drives the light source unit 401 and the image sensor 403.

[0158] The signal processing circuit 405 performs various signal processing operations on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing and peak detection processing) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing circuit 405 is supplied to the monitor 406 and also to the memory 407.

[0159] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. For example, a panel-type display device such as a liquid crystal panel or an organic EL panel can be used as the monitor 406.

[0160] The memory 407 stores image data supplied from the signal processing circuit 405, that is, image data of the distance image captured by the image sensor 403. Various types of storage devices can be used as the memory 407.

[0161] In the distance measuring device 400 configured in this way, the same effects as in the above-described embodiment can be obtained by applying the above-described light detection device 101 or light detection device 201 as the image sensor 403.

[0162] As described above, the light detection device 101 or light detection device 201 can be implemented in various electronic devices. For example, in addition to the imaging device 300 and the distance measuring device 400, the light detection device 101 or light detection device 201 may be installed in various electronic devices such as HDDs (hard disk drives), notebook PCs (personal computers), mobile devices (e.g., smartphones and tablet PCs), PDAs (personal digital assistants), wearable devices, game consoles, and music players.

[0163] <6. Addendum> The technology can also be configured as follows: (1) A photodetector comprising: a substrate; an insulating layer laminated on the substrate; a photoelectric conversion unit provided on the substrate that generates charge by photoelectric conversion; and a shield wiring provided on the insulating layer and extending in the thickness direction of the insulating layer, wherein the shield wiring includes a shield film extending in the thickness direction. (2) The photodetector according to (1), wherein the shield wiring includes a capacitance. (3) The photodetector according to (1) or (2), wherein the shield wiring is electrically connected to a wiring capacitance. (4) The photodetector according to any one of (1) to (3), wherein the shield wiring is electrically connected to a plurality of wiring capacitances. (5) The photodetector according to any one of (1) to (4), further comprising: a charge storage unit provided on the substrate that stores the charge; wherein the shield wiring is electrically connected to the charge storage unit. (6) The photodetector according to (5), wherein a plurality of charge storage units are provided, and the shield wiring is electrically connected to any of the plurality of charge storage units. (7) The photodetector according to (5) or (6), wherein the shield wiring includes an insulating film and a conductor, each stretched in the thickness direction, and the shield film and the conductor are provided via the insulating film. (8) The photodetector according to (7), wherein the shield film is not in contact with the charge storage unit, and the conductor is in contact with the charge storage unit. (9) The photodetector according to (8), wherein the length of the shield film in the thickness direction is shorter than the length of one or both of the insulating film and the conductor in the thickness direction. (10) The photodetector according to any one of (7) to (9), further comprising a first capacitance wiring provided in the insulating layer, and the conductor being electrically connected to the first capacitance wiring. (11) The photodetector according to (10), wherein the shielding film is not in contact with the first capacitance wiring, and the conductor is in contact with the first capacitance wiring.(12) The photodetector according to (10), further comprising a reference potential line provided in the insulating layer, wherein the reference potential line is provided between the first capacitance wiring and the charge storage portion and on the side of the first capacitance wiring. (13) The photodetector according to (12), wherein the shield wiring penetrates the reference potential line, the shield film is in contact with the reference potential line, and the conductor is not in contact with the reference potential line. (14) The photodetector according to (10), further comprising a reference potential line provided in the insulating layer, wherein the reference potential line is provided on the side of the first capacitance wiring opposite to the side of the charge storage portion. (15) The photodetector according to any one of (10) to (14), further comprising a second capacitance wiring provided in the insulating layer and extending in the thickness direction, wherein the conductor is electrically connected to the second capacitance wiring via the first capacitance wiring. (16) The photodetector according to any one of (7) to (15), further comprising: a second substrate laminated on the insulating layer; and a shield layer provided on the second substrate, wherein the shield wiring penetrates the shield layer, the shield film is in contact with the shield layer, and the conductor is not in contact with the shield layer. (17) The photodetector according to any one of (7) to (15), further comprising: a shield layer provided on the insulating layer; the shield wiring penetrates the shield layer; the shield film is in contact with the shield layer, and the conductor is not in contact with the shield layer. (18) The photodetector according to (16) or (17), further comprising: a second capacitance wiring provided on the insulating layer and extending in the thickness direction, wherein the second capacitance wiring penetrates the shield layer. (19) The photodetector according to (18), wherein the second capacitance wiring includes an insulating film and a conductor that are respectively stretched in the thickness direction, the insulating film is in contact with the shield layer, and the conductor is not in contact with the shield layer.(20) The photodetector according to any one of (1) to (19), further comprising a transistor provided on the insulating layer, wherein the shield wiring is connected to the gate of the transistor, and the gate potential of the transistor is the same as the source potential of the transistor. (21) The photodetector according to (20), wherein the shield wiring includes an insulating film and a conductor, each stretched in the thickness direction, the shield film and the conductor are provided via the insulating film, and the insulating film is formed of a low dielectric constant material. (22) An electronic device comprising a photodetector, wherein the photodetector comprises a substrate, an insulating layer laminated on the substrate, a photoelectric conversion unit provided on the substrate that generates charge by photoelectric conversion, and a shield wiring provided on the insulating layer that stretches in the thickness direction of the insulating layer, wherein the shield wiring includes a shield film stretched in the thickness direction. (23) An electronic device comprising a photodetector according to any one of (1) to (21). (24) A semiconductor device comprising any of the components of the photodetector described in any one of (1) to (21).

[0164] 11 Photoelectric conversion section 12 Transfer transistor 13 First charge storage section 13a Capacitor 14 Reset transistor 15 Amplifier transistor 16 Selection transistor 17 Second charge storage section 17a Capacitor 17b Capacitor 17c Capacitor 18 Switching transistor 20 Substrate 20A Second substrate 20a Insulating film 21 Power line 22 Pixel separation section 23 Ground line 23A Ground line 24 Power line 25 AMP-SEL line 26 Signal line 30 Wiring layer 30A Second wiring layer 30a Junction 30b Junction 31 Insulating layer 31a Stopper layer 31b Oxide film 32 Wiring 32a Connection line 32b Connection line 32c Connection 32d Connection 33 Control line 33a Wiring 34 Reference potential line 34a Wiring 35 First capacitance wiring 36 Shield wiring 36a Shield film 36b Insulating film 36c Conductor 37 Second capacitance wiring 37a Insulating film 37b Conductor 38 Shield wiring 38a Shield film 38b Insulating film 38c Conductor 40 Logic board 41 Insulating layer 42 Shield layer 43 Reference potential line 44 Power line 101 Light detection device 102 Pixel 103 Pixel section 104 Vertical drive circuit 105 Column signal processing circuit 106 Horizontal drive circuit 107 Output circuit 108 Control circuit 109 Vertical signal line 110 Horizontal signal line 111 Semiconductor substrate 112 Input / output terminals H1 Hole H1a Connection hole H2 Hole H2a Hole V1 Via V2 Via V3 Via V4 Via

Claims

1. A photodetector comprising: a substrate; an insulating layer laminated on the substrate; a photoelectric conversion unit provided on the substrate that generates electric charge by photoelectric conversion; and a shield wiring provided on the insulating layer and extending in the thickness direction of the insulating layer, wherein the shield wiring includes a shield film extending in the thickness direction.

2. The light detection device according to claim 1, wherein the shielded wiring includes capacitance.

3. The light detection device according to claim 1, wherein the shielded wiring is electrically connected to the wiring capacitance.

4. The photodetector according to claim 1, wherein the shielded wiring is electrically connected to a plurality of wiring capacitances.

5. The photodetector according to claim 1, further comprising a charge storage unit provided on the substrate for storing the charge, wherein the shield wiring is electrically connected to the charge storage unit.

6. The photodetector according to claim 5, wherein a plurality of charge storage units are provided, and the shield wiring is electrically connected to any of the plurality of charge storage units.

7. The photodetector according to claim 5, wherein the shield wiring includes an insulating film and a conductor that are respectively extended in the thickness direction, and the shield film and the conductor are provided via the insulating film.

8. The photodetector according to claim 7, wherein the shielding film is not in contact with the charge storage portion, and the conductor is in contact with the charge storage portion.

9. The photodetector according to claim 8, wherein the length of the shielding film in the thickness direction is shorter than the length of one or both of the insulating film and the conductor in the thickness direction.

10. The photodetector according to claim 7, further comprising a first capacitance wiring provided in the insulating layer, wherein the conductor is electrically connected to the first capacitance wiring.

11. The photodetector according to claim 10, wherein the shielding film is not in contact with the first capacitance wiring, and the conductor is in contact with the first capacitance wiring.

12. The photodetector according to claim 10, further comprising a reference potential line provided in the insulating layer, wherein the reference potential line is provided between the first capacitance wiring and the charge storage unit, and on the side of the first capacitance wiring.

13. The photodetector according to claim 12, wherein the shield wiring penetrates the reference potential line, the shield film is in contact with the reference potential line, and the conductor is not in contact with the reference potential line.

14. The photodetector according to claim 10, further comprising a reference potential line provided in the insulating layer, wherein the reference potential line is provided on the side opposite to the charge storage portion in the first capacitance wiring.

15. The photodetector according to claim 10, further comprising a second capacitance wiring provided in the insulating layer and extending in the thickness direction, wherein the conductor is electrically connected to the second capacitance wiring via the first capacitance wiring.

16. The photodetector according to claim 7, further comprising: a second substrate laminated on the insulating layer; and a shield layer provided on the second substrate, wherein the shield wiring penetrates the shield layer, the shield film is in contact with the shield layer, and the conductor is not in contact with the shield layer.

17. The photodetector according to claim 7, further comprising a shield layer provided on the insulating layer, wherein the shield wiring penetrates the shield layer, the shield film is in contact with the shield layer, and the conductor is not in contact with the shield layer.

18. The photodetector according to claim 1, further comprising a transistor provided in the insulating layer, wherein the shielding wiring is connected to the gate of the transistor, and the gate potential of the transistor is the same as the source potential of the transistor.

19. The photodetector according to claim 17, wherein the shield wiring includes an insulating film and a conductor that are respectively stretched in the thickness direction, the shield film and the conductor are provided via the insulating film, and the insulating film is formed of a low dielectric constant material.

20. An electronic device comprising a light detection device, the light detection device comprising: a substrate; an insulating layer laminated on the substrate; a photoelectric conversion unit provided on the substrate and generating an electric charge by photoelectric conversion; and a shield wiring provided on the insulating layer and extending in the thickness direction of the insulating layer, wherein the shield wiring includes a shield film extending in the thickness direction.

Images