Epitaxial superlattice structure
By forming film stacks with varying dopant concentrations and germanium content, the method addresses wafer bowing issues in 3D DRAM devices, ensuring stable film stacks and efficient manufacturing processes.
WO2026101868A1 Publication Date: 2026-05-15APPLIED MATERIALS INC
5 Cites 0 Cited by
Patent Information
- Application Number
- PCT/US2025/053886
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-10-30
- Filing Date
- 2025-11-04
- Publication Date
- 2026-05-15
AI Technical Summary
Technical Problem
The challenge in manufacturing 3D DRAM devices is the control of stress and epitaxial defects due to lattice mismatch between silicon and germanium layers, leading to wafer bowing that hinders subsequent processes, and current stress relief methods are inadequate.
Method used
A method involving the formation of film stacks with varying dopant concentrations and germanium content, including silicon channel layers, doped silicon layers, and sacrificial layers, to modulate stress and reduce wafer bowing.
Benefits of technology
The method achieves reduced or neutral wafer bowing, enabling accurate lithography and reducing process complexity and costs by stabilizing the film stacks.
✦ Generated by Eureka AI based on patent content.
Abstract
Methods of reducing wafer bowing in 3D DRAM devices are described using stacks including one or more of epitaxial silicon (Si), carbon doped silicon (SiC), silicon germanium (SiGe), and carbon-doped silicon germanium (SiGeC). A plurality of film stacks is formed on a substrate surface, each of the film stacks comprises two doped silicon layers having different dopant amounts and a sacrificial layer that may be doped or undoped. 3D DRAM devices are also described.
Need to check novelty before this filing date? Find Prior Art