Integration of compound semiconductor thin film structures on large-diameter substrates with wafer bonding and substrate removal

Abstract

The present invention provides scalable manufacturing approaches to add compound semiconductor (CS) materials and devices to large-diameter substrate platforms. The method includes forming a CS buffer layer overlying the large-diameter substrate wafer, then a stop etch layer, and finally a device layer structure for high carrier mobility, optical gain or absorption, or optical nonlinearity. This device wafer is then bonded, topside down, to a photonics substrate platform. The underlying substrate is removed with grinding, polishing, or etching processes. Some of the CS layers, including the buffer and the stop etch layer, may be removed thereby leaving only the final device layer. This final layer may be patterned to form waveguides or device structures; may be exposed to ion implantation steps to form p-n junctions; and may be subjected to other common fabrication steps to form devices. These device structures may also be encapsulated and addressed through top-level metal contacts and vias.

Description

PATENTAttorney Docket No.: 988R00014PCINTEGRATION OF COMPOUND SEMICONDUCTOR THIN FIEM STRUCTURES ON LARGE-DIAMETER SUBSTRATES WITH WAFER BONDING AND SUBSTRATE REMOVALCROSS-REFERENCES TO RELATED APPLICATIONS

[0001] The present application claims priority to and incorporates by reference, for all purposes, the following pending patent application: U.S. Pat. App. No. 63 / 717,083, filed November 06, 2024.BACKGROUND OF THE INVENTION

[0002] Existing integrated circuit (IC) platforms form circuit elements on silicon (Si) wafers, including silicon-on-insulator (SOI) wafers comprising a thick Si substrate plus a thin Si device layer that is separated from the substrate by a “buried oxide” layer of silicon dioxide (SiO2).Such IC platforms do not support any photonic devices, but may be assembled with co-packaged optics (CPO) formed on separate compound semiconductor (CS) or silicon photonics (SiPh) chiplets which provide functions such as optical interconnect. Existing SiPh platforms use Si or silicon nitride (SisN4) waveguides clad by SiCh; non-stoichiometric silicon nitride may also be used, but for simplicity, the chemical formula SLN4 is used here when either stoichiometric or non-stoichiometric silicon nitride is meant. Similar to some IC wafers, silicon waveguides are built on SOI wafers. After waveguide cores are etched from the Si device layer, they are generally clad by additional deposited SiO2. Silicon nitride waveguides are built from wafers of similar structure where the waveguide cores are formed from a deposited film of S13N4 rather than a Si device layer. Various SiPh platforms may employ multiple waveguide layers sandwiched between layers of planarized oxide or other dielectric, and may employ both Si and SiiN4 waveguide layers. They may also integrate germanium (Ge) or silicon-germanium (SiGe) layers from which photodiodes are formed. These various SiPh platforms support large-scale integration of photonic devices such as modulators, resonators, switches, detectors, and couplers, but owing to the fundamental material properties of Si, Si.iN4, SiCh, Ge, and SiGe, they cannot provide the efficient optical gain needed to directly integrate lasers and semiconductor optical amplifiers (SOAs). Those devices remain the purview of separate CS chips. The material setused by existing SiPh and IC platforms is likewise unsuitable for integrating efficient nonlinear optical devices.

[0003] Compound semiconductor materials like GaAs, Alo.i8Gao.82As, Ino.49Gao.51P, Ino.53Gao.47As, and Alo 85Gao.15Aso.56Sbo.44 formed from group-III elements gallium (Ga), aluminum (Al), and indium (In) in equal ratio to group-V elements phosphorus (P), arsenic (As), and antimony (Sb), are used in semiconductor optoelectronics to provide optical gain and absorption, and can provide strong nonlinear optical response as well. Some CS are also characterized by much higher carrier mobilities than can be achieved with Si or SiGe and are used in radio frequency (RF) electronics and magnetic sensors. CS optical gain media based on quantum well, quantum wire and quantum dot active structures may be integrated to form SOAs and lasers. CS optical absorption media may be integrated to form detectors including photodiodes and avalanche photodiodes (APDs). CS materials with strong nonlinear optical properties may be integrated to form wavelength converters, entangled photon sources, and highspeed low-loss modulators. CS materials with high carrier mobility may be integrated to form RF transistors and magnetic Hall effect sensors. Integration of these CS materials supports devices applicable to optical interconnects, sensing, RF electronics, and quantum information which cannot be made using existing SiPh or IC platforms.

[0004] Currently, CS films suitable for fabricating photonic or high-mobility devices are grown on substrates that are unavailable in diameters as large as the silicon and SOI substrates used by the silicon industry. Generally, these are native CS substrates made from GaAs, InP, or GaSb. The difference in substrate diameter is a barrier to using silicon industry tooling to efficiently integrate CS films onto SiPh or IC wafers.

[0005] From the above, it is desirable to improve integration of CS films with large-diameter substrates for silicon photonics and IC applications.BRIEF SUMMARY OF THE INVENTION

[0006] The present invention is generally related to electronic devices. More specifically, the present invention provides techniques related to high-mobility electronic devices and to optoelectronic devices employing optical gain, optical absorption, or strong nonlinear optical response, integrated with silicon electronics (SiE) or silicon photonics (SiPh) using heteroepitaxy of compound semiconductor (CS) materials on silicon and other large-diameter substrates, alongwith subsequent wafer fabrication and integration methods. Example high-mobility devices that can be integrated in this manner include, but are not limited to, transistors for radio frequency (RF) electronics and magnetic Hall effect sensors. Example optoelectronic devices that can be integrated in this manner include, but are not limited to, lasers, semiconductor optical amplifiers (SOAs), photodiodes, avalanche photodiodes (APDs), electro-optic modulators, wavelength converters, and entangled photon sources. Merely by way of example, the present invention can be applied to various applications including RF power amplification, magnetic sensing, optical interconnect, image sensing (including lidar), quantum computing and cryptography, among others, but it will be recognized that there are many other applications.

[0007] According to an example, the present invention includes a method of integrating high- performance CS materials on large-diameter substrate platforms for high-mobility, optical gain, optical absorption, and / or nonlinear optical functionality, as well as the resulting device configurations. This method includes depositing CS films on large-diameter substrates such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs), transferring the CS film to a SiE or SiPh wafer of the same diameter, and then removing the large-diameter substrate that initially carried the CS film. Currently, Si is commonly available as 200- or 300-mm substrates; Ge as 200- or 300-mm; and GaAs as 200-mm, however, 300-mm GaAs may become available in the future.

[0008] The integration method begins with deposition of a CS buffer layer overlying the large- diameter substrate, then includes deposition of a CS etch stop layer, a CS device layer, and finally a dielectric passivation layer suitable for direct or hybrid wafer bonding. The composition, structure, and method of preparation of the CS buffer layer is such as to accommodate any difference between the crystal lattice of the large-diameter substrate and the overlying CS etch stop and device layers, ensuring those overlying layers are formed with low density of crystal defects and with smooth morphology. The composition of the CS etch stop layer is chosen to facilitate removal of the buffer layer and large-diameter substrate during a later manufacturing step. In an example, the etch stop layer may be both resistant to particular etches that attack buffer and / or substrate, yet also susceptible to certain other etches to which the CS device layer is resistant. The CS device layer itself is structured to provide either high charge carrier mobility or optoelectronic functionality such as optical gain, optical absorption, or a strong nonlinear optical response. This CS-bearing wafer is then bonded dielectric passivation- side-down to the top surface of a SiE or SiPh wafer which has been prepared with a compatibledielectric surface. The SiE or SiPh wafer may have a silicon-on-insulator (SOI) structure, or the SiPh wafer may incorporate silicon nitride (SiaNT) waveguide layers. The substrate of the CS- bearing wafer is removed by grinding, chemical mechanical polishing, and / or chemical etching. The CS buffer and etch stop layers may also be removed, thereby leaving only the CS device layer attached to the top surface of the SiE or SiPh wafer by a direct or hybrid wafter bond.

[0009] According to a variation of the integration method, at least the device layer of the CS- bearing wafer may be patterned into raised islands by removing the surrounding material, and complementary recessed pockets may be patterned in the dielectric surface of the SiE or SiPh wafer to receive those islands, such that following wafer bonding and substrate removal, sections of the CS device layer originally patterned into islands on the CS-bearing wafer are transferred into pockets formed on the SiE or SiPh wafer. In an embodiment of this method, the structure of the SiPh wafer and the depth of the recess in its surface dielectric are chosen so that once the CS device layer has been transferred into the recess, its alignment to structures in the SiPh wafer facilitates efficient optical coupling between SiPh and CS components.

[0010] To form devices, the CS device layer transferred to the SiE or SiPh wafer may be patterned to form waveguides, gratings, mesa-isolated diodes, or other device structures; may be exposed to dopant diffusion or ion implantation steps to form p-n junctions or regions of increased or reduced carrier concentration; may have additional metal or dielectric layers deposited on it; and may be subjected to other common fabrication steps like thermal annealing and planarization. The resulting CS devices may interface electrically to integrated circuits formed in a SiE wafer through filled vias and may interface optically to photonic integrated circuits formed in a SiPh wafer through evanescent coupling between waveguides or the use of grating couplers, etc.

[0011] Many benefits or advantages are achieved over conventional techniques. For example, embodiments of the present invention provide scalable manufacturing approaches to directly integrate CS materials and devices with SiE or SiPh devices on the same chip, as opposed to providing those functions in separate co-packaged chiplets. A further advantage is that CS integration with SiE or SiPh wafers is accomplished by a single wafer-wafer bonding operation as opposed to multiple die or coupon hybridization steps. It is anticipated that the invention can be widely and cost-effectively applied as all deposition, bonding, and fabrication steps may be carried out using scalable manufacturing processes commonly practiced by the siliconmicroelectronics industry. These and other benefits or advantages are described throughout the present specification and more particularly below.

[0012] A further understanding of the nature and advantages of the invention may be realized by reference to the latter portions of the specification and attached drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to better understand the present invention, reference is made to the accompanying drawings. Understanding that these drawings are not to be considered limitations in the scope of the invention, the presently described embodiments and the presently understood best mode of the invention are described with additional detail through use of the accompanying drawings in which:

[0014] FIG. 1 is a simplified diagram of a device including CS buffer materials on a Si substrate realized by heteroepitaxy according to an example of the present invention;

[0015] FIG. l is a simplified diagram of a device including CS buffer materials and CS device materials for a photodetector on a Si substrate realized by heteroepitaxy according to an example of the present invention;

[0016] FIGs. 3A-3E are simplified diagrams illustrating a method of forming a template wafer device according to an example of the present invention.

[0017] FIGs. 4A-4F are simplified diagrams illustrating cross-sectional views of a method of manufacturing an integrated compound semiconductor (CS) device according to an example of the present invention.

[0018] FIGs. 5A-5F are simplified diagrams illustrating cross-sectional views of a method of manufacturing an integrated CS device according to an example of the present invention.

[0019] FIG. 6 is a simplified diagram illustrating a cross-sectional view of an integrated CS system according to an example of the present invention.

[0020] FIG. 7A-7C are simplified diagrams illustrating cross-sectional views of a method of manufacturing a CS device using alternative template wafers and handle wafers according to examples of the present invention.

[0021] FIGs. 8A-8C are simplified diagrams illustrating cross-sectional views of a method of manufacturing a CS device wafer according to an example of the present invention.

[0022] FIGs. 9A-9E are simplified diagrams illustrating cross-sectional views of a method of manufacturing a photonics wafer according to an example of the present invention.

[0023] FIGs. 10A-10C are simplified diagrams illustrating cross-sectional views of a method of manufacturing an integrated CS photonics device according to an example of the present invention.

[0024] FIGs. 11A and 11B are simplified diagrams illustrating cross-sectional views of integrated CS photonics device wafers according to examples of the present invention.

[0025] FIGs. 12A-12C are simplified diagrams illustrating top views of a method of forming a PIN device on an integrated photonics wafer according to an example of the present invention.

[0026] FIGs. 13A-13C are simplified diagrams illustrating cross-sectional views of a method of preparing a silicon electronics (SiE) wafer for integration with one or more CS devices according to an example of the present invention.

[0027] FIGs. 14A-14D are simplified diagrams illustrating cross-sectional views of a method of integrating vertically-coupled CS lasers and detectors with transceiver circuitry implemented in a SiE platform according to an example of the present invention.

[0028] FIG. 15 is a simplified block diagram illustrating an integrated electronic-photonic system according to an example of the present invention.DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention is generally related to electronic devices. More specifically, the present invention provides techniques related to high-mobility electronic devices and to optoelectronic devices employing optical gain, optical absorption, or strong nonlinear optical response, integrated with silicon electronics (SiE) or silicon photonics (SiPh) using heteroepitaxy of compound semiconductor (CS) materials on silicon and other large-diameter substrates, along with subsequent wafer fabrication and integration methods. Example high-mobility devices that can be integrated in this manner include, but are not limited to, transistors for radio frequency (RF) electronics and magnetic Hall effect sensors. Example optoelectronic devices that can beintegrated in this manner include, but are not limited to, lasers, semiconductor optical amplifiers (SOAs), photodiodes, avalanche photodiodes (APDs), electro-optic modulators, wavelength converters, and entangled photon sources. Merely by way of example, the present invention can be applied to various applications including RF power amplification, magnetic sensing, optical interconnect, image sensing (including lidar), quantum computing and cryptography, among others, but it will be recognized that there are many other applications.

[0030] In various examples, the present invention provides scalable and highly manufacturable methods and devices for realizing lasers, semiconductor optical amplifiers (SOAs), or entangled photon sources integrated with SiPh, and arrays of vertically-coupled optical interconnects integrated with SiE. By directly depositing CS materials on Si substrates, mature Si microelectronics manufacturing processes can be leveraged to fabricate high performance photonic integrated circuits and optical transceivers. Deposition on 200- and 300-mm Si substrates, which are common for complementary metal-oxide-semiconductor (CMOS) technologies, enables subsequent fabrication in CMOS manufacturing lines. However, the technology is not limited to Si substrates or these wafer diameters only.

[0031] Layered deposition of dissimilar materials, including CS materials on silicon, is referred to herein as heteroepitaxy. A heteroepitaxy step or steps may be carried out with techniques including, but not limited to, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), metalorganic MBE (MOMBE), chemical beam epitaxy (CBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), or any combination thereof.

[0032] In addition to Si substrates, alternative substrates may be used including, but not limited to, silicon-on-insulator (SOI), miscut Si, SOI on miscut Si, germanium (Ge)-on-Si, Ge, or gallium arsenide (GaAs) substrates, without departing from the scope of the invention.

[0033] In the figures, shared reference numerals in subsequent figures refer to the same elements as described in previous figures. FIG. 1 is a simplified diagram of a CS template 100 including CS buffer materials on a Si substrate realized by heteroepitaxy according to an example of the present invention. In this embodiment, a CS buffer layer 120 is deposited overlying a surface region 111 of a Si substrate 110 in order to nucleate the CS material 120 and to trap and / or filter defects within the buffer material 120 and near the interface between the CS material 120 and Si surface 111. Additional CS layers may be heteroepitaxially grown on the template 100.

[0034] FIG. 2 is a diagram of a CS-bearing wafer 200 prepared from CS template 100 by growing additional layers. The CS-bearing wafer 200 comprises a large-diameter substrate 110, on which a CS buffer 120, CS etch stop 210, and CS device layer 220 are grown by heteroepitaxy. A further dielectric passivation layer 230 is deposited on top of the CS layers and planarized.

[0035] In an embodiment of the present invention, CS material is deposited onto a Si substrate 110 by heteroepitaxy, by firstly depositing a buffer material 120 that includes an initial nucleation on the Si surface and enables the trapping, annihilation, and / or filtering of defects near the interface between the CS material and the Si surface. The initial nucleation step may be carried out at a relatively low temperature, and the subsequent buffer material growth intended to trap, annihilate and / or filter defects may be carried out at a higher temperature. Surface treatment may be carried out prior to the initial nucleation on the Si surface. This treatment may include, but is not limited to, chemical cleaning and / or treatment of the Si surface, reordering of the Si surface with high-temperature annealing in an ambient atmosphere, high-temperature annealing in an ambient atmosphere to remove and / or treat a surface oxide, or the exposure of various Si crystal planes at the Si surface by treatment or etching.

[0036] The initial nucleation and buffer growth can be carried out with a number of methodologies, and combinations of methodologies, including, but not limited to, initial group IV (e.g., Si or Ge material) growth for surface reordering or reparation followed by CS growth for defect trapping, or Si surface patterning or structuring, that may include exposure of various Si crystal planes at the wafer surface, followed by CS nucleation and growth, or low-temperature CS nucleation, or low-temperature CS nucleation followed by multi-step growth with temperature grading for defect bending and annihilation, or use of strained layer superlattices (SLSs), interfaces with high strain fields, graded or step-graded layers, or other similar techniques to redirect, trap, convert, and / or annihilate defects.

[0037] The etch stop layer 210 grown above the buffer facilitates reliable and reproducible removal of the substrate 110 in a later manufacturing step. A typical substrate 110 is hundreds of microns thick but a typical CS buffer layer 120 is a few microns thick - around one percent of the substrate thickness. This makes removal of the substrate 110 without damaging the device layer 220 challenging, as physical processes capable of efficiently removing hundreds of microns of substrate can easily overshoot by a few microns. Moreover, substrate removal processes maybe subject to nonuniformity across the area of a wafer, such that a greater thickness is removed in some regions than in others, and it is impossible to remove all of the substrate across the wafer area without penetrating into the device layer in some regions. The composition and thickness of the etch stop layer 210 is chosen so that a chemically-selective etch may be employed to avoid overshoot or incomplete removal of the substrate 110. In one embodiment, the substrate 110 is made from Si, the buffer 120 is made from GaAs and various compositions of Inx-iGaxAs, the etch stop 210 is made from Alo.s Gao.2As, the device layer 220 is made from GaAs, and the SiE or SiPh wafer to which the CS-bearing wafer will be bonded is coated in SiCh. The etch stop 210 of this embodiment is designed for the following process sequence that takes place later in the manufacturing process. After grinding down the Si substrate 110 to the minimum thickness that can be controlled, the remaining Si can be removed by an etchant such as tetramethylammonium hydroxide (TMAH) which readily attacks Si but does not etch SiO2 or GaAs at appreciable rates. The GaAs / InGaAs buffer 120 can then be stripped from the Al0.sGa0.2As etch stop 210 using an etchant such as 4: 1 citric acid:H2O2 that etches high-aluminum-content AlGaAs much more slowly than GaAs or TnGaAs, and does not attack SiCh; the thickness of the etch stop layer 210 is chosen based on the selectivity of the etch that removes the buffer 120 to ensure no overshoot. Lastly, an AlGaAs-selective etchant such as chilled HC1 that does not attack GaAs or SiCh is used to remove the etch stop 210 itself, leaving the CS device layer 220 attached to the SiE or SiPh wafer.

[0038] The buffer 120 and the device layer 220 can also effectively function as etch stops. For example, the method can include etching silicon with TMAH and stopping on the GaAs / InGaAs buffer, then stripping the GaAs / InGaAs buffer in citric acid / peroxide that stops on an AlGaAs etch stop, and then finally stripping the AlGaAs etch stop using chilled HC1 and stopping on a GaAs device layer. In cases that the buffer 120 is chemically similar to the device layer 220, an extra etch stop 210 that is different from the buffer and device layer chemistry is required to remove the buffer 120. However, the present invention also includes embodiments in which the buffer 120 serves as an etch stop. In this case, there is enough chemical difference between the buffer 120 and device layer 220 such that removal of the buffer 120 is possible without a separate etch stop.

[0039] In another example, silicon materials can be stripped using dry etch chemistry based on fluorine, such as a "Bosch" etch process that uses SFe alternating with a fluorocarbon like C4F6, or a process based on XeF2. In such cases, the fluorine dry etches will generally stop of eitherindium- or aluminum-containing compounds, and may be configured to stop on certain Ga- containing compounds. For example, either of these dry etches can be used to strip off silicon substrate remnants and terminate on a buffer that contains InGaAs, assuming the indium concentration was high enough in the alloy used in the buffer. Thus, fluorine dry etches followed by wet chemistry can also be used to remove what remains of the buffer and etch stop.

[0040] As discussed previously, the etch stop layer facilitates reliable removal of substrate and buffer layers during subsequent manufacturing steps. The composition of the etch stop layer can be selected to contrast chemically with at least the substrate and device layers in such a way that at least one etch process proceeds at least ten times faster through the substrate than through the etch stop (i.e., chemically resistant to etch processes of the substrate and / or buffer layers) and at least one etch process proceeds at least ten times faster through the etch stop than through the device layer. For example, the etch stop composition can include chemical contrasts between silicon or germanium substrates which are readily etched by fluorine-based dry etches and aluminum- or indium-containing CS materials which are not; between aluminum-free arsenide CS materials which are readily etched by citric acid / peroxide wet etches and aluminum- containing arsenide CS materials which are not; between arsenide CS materials which are readily etched by phosphoric acid / peroxide wet etches and phosphide CS materials which are not; as well as other such material pairings and etch chemistries familiar to one of ordinary skill in the art.

[0041] The CS device layer 220 is structured so that various high-mobility or optoelectronic devices may be formed from it for integration with SiE or SiPh circuitry. In various embodiments, these CS devices include, but are not limited to, high-mobility devices such as transistors and Hall effect sensors; conventional photonic devices such as lasers, semiconductor optical amplifiers (SOAs), modulators, and photodetectors; and nonlinear optical devices for entangled photon generation or optical frequency comb generation. Specific integrated structures that can be formed by the methods of this invention include, but are not limited to, CS distributed feedback (DFB) laser sources and SOAs integrated with SiPh transceivers and switches; CS vertical-cavity surface-emitting lasers (VCSELs) and vertically-illuminated photodiodes integrated with SiE transceiver electronics; and CS waveguide spontaneous parametric downconversion sources integrated with quantum information-processing photonic integrated circuitry implemented in SiPh.

[0042] In an example, the CS device layer 220 is structured to efficiently generate optical gain with a sequence of layers that are set within a forward-biased p / n junction. The layers are differentiated with respect to band gap, particularly by the energies of their respective conduction and valence band edges relative to the vacuum, which together form a heterostructure with a spatially-varying potential that confines carriers injected by the forward-bias current of the junction to an active region within the confining heterostructure that further contains gain structures such as quantum wells, quantum wires, or quantum dots inside which direct crystal momentum-conserving optical dipole transitions between conduction and valence band states can readily occur without participation of phonons in the transition. The gain structures are further characterized by carrier-confining potential wells in at least one spatial direction and a corresponding reduction of the density of electronic states compared to bulk semiconductor material that reduces the electrical current which must be supplied to the junction to generate a population inversion within the active region.

[0043] In an example, the CS device layer 220 is structured to efficiently generate current from light by a configuration in which optical signals of wavelengths within a desired waveband that are incident on the structure can reach a light-sensing region within the structure without attenuation by more than 50% of the incident signal power. The light-sensing region is a structure such as a photoconductive channel or photodiode junction, including p / n junctions, heterojunctions, Schottky junctions, and nBn or other barrier diode junctions, that is of variable electrical conductivity that depends on the charge carrier concentration within the photoconductive channel or photodiode junction. This region includes at least, in part, a material that generates mobile electrons and holes by absorbing light within the desired waveband of the optical signal. Further, the structure is physically configured so that at least 50% of the optical power that reaches the light-sensing region is absorbed within one minority carrier diffusion length of the photodiode junction, photoconductive channel, or other variable-conductivity lightsensing structure.

[0044] In an example, the CS device layer 220 is structured to mix optical wave frequencies by including at least, in part, materials with second-order nonlinear susceptibility exceeding 100 pm / V at desired optical signal wavelengths and organized into optical phase-matching structures such as waveguides, resonators, or photonic crystals.

[0045] In an example, the CS device layer 220 is structured to transport electrons or holes with high mobility by including a high-mobility channel composed of a material with bulk roomtemperature electron mobility exceeding 4000 cm2 / V-s. Such channels are formed with the smoothest possible layer interfaces, the lowest possible density of defects in its crystal lattice, and are physically separated from space charge associated with intentionally doped regions of the semiconductor structure. The channels can also be configured according to heterostructure channel designs in which a two-dimensional electron gas is confined in a potential well that separates it from the nearby ionized dopants that populated the gas.

[0046] In an embodiment, the dielectric surface passivation layer 230 is composed of SiC>2 that has been planarized in preparation for oxide-oxide direct bonding to a SiE or SiPh wafer. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives.

[0047] FIGs. 3A to 3E are simplified diagrams illustrating a method of forming a template wafer device (devices 301 to 305) according to an example of the present invention. The method steps illustrated in these figures can be combined with any method steps discussed previously for forming a photodetector device. Further, the same numerals across these figures refer to the same elements, regions, configurations, etc.

[0048] In an example, the present method begins by providing a large silicon substrate 310, as shown in FIG. 3A. The silicon substrate 310 has a diameter of about two inches to about twelve inches. In an example, the surface of the silicon substrate is cleaned to remove any native oxide material. The substrate is cleaned using a high temperature environment including hydrogen or other suitable species. In an example, the method includes forming a plurality of v-grooves 311, as shown in FIG. 3B, each of which can have a feature size of 30 to 500 nanometers in width. In an example, each of the v-grooves exposes { 111 } crystalline planes of the silicon substrate. The plurality of grooves 311 are commonly formed using an etchant such as potassium hydroxide (KOH) and tetramethyl ammonium hydroxide (TMAH), or other suitable etchants.

[0049] In an example, the method includes forming a nucleation layer 320 comprising a gallium arsenide material to coat a surface region of the silicon substrate 310, as shown in FIG. 3C. The nucleation layer 320 has a thickness ranging from 10 nm to 100 nm, but can be others.

[0050] In an example, the method includes forming a buffer material 330 comprising a plurality of nanowires formed overlying each of the plurality of grooves and extending along alength of each of the v-grooves, as shown in FIG. 3D. The buffer material 330 includes a first transitionary region 331 extending from each of the plurality of nanowires, and a second transitionary region 332 characterized by a { 100} -oriented crystalline planar growth of a gallium arsenide compound semiconductor (CS) material configured using a direct heteroepitaxy such that the CS material is characterized by a first bandgap characteristic, a first thermal characteristic, a first polarity, and a first crystalline characteristic, and the silicon substrate 310 is characterized by a second bandgap characteristic, a second thermal characteristic, a second polarity, and a second crystalline characteristic.

[0051] In an example, the buffer material further comprises a gallium arsenide containing material and an indium phosphide containing transitionary region (e g., InGaAs, or the like) and an interface region comprising a trapping layer comprising indium gallium arsenide and indium phosphide overlying the gallium arsenide containing material and indium phosphide containing transitionary region. In a specific example, the transitionary region can be closer to GaAs at the start and can be closer to InP towards an InP graded region.

[0052] In an example, the method also includes forming one or more device material layers overlying the buffer material 330, such as a n-type material layer 340 shown in FIG. 3E. The device materials can include photodetector device materials, such as those discussed previously. As such, these method steps for forming the v-groove patterned substrate can be combined with any method steps for optoelectronic and sensor devices discussed herein.

[0053] FIGs. 4A-4F are simplified diagrams illustrating cross-sectional views of a method of integrating a CS device layer with a SiE or SiPh wafer according to an example of the present invention. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One of ordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0054] As shown in FIG. 4A, the method includes a step 401 in which a CS device wafer is coupled to a SiE or SiPh wafer 450 using a wafer-to-wafer bonding process. Here, the CS device wafer includes a template wafer 410 having at least a substrate layer 412 with an overlying CS buffer layer 414. Depending on the application, different combinations of substrate and buffermaterials may be used, and the substrate may be pretreated prior to growth of the buffer. In a specific example, the substrate layer 412 can include a Si substrate, a Ge substrate, a GaAs substrate, and the like. Pretreatment of the substrate can include chemical cleaning and / or treatment of the substrate surface, reordering of the substrate surface with high-temperature annealing in an ambient atmosphere, high-temperature annealing in an ambient atmosphere to remove and / or treat a surface oxide, or the exposure of various crystal planes at the substrate surface by treatment or etching. The CS buffer layer can include a nucleation layer and structures that promote annihilation or trapping of defects. In other cases, a template wafer 410 can have a single material layer (see FIG. 8B) or additional layers, and there can also be additional buffer layers (see FIG. 8A). The CS device wafer also includes a CS etch stop layer 420 formed overlying the template wafer 410, a CS device layer 430 formed overlying the etch stop layer 420, and a dielectric passivation layer 440 overlying the CS device layer 430.

[0055] The SiE or SiPh wafer 450 includes a device layer 452 in which electronic or photonic devices can be formed and a dielectric layer 454 overlying the device layer 452. The device layer 452 can be structured as a silicon-on-insulator (SOI) wafer, or may be made from other materials in other configurations. In a specific example, this wafer 450 is configured as a SiE wafer 452 from which electronic circuitry can be fabricated and its dielectric layer 454 is planarized SiO2. In another specific example, this wafer 450 is configured as a SiPh wafer from which photonic integrated circuits can be fabricated and its dielectric layer 454 is planarized SiO2. In this method step 401, the CS device wafer is bonded, topside down, to the SiE or SiPh wafer 450. The resulting wafer 402 integrating a CS device layer with a SiE or SiPh wafer is shown in FIG. 4B.

[0056] Then, the method also includes subjecting the template wafer 410 to a substrate removal process, resulting in the device 403 shown in FIG. 4C. The substrate removal process can include a grinding process, a chemical mechanical polishing process, a chemical etching process, and the like. In this process, some of the CS layers, including the buffer layer 414 and the etch stop layer 420, may be removed thereby leaving only the CS device layer 430 overlying the dielectric passivation layer 440 from the original CS device wafer, the dielectric layer 454 from the SiE or SiPh wafer 450, and the device layer 452 of the SiE or SiPh wafer 450.

[0057] Following the substrate removal process, the CS device layer 430 may be subjected to various device forming processes, such as patterning to form waveguides, gratings, mesa-isolated diodes, or other device structures; dopant diffusion or ion implantation to form p-n junctions orregions of increased or reduced carrier concentration; deposition of additional metal or dielectric layers; and other common fabrication steps like thermal annealing and planarization. The resulting CS devices may interface electrically to integrated circuits formed in a SiE wafer through filled vias and may interface optically to photonic integrated circuits formed in a SiPh wafer through evanescent coupling between waveguides or the use of grating couplers, etc.

[0058] In a specific example, device layer 430 can be configured for optical gain by using CS alloys including indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum gallium arsenide (InAlGaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), indium gallium phosphide (InGaP), GaAs, InP, and related materials. Optical gain devices could leverage bulk, quantum well, quantum wire, or quantum dot active regions as well. Further, the device layer 430 may be used to realize laser and gain devices such as SOAs, Fabry-Perot lasers, distributed Bragg reflector (DBR) lasers, distributed feedback (DFB) lasers, sampled grating DBR (SGDBR) lasers, ring resonator based lasers, and the like.

[0059] In a specific example, the device layer 430 can be configured for optical nonlinearity by using materials such as AlGaAs, InGaP, and the like. The optical nonlinear devices may include those such as microring resonators for entangled-photon pair generation, end-fire and gratingbased chip-to-fiber couplers, thermo-optically tunable interferometers for filtering and demultiplexing, over-coupled resonators and photonic molecules for squeezed light generation, waveguide spirals for propagation loss and non-resonant entangled-pair generation, and the like.

[0060] The device 404 of FIG. 4D shows the device layer 430 after patterned etching using a mask layer 460. In an example, a CS waveguide core incorporating optical gain or strong nonlinear response has been formed but is not yet clad. The device structures may subsequently be covered with additional dielectric cladding (e.g., SiOz) and electrically contacted from metal pads on the surface of the device through filled vias. FIG. 4E shows the device 405 with the encapsulation material 462 formed overlying the CS device material 430. And FIG. 4F shows the device 406 with metal contacts 470 formed overlying the encapsulation material 462.

[0061] The high-mobility and optoelectronic devices realized by deposition of CS materials on Si and integration with SiE or SiPh circuits can be leveraged in various applications, including, but not limited to, RF power amplification for microwave communications and radar; magnetic proximity and orientation sensing; optical data transmission for chip-to-chip, chip-to-board, andboard-to-board interconnect; optical and quantum information processing; and lidar and infrared imaging for autonomous navigation and advanced driver assistance systems (ADAS), machine vision, industrial inspection, augmented and virtual reality (AR / VR), and military sensing.

[0062] In addition to the group III-V CS materials, the techniques of the present invention could apply to other CS alloy systems including, but not limited to, II- VI compounds, IV-VI compounds, II- V compounds, or lV-IV compounds.

[0063] Many benefits or advantages are achieved over conventional techniques. For example, embodiments of the present invention provide scalable manufacturing approaches to add CS materials and devices to large-diameter substrate platforms such as 200- and 300-mm SiPh wafers through epitaxial film deposition, wafer bonding, substrate removal, and common semiconductor manufacturing steps. More specifically, growing CS films on large-diameter substrates supports manufacturing efficiency because the resulting wafers can be handled using silicon industry standard tooling and film transfer to silicon wafers can be done one-to-one because the donor wafer and receiving wafer match in size. Also, transferring CS films to large- diameter silicon photonics wafers is an efficient way to integrate light-emitting, light-detecting, and nonlinear optical functionality rather than performing these functions on separately manufactured chips. Further, all deposition, bonding, and fabrication steps may be carried out using scalable, Si microelectronics manufacturing processes. Other examples exhibiting such benefits or advantages are discussed with respect to the subsequent figures.

[0064] FIGs. 5A-5F are simplified diagrams illustrating cross-sectional views of a method of manufacturing an integrated CS device according to an example of the present invention. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One of ordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0065] As shown in FIG. 5A, the method includes a step in which a substrate platform 500 is coupled to a device wafer 501 using a wafer-to-wafer bonding process. Here, the substrate platform 500 includes a silicon (Si) substrate 510 with an overlying dielectric layer 520 (e.g., silicon dioxide [SiCh], and the like). In a specific example, the substrate platform 500 is formedby a thermal oxidation process or a dielectric deposition process on the Si substrate (i.e., handle wafer).

[0066] The device wafer 500 includes a device layer 550 overlying a template wafer, which includes a compound semiconductor (CS) buffer layer 540 overlying a substrate layer 530. As discussed previously, the device layer 550 can include III-V CS materials deposited on the template wafer, and the template wafer can include various combinations of substrates and buffer materials. In a specific example, the substrate layer 530 is a gallium arsenide (GaAs) substrate layer, the buffer layer 540 is an aluminum gallium arsenide (Al GaAs) buffer layer (e.g., Alo.8Gao.2As), and the device layer 550 is an indium gallium phosphate (InGaP) device layer (e.g., Ino.49Gao.51P).

[0067] Similar to the previous example method, the device wafer 501 is coupled, topside down, to the substrate platform 500 (i.e., hybridization via wafer-to-wafer bonding), resulting in device 502 shown in FIG. 5B. Then the method includes subjecting the template wafer to a removal process (i.e., backside removal), resulting in device 503 shown in FIG. 5C. And then, in FIG. 5D, the device layer 550 is subjected to device forming processes.

[0068] Here, the device layer 550 is patterned to form one or more waveguides and / or photonic devices using a mask layer 560. Then, in FIG. 5E, a cladding material 522 is formed overlying and encapsulating the patterned device layer 550. Afterwards, a metal layer is formed overlying the cladding material 522 and then patterned to form a resistive heater 570 overlying the waveguide / photonics device. In a specific example, the resistive heater 570 includes compatible metal materials such as titanium (Ti), platinum (Pt), and the like. Of course, there can be other variations, modifications, and alternatives.

[0069] FIG. 6 is a simplified diagram illustrating a cross-sectional view of an integrated CS system according to an example of the present invention. As shown, the system 600 includes several different devices integrated on the same silicon substrate 610, all of which can be formed within the thermal oxide layer 620 by similar device forming processes as discussed previously.

[0070] Here, the first device on the left is a low-loss phase shifter device 630 (e.g., silicon nitride [SiN] phase shifter), which includes a heater element 632 coupled to metal contacts and overlying a SiN layer 634, which is also configured overlying a silicon-on-insulator (SOI) layer 636. And the second device is a quantum dot (QD) emitter device 640, which includes anintegrated gain device 642 coupled to metal contacts and having a selective growth of quantum dots 644 (e.g., InAs quantum dots, and the like).

[0071] The third device is another nonlinear III-V device 650 (e g., indium gallium phosphide- on-insulator [InGaPOI] device). This device 650 includes an integrated source layer 652 coupled to metal contacts. This integrated source layer 652 can include a nonlinear InGaP material, a nonlinear aluminum gallium arsenide (AlGaAs) material, or other similar nonlinear CS material. And the fourth device is a photodiode device 660 (e.g., germanium [Ge] photodiode), which includes a photodiode device layer 662 overlying a SOI layer 664.

[0072] The fifth, sixth, and seventh device structures include a grating coupler 670, a low-loss SOI layer 680, and an edge coupler 690, respectively, that are coupled together. In a specific example, this system 600 shows the integration of nonlinear III-V devices in 300mm SOI silicon photonics manufacturing process, but can implemented via other processes as well.

[0073] FIG. 7A-7C are simplified diagrams illustrating cross-sectional views of a method of manufacturing a CS device using alternative template wafers and handle wafers according to examples of the present invention. These figures show a wafer-to-wafer bonding step, which can be combined with any of the manufacturing methods discussed herein. Further, elements with the same reference numbers as past figures refer to the same elements and can include the same materials and configurations discussed previously.

[0074] In FIG. 7A, the device wafer is similar to that in FIG. 4 A except another buffer layer 712 is first formed overlying the template wafer 410. This buffer layer 712 can be including in a III-V material deposition process along with the etch stop layer 420 and the device layer 430. As discussed previously, this device wafer is coupled, topside down, to the substrate platform 450 in the method step 701.

[0075] In FIG. 7B, the device wafer is similar to that in FIG. 7A except the template wafer 720 is a single material layer (e.g., GaAs). Similarly, this device wafer is coupled, topside down, to the substrate platform 450 in the method step 702.

[0076] And in FIG. 7C, the device wafer is the same as in FIG. 7B, but the substrate platform 730 includes the additional layers of a handle substrate 732 with an overlying buried oxide (BOX) layer 734 that are configured underlying the SOI layer 452 and the dielectric layer 454.This device wafer is also coupled, topside down, to the substrate platform 730 in the method step 703. There can be other variations, modifications, and alternatives as well.

[0077] FIGs. 8A-8C are simplified diagrams illustrating cross-sectional views of a method of manufacturing a CS device wafer according to an example of the present invention. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One of ordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0078] In FIG. 8A, the method includes the step 801 of providing a template (or handle) wafer 810, which can include the materials and configurations discussed previously (e.g., CS buffer layer overlying a substrate layer). In FIG. 8B, the method includes the step 802 of forming an etch stop layer 820 overlying the template wafer 810 and then forming a device layer 830 (e.g., III-V device material layer configured for optical gain) overlying the etch stop layer 820.Similar to the previous example methods, the method includes the step 803 during which the device layer 830 can be subjected to different device forming processes (e.g., to form waveguides / silicon photonics devices), shown in FIG. 8C.

[0079] FIGs. 9A-9E are simplified diagrams illustrating cross-sectional views of a method of manufacturing a photonics wafer according to an example of the present invention. Elements with the same reference numbers as past figures refer to the same elements and can include the same materials and configurations discussed previously. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One of ordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0080] In FIG. 9A, the method includes the step 901 of forming a photonics device material 920 (e.g., SiPh or SiN) overlying a substrate platform 910 (e.g., Si or SOI). In FIG. 9B, the method includes the step 902 of patterning the photonics device material 920 to form one or more photonics structures 922 (e.g., waveguides). In FIG. 9C, the method includes the step 903 of forming a dielectric layer 930 (e.g., encapsulation layer) overlying the photonics structures922. In FIG. 9D, the method includes the step 904 in which the dielectric layer 930 is subjected to a thinning process (e.g., grinding, etching, etc.), and then a portion of the thinned dielectric layer 930 is removed (e.g., etching, lithography, etc.) to form a recessed cavity region 932 in step 905

[0081] Here, the cavity region 932 is centered overlying the middle photonics structure 922. In an example, the cavity region 932 is configured with an approximate shape and size according to the device material 830 of FIG. 8C (e.g., III-V material). Also, the cavity region 932 can be formed within the dielectric layer 930 used to planarize the wafer, bury the photonics structures 922, host other photonic components, as well as metal contact vias and traces. Further, the cavity region 932 can be purposely placed aligned with the underlying photonic components, such as waveguides patterned in a SiN material.

[0082] FIGs. 10A-10C are simplified diagrams illustrating cross-sectional views of a method of manufacturing an integrated CS photonics device according to an example of the present invention. Elements with the same reference numbers as past figures refer to the same elements and can include the same materials and configurations discussed previously. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One of ordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0083] In FIG. 10A, the method includes the step device wafer from FIG. 8C is coupled, topside down, overlying the photonics wafer from FIG. 9E, which results in the integrated device wafer 1002 shown in FIG. 10B. Here, the device layer 830 of the device wafer is configured within the cavity region 932 of the photonics wafer. Then, in FIG. 10C, the template substrate 810 and the etch stop layer 820 are removed (e.g., grinding, chemical mechanical polishing, chemical etching, etc.), which leaves the integrated device wafer 1003 with the device layer 830 within the cavity region 932 overlying the photonics structures 922.

[0084] In other cases, other portions or layers may remain depending on the subsequent device forming processes. As discussed previously, this device material 830 may be patterned to form waveguides or device structures; may be exposed to ion implantation steps to form p-n junctions; may have metal contacts applied to it; and may be subjected to other common fabrication steps toform devices (e.g., III-V devices). The subsequent device structures may also be covered with additional dielectric materials for encapsulation and addressed through top-level metal contacts and vias. CS lasers may also be directly integrated into the photonics platform with light generation being evanescently coupled to waveguides.

[0085] FIGs. 11A and 11B are simplified diagrams illustrating cross-sectional views of integrated CS photonics device wafers according to examples of the present invention. Elements with the same reference numbers as past figures refer to the same elements and can include the same materials and configurations discussed previously. In FIG. 11A, device 1101 shows a similar device to that shown in FIG. 10C except there is only one photonics structure 922 shown. As discussed previously, the device layer 830 can be subjected to additional device forming processes to create different electronic and optoelectronic components, such as shown in FIG.11B

[0086] FIG. 11B shows the result of the device layer 830 being subjected to additional device forming processes, resulting in a PIN device 1102. Here, the PIN device 1102 includes a n-type layer 1110 coupled to the dielectric material 930 within the cavity region. A patterned intrinsic layer 1120 is coupled overlying the n-type layer 1110, and a patterned p-type layer 1130 is coupled overlying the intrinsic layer 1120. Further, there are one or more n-layer metal contacts 1140 coupled to the n-type layer 1110 and one or more p-layer metal contacts coupled the p-type layer 1130. In this case, there is a first n-layer metal contact 1140 overlying a first portion of the n-type layer 1110 adjacent to the intrinsic and p-type layers 1120, 1130, and there is a second n- layer metal contact 1140 overlying a second portion of the n-type layer 1110 adjacent to and on the opposite side of the intrinsic and p-type layers 1120, 1130. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives to this PIN device configuration.

[0087] FIGs. 12A-12C are simplified diagrams illustrating top views of a method of forming a PIN device on an integrated photonics wafer according to an example of the present invention. Elements with the same reference numbers as past figures refer to the same elements and can include the same materials and configurations discussed previously. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One ofordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0088] FIG. 12A shows a top view of a device 1201 similar to the PIN device 1101 in FIG. 11 A, which can represent a cross-sectional view of the device 1201 across the A-A dotted line. From this view, a p-type layer 1130 is shown to be configured within the cavity region 932 in the dielectric layer 930. Referring to FIG. 11B, the p-type layer 1130, the intrinsic layer 1120, and the n-type layer 1110 can be formed by subjecting the device layer 830 to doping processes. These doping processes can include those performed during the material growth process, such as molecular beam epitaxy (MBE), metal-organic vapor phase epitaxy (MOVPE), and the like. The processes can include those performed post-growth, such as ion implantation, thermal diffusion, surface charge transfer doping, and the like.

[0089] In FIG. 12B, the device 1202 shows the result of a method step to remove one or more portions of the p-type layer 1130 (and also the intrinsic layer 1120), which exposes the n-type layer 1110 underneath. This removal process can include those such as etching, lithography, and the like. Then, in FIG. 12C, the device 1203 shows the result of a method step to form n-layer metal contacts 1140 and a p-layer metal contact 1142. Similar to device 1102, the two n-layer metal contacts 1140 are configured overlying the n-type layer 1110 and on opposite sides of the p-type layer 1130 (and also the intrinsic layer 1120). Of course, there can be other variations, modifications, and alternatives.

[0090] FIGs. 13A-13C are simplified diagrams illustrating cross-sectional views of a method of preparing a silicon electronics (SiE) wafer for integration with one or more CS devices according to an example of the present invention. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One of ordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0091] In FIG. 13A, the method includes the step 1301 of providing a SiE platform wafer 1310, which can include various integrated circuits and electronic components, such as transceiver circuitry, and the like. In FIG. 13B, the method includes the step 902 of forming a dielectric layer 1320 overlying the SiE wafer 1310. And in FIG. 13C, the method includes thestep 1303 in which one or more portions of the dielectric layer 1320 is removed (e.g., etching, lithography, etc.) to form one or more recessed cavity regions 1322. These cavity regions 1322 can be configured to receive one or more CS devices in a wafer-to- wafer bonding process, as described below.

[0092] 14A-14D are simplified diagrams illustrating cross-sectional views of a method of integrating vertically-coupled CS lasers and detectors with transceiver circuitry implemented in a SiE platform according to an example of the present invention. Elements with the same reference numbers as past figures refer to the same elements and can include the same materials and configurations discussed previously. Depending on the embodiment, one or more of the steps illustrated here can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. Such additional steps can include those relating to the methods and device structures discussed previously. One of ordinary skill in the art will recognize other variations, modifications, and alternatives. Further details of this method and resulting device are provided below.

[0093] In FIG. 14A, the method includes the step device wafer from FIG. 8C is coupled, topside down, overlying the SiE wafer from FIG. 13C, which results in the integrated device wafer 1402 shown in FIG. 14B. Here, the device layer 830 of the device wafer is configured within the cavity region 1322 of the SiE wafer. Then, in FIG. 14C, the template substrate 810 and the etch stop layer 820 are removed (e.g., grinding, chemical mechanical polishing, chemical etching, etc.), which leaves the integrated device wafer 1403 with the device layer 830 within the cavity region 1322.

[0094] In an example, the method can include the steps of forming raised islands on a CS- bearing wafer (e.g., forming additional CS devices from the CS device layer in the method shown in FIGs. 8A-8C) and complementary recessed pockets (e.g., additional recessed cavities in the method shown in FIGs. 13A-13C) in dielectric material deposited on the surface of the SiE wafer, and transferring the CS material into the recessed pockets by wafer bonding and subsequent substrate removal, as shown previously. A feature of this embodiment is that the CS film transferred to the recessed pockets of the SiE wafer is structured such that both vertically- coupled lasers and detectors can be formed from the film depending on processing methods. For example, efficient light-absorbing layers for a detector may be grown on top of efficient light-emitting layers from which a laser may be formed by etching away the detector layers and completing an optical cavity.

[0095] FIG. 14D shows a specific example of subsequent wafer-processing steps in which the circuity 1410 in the SiE wafer 1310 is connected to lasers or photodiodes 1420 formed in the CS material 830 to form arrays of vertically-coupled optical transceivers. Here, both the circuitry 1410 and the lasers or photodiodes 1420 are coupled to a metal contact 1450 by vias 1440.Those of ordinary skill in the art will recognize other variations, modifications, and alternatives to these methods of integrating CS devices with a SiE platform.

[0096] FIG. 15 is a simplified block diagram illustrating an integrated electronic-photonic system according to an example of the present invention. This system 1500 integrates electronic and photonic functions using an integration method such as that shown previously in FIGs. 14A- 14D. As shown, a plurality of processors 1510 are coupled to a serializer / deserializer (SERDES) device 1520, which can be configured to interface with a variety of devices. Here, the SERDES device 1520 is coupled to a plurality of transimpedance amplifiers (TIAs) 1530, which are coupled to a photodiode (PD) array 1540. This SERDES device 1520 is also coupled to a plurality of laser drivers 1550, which are coupled to a vertical-cavity surface-emitting laser (VCSEL) array 1560.

[0097] In an example, the processors 1510, SERDES circuitry 1520, TIAs 1530, and laser drivers 1540 are formed in the SiE platform adjacent to recessed pockets filled with CS material. The arrays of PDs and VCSELs are formed from the CS material in the recessed pockets, and are respectively connected to the TIAs 1530 and laser drivers 1540. Optical fibers aligned over the PD and VCSEL arrays can be used to couple signals to and from the transceiver arrays. Of course, there can be other variations, modifications, and alternatives.

[0098] While the above is a full description of the specific embodiments, various modifications, alternative constructions, and equivalents may be used. As an example, the packaged device can include any combination of elements described above, as well as outside of the present specification. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method of manufacturing an integrated compound semiconductor (CS) device, the method comprising: providing a template wafer having a CS buffer layer overlying a substrate layer; forming an etch stop layer overlying the CS buffer layer of the template wafer; forming a CS device layer overlying the etch stop layer; forming a passivation layer overlying the CS device layer, thereby forming a CS device wafer having a topside surface region; coupling the CS wafer to a large-diameter substrate platform with the topside surface region facing down overlying the large-diameter substrate platform; removing the template wafer and the etch stop layer using a removal process; and subjecting the CS device layer to one or more device forming processes to form one or more CS device structures.

2. The method of claim 1 wherein the substrate layer includes a silicon (Si) substrate, a germanium (Ge) substrate, or a gallium arsenide (GaAs) substrate; and wherein the CS buffer layer includes a III-V buffer layer; and wherein the etch stop layer is chemically resistant to etching by methods that efficiently remove either the substrate layer or the CS buffer layer;; and wherein the large-diameter substrate platform includes a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate having at least one Si device or waveguide layer overlying a buried oxide (BOX) layer that overlies a silicon handle wafer, or a silicon substrate having at least one silicon nitride waveguide layer overlying a BOX layer that overlies a silicon handle wafer; and wherein the removal process includes at least a grinding process, a chemical mechanical polishing process, or a chemical etching process.

3. The method of claim 1 wherein the CS device layer includes compounds formed from group-III elements gallium (Ga), aluminum (Al), and indium (In) in equal ratio to group-V elements phosphorus (P), arsenic (As), and antimony (Sb), including at least gallium arsenide (GaAs), gallium antimonide (GaSb), indium arsenide (InAs), indium phosphide (InP), aluminum gallium arsenide (AlxGai-xAs), indium gallium arsenide (lni-xGaxAs), indium aluminum arsenide (Ini-xAlxAs), indium gallium phosphide (Ini-xGaxP), indium gallium arsenide phosphide (Ini-xGaxAsi-yPy) and indium aluminum gallium arsenide (Ini-x-yAkGayAs); andwherein the CS device layer is structured to efficiently generate optical gain when pumped with electrical current, or efficiently generate electrical current when illuminated by light, or efficiently mix optical wave frequencies via a strong nonlinear optical response, or transport electrons or holes with very high mobility.

4. The method of claim 1 further comprising forming an encapsulation material overlying the one or more CS device structures; and forming one or more metal contacts overlying the encapsulation material and coupled to one or more of the CS device structures.

5. The method of claim 1 wherein the one or more device forming processes includes a patterning process or an ion implantation process; and wherein the one or more CS device structures include a transistor or a Hall effect magnetic sensor fabricated from CS material structured to transport carriers with high mobility; or a semiconductor optical amplifier (SO A), Fabry-Perot laser, distributed Bragg reflector (DBR) laser, distributed feedback (DFB) laser, sampled grating DBR (SGDBR) laser, ring resonator based laser, or vertical-cavity surface-emitting laser (VCSEL) fabricated from CS material structured to efficiently generate optical gain when pumped with electrical current; or a photodiode or avalanche photodiode (APD) fabricated from CS material structured to efficiently generate electric current when illuminated by light; or a entangled photon generator or electro-optic modulator fabricated from CS material structured to efficiently mix optical wave frequencies via a strong nonlinear optical response; or a microring resonator, an end-fire and grating-based chip-to-fiber coupler, a thermo- optically tunable interferometer, an over-coupled resonator, or a waveguide spiral.

6. An integrated compound semiconductor (CS) device comprising: a large-diameter substrate platform; a passivation layer overlying the substrate platform; a CS device layer overlying the passivation layer and the substrate platform, the CS device layer including one or more CS device structures; and an encapsulation material overlying the one or more CS device structures.

7. The device of claim 6 wherein the large-diameter substrate platform includes a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate having at least one Si device or waveguide layer overlying a buried oxide (BOX) layer that overlies a silicon handlewafer, or a silicon substrate having at least one silicon nitride waveguide layer overlying a BOX layer that overlies a silicon handle wafer.

8. The device of claim 6 wherein the CS device layer includes compounds formed from group-III elements gallium (Ga), aluminum (Al), and indium (In) in equal ratio to group-V elements phosphorus (P), arsenic (As), and antimony (Sb), including at least gallium arsenide (GaAs), gallium antimonide (GaSb), indium arsenide (InAs), indium phosphide (InP), aluminum gallium arsenide (AlxGai-xAs), indium gallium arsenide (Ini-xGaxAs), indium aluminum arsenide (Ini-xAkAs), indium gallium phosphide (Ini-xGaxP), indium gallium arsenide phosphide (Ini-xGaxAsi-yPy) and indium aluminum gallium arsenide (Ini-x-yAkGayAs).

9. The device of claim 6 further comprising one or more metal contacts overlying the encapsulation material and coupled to one or more of the CS device structures or a resistive heater structure overlying the encapsulation material.

10. The device of claim 6 wherein the one or more CS device structures include a transistor or a Hall effect magnetic sensor fabricated from CS material structured to transport carriers with high mobility; or a semiconductor optical amplifier (SOA), Fabry-Perot laser, distributed Bragg reflector (DBR) laser, distributed feedback (DFB) laser, sampled grating DBR (SGDBR) laser, ring resonator based laser, or vertical-cavity surface-emitting laser (VCSEL) fabricated from CS material structured to efficiently generate optical gain when pumped with electrical current; or a photodiode or avalanche photodiode (APD) fabricated from CS material structured to efficiently generate electric current when illuminated by light; or a entangled photon generator or electro-optic modulator fabricated from CS material structured to efficiently mix optical wave frequencies via a strong nonlinear optical response; or a microring resonator, an end-fire and grating-based chip-to-fiber coupler, a thermo-optically tunable interferometer, an over-coupled resonator, or a waveguide spiral.

11. A method of manufacturing an integrated compound semiconductor (CS) device, the method comprising: providing a template wafer having a CS buffer layer overlying a substrate layer; forming an etch stop layer overlying the CS buffer layer of the template wafer; forming a CS device layer overlying the etch stop layer;subjecting the CS device layer to one or more device forming processes to form one or more CS device structures, thereby resulting in a CS device wafer with a topside region; providing a large-diameter substrate platform; forming a photonics device material overlying the substrate platform; patterning the photonics device material to form one or more photonics device structures; forming an encapsulation layer overlying the one or more photonics device structures, thereby resulting in a photonics wafer; coupling the CS wafer to the photonics wafer with the topside region of the CS wafer facing down overlying the photonics wafer; removing the template wafer and the etch stop layer using a removal process.

12. The method of claim 11 wherein the substrate layer include a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate having at least one Si device or waveguide layer overlying a buried oxide (BOX) layer that overlies a silicon handle wafer, or a silicon substrate having at least one silicon nitride waveguide layer overlying a BOX layer that overlies a silicon handle wafer; and wherein the removal process includes at least a grinding process, a chemical mechanical polishing process, or a chemical etching process.

13. The method of claim 11 wherein the CS device layer includes compounds formed from group-III elements gallium (Ga), aluminum (Al), and indium (In) in equal ratio to group-V elements phosphorus (P), arsenic (As), and antimony (Sb), including at least gallium arsenide (GaAs), gallium antimonide (GaSb), indium arsenide (InAs), indium phosphide (InP), aluminum gallium arsenide (AlxGai-xAs), indium gallium arsenide (Ini-xGaxAs), indium aluminum arsenide (Ini-xAkAs), indium gallium phosphide (Ini-xGaxP), indium gallium arsenide phosphide (Ini-xGaxAsi-yPy) and indium aluminum gallium arsenide (Ini-x-yAlxGayAs).

14. The method of claim 11 further comprising forming a cavity region within a portion of the encapsulation layer overlying one or more of the photonics device structures; and wherein the coupling of the CS wafer to the photonics wafer results in one or more of the CS device structures being configured within the cavity region.

15. The method of claim 11 wherein the one or more device forming processes includes a patterning process or an ion implantation process; and wherein the one ormore CS device structures include a transistor or a Hall effect magnetic sensor fabricated from CS material structured to transport carriers with high mobility; or a semiconductor optical amplifier (SOA), Fabry-Perot laser, distributed Bragg reflector (DBR) laser, distributed feedback (DFB) laser, sampled grating DBR (SGDBR) laser, ring resonator based laser, or vertical -cavity surface-emitting laser (VCSEL) fabricated from CS material structured to efficiently generate optical gain when pumped with electrical current; or a photodiode or avalanche photodiode (APD) fabricated from CS material structured to efficiently generate electric current when illuminated by light; or a entangled photon generator or electro-optic modulator fabricated from CS material structured to efficiently mix optical wave frequencies via a strong nonlinear optical response; or a microring resonator, an end-fire and grating-based chip-to-fiber coupler, a thermo- optically tunable interferometer, an over-coupled resonator, or a waveguide spiral.

16. An integrated compound semiconductor (CS) device comprising: a large-diameter substrate platform; a photonics device layer overlying the large-diameter substrate platform, the photonics device layer having one or more photonics device structures; an encapsulation layer overlying the photonics device layer; and a CS device layer overlying the encapsulation layer, the photonics device layer, and the substrate platform; the CS device layer including one or more CS device structures.

17. The device of claim 16 wherein the large-diameter substrate platform includes a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate having at least one Si device or waveguide layer overlying a buried oxide (BOX) layer that overlies a silicon handle wafer, or a silicon substrate having at least one silicon nitride waveguide layer overlying a BOX layer that overlies a silicon handle wafer.

18. The device of claim 16 wherein the CS device layer includes compounds formed from group-III elements gallium (Ga), aluminum (Al), and indium (In) in equal ratio to group-V elements phosphorus (P), arsenic (As), and antimony (Sb), including at least gallium arsenide (GaAs), gallium antimonide (GaSb), indium arsenide (InAs), indium phosphide (InP), aluminum gallium arsenide (AlxGai-xAs), indium gallium arsenide (lni-xGaxAs), indium aluminum arsenide (Ini-xAlxAs), indium gallium phosphide (Ini-xGaxP), indium gallium arsenide phosphide (Ini-xGaxAsi-yPy) and indium aluminum gallium arsenide (Ini-x-yAlxGayAs).

19. The device of claim 16 wherein the photonics wafer includes a cavity region configured within a portion of the encapsulation layer overlying one or more of the photonics device structures.

20. The device of claim 16 wherein the one or more CS device structures include a transistor or a Hall effect magnetic sensor fabricated from CS material structured to transport carriers with high mobility; or a semiconductor optical amplifier (SOA), Fabry -Perot laser, distributed Bragg reflector (DBR) laser, distributed feedback (DFB) laser, sampled grating DBR (SGDBR) laser, ring resonator based laser, or vertical-cavity surface-emitting laser (VCSEL) fabricated from CS material structured to efficiently generate optical gain when pumped with electrical current; or a photodiode or avalanche photodiode (APD) fabricated from CS material structured to efficiently generate electric current when illuminated by light; or a entangled photon generator or electro-optic modulator fabricated from CS material structured to efficiently mix optical wave frequencies via a strong nonlinear optical response; or a microring resonator, an end-fire and grating-based chip-to-fiber coupler, a thermo-optically tunable interferometer, an over-coupled resonator, or a waveguide spiral.

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