Wireless communication method and communication device

By introducing LP-SS signals, the problem of synchronization failure for terminal devices with lower capabilities was solved, improving transmission performance and reducing power consumption.

WO2026102704A1PCT designated stage Publication Date: 2026-05-21GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP LTD
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP LTD
Filing Date
2024-11-15
Publication Date
2026-05-21

AI Technical Summary

Technical Problem

Terminal devices with lower capabilities are unable to receive synchronization signal broadcast channel blocks (SSBs), resulting in the inability to synchronize.

Method used

A low-power synchronization signal (LP-SS) is introduced, which is based on a first sequence generated by bit stuffing and/or sequence concatenation, and is used to wake up the receiver for synchronization and measurement.

Benefits of technology

It improves the transmission performance of LP-SS signals, helps the wake-up receiver to better decode the wake-up signal, and reduces the power consumption of terminal devices.

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Abstract

Provided are a wireless communication method and a communication device. The method comprises: receiving an LP-SS, or sending the LP-SS, wherein the LP-SS is generated on the basis of a first sequence, and the first sequence is a sequence obtained after the following processing: bit padding processing and / or sequence concatenation processing. An LP-SS for a low-power receiver is introduced, and the LP-SS for a low-power receiver is designed, wherein the LP-SS is generated on the basis of a first sequence, and the first sequence is obtained by means of bit padding processing and / or sequence concatenation processing, such that the LP-SS has good transmission performance.
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Description

Wireless communication methods and communication devices Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a method and device for wireless communication. Background Technology

[0002] With the widespread application of communication systems, various types of terminal devices have been introduced, and these devices have different capabilities. For example, terminal devices with lower capabilities may not have the ability to receive synchronization signal block / physical broadcast channel block (SS / PBCH block, SSB), making it impossible for them to synchronize based on SSB. Summary of the Invention

[0003] This application provides a method and apparatus for wireless communication. The various aspects covered by this application are described below.

[0004] In a first aspect, a wireless communication method is provided, comprising: receiving a low power synchronization signal (LP-SS) signal, or transmitting the LP-SS signal; wherein the LP-SS signal is generated based on a first sequence, the first sequence being a sequence obtained after the following processing: bit stuffing processing; and / or sequence concatenation processing.

[0005] Thirdly, a communication device is provided, comprising: a transceiver unit for receiving or transmitting an LP-SS signal; wherein the LP-SS signal is generated based on a first sequence, the first sequence being a sequence obtained after the following processing: bit stuffing processing; and / or sequence concatenation processing.

[0006] Thirdly, a communication device is provided, including a transceiver, a memory, and a processor, wherein the memory is used to store a program, and the processor is used to invoke the program in the memory and control the transceiver to receive or send signals, so that the communication device performs the method as described in the first aspect.

[0007] Fourthly, an apparatus is provided, including a processor for calling a program from a memory to cause the apparatus to perform the method as described in the first aspect.

[0008] Fifthly, a chip is provided, including a processor for calling a program from memory, causing a device on which the chip is mounted to perform the method as described in the first aspect.

[0009] A sixth aspect provides a computer-readable storage medium having a program stored thereon that causes a computer to perform the method as described in the first aspect.

[0010] A seventh aspect provides a computer program product, including a program that causes a computer to perform the method as described in the first aspect.

[0011] Eighthly, a computer program is provided that causes a computer to perform the method as described in the first aspect.

[0012] In this embodiment, an LP-SS signal for a low-power receiver is introduced and designed. The LP-SS signal is generated based on a first sequence, which is obtained by bit stuffing and / or sequence concatenation, so that the LP-SS signal has better transmission performance. Attached Figure Description

[0013] Figure 1 is a system architecture example diagram of a wireless communication system applicable to embodiments of this application.

[0014] Figure 2 is a schematic diagram of the SSB structure.

[0015] Figure 3 is a schematic diagram of DRX.

[0016] Figure 4 is a schematic diagram of waking up the receiver.

[0017] Figure 5 is a flowchart illustrating the wireless communication method according to an embodiment of this application.

[0018] Figure 6 is a schematic diagram of the mapping relationship between the modulated OOK symbol and the OFDM symbol.

[0019] Figure 7 is a schematic diagram of the structure of the terminal device according to an embodiment of this application.

[0020] Figure 8 is a schematic diagram of the structure of a network device according to an embodiment of this application.

[0021] Figure 9 is a schematic diagram of a communication apparatus according to an embodiment of this application. Detailed Implementation

[0022] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0023] Wireless communication system

[0024] Figure 1 is an example diagram of the system architecture of a wireless communication system 100 to which embodiments of this application can be applied. The wireless communication system 100 may include a network device 110 and a terminal device 120. The network device 110 may be a device that communicates with the terminal device 120. The network device 110 can provide network coverage for a specific geographical area and can communicate with the terminal device 120 located within that coverage area. The terminal device 120 can access a network, such as a wireless network, through the network device 110. Optionally, the wireless communication system 100 may also include other network entities such as a network controller and a mobility management entity; this embodiment of the application does not limit this.

[0025] It should be understood that the technical solutions of the embodiments of this application can be applied to various communication systems, such as: fifth generation (5G) systems, new radio (NR), long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided in this application can also be applied to future communication systems, such as sixth generation mobile communication systems, satellite communication systems, etc.

[0026] In this application embodiment, the terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station (MS), mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. The terminal device in this application embodiment can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, vehicle-mounted device, etc. Terminal devices can also be mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, self-driving, remote medical surgery, smart grids, transportation safety, smart cities, and smart homes. Optionally, terminal devices can act as base stations. For example, a terminal device can act as a dispatching entity, providing sidelink signals between terminal devices in vehicle-to-everything (V2X) or device-to-device (D2D) systems. For instance, cellular phones and cars communicate with each other using sidelink signals. Cellular phones and smart home devices communicate without relaying communication signals through base stations.

[0027] In this embodiment, the network device can be a device used to communicate with a terminal device. The network device can be an access network device or a wireless access network device. For example, the network device can be a base station. The term "base station" can broadly encompass various names as follows, or can be replaced by names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, transmitting and receiving point (TRP), transmitting point (TP), master station (MeNB), secondary station (SeNB), multi-mode radio (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or similar entity, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, or an entity that performs base station functions in device-to-device (D2D), vehicle-to-everything (V2X), and machine-to-machine (M2M) communications, a network-side device in a 6G network, or an entity that performs base station functions in future communication systems. A base station can support networks using the same or different access technologies. The embodiments of this application do not limit the specific technologies or device forms used in the network equipment.

[0028] Furthermore, base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0029] Network devices and terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and satellites. This application does not limit the scenario in which the network devices and terminal devices are located.

[0030] It should be understood that all or part of the functions of the communication device in this application can also be implemented by software functions running on hardware, or by virtualization functions instantiated on a platform such as a cloud platform.

[0031] SSB

[0032] In NR systems, the SSB plays a fundamental role in the initial access process, carrying out crucial functions such as carrying cell identity (ID), time-frequency synchronization, indicating symbol-level / time-slot-level / frame timing, and measuring cell / beam signal strength / signal quality. To support these functions, the SSB typically includes a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a physical broadcast channel (PBCH), and its reference signal (e.g., demodulation reference symbol (DMRS)). The PSS and SSS are used to carry cell identity (e.g., up to 1008 cell identities), complete time-frequency synchronization, and obtain symbol-level timing; the reference signal (e.g., DMRS) of the SSS and PBCH can be used for measuring cell or beam signal strength / signal quality; and the PBCH is used to indicate time-slot / frame timing and other information.

[0033] In NR systems, SSBs are transmitted via beam scanning. Each downlink beam requires an SSB, and each SSB includes a PSS, an SSS, and a PBCH. The PSS and SSS sequences are both 127 bytes long, occupying 12 physical resource blocks (PRBs), including the guard subcarrier. To provide sufficient resources for the PBCH to be transmitted at a sufficiently low code rate, simulation evaluation shows that with a bandwidth of 24 PRBs per symbol, the PBCH only needs 2 symbols to meet performance requirements. Therefore, the PBCH bandwidth is 24 PRBs.

[0034] The structure of the SSB, especially the temporal arrangement of the symbols PSS, SSS, and PBCH, has unique characteristics. Since the terminal device processes the PSS before the SSS when receiving and processing the SSB, if the PSS is placed after the SSS, the terminal device needs to buffer the SSS to process it after the PSS. Therefore, the PSS is usually placed before the SSS. However, there are various options for the specific temporal mapping order of the PSS, SSS, and PBCH within the SSB, based on permutations and combinations. Different options will result in different symbol spacing between PSS and SSS, different spacing between two PBCH symbols, and different relative relationships between PBCH symbols and PSS and SSS symbols.

[0035] The SSS design in an NR system can be seen in Figure 2. This approach allows the SSS to assist in channel estimation between two PBCH symbols, improving the demodulation performance of the PBCH. Therefore, the SSS is located between the two PBCH symbols. Simultaneously, it ensures the symbol spacing between the PSS and SSS, which helps improve the accuracy of frequency offset estimation. The PSS is generated from an m-sequence with a length of 127 points. The SSS is generated from a Gold sequence, also with a length of 127 points.

[0036] Discontinuous reception (DRX)

[0037] To save power in terminal devices, the DRX transmission mechanism was introduced. Its main principle is to achieve discontinuous signal reception in the time domain through semi-static configuration. When there is no data transmission, power consumption can be reduced by stopping the reception of the physical downlink control channel (PDCCH). In this case, the terminal device will stop blind detection of the PDCCH.

[0038] For terminal devices in the radio resource control (RRC) connected state (RRC_CONNECTED), as shown in Figure 3, each DRX cycle includes an active time and an inactive time. During the active time, the terminal device listens for and receives the PDCCH; this period can also be called the active phase. During the inactive time, the terminal device does not receive the PDCCH to reduce power consumption; this period can also be called the sleep phase.

[0039] In power-saving enhancements for NR systems, DRX activation (i.e., DRX ON) can also be combined with a wake-up signal (WUS) mechanism. The terminal device receives an indication of the power-saving wake-up signal before the DRX ON duration. Referring again to Figure 3, when there is data transmission during the DRX cycle, the terminal device is "wake up" via the wake-up signal to detect the PDCCH during the DRX ON duration; when there is no data transmission during the DRX cycle, the terminal device is not "wake up," and it does not need to detect the PDCCH during the DRX ON duration. Compared to the traditional DRX mechanism, when there is no data transmission, the terminal device can omit PDCCH detection during the DRX ON duration, thus achieving power saving. The time before the DRX ON duration is called the inactive time. The time during the DRX ON duration is called the active time. That is, the active time can include the time after DRX ON or the time before the terminal device's inactivity timer expires. The DRX wake-up signal itself also uses a similar waveform and structure to the PDCCH.

[0040] Terminal energy saving based on wake-up receiver (WUR)

[0041] Furthermore, to save power in terminal devices, the 3GPP R18 standard introduced a wake-up receiver (WUS), also known as a low-power WUR (LP-WUR) or low-power receiver (LR), for receiving wake-up signals (WUS). The introduction of the wake-up receiver provides a deeper sleep mode. The wake-up receiver boasts extremely low cost, low complexity, and extremely low power consumption, primarily receiving the wake-up signal through envelope detection. Of course, other methods similar to those used by traditional receivers are also possible. In short, the power consumption of the wake-up receiver is several orders of magnitude lower than that of traditional receivers. For example, traditional receivers typically consume more than 100 milliwatts, while low-power receivers can consume less than 1 milliwatt.

[0042] Therefore, the wake-up signal received by the wake-up receiver (or low-power wake-up signal (LP-WUS)) differs from the wake-up signal based on PDCCH as defined in the existing 3GPP NR standard in terms of modulation method and waveform. This wake-up signal mainly consists of an envelope signal obtained by amplitude shift keying (ASK) modulation of the carrier signal. The demodulation of this envelope signal is also primarily driven by the energy provided by the radio frequency signal to power the low-power circuitry, thus it can be passive. The wake-up receiver can also be powered by the terminal device. Regardless of the power supply method, the low-power receiver significantly reduces power consumption compared to traditional receivers in the terminal device. It should be noted that the wake-up receiver can be integrated with the terminal device as an additional module of the terminal device's receiver, or it can be set up independently of the terminal device's receiver, for example, as a standalone wake-up function module of the terminal device.

[0043] As an example, as shown in Figure 4, the terminal device includes a main receiver (MR) and a wake-up receiver for receiving wake-up signals. If the terminal device needs to turn on the main receiver, it can be instructed to do so; otherwise, the main receiver can remain off. The wake-up receiver can be activated at any time by a wake-up signal and begin receiving wake-up information. For example, in the 802.11 protocol, the wake-up signal for the wake-up receiver can use on-off keying (OOK) modulation. The modulation principle of OOK is to modulate the amplitude of the carrier signal to non-zero and zero values, corresponding to on and off respectively, to represent information bits. OOK is also known as binary amplitude shift keying (2ASK). For example, bit 1 is modulated as on, and bit 0 is modulated as off.

[0044] During the process of listening for the wake-up signal, the wake-up receiver experiences time-frequency deviations due to the accuracy of its local oscillator. Therefore, it needs to listen for a synchronization signal for resynchronization. To address this, this application introduces an LP-SS signal, primarily used for synchronization and / or measurement of the wake-up receiver (e.g., cell search-related measurements or radio resource management (RRM) measurements). Of course, some more advanced wake-up receivers may also listen for synchronization using the legacy PSS and / or SSS. Sending the LP-SS signal before sending the wake-up signal helps the wake-up receiver better decode the wake-up signal. However, there is currently no solution for how to design the LP-SS signal for optimal transmission to the wake-up receiver.

[0045] Therefore, embodiments of this application provide a wireless communication method that introduces an LP-SS signal for a low-power receiver and designs the LP-SS signal for the low-power receiver. The LP-SS signal is generated based on a first sequence, which is obtained by bit stuffing and / or sequence concatenation, so that the LP-SS signal has better transmission performance.

[0046] The embodiments of this application will be described in detail below with reference to Figure 5.

[0047] Figure 5 is a flowchart illustrating a wireless communication method provided in an embodiment of this application. The method 500 shown in Figure 5 can be executed by a terminal device (e.g., a wake-up receiver in the terminal device) and a network device. The terminal device can be, for example, the terminal device 120 shown in Figure 1, and the network device can be, for example, the network device 110 shown in Figure 1. As shown in Figure 5, the method 500 may include some or all of the following steps.

[0048] Referring to Figure 5, in step 510, the network device sends a measurement signal to the terminal device.

[0049] In step 520, the terminal device receives the measurement signal sent by the network device.

[0050] The measurement signal can be used, for example, for measurements of the wake-up receiver of a terminal device (e.g., synchronization measurements, cell search-related measurements, RRM measurements, etc.). Furthermore, the measurement signal may also be used for level adaptation of the wake-up receiver. The measurement signal can be the aforementioned LP-SS signal. Hereinafter, the technical solution of the embodiments of this application will be described using the LP-SS signal as an example. By sending the LP-SS signal, the receiver of the terminal device can decode the wake-up signal. For example, sending the LP-SS signal before the wake-up signal allows the receiver to perform various measurements such as synchronization using the LP-SS signal, thereby facilitating the reception of the wake-up signal.

[0051] In some implementations, the LP-SS signal can be generated based on a first sequence. This first sequence can be, for example, a sequence obtained through bit stuffing and / or sequence concatenation. Bit stuffing and / or sequence concatenation are used to adjust the number and / or values ​​of bits in the first sequence. For example, bit stuffing and / or sequence concatenation can be used to balance (or equalize) the number of 0s and 1s in the first sequence, or to make the number of 0s and 1s in the first sequence the same or substantially the same; or, for example, bit stuffing and / or sequence concatenation can be used to adjust the bit length of the first sequence, such as adjusting the bit length of the first sequence to an even number. Here, the bit length of the sequence refers, for example, to the number of bits, i.e., the total number of 0s and 1s in the sequence. Therefore, the first sequence in the embodiments of this application can, for example, have the following characteristics: the number of 0s and 1s in the first sequence is balanced; and / or, the bit length of the first sequence is an even number. The purpose of making the bit length of the first sequence even is to better map the modulated LP-SS signal onto the time-domain symbols (e.g., orthogonal frequency division multiplexing (OFDM) symbols) in the time slots, since the number of time-domain symbols used to transmit the LP-SS signal in a time slot is typically even. This can also be understood as increasing the transmission resources of the LP-SS signal through bit stuffing. Balancing the number of 0s and 1s in the first sequence improves the transmission performance of the LP-SS signal. For example, when the first sequence is subsequently modulated using OOK modulation, the high and low levels of the OOK signal can be balanced, ensuring that the total duration of the high and low levels is the same and the energy is constant.

[0052] The bit stuffing process and sequence concatenation process are described below.

[0053] Bit stuffing processing

[0054] Bit stuffing processing may include, for example, generating a second sequence; and stuffing the second sequence with 0s or 1s based on the number of 0s and 1s in the second sequence to obtain a first sequence. The second sequence has good autocorrelation and cross-correlation characteristics; for example, the second sequence may include a binary random sequence (or, in other words, an orthogonal sequence). Binary random sequences include, but are not limited to, m-sequences or Gold sequences. Optionally, the bit length of the second sequence is 2^n bits. N -1, where N is a positive integer. Preferably, to match the wake-up receiver's capability, N=2, N=3, N=4, or N=5 can be selected, and correspondingly, the length of the second sequence is 2. 2 -1 = 3, 2 3 -1 = 7, 2 4 -1 = 15, 2 5 -1 = 31.

[0055] For example, the second sequence has an odd bit length (e.g., 7 bits, 15 bits, or 31 bits), and the second sequence is filled with 1 0 or 1, resulting in a first sequence with an even bit length (e.g., 8 bits, 16 bits, or 32 bits).

[0056] For example, if the number of 0s in the second sequence is one more than the number of 1s, then fill the second sequence with one 0 to obtain the first sequence, in which the number of 0s and 1s is balanced; if the number of 1s in the second sequence is one more than the number of 0s, then fill the second sequence with one 1 to obtain the first sequence, in which the number of 0s and 1s is balanced.

[0057] Sequence cascading processing

[0058] Sequence concatenation processing may include, for example, generating a second sequence; generating a third sequence; and concatenating the second and third sequences to obtain a first sequence. The second sequence has good autocorrelation and cross-correlation; for example, the second sequence may include a binary random sequence (or, in other words, an orthogonal sequence). Binary random sequences include, but are not limited to, m-sequences or Gold sequences. Optionally, the bit length of the second sequence is 2^n bits. N -1, where N is a positive integer. Preferably, to match the wake-up receiver's capability, N=2, N=3, N=4, or N=5 can be selected, and correspondingly, the length of the second sequence is 2. 2 -1 = 3, 2 3 -1 = 7, 2 4 -1 = 15, 2 5 -1 = 31.

[0059] In one implementation, the third sequence and the second sequence can be generated in the same way. The second sequence has an odd bit length, the third sequence has an odd bit length, and thus the first sequence obtained by concatenating the second and third sequences has an even bit length. Here, the bit lengths of the second and third sequences can be the same or different. For example, the second sequence is an m-sequence with a bit length of 15, the third sequence is an m-sequence with a bit length of 7, and the first sequence obtained by concatenating the second and third sequences is an m-sequence with a bit length of 22. Another example is that the second sequence is an m-sequence with a bit length of 7, the third sequence is an m-sequence with a bit length of 3, and the first sequence obtained by concatenating the second and third sequences is an m-sequence with a bit length of 10.

[0060] In another implementation, the third sequence can be a balancing sequence (or a 0-1 balancing sequence). When generating the third sequence, the number of 0s and 1s in the third sequence can be determined based on the number of 0s and 1s in the second sequence, so that the number of 0s and 1s in the first sequence obtained by concatenating the third and second sequences is balanced. In other words, the number of 0s and 1s in the third sequence is determined based on the number of 0s and 1s in the second sequence, so that the number of 0s and 1s in the first sequence obtained by concatenating the third and second sequences is balanced. For example, the balancing sequence could be 010 or 100, etc.

[0061] The generation method of the second sequence described above is described below. Taking the second sequence as an m-sequence as an example, the generation of the second sequence may include: determining the cyclic shift value corresponding to the second sequence; and determining the second sequence based on the cyclic shift value and the bit length of the second sequence.

[0062] First, the method for determining the cyclic shift value corresponding to the second sequence is described. The second sequence can be generated from a set of candidate sequences. Optionally, the step size corresponding to the second sequence can be determined based on the number of candidate sequences and the bit length of the second sequence, and the cyclic shift value corresponding to the second sequence can be determined based on the step size and the sequence number of the second sequence in the candidate sequences.

[0063] The step size can be determined, for example, in the following way: or Where I is the step size, c is the number of candidate sequences, and 2 N -1 represents the bit length of the second sequence.

[0064] The cyclic shift value corresponding to the second sequence can be determined, for example, as follows: k = p * I; where k is the cyclic shift value corresponding to the second sequence, p is the sequence number of the second sequence in the candidate sequences, 0 ≤ p ≤ c, c is the number of candidate sequences, and I is the step size. The sequence number of the second sequence in the candidate sequences is associated with the cell of the terminal device, for example, with the system information of the terminal device's cell, or with the cell identifier of the terminal device. The sequence associated with the LP-SS signal received by the terminal device can be one of c candidate sequences, and the selected sequence can be determined based on the sequence number p, the value of which is associated with the cell.

[0065] Taking N=5 as an example, the bit length of the second sequence is 31, meaning the second sequence is an m-sequence with a bit length of 31. Therefore... or Suppose the number of candidate sequences is 4, i.e., c = 4, then I = 8 or 7. Next, based on k = p * I, calculate the cyclic shift value k, 0 ≤ p < 4, where the cyclic shift value is 0 when p = 0 (equivalent to no cyclic shift), the cyclic shift value is k = I when p = 1, the cyclic shift value is k = 2 * I when p = 2, and the cyclic shift value is k = 3 * I when p = 3. These four sequences with different cyclic shift values ​​are orthogonal.

[0066] Secondly, after determining the cyclic shift value, the second sequence can be calculated using the corresponding polynomial based on the cyclic shift value and the bit length of the second sequence.

[0067] In some implementations, the second sequence can be determined based on the following polynomial: s (k) (n) = x((n+k)mod M); where, s (k) (n) is the nth sequence item in the second sequence, k is the cyclic shift value corresponding to the second sequence, M is the bit length of the second sequence, and x is a predetermined polynomial.

[0068] As an example, still taking N=5 as an example, that is, the bit length of the second sequence is M=2. N -1 = 31. Given that the bit length of the second sequence is M, n also has M different values. Based on the above method, the cyclic shift value k is determined, and substituted into the polynomial, s is obtained. (k) (n) = x((n+k)mod 31). This application does not limit the type of the predetermined polynomial x; for example, the predetermined polynomial can be... or etc.

[0069] by For example, the bit length of the second sequence is 2. N -1, It is a positive integer. Among them, x(0), x(1), x(2), x(3), and x(4) have initial values. Assume the bit length of the second sequence is 31. Right now It has 26 different values, and x(0), x(1), x(2), x(3), and x(4) have initial values ​​of x(0) = 0, x(1) = 0, x(2) = 0, x(3) = 0, and x(4) = 1, respectively. Based on the values ​​of the first 5 sequence items with initial values ​​(i.e., x(0) to x(4)), the values ​​of the remaining 26 sequence items (i.e., x(5) to x(30)) can be calculated. Here, taking the assignment of values ​​to the first 5 sequence items x(0), x(1), x(2), x(3), and x(4) as an example, the embodiments of this application do not limit the initial values ​​of the predetermined polynomial and related sequence items. Depending on the polynomial used, the number of sequence items with initial values ​​may also be other, and the initial values ​​of these sequence items may also be other values.

[0070] Furthermore, the polynomials used to compute the second sequence are not limited to the examples in the embodiments of this application. Any polynomial that can be used to generate a sequence can be applied to the embodiments of this application to generate the second sequence.

[0071] After generating the second sequence using the above method, a first sequence can be obtained through bit stuffing and / or sequence concatenation. Then, the first sequence can be modulated based on a predetermined modulation scheme to obtain an LP-SS signal. That is, the LP-SS signal is the signal obtained by modulating the first sequence using a predetermined modulation scheme. This modulation scheme can be, for example, OOK modulation. Optionally, the modulated LP-SS signal is mapped to multiple time-domain symbols in a predetermined time slot (e.g., the last multiple time-domain symbols in the predetermined time slot), where the predetermined time slot is used for transmitting the LP-SS signal (or, a synchronization time slot, etc.). The number of multiple time-domain symbols used for transmitting the LP-SS signal in the predetermined time slot is even. The time slot used for transmitting the LP-SS signal can be pre-configured, for example, and can be configured based on a certain period. Mapping the modulated LP-SS signal to the last multiple symbols in the predetermined time slot takes into account that the first few symbols in the time slot may be used for control signal transmission.

[0072] As an example, as shown in Figure 6, after OOK modulation of the first sequence, the resulting OOK modulation symbols are sequentially mapped to the last 12 OFDM symbols in time slot 0.

[0073] Optionally, the modulated LP-SS signal can be spread spectrum based on a predetermined spreading coefficient and then mapped to multiple time-domain symbols. For example, as shown in Figure 6, with a spreading coefficient of 4 as an example, one OFDM symbol corresponds to four OOK modulation symbols, where 0 corresponds to the OOK low-level symbol and 1 corresponds to the OOK high-level symbol.

[0074] The LP-SS signal in this application embodiment can be used to assist in receiving wake-up signals to activate the active transmission module. Furthermore, the LP-SS signal in this application embodiment can also be extended to passive terminal devices, such as terminal devices that transmit signals via passive backscattering. These terminal devices can also receive the LP-SS signal described in this application embodiment to obtain timing or a clock signal.

[0075] Terminal devices detect sequences within a set of sequences through sequence correlation detection. Correlation detection typically includes a local sequence and a target sequence. By calculating the correlation between the target sequence and the local sequence, a numerical value is obtained, representing the similarity between the two sequences. When the target sequence and the local sequence are very similar, the calculated correlation value will be high, which can be considered a "peak." Using sequence correlation, a high correlation peak value is considered a detected target sequence, while the correlation detection output for non-target sequences is a lower value, much smaller than the correlation peak value. Here, the target sequence is the first sequence carried in the LP-SS signal in this embodiment. The local sequence can be, for example, a sequence generated by the terminal device according to the method described in this embodiment. Of course, the correlation parameters used by the terminal device to generate the local sequence are the same as those used by the network device to generate the first sequence carried in the LP-SS signal for that terminal device.

[0076] The method embodiments of this application have been described in detail above with reference to Figures 1 to 6. The apparatus embodiments of this application will be described in detail below with reference to Figures 7 to 9. It should be understood that the descriptions of the method embodiments correspond to the descriptions of the apparatus embodiments; therefore, any parts not described in detail can be referred to the preceding method embodiments.

[0077] Figure 7 is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. The terminal device 700 shown in Figure 7 may include a transceiver unit 710. The transceiver unit 710 is used to receive an LP-SS signal; wherein the LP-SS signal is generated based on a first sequence, the first sequence being a sequence obtained after the following processing: bit stuffing processing; and / or, sequence concatenation processing.

[0078] In some implementations, the number of 0s and 1s in the first sequence is balanced; and / or, the bit length of the first sequence is even.

[0079] In some implementations, the bit stuffing process includes: generating a second sequence; and stuffing the second sequence with 0s or 1s based on the number of 0s and 1s in the second sequence to obtain the first sequence.

[0080] In some implementations, the bit length of the second sequence is odd, the bit length of the first sequence is even, and the number of 0s or 1s filled in the second sequence is 1.

[0081] In some implementations, the sequence concatenation process includes: generating a second sequence; generating a third sequence; and concatenating the second sequence and the third sequence to obtain the first sequence.

[0082] In some implementations, the third sequence is generated in the same way as the second sequence, the second sequence has an odd bit length, the third sequence has an odd bit length, and the first sequence has an even bit length.

[0083] In some implementations, the third sequence is a balancing sequence, and generating the third sequence includes: determining the number of 0s and 1s in the third sequence based on the number of 0s and 1s in the second sequence, so as to balance the number of 0s and 1s in the first sequence obtained by concatenating the third sequence with the second sequence.

[0084] In some implementations, the bit length of the second sequence is 2. N -1, where N is a positive integer.

[0085] In some implementations, N=2, N=3, N=4, or N=5.

[0086] In some implementations, the second sequence includes a binary random sequence.

[0087] In some implementations, the binary random sequence includes: an m-sequence; or, a Gold sequence.

[0088] In some implementations, the second sequence is an m-sequence, and generating the second sequence includes: determining the cyclic shift value corresponding to the second sequence; and determining the second sequence based on the cyclic shift value and the bit length of the second sequence.

[0089] In some implementations, determining the cyclic shift value corresponding to the second sequence includes: determining the step size corresponding to the second sequence based on the number of candidate sequences of the second sequence and the bit length of the second sequence; and determining the cyclic shift value corresponding to the second sequence based on the step size corresponding to the second sequence and the sequence number of the second sequence in the candidate sequences.

[0090] In some implementations, the step size is determined based on the following method: or Where I is the step size, c is the number of candidate sequences, and 2 N-1 represents the bit length of the second sequence.

[0091] In some implementations, the cyclic shift value corresponding to the second sequence is determined based on the following method: k = p * I; where k is the cyclic shift value corresponding to the second sequence, p is the sequence number of the second sequence in the candidate sequences, 0 ≤ p ≤ c, c is the number of the candidate sequences, and I is the step size.

[0092] In some implementations, the second sequence number in the candidate sequence is associated with the cell of the terminal device.

[0093] In some implementations, the second sequence is determined based on the following: s (k) (n) = x((n+k)mod M); where, s (k) (n) is the nth sequence item in the second sequence, k is the cyclic shift value corresponding to the second sequence, M is the bit length of the second sequence, and x is a predetermined polynomial.

[0094] In some implementations, the bit length of the second sequence is 2. N -1, the predetermined polynomial is: It is a positive integer. x(0), x(1), x(2), x(3), x(4) have initial values.

[0095] In some implementations, the LP-SS signal is the signal obtained by modulating the first sequence according to a predetermined modulation scheme.

[0096] In some implementations, the modulation method is OOK modulation.

[0097] In some implementations, the modulated LP-SS signal is mapped to the last multiple time-domain symbols in a predetermined time slot, the predetermined time slot being a time slot used to transmit the LP-SS signal, and the number of the multiple time-domain symbols is even.

[0098] In some implementations, the modulated LP-SS signal is spread based on predetermined spreading coefficients and then mapped to the plurality of time-domain symbols.

[0099] It is understood that the transceiver unit 710 may be, for example, a transceiver 930. Additionally, the terminal device 700 may optionally include a processor 910 and a memory 920, as shown in Figure 9.

[0100] Figure 8 is a schematic diagram of the structure of a network device provided in an embodiment of this application. The network device 800 shown in Figure 8 may include a transceiver unit 810. The transceiver unit 810 is used to transmit the LP-SS signal; wherein the LP-SS signal is generated based on a first sequence, the first sequence being a sequence obtained after the following processing: bit stuffing processing; and / or, sequence concatenation processing.

[0101] In some implementations, the number of 0s and 1s in the first sequence is balanced; and / or, the bit length of the first sequence is even.

[0102] In some implementations, the bit stuffing process includes: generating a second sequence; and stuffing the second sequence with 0s or 1s based on the number of 0s and 1s in the second sequence to obtain the first sequence.

[0103] In some implementations, the bit length of the second sequence is odd, the bit length of the first sequence is even, and the number of 0s or 1s filled in the second sequence is 1.

[0104] In some implementations, the sequence concatenation process includes: generating a second sequence; generating a third sequence; and concatenating the second sequence and the third sequence to obtain the first sequence.

[0105] In some implementations, the third sequence is generated in the same way as the second sequence, the second sequence has an odd bit length, the third sequence has an odd bit length, and the first sequence has an even bit length.

[0106] In some implementations, the third sequence is a balancing sequence, and generating the third sequence includes: determining the number of 0s and 1s in the third sequence based on the number of 0s and 1s in the second sequence, so as to balance the number of 0s and 1s in the first sequence obtained by concatenating the third sequence with the second sequence.

[0107] In some implementations, the bit length of the second sequence is 2. N -1, where N is a positive integer.

[0108] In some implementations, N=2, N=3, N=4, or N=5.

[0109] In some implementations, the second sequence includes a binary random sequence.

[0110] In some implementations, the binary random sequence includes: an m-sequence; or, a Gold sequence.

[0111] In some implementations, the second sequence is an m-sequence, and generating the second sequence includes: determining the cyclic shift value corresponding to the second sequence; and determining the second sequence based on the cyclic shift value and the bit length of the second sequence.

[0112] In some implementations, determining the cyclic shift value corresponding to the second sequence includes: determining the step size corresponding to the second sequence based on the number of candidate sequences of the second sequence and the bit length of the second sequence; and determining the cyclic shift value corresponding to the second sequence based on the step size corresponding to the second sequence and the sequence number of the second sequence in the candidate sequences.

[0113] In some implementations, the step size is determined based on the following method: or Where I is the step size, c is the number of candidate sequences, and 2 N -1 represents the bit length of the second sequence.

[0114] In some implementations, the cyclic shift value corresponding to the second sequence is determined based on the following method: k = p * I; where k is the cyclic shift value corresponding to the second sequence, p is the sequence number of the second sequence in the candidate sequences, 0 ≤ p ≤ c, c is the number of the candidate sequences, and I is the step size.

[0115] In some implementations, the second sequence number in the candidate sequence is associated with the cell of the terminal device.

[0116] In some implementations, the second sequence is determined based on the following: s (k) (n) = x((n+k)mod M); where, s (k) (n) is the nth sequence item in the second sequence, k is the cyclic shift value corresponding to the second sequence, M is the bit length of the second sequence, and x is a predetermined polynomial.

[0117] In some implementations, the bit length of the second sequence is 2. N -1, the predetermined polynomial is: It is a positive integer. x(0), x(1), x(2), x(3), x(4) have initial values.

[0118] In some implementations, the LP-SS signal is the signal obtained by modulating the first sequence according to a predetermined modulation scheme.

[0119] In some implementations, the modulation method is OOK modulation.

[0120] In some implementations, the modulated LP-SS signal is mapped to the last multiple time-domain symbols in a predetermined time slot, the predetermined time slot being a time slot used to transmit the LP-SS signal, and the number of the multiple time-domain symbols is even.

[0121] In some implementations, the modulated LP-SS signal is spread based on predetermined spreading coefficients and then mapped to the plurality of time-domain symbols.

[0122] It is understood that the transceiver unit 810 may be, for example, a transceiver 930. Additionally, the network device 800 may optionally include a processor 910 and a memory 920, as detailed in Figure 9.

[0123] Figure 9 is a schematic structural diagram of a communication apparatus according to an embodiment of this application. The dashed lines in Figure 9 indicate that the unit or module is optional. The apparatus 900 can be used to implement the methods described in the above method embodiments. The apparatus 900 may be, for example, a chip, a terminal device, or a network device.

[0124] The apparatus 900 may include one or more processors 910. The processors 910 may support the apparatus 900 in implementing the methods described in the foregoing method embodiments. The processor 910 may be a general-purpose processor or a special-purpose processor. For example, the processor 910 may be a central processing unit (CPU). Alternatively, the processor 910 may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0125] The apparatus 900 may further include one or more memories 920. The memories 920 store programs that can be executed by the processor 910, causing the processor 910 to perform the methods described in the above method embodiments. The memories 920 may be independent of the processor 910, or they may be integrated into the processor 910.

[0126] The device 900 may also include a transceiver 930. The processor 910 can communicate with other devices or chips via the transceiver 930. For example, the processor 910 can send and receive data with other devices or chips via the transceiver 930.

[0127] This application also provides a communication system. The communication system includes the terminal device and network device described above. In some implementations, the system further includes other devices that interact with the terminal device and network device.

[0128] This application also provides a computer-readable storage medium for storing a program. This computer-readable storage medium can be applied to a terminal device or network device provided in this application, and the program causes a computer to execute the methods performed by the terminal device or network device in various embodiments of this application.

[0129] This application also provides a computer program product. The computer program product includes a program. This computer program product can be applied to a terminal device or network device provided in this application embodiment, and the program causes a computer to execute the methods performed by the terminal device or network device in the various embodiments of this application.

[0130] This application also provides a computer program. This computer program can be applied to the terminal device or network device provided in this application, and the computer program causes the computer to execute the methods performed by the terminal device or network device in the various embodiments of this application.

[0131] It should be understood that the terms "system" and "network" in the embodiments of this application can be used interchangeably. Furthermore, the terminology used in this application is only for explaining specific embodiments of this application and is not intended to limit this application. The terms "first," "second," "third," and "fourth," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. In addition, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0132] In the embodiments of this application, the term "instruction" can be a direct instruction, an indirect instruction, or an indication of a relationship. For example, A instructing B can mean that A directly instructs B, such as B being able to obtain information through A; it can also mean that A indirectly instructs B, such as A instructing C, so B can obtain information through C; or it can mean that there is a relationship between A and B.

[0133] In the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0134] In the embodiments of this application, the term "correspondence" can indicate a direct or indirect correspondence between two things, or an association between two things, or a relationship such as instruction and being instructed, configuration and being configured.

[0135] In this application embodiment, "predefined" or "preconfigured" can be implemented by pre-storing corresponding codes, tables, or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices). This application does not limit the specific implementation method. For example, predefined can refer to what is defined in the protocol.

[0136] In this application embodiment, the "protocol" may refer to a standard protocol in the field of communication, such as the LTE protocol, the NR protocol, and related protocols applied to future communication systems. This application does not limit this.

[0137] In the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0138] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0139] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0140] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0141] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0142] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can read or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0143] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of wireless communication, comprising: include: Receive a low-power synchronous LP-SS signal, or send the LP-SS signal; The LP-SS signal is generated based on a first sequence, which is a sequence obtained after the following processing: Bit stuffing processing; and / or, Sequence cascading processing.

2. The method according to claim 1, characterized in that, The number of 0s and 1s in the first sequence is balanced; and / or, The bit length of the first sequence is even.

3. The method according to claim 1 or 2, characterized in that, The bit stuffing process includes: Generate a second sequence; Based on the number of 0s and 1s in the second sequence, fill the second sequence with 0s or 1s to obtain the first sequence.

4. The method of claim 3, wherein, The second sequence has an odd bit length, the first sequence has an even bit length, and the second sequence is filled with one 0 or 1.

5. The method according to any one of claims 1 to 4, characterized in that, The sequence concatenation process includes: Generate a second sequence; Generate a third sequence; The second sequence and the third sequence are concatenated to obtain the first sequence.

6. The method of claim 5, wherein, The third sequence is generated in the same way as the second sequence, the second sequence has an odd bit length, the third sequence has an odd bit length, and the first sequence has an even bit length.

7. The method of claim 5, wherein, The third sequence is a balancing sequence, and generating the third sequence includes: Based on the number of 0s and 1s in the second sequence, the number of 0s and 1s in the third sequence is determined to balance the number of 0s and 1s in the first sequence obtained by concatenating the third sequence with the second sequence.

8. The method according to any one of claims 3 to 7, characterized in that, The bit length of the second sequence is 2 N -1, N is a positive integer.

9. The method of claim 8, wherein, N = 2, N = 3, N = 4, or N = 5.

10. The method according to any one of claims 3 to 9, characterized in that, The second sequence includes a binary random sequence.

11. The method of claim 10, wherein, The binary random sequence includes: m-sequence; or, Gold sequence.

12. The method according to any one of claims 3 to 11, characterized in that, The second sequence is an m-sequence, and generating the second sequence includes: Determine the cyclic shift value corresponding to the second sequence; The second sequence is determined based on the cyclic shift value and the bit length of the second sequence.

13. The method of claim 12, wherein, Determining the cyclic shift value corresponding to the second sequence includes: Based on the number of candidate sequences of the second sequence and the bit length of the second sequence, the step size corresponding to the second sequence is determined; Based on the step size corresponding to the second sequence and the index of the second sequence in the candidate sequence, the cyclic shift value corresponding to the second sequence is determined.

14. The method of claim 13, wherein, The step size is determined based on the following way: or where I is the step size, c is the number of candidate sequences, 2 N -1 is the bit length of the second sequence.

15. The method according to claim 13 or 14, characterized in that, The cyclic shift value corresponding to the second sequence is determined based on the following method: k = p * I; Where k is the cyclic shift value corresponding to the second sequence, p is the index of the second sequence in the candidate sequence, 0≤p≤c, c is the number of the candidate sequences, and I is the step size.

16. The method according to any one of claims 13 to 15, characterized in that, The second sequence number in the candidate sequence is associated with the cell of the terminal device.

17. The method according to any one of claims 13 to 16, characterized in that, The second sequence is determined based on the following manner: s (k) (n) = x((n+k) mod M); wherein s (k) (n) is the nth sequence item in the second sequence, k is a cyclic shift value corresponding to the second sequence, M is a bit length of the second sequence, and x is a predetermined polynomial.

18. The method of claim 17, wherein, The bit length of the second sequence is 2 N -1, and the predetermined polynomial is: for a positive integer, x(0), x(1), x(2), x(3), x(4) have initial values.

19. The method of any one of claims 1 to 18, wherein, The LP-SS signal is the signal obtained by modulating the first sequence according to a predetermined modulation method.

20. The method of claim 19, wherein, The modulation method is an on / off key control OOK modulation method.

21. The method according to claim 19 or 20, characterized in that, The modulated LP-SS signal is mapped to the last multiple time-domain symbols in a predetermined time slot, which is a time slot used to transmit the LP-SS signal, and the number of the multiple time-domain symbols is even.

22. The method of claim 21, wherein, The modulated LP-SS signal is spread based on predetermined spreading coefficients and then mapped to the plurality of time-domain symbols.

23. A communications device, characterized by include: A transceiver unit is used to receive low-power synchronous LP-SS signals or to transmit the LP-SS signals; The LP-SS signal is generated based on a first sequence, which is a sequence obtained after the following processing: Bit stuffing processing; and / or, Sequence cascading processing.

24. The communication device according to claim 23, characterized in that, The number of 0s and 1s in the first sequence is balanced; and / or, The bit length of the first sequence is even.

25. The communication device of claim 23 or 24, wherein, The bit stuffing process includes: Generate a second sequence; Based on the number of 0s and 1s in the second sequence, fill the second sequence with 0s or 1s to obtain the first sequence.

26. The communication device of claim 25, wherein, The second sequence has an odd bit length, the first sequence has an even bit length, and the second sequence is filled with one 0 or 1.

27. The communication device of any one of claims 23-26, wherein, The sequence concatenation process includes: Generate a second sequence; Generate a third sequence; The second sequence and the third sequence are concatenated to obtain the first sequence.

28. The communication device of claim 27, wherein, The third sequence is generated in the same way as the second sequence, the second sequence has an odd bit length, the third sequence has an odd bit length, and the first sequence has an even bit length.

29. The communication device of claim 27, wherein, The third sequence is a balancing sequence, and generating the third sequence includes: Based on the number of 0s and 1s in the second sequence, the number of 0s and 1s in the third sequence is determined to balance the number of 0s and 1s in the first sequence obtained by concatenating the third sequence with the second sequence.

30. The communication device of any one of claims 25-29, wherein, The bit length of the second sequence is 2 N -1, N is a positive integer.

31. The communication device of claim 30, wherein, N = 2, N = 3, N = 4, or N = 5.

32. The communication device of any one of claims 25 to 31, wherein, The second sequence includes a binary random sequence.

33. The communication device of claim 32, wherein, The binary random sequence includes: m-sequence; or, Gold sequence.

34. The communication device of any one of claims 25 to 33, wherein, The second sequence is an m-sequence, and generating the second sequence includes: Determine the cyclic shift value corresponding to the second sequence; The second sequence is determined based on the cyclic shift value and the bit length of the second sequence.

35. The communication device of claim 34, wherein, Determining the cyclic shift value corresponding to the second sequence includes: Based on the number of candidate sequences of the second sequence and the bit length of the second sequence, the step size corresponding to the second sequence is determined; Based on the step size corresponding to the second sequence and the index of the second sequence in the candidate sequence, the cyclic shift value corresponding to the second sequence is determined.

36. The communication device of claim 35, wherein, The step size is determined based on the following way: or where I is the step size, c is the number of candidate sequences, 2 N -1 is the bit length of the second sequence.

37. The communication device of claim 35 or 36, wherein, The cyclic shift value corresponding to the second sequence is determined based on the following method: k = p * I; Where k is the cyclic shift value corresponding to the second sequence, p is the index of the second sequence in the candidate sequence, 0≤p≤c, c is the number of the candidate sequences, and I is the step size.

38. The communication device of any one of claims 35 to 37, wherein, The second sequence number in the candidate sequence is associated with the cell of the terminal device.

39. The communication device of any one of claims 35 to 38, wherein, The second sequence is determined based on the following manner: s (k) (n) = x((n+k) mod M); wherein s (k) (n) is the nth sequence item in the second sequence, k is a cyclic shift value corresponding to the second sequence, M is a bit length of the second sequence, and x is a predetermined polynomial.

40. The communication device of claim 39, wherein, The bit length of the second sequence is 2 N -1, the predetermined polynomial is: for a positive integer, x(0), x(1), x(2), x(3), x(4) have initial values.

41. The communication device of any one of claims 23 to 40, wherein, The LP-SS signal is the signal obtained by modulating the first sequence according to a predetermined modulation method.

42. The communications device of claim 41, wherein, The modulation method is an on / off key control OOK modulation method.

43. The communication device of claim 41 or 42, wherein, The modulated LP-SS signal is mapped to the last multiple time-domain symbols in a predetermined time slot, which is a time slot used to transmit the LP-SS signal, and the number of the multiple time-domain symbols is even.

44. The communication device of claim 43, wherein, The modulated LP-SS signal is spread based on predetermined spreading coefficients and then mapped to the plurality of time-domain symbols.

45. A communications device, characterized by The device includes a transceiver, a memory, and a processor. The memory stores a program, and the processor invokes the program in the memory and controls the transceiver to receive or transmit signals so that the communication device performs the method according to any one of claims 1 to 22.

46. An apparatus comprising: Includes a processor for calling a program from memory to cause the apparatus to perform the method according to any one of claims 1 to 22.

47. A chip, comprising: Includes a processor for calling a program from memory, causing a device on which the chip is mounted to perform the method according to any one of claims 1 to 22.

48. A computer-readable storage medium, characterized in that, It contains a program that causes a computer to perform the method according to any one of claims 1 to 22.

49. A computer program product, characterised in that, Includes a program that causes a computer to perform the method according to any one of claims 1 to 22.

50. A computer program, characterized in that, The computer program causes the computer to perform the method according to any one of claims 1 to 22.