3D chip placement model and construction method therefor, and 3D chip placement method

Abstract

Disclosed in the present application are a 3D chip placement model and a construction method therefor, and a 3D chip placement method. The 3D chip placement model comprises: a first sub-model and a second sub-model, wherein the result of a K-th iteration of the first sub-model serves as an iterative input parameter for a K-th iteration of the second sub-model, and the result of the K-th iteration of the second sub-model serves as an iterative input parameter for a (K+1)-th iteration of the first sub-model, where K≥1; the first sub-model is used for determining tier coordinates of each cell on the basis of net information, horizontal coordinates of each cell and the rules of the shortest wire length and the minimum number of terminals, the net information comprising information of cells forming a net; and the second sub-model is used for performing iterative optimization calculation on unified horizontal coordinates on the basis of the tier coordinates of each cell and the net information.

Description

3D chip layout model and its construction method, 3D chip layout method

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 202411637071.2, filed on November 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of 3D chip physical design technology, and in particular to 3D chip layout models and their construction methods, and 3D chip layout methods. Background Technology

[0004] With the advancement of advanced process nodes, the scale of nanoscale chip basic devices has reached billions. Compared with traditional 2D chips (two-dimensional integrated circuits), 3D chip (three-dimensional integrated circuit) technology has attracted a lot of attention due to its advantages in chip design. Compared with 2D chips, 3D chips can provide higher integration density, shorter wire lengths, and better energy efficiency.

[0005] Integrated circuit layout design is trending towards large-scale, multi-design-constraint-and-go, and closely integrated front-end and back-end design flows. Firstly, design flows that use 2D chip physical design flows to achieve pseudo-3D effects often result in poor quality layout design results.

[0006] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0007] The main purpose of this application is to provide a 3D chip layout model and its construction method, as well as a 3D chip layout method, in order to solve the technical problem of poor quality of 3D chip physical design results in related technologies.

[0008] To achieve the above objectives, this application proposes a 3D chip layout model, which includes a first sub-model and a second sub-model. The first sub-model includes a function representing the relationship between the net length and the cell coordinates and terminal coordinates. The second sub-model includes an iterative function for unifying the horizontal coordinates, wherein the unified horizontal coordinates include the horizontal coordinates and terminal coordinates of each cell.

[0009] The result of the Kth iteration of the first sub-model is used as the iteration input parameter of the Kth iteration of the second sub-model, and the result of the Kth iteration of the second sub-model is used as the iteration input parameter of the (K+1)th iteration of the first sub-model, where K≥1;

[0010] The first sub-model is used to determine the hierarchical coordinates of each unit based on the shortest line length and the fewest terminal rules, according to the net information and the horizontal coordinates of each unit, wherein the net information includes the unit information constituting the net;

[0011] The second sub-model is used to perform iterative optimization calculations on the integrated horizontal coordinates based on the hierarchical coordinates of each unit and the network information;

[0012] In this process, each of the units in the 3D chip layout model is assigned to a wafer, and the 2D layout solution obtained by doubling the memory density threshold is used as the initial horizontal coordinates of each unit.

[0013] In one embodiment, the first sub-model includes a traversal adjustment module and a first optimization module;

[0014] The traversal adjustment module is used to traverse and adjust the hierarchical coordinates of each unit;

[0015] The first optimization module is used to obtain the adjustment benefit parameters of each unit according to a preset evaluation algorithm, and determine the optimization level coordinates of each unit based on the adjustment benefit parameters of each unit.

[0016] The second sub-model is also used to optimize the horizontal coordinates of each unit in a hierarchical manner based on the optimization level coordinates of each unit.

[0017] In one embodiment, the 3D chip layout model further includes a third sub-model, which includes a partitioning module and an optimization module;

[0018] The partitioning module is used to divide the metal layers of the wafer into squares, and to obtain the resources of each square according to the wiring track information and the effective utilization rate of each square, wherein the resources of the square are the number of wiring tracks covered by the square.

[0019] The optimization module is used to determine the prior probability distribution of each net based on the requirements of each net, determine the congestion region based on the prior probability distribution and the resources of each grid, determine the posterior probability distribution of each net based on the congestion region and the prior probability distribution, use the posterior probability distribution of each net as a resource weight map, and perform routing optimization operations. The requirements of each net are determined based on the length of the right-angle Steiner minimum tree. The routing optimization operation includes merging the resource weight map and the congestion map to generate a routing weight map of the net; determining the next routing distribution based on the routing weight map; updating the congestion map based on the determined routing distribution; and returning to execute the step of merging the resource weight map and the congestion map to generate a routing weight map of the net.

[0020] In one embodiment, the optimization module is further configured to obtain pin information of each of the wafers, establish a 3D minimum weight Steiner tree based on the pin information and the wiring weight map, and obtain global wiring information.

[0021] In one embodiment, the 3D chip layout model further includes a fourth sub-model;

[0022] The fourth sub-model is a terminal allocation model constructed based on the minimum cost weighted bipartite graph matching problem. The fourth sub-model is used to optimize the coordinates of each terminal. The cost is determined by calculating the minimum spanning tree length between the unit pins of the net and the terminal set. Each net has a maximum number of terminals that can be matched.

[0023] Secondly, this application also provides a method for constructing a 3D chip layout model, the method comprising:

[0024] Based on the line length characteristics in 3D chip layout, the mesh, cell coordinates and terminal coordinates are defined to construct an initial definition model of the 3D chip mesh. The first planning model includes a first objective function and a first constraint function. The first objective function is a function that represents the relationship between the line length of the mesh and the cell coordinates and terminal coordinates. The first constraint function includes a cell area constraint function, a mesh density constraint function and a terminal number constraint function.

[0025] The coordinate variables in the initial defined model are divided into horizontal coordinate variables and hierarchical coordinate variables to construct a two-level programming model;

[0026] A 3D chip layout model is constructed based on the two-layer planning model and the horizontal coordinate iterative model, wherein the horizontal coordinate iterative module is an iterative model constructed based on the two-dimensional layout planning method.

[0027] Thirdly, this application also provides a 3D chip layout method, the method comprising:

[0028] Obtain input parameters, wherein the input parameters include mesh information, and the mesh information includes unit information constituting the mesh;

[0029] The input parameters are input into the 3D chip layout model so that the 3D chip layout model performs iterative calculations until the preset iterative convergence condition is met, wherein the 3D chip layout model is the 3D chip layout model described in the first aspect.

[0030] Under the condition of satisfying the preset iteration convergence, the target layout information is determined according to the iteration result of the 3D chip layout model. The target layout information includes unit coordinates and the number of terminals.

[0031] In one embodiment, the iterative convergence condition is that the number of iterations of the 3D chip layout model reaches a preset threshold.

[0032] Fourthly, this application also provides a computer device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the method for constructing a 3D chip layout model as described in the second aspect or the 3D chip layout method as described in the third aspect.

[0033] Fifthly, this application also provides a storage medium, which is a computer-readable storage medium, on which a computer program is stored, the computer program being configured to implement the steps of the method for constructing a 3D chip layout model as described in the second aspect or the 3D chip layout method as described in the third aspect.

[0034] The aforementioned 3D chip layout model includes a first sub-model and a second sub-model. The 2D layout solution obtained by allocating each unit of the 3D chip layout model to a single wafer and doubling the memory density threshold serves as the initial horizontal coordinates of each unit. The first sub-model, based on the shortest line length and fewest terminal rules, determines the hierarchical coordinates of each unit according to the netting information and the horizontal coordinates of each unit. The second sub-model iteratively optimizes the unified horizontal coordinates based on the hierarchical coordinates of each unit and the netting information. Since the Kth iteration result of the first sub-model serves as the iterative input parameter for the Kth iteration of the second sub-model, and the Kth iteration result of the second sub-model serves as the iterative input parameter for the (K+1)th iteration of the first sub-model, the first and second sub-models alternately optimize and solve for the coordinates of each unit and the number of terminals. After multiple iterations, a better unit coordinate and terminal number can be determined, achieving a better layout plan for the 3D chip.

[0035] The above-mentioned method for constructing a 3D chip layout model is based on the line length characteristics in the 3D chip layout to construct an initial definition model of the 3D chip net. Then, by dividing the coordinate variables into horizontal coordinate variables and hierarchical coordinate variables, a two-level programming model is constructed. After dividing the horizontal coordinate variables and hierarchical coordinate variables, the horizontal coordinate variables and hierarchical coordinate variables can be solved by alternating optimization. Therefore, a 3D chip layout model can be constructed based on the two-level programming model and the horizontal coordinate iterative model. The constructed 3D chip layout model can solve for the coordinates of each unit and terminal through alternating optimization. After multiple iterations, the optimal unit coordinates and terminal coordinates can be determined.

[0036] The aforementioned 3D chip layout method, computer equipment, and storage medium obtain initial horizontal coordinates through a 2D solution. The initial horizontal coordinates are obtained by allocating each unit of the 3D chip to a wafer and doubling the memory density threshold in a 2D layout solution. Then, the initial horizontal coordinates are input into the 3D chip layout model for iterative calculation. The 3D chip layout model iteratively solves the coordinates of each unit and terminal by using an alternating optimization solution. When the preset iterative convergence condition is met, the 3D chip layout model can obtain a better iterative result, and thus a better unit coordinate and terminal number can be determined based on the iterative result. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 is a schematic diagram of the 3D design process using the 2D chip physical design flow in related technologies;

[0040] Figure 2 is a schematic diagram of the structure of a 3D chip layout model in one embodiment of this application;

[0041] Figure 3 is a schematic diagram of the structure of 2D mesh and 3D mesh in one embodiment of this application;

[0042] Figure 4 is a schematic diagram of the principle of optimized wiring in one embodiment of this application;

[0043] Figure 5 is a schematic diagram of the principle of determining the routing based on the wiring weight diagram in one embodiment of this application;

[0044] Figure 6 is a schematic diagram illustrating the principle of optimizing terminal positions in one embodiment of this application;

[0045] Figure 7 is a flowchart illustrating a method for constructing a 3D chip layout model according to an embodiment of this application;

[0046] Figure 8 is a flowchart illustrating a 3D chip layout method in one embodiment of this application;

[0047] Figure 9 is a schematic diagram of the module structure of the 3D chip layout device according to an embodiment of this application;

[0048] Figure 10 is a schematic diagram of the device structure of the hardware operating environment involved in the 3D chip layout method in the embodiments of this application.

[0049] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0050] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0051] Currently, with the advancement of advanced process nodes, integrated circuit layout design is trending towards large-scale, multi-design-constraints-and-go, and closely integrated front-end and back-end design flows. Firstly, the scale of nanoscale chip basic devices has reached billions, thus creating an increasingly urgent need for fast and efficient 3D chip physical design tools, such as face-to-face bonding stacked (F2F) 3D chips. The heterogeneous manufacturing requirements in 3D chips make the research of physical design technologies that support good heterogeneous designs crucial; currently, physical design EDA tools that can meet the requirements of these trends are still in their early stages. Similar to 2D chip physical design, the main focus of 3D chip physical design is performance-power-area-cost (PPAC). However, due to the lack of support for 3D chip physical design tools and technologies in the entire EDA (Electronic Design Automation) industry, as shown in Figure 1, 3D chip physical design is currently mainly performed using 2D chip design tools and technologies, with certain 3D factors considered and optimized during the design process.

[0052] However, design processes that use 2D chip physical design flow to achieve pseudo-3D effects often result in poor quality of layout design results.

[0053] Based on this, as shown in Figure 2, this application provides a 3D chip layout model 1. The 3D chip layout model 1 includes a first sub-model 11 and a second sub-model 12. The first sub-model 11 includes a function representing the relationship between the net length and the unit coordinates and terminal coordinates. The second sub-model 12 includes an iterative function that integrates the horizontal coordinates, wherein the integrated horizontal coordinates include the horizontal coordinates and terminal coordinates of each unit.

[0054] The result of the Kth iteration of the first sub-model 11 is used as the iteration input parameter of the Kth iteration of the second sub-model 12, and the result of the Kth iteration of the second sub-model 12 is used as the iteration input parameter of the (K+1)th iteration of the first sub-model 11, where K≥1.

[0055] The first sub-model 11 is used to determine the hierarchical coordinates of each unit based on the shortest line length and fewest terminal rules, according to the net information and the horizontal coordinates of each unit. The net information includes the unit information that constitutes the net. The second sub-model 12 is used to perform iterative optimization calculations on the integrated horizontal coordinates based on the hierarchical coordinates of each unit and the net information.

[0056] In this model, each unit of the 3D chip layout model 1 is assigned to a wafer, and the 2D layout solution obtained by doubling the memory density threshold is used as the initial horizontal coordinate of each unit.

[0057] In the application, the relational function included in the first sub-model 11 is represented as the following subproblem 1, and the iterative function included in the second sub-model 12 can be represented as the following subproblem 2.

[0058] Subproblem 1:

[0059] Subproblem 2:

[0060] This 3D chip layout model 1 can be applied to the layout design of F2F chips. The following explanation uses F2F chip layout as an example to illustrate the process of determining sub-problems 1 and 2. The F2F chip layout problem requires allocating cells to two dies, creating bonding terminals for cross-layer connections, and connecting the upper and lower dies of the interconnect network. Therefore, after determining the relevant information of the 3D net, the number of terminals can be determined based on the 3D net information. Define H = (V, E) to represent cells and the nets connecting cells, where cells are represented by the set V = {c1, c2, ..., c...}. n} indicates that unit c i The coordinates are represented as (x i ,y i ,z i ), where x i y i Represents the horizontal coordinate, z i ∈{0,1} represents the layer where the unit is located, i.e., the layer coordinate. As shown in Figure 3, 2D meshes are located on a single wafer, and 3D meshes are connected across layers. The mesh can be formed by the set E={e1,e2,…,e…}. m} indicates that if e j If ∈E contains top (corresponding to the top layer) and bottom (corresponding to the bottom layer) cells, then it is a 3D mesh, which we plan to use. and Let e ​​represent 3D meshes respectively j The bottom and top parts of ∈E. Set T = {t1, t2, ..., t...} m} is used to represent the terminal set used by 3D meshes. Indicates terminal t j The coordinates. WLt (e j ;·) and WL(e j ;·) indicates a wire mesh e j The line lengths in 3D and 2D forms are defined as follows: The line length of a 3D mesh is equal to the sum of its line lengths on the bottom substrate and the top substrate.

[0061] in,

[0062] Therefore, the F2F layout can be represented as the following optimization problem (1).

[0063] Optimization problem (1):

[0064] Among them, D b (·) represents the density of grid (bin)b and M b S is the threshold density of grid b. b It is the collection of all meshes in the top, bottom, and terminal layers. A1(c i ) and A0(c i ) represents unit c i In terms of the area of ​​the top and bottom floors, It is an indicator function. Furthermore, ρ represents the cost of a terminal, u... t and u b This represents the area utilization rate of the upper and lower wafer layers, where A refers to the area of ​​the upper and lower wafer layers, and N represents the area utilization rate of the upper and lower wafer layers. t This is the upper limit of the number of available terminals, ε(e j ;z)=1 indicates that the wire mesh requires one terminal to connect the upper and lower layers of chips.

[0065] It is understandable that the optimization objective of this optimization problem (1) is mainly to optimize the 3D line length and the number of terminals. Constraint (1.1) indicates that the density of each grid bin cannot exceed the preset threshold density M. b Constraints (1.2) and (1.3) state that the cell area for placing the upper and lower layer wafers cannot exceed the area multiplied by the utilization rate. Constraint (1.4) states that the number of terminals used cannot exceed N. t .

[0066] Since the optimization problem (1) has a nonlinear objective and integer variables, direct solution is very challenging. Partition-based algorithms in related technologies are easy to solve, but they lose the global nature of the solution space. Therefore, a modeling method that is easy to solve and preserves the global nature of the solution space is necessary. Analysis of the original optimization problem shows that WL tThe (·) is crucial for computation. Fortunately, once the hierarchical coordinates (the layer where the cell is located) z are determined, the function becomes easy to compute, and the remaining subproblems are similar to traditional layout problems. Therefore, there is a dominance relationship between the decision variables, which corresponds to the definition of bilevel programming. The variables of the inner-level optimization problem can be defined as x. l =(x,y,x) t ,y t ), and the outer optimization problem variable is z, so the objective function of optimization problem (1) can be rewritten as:

[0067] The inner optimization problem can be defined as follows:

[0068] Furthermore, the solution to the above problem F(x) l ,z)=g(z), where

[0069] Using this property, this plan can transform the optimization problem (1) of F2F layout into the following optimization problem (2):

[0070] It must be pointed out that evaluating g(z) is very time-consuming, therefore this plan will construct a surrogate function. Perform an effective evaluation. The surrogate function contains two parameters: the horizontal position x of the cell and the terminal. l And the vertical coordinate z of the element. Furthermore, as shown in the equation above, the constraints and the objective function are separable because x... l This has no impact on the objective or other constraints. Therefore, this plan divides the original problem into subproblem 1 and subproblem 2, and replaces the objective function of subproblem 1 with... We can obtain the aforementioned subproblems 1 and 2.

[0071] It is understandable that a first sub-model 11 can be constructed based on sub-problem 1, and a second sub-model 12 can be constructed based on sub-problem 2. Using the initial horizontal coordinates of each unit as the horizontal coordinates of each unit in the first sub-model 11, the hierarchical coordinates of each unit can be determined through these horizontal coordinates, achieving initial iteration of the hierarchical coordinates. The second sub-model 12 can receive the iterated hierarchical coordinate information and perform iterative optimization calculations on the unified horizontal coordinates based on the hierarchical coordinates of each unit and the mesh information, thereby further optimizing the unified horizontal coordinates. The first sub-model 11 and the second sub-model 12 solve for the coordinates of each unit and the number of terminals through alternating optimization. After multiple iterations, a better unit coordinate and terminal number can be determined, achieving a better layout plan for the 3D chip.

[0072] The aforementioned 3D chip layout model 1 includes a first sub-model 11 and a second sub-model 12. By allocating each unit of the 3D chip layout model 1 to a wafer and doubling the memory density threshold, the 2D layout solution obtained is used as the initial horizontal coordinates of each unit. The first sub-model 11, based on the shortest line length and fewest terminal rules, can determine the hierarchical coordinates of each unit according to the net information and the horizontal coordinates of each unit. The second sub-model 12 can perform iterative optimization calculations on the unified horizontal coordinates according to the hierarchical coordinates of each unit and the net information. Since the Kth iteration result of the first sub-model 11 is used as the iteration input parameter of the Kth iteration of the second sub-model 12, and the Kth iteration result of the second sub-model 12 is used as the iteration input parameter of the (K+1)th iteration of the first sub-model 11, the first sub-model 11 and the second sub-model 12 achieve the solution of the coordinates of each unit and the number of terminals by alternating optimization solutions. After multiple iterations, a better unit coordinate and terminal number can be determined, achieving a better layout planning for the 3D chip.

[0073] In one embodiment, the first sub-model 11 includes a traversal adjustment module and a first optimization module.

[0074] The traversal adjustment module is used to traverse and adjust the hierarchical coordinates of each unit. The first optimization module is used to obtain the adjustment benefit parameters of each unit according to the preset evaluation algorithm, and determine the optimized hierarchical coordinates of each unit based on the adjustment benefit parameters of each unit.

[0075] It is understandable that in a 2D planar layout, the size of the region is still larger than the size of the mesh bin, which may lead to inaccurate estimation of the surrogate function. Therefore, to make the surrogate function as accurate as possible, for performance and stability considerations, this application optimizes the hierarchical coordinates of each element by iterating through and adjusting the hierarchical coordinates of each element and evaluating the benefits of the adjustment.

[0076] Specifically, the evaluation algorithm includes a priority function, which is a set function used to evaluate the gains of cells in set S when moving across wafers. The priority function p(S) can be as follows:

[0077] Where T(S) is the set of terminal coordinates S determined during the acquisition process. Furthermore, when the hierarchical coordinates of a cell change, only cells within the same mesh or region need to be re-evaluated. This is key to reducing the number of calculations, and it allows for parallel computation. Next, to evaluate the benefits, this application presents a form based on discrete gradients as follows: p(S∪{c i})-p(S)=ΔWL+ρΔ|BT| +α(d(S∪{c i})-d(S))+β(o(S∪{c i})-o(S))-γd(S), and

[0078] Where ΔWL and Δ|BT| are the changes in wire length and number of terminals, respectively, and h r A r M r These represent the row height of region r, the total area of ​​the region's cells, and the maximum usable area, respectively. It is unit c i The row height of the chip in question. The discrete gradient analysis of the priority function described above considers several factors that may affect the results, including bus length and number of terminals, area overflow within the region, and overlap between cells.

[0079] Based on the priority function and its discrete gradient form, an evaluation algorithm can be constructed to evaluate the adjustment benefit parameters of each unit. The first optimization module can obtain the adjustment benefit parameters of each unit according to the preset evaluation algorithm, and determine the optimization level coordinates of each unit based on the adjustment benefit parameters of each unit.

[0080] The second sub-model 12 is also used to optimize the horizontal coordinates of each unit in layers based on the optimization level coordinates of each unit.

[0081] It is understandable that after determining the optimized hierarchical coordinates of each unit, the layer in which each unit is located can be determined. Then, the horizontal coordinates of each unit can be optimized separately by using the 2D layout specification method, thereby achieving hierarchical horizontal coordinate optimization and realizing iterative calculation of unified horizontal coordinates. Therefore, the first sub-model 11 and the second sub-model 12 solve for the coordinates of each unit and the number of terminals by alternating optimization solutions. After multiple iterations, the optimal unit coordinates and the number of terminals can be determined, thereby achieving a better layout plan for the 3D chip.

[0082] In application, after determining the coordinates of each unit, that is, after placing all units, it is necessary to determine the position of the terminals. The terminal legalization problem can be expressed as the following problem (3):

[0083] It should be noted that the objective functions of different terminals do not affect each other; in other words, the objective functions can be calculated independently. Furthermore, all terminals are of the same size. Due to these two factors, if the coordinates of all terminals are restricted to integer multiples of the spacing constraint C, an optimal solution for weighted bipartite graph matching can be obtained. Specifically, the layout is divided into uniform square grids of length C. Then, k candidate grids are selected around each terminal's Terminal Optimal Region (TOR). The cost of a candidate grid is its Manhattan distance to its TOR. Therefore, one part of the bipartite graph is the candidate grids, and the other part is defined as the terminals. Through this method, the number and location of terminals can be initially determined, thereby realizing the routing planning of the wire mesh.

[0084] In one embodiment, the 3D chip layout model 1 further includes a third sub-model, which includes a partitioning module and an optimization module.

[0085] The partitioning module is used to divide the wafer into grids of metal layers and obtain the resources of each grid based on the wiring track information and the effective utilization rate of each grid. The resources of a grid are the number of wiring tracks covered by the grid.

[0086] In F2F chip design, the metal lines of each die are typically placed on routing tracks. These tracks are evenly distributed across different metal layers, and their information is usually known. During global routing, the entire design is divided into grids (GCells). The resources occupied by a single grid correspond to the number of routing tracks it covers. The track resources of each die's metal routing layer are pressed onto its corresponding die, forming two planar grids. The bonding terminal layer is treated as a separate layer. In global routing, the nets are allocated to the evenly distributed available routing tracks on different layers. Each GCell contains multiple routing tracks, which are used as initial resources. According to design rules, there are routing obstacles on the layout that can block routing resources on one or more layers, preventing routing in these areas. Therefore, the impact of these obstacles on GCell resources needs to be considered, as follows:

[0087] Where r i It is the first The wiring track resources (referred to as resources) of each GCell, g i ∈G, It is a collection of GCells. Num(track) i ) is g i The number of wiring tracks in the area. Area(g) i ) and Area(obs i ) are respectively g i area and g iThe effective utilization rate of the obstacle area is 1-g. i Barrier area / g i The area within.

[0088] The optimization module is used to determine the prior probability distribution of each network based on its requirements, identify congested areas based on the prior probability distribution and the resources of each grid, determine the posterior probability distribution of each network based on the congested areas and the prior probability distribution, and use the posterior probability distribution of each network as a resource weight map to perform routing optimization operations. The requirements of each network are determined based on the length of the right-angle Steiner minimum tree. The routing optimization operations include merging the resource weight map and the congestion map to generate a routing weight map for the network; determining the next routing distribution based on the routing weight map; updating the congestion map based on the determined routing distribution; and returning to execute the step of merging the resource weight map and the congestion map to generate a routing weight map for the network.

[0089] As shown in Figure 4, the two leftmost rectangles represent the routing probability distributions of nets n1 and n2, i.e., their prior probability distributions. Initially, the prior probability distribution of each net is uniform, but the prior probability distributions of n1 and n2 overlap. Each GCell in the wafer is not uniform. If n1 and n2 are routed into the overlapping area, congestion is likely to occur. Therefore, by adjusting the probability distribution based on the congestion area and the prior probability distribution, the posterior probability distribution of each net can be determined. As shown in the right-hand graph of Figure 4, through resource allocation, the total demand distribution of GCells in the entire wafer is relatively uniform. For nets n1 and n2, allocating resources from the initial uniform demand distribution to the differentiated demand posterior distribution shown in the right-hand graph allows for more even resource allocation and avoids congestion. Furthermore, the differentiated distribution of nets after resource allocation can guide subsequent routing, and net demand can be converted into a corresponding weighted graph.

[0090] It should be noted that in Figure 4, darker colors indicate greater demand. In the initial stage, the prior demand distribution of nets n1 and n2 in the left figure is uniform. In the overlapping area, the total demand of GCell equals the sum of the demands of the nets it covers. The total demand of GCell cells g1 and g2 exceeds their available resources, leading to cabling congestion. After iterative optimization of resource allocation, the resources in GCells in the right figure will be more rationally allocated to different nets.

[0091] Among them, the wire network n j ∈N( The requirement for a net (a set of nets) is determined by the total routing length of the resulting right-angle Steiner tree. The length of the minimum right-angle Steiner tree (RSMT) is used as the requirement for each net, which will serve as a lower bound for the final routing length of that net. Net n j Demand d j The calculation is as follows: d j=WL(RSMT) j )

[0092] It can be seen that WL(RSMT) j ) is a wire network n j Lower bound of requirements. To obtain a more accurate estimate of the actual requirements for the final cabling, this application calculates the total length of all network cabling.

[0093] Analyzing a global routing result with good detailed routing capabilities, the net routing results in the design are uniformly superimposed on the planar grid. This ensures that all routing results within the design have sufficient resources for detailed routing, avoiding congestion, and allowing for more efficient use of resources within the GCcell. Therefore, it is necessary to guide the routing results of each net to be uniformly superimposed globally. During the routing process, nets will be routed in a certain order, which will affect the net routing. By pre-allocating virtual resources for each net to be routed and converting these virtual resources into a resource cost map for routing, routing conflicts can be resolved before routing, thereby avoiding congestion.

[0094] Specifically, the optimization module can obtain the requirements of each net based on the aforementioned calculation method. It can then determine the prior probability distribution of each net based on its requirements. The prior probability distribution of a net is its routing probability map; the sum of the prior probability distributions of nets equals the requirement of that net, while the net's requirement remains unchanged. It can be understood that in applications, the prior probability distributions of nets may overlap in the target area. If the resources in the overlapping area are insufficient to support the routing of the nets, congestion may occur. Therefore, the prior probability distributions of each net and the resources of each grid cell can be used to determine congested areas. By reducing the probability of congested areas and increasing the routing probability of unobstructed areas (i.e., non-congested areas), the probability of routing nets in congested areas can be reduced, thereby adjusting and reducing the probability of congestion in congested areas. In other words, by adjusting the probability distribution based on the congested areas and the prior probability distribution, the posterior probability density of each net can be determined. As shown in Figure 5, the posterior probability density of each net is used as a resource weight map. By merging the resource weight map with the congestion map, a routing weight map of the net can be generated. Then, the routing distribution for the next step is determined based on the routing weight map.

[0095] It should be noted that the congestion map represents a predetermined routing distribution. Therefore, once the next routing distribution is determined based on the routing weight map, the next routing step is also determined. At this point, the congestion map needs to be updated based on the next routing distribution so that the resource weight map can be merged with the updated congestion map to determine the subsequent routing distribution.

[0096] To obtain the optimal posterior distribution of demand for each net, this plan allocates the limited resources of GCell to its corresponding net. By analyzing the relationship between GCell resources and net demands, it is modeled as a mathematical programming problem as follows:

[0097] In the above function, the objective function is to minimize the sum of squares of the differences between the total allocated resources and the resources of each GCell. The constraint is that the sum of the allocated resources of the nets covering the GCells should equal the total demand of the nets. By solving the constrained programming problem, the resources of the GCells can be fully utilized while simultaneously satisfying the needs of all nets. Where x... i,j r is the number of resources allocated to the j-th net on the i-th GCell. i Let n be the total resources of the i-th GCell. This means that the sum of the resource demands of all networks on the i-th GCell should be close to the total resources of the GCell. This allows the networks to fully utilize the resources of the GCell without exceeding its capacity. j Let d be the j-th wire mesh, and d j This represents the total demand for the j-th net. In addition, the pre-allocation model should satisfy the constraint that net demand remains constant. Resource pre-allocation does not reduce net demand; that is, the net bus length remains unchanged. The set of GCells corresponding to a net consists of the GCells covered by the BBox of that net.

[0098] The optimization problem (4) above can be transformed into the following problem (5). The optimization problem (5) is already a linear programming problem. This linear programming problem can be solved by a linear programming solver or algorithm, and then the pre-allocated resources of each net in each GCell area can be obtained, which can be used to guide the net routing.

[0099] It is understandable that the optimization module can be constructed based on the above problem (5), so as to pre-allocate resources according to the prior probability distribution and the resources of each grid. After resource allocation, the posterior probability density of each network is used as the resource weight map. The resource weight map is merged with the congestion map to generate the network routing weight map, so as to realize the optimal routing plan of the network according to the routing weight map.

[0100] In one embodiment, the optimization module is also used to obtain the pin information of each chip, establish a 3D minimum weight Steiner tree based on the pin information and the routing weight map, and obtain global routing information.

[0101] The routing weight map and pin coordinates are used to build a 3D minimum weight Steiner tree (RSMT). This tree is then decomposed into multiple two-pin nets, and weighted A* routing is performed. The global routing process is shown in Figure 5. Each 3D and 2D net has its corresponding priority routing weight map on its respective chip layer, and the impact on subsequent nets is updated after the preceding net is routed.

[0102] To more accurately measure the resources of each GCell, the number of resources in each horizontal / vertical direction within each wafer layer. The resource used in GCell is d, determined by the number of wiring tracks. g The requirement d for a standard through-hole via and the need for wiring cables d wire d can be calculated g This allows us to calculate the congestion weighting function W. c As follows: d g =d wire +λ·d via

[0103] The weighting of GCell in this application needs to consider not only routing congestion but also the results of resource allocation. To fully account for these effects, this application proposes an efficient routing cost function. As shown in the following formula, where W r It is a resource weighting function. and These are congestion and resource factors, respectively.

[0104] Global routers employing related technologies can quickly acquire RSMT and build Steiner tree lookup tables for nets with fewer than 9 points. However, global routers use only a single Steiner tree topology for each point combination, which is insufficient when handling different weights. To address this issue, this application constructs an improved lookup table that includes additional Steiner tree topologies. The Steiner lookup table in this application can generate a more comprehensive Steiner tree topology for each point combination, resulting in better results and finding the minimum weighted Steiner tree with optimal wire length. After obtaining the Steiner tree topology, it is decomposed into multiple two-pin nets, and then 3D weighted A* routing is performed to obtain the global routing result.

[0105] In one embodiment, the 3D chip layout model 1 also includes a fourth sub-model.

[0106] The fourth sub-model is a terminal allocation model constructed based on the weighted bipartite graph matching problem with minimum cost. The fourth sub-model is used to optimize the coordinates of each terminal. The cost is determined by calculating the minimum spanning tree length between the unit pins of the net and the terminal set. Each net has a maximum number of terminals that can be matched.

[0107] After the partitioning and layout phases, 3D and 2D netting routing is required. The main difference between 2D and 3D netting routing lies in the criticality of the bonding terminals. Unlike traditional multi-layer wiring, in F2F chip design, cells are assigned to two different wafers. In this case, F2F chip routing requires inter-wafer connections via bonding terminals. Furthermore, the size and spacing of bonding terminals are much larger than the via spacing, making available terminal resources very limited. Therefore, terminal and net allocation becomes a crucial factor affecting the quality of the final routing solution, as shown in Figure 6. The left image in Figure 6 shows a 3D net with unoptimized terminal positions, while the right image shows a 3D net with optimized terminal positions. It can be observed that the line length of the 3D net is significantly reduced. Terminal allocation can be naturally described as a minimum-cost weighted bipartite graph matching problem. First, a set of candidate bonding terminals is initialized. k ∈T represents the terminal, x ik Indicates terminal t k to n i The match, w ij This represents the matching weight. Furthermore, this plan defines T. i This indicates that it can be connected to the net n. i A set of matching bonding terminals. This plan uses c(T) i ) to represent the allocation T i The estimated cabling cost, which is determined by the network n i Pin and bonding terminal set T i The minimum spanning tree length between the two is approximately calculated. Each net n... i There is a limit to the maximum number of matching bonding terminals. i The problem aims to find a match from the bonding terminals to the wire mesh to minimize the total cost, and can be described as follows:

[0108] The fourth sub-model can be constructed using the above functional relationships. The fourth sub-model can be optimized based on the number and position of terminals initially determined in the aforementioned embodiments, and the position of the terminals can be adjusted to further optimize the line length of the 3D mesh.

[0109] In one embodiment, this application also provides a method for constructing a 3D chip layout model, as shown in FIG7. The method for constructing a 3D chip layout model includes the following steps S701 to S703.

[0110] S701: Based on the line length characteristics in 3D chip layout, the mesh, cell coordinates and terminal coordinates are defined, and an initial definition model of the 3D chip mesh is constructed. The first planning model includes a first objective function and a first constraint function. The first objective function is a function that represents the relationship between the line length of the mesh and the cell coordinates and terminal coordinates. The first constraint function includes the cell area constraint function, the mesh density constraint function and the terminal number constraint function.

[0111] S702: Divide the coordinate variables in the initial model definition into horizontal coordinate variables and hierarchical coordinate variables to construct a two-level programming model.

[0112] S703: Construct a 3D chip layout model based on a two-level programming model and a horizontal coordinate iterative model. The horizontal coordinate iterative module is an iterative model constructed based on a two-dimensional layout programming method.

[0113] The process of constructing the 3D chip layout model can be found in the description of the aforementioned scheme, and will not be repeated here.

[0114] The above-mentioned method for constructing a 3D chip layout model is based on the line length characteristics in the 3D chip layout to construct an initial definition model of the 3D chip net. Then, by dividing the coordinate variables into horizontal coordinate variables and hierarchical coordinate variables, a two-level programming model is constructed. After dividing the horizontal coordinate variables and hierarchical coordinate variables, the horizontal coordinate variables and hierarchical coordinate variables can be solved by alternating optimization. Therefore, a 3D chip layout model can be constructed based on the two-level programming model and the horizontal coordinate iterative model. The constructed 3D chip layout model can solve for the coordinates of each unit and terminal through alternating optimization. After multiple iterations, the optimal unit coordinates and terminal coordinates can be determined.

[0115] In one embodiment, this application also provides a 3D chip layout method, which includes the following steps S801 to S803.

[0116] S801: Obtain input parameters, wherein the input parameters include net information, and the net information includes the unit information constituting the net.

[0117] In applications, input parameters can also include constraint parameters to adjust relevant constraints in the 3D chip layout model. Furthermore, input parameters can also include the initial horizontal coordinates of each element, thereby directly determining the initial horizontal coordinates of each element without needing to calculate them through the 3D chip layout model.

[0118] S802: Input the input parameters into the 3D chip layout model so that the 3D chip layout model can perform iterative calculations until the preset iterative convergence condition is met, wherein the 3D chip layout model is any of the above schemes.

[0119] S803: Under the condition of satisfying the preset iteration convergence condition, determine the target layout information based on the iteration result of the 3D chip layout model. The target layout information includes at least the unit coordinates and the number of terminals.

[0120] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, personal computer, mobile phone, etc., or an electronic device that can realize the above functions.

[0121] The aforementioned 3D chip layout method obtains the initial horizontal coordinates through a 2D solution. The initial horizontal coordinates are obtained by allocating each unit of the 3D chip to a wafer and doubling the memory density threshold in the 2D layout solution. Then, the initial horizontal coordinates are input into the 3D chip layout model for iterative calculation. The 3D chip layout model iteratively solves the coordinates of each unit and terminal by means of alternating optimization. When the preset iterative convergence condition is met, the 3D chip layout model can obtain a better iterative result, and thus a better unit coordinate and terminal number can be determined based on the iterative result.

[0122] In one embodiment, the iterative convergence condition is that the number of iterations of the 3D chip layout model reaches a preset threshold.

[0123] In another embodiment, the iterative convergence condition includes a first sub-condition and a second sub-condition. The first sub-condition is that the change in line length is less than a first preset threshold, and the second sub-condition is that the number of terminals is less than a second preset threshold.

[0124] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the 3D chip layout method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0125] This application also provides a 3D chip layout apparatus. Referring to Figure 9, the 3D chip layout apparatus includes:

[0126] The acquisition module 10 is used to acquire the initial horizontal coordinates, wherein the initial horizontal coordinates are the 2D layout solution obtained by allocating all cells to one chip and doubling the memory density threshold;

[0127] The calculation module 20 is used to input the initial horizontal coordinates into the 3D chip layout model for iterative calculation until the iterative result of the 3D chip layout model meets the preset convergence condition. The 3D chip layout model is the 3D chip layout model described in any of the above schemes.

[0128] The determination module 30 is used to determine the target layout information based on the iteration results when the iteration results of the 3D chip layout model meet the preset convergence conditions. The target layout information includes the unit coordinates and the number of terminals.

[0129] The 3D chip layout apparatus provided in this application, employing the 3D chip layout method in the above embodiments, can solve the technical problems of 3D chip layout. Compared with related technologies, the beneficial effects of the 3D chip layout apparatus provided in this application are the same as those of the 3D chip layout method provided in the above embodiments, and other technical features in the 3D chip layout apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0130] This application provides a computer device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method for constructing a 3D chip layout model or a 3D chip layout method in any of the above-described schemes.

[0131] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute a method for constructing a 3D chip layout model or a 3D chip layout method in any of the above schemes.

[0132] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the 3D chip layout model construction method or the 3D chip layout method described above.

[0133] The computer program product provided in this application can solve the technical problem of poor quality of 3D chip physical design results in related technologies. Compared with related technologies, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the 3D chip layout method provided in the above embodiments, and will not be repeated here.

[0134] Referring now to Figure 10, a schematic diagram of a computer device suitable for implementing embodiments of this application is shown. The computer device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. The computer device shown in Figure 10 is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0135] As shown in Figure 10, the computer device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the computer device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the computer device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows computer devices with various systems, it should be understood that it is not required to implement or possess all of the systems shown. More or fewer systems may be implemented alternatively.

[0136] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0137] The computer device provided in this application, employing the 3D chip layout method in the above embodiments, can solve the technical problem of poor quality of 3D chip physical design results in related technologies. Compared with the prior art, the beneficial effects of the computer device provided in this application are the same as those of the 3D chip layout method provided in the above embodiments, and other technical features of this computer device are the same as those disclosed in the 3D chip layout method in the above embodiments, and will not be repeated here.

[0138] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0139] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0140] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0141] The aforementioned computer-readable storage medium may be included in a computer device or may exist independently and not assembled into a computer device.

[0142] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by a computer device, cause the computer device to perform the method for constructing a 3D chip layout model or the 3D chip layout method in any of the aforementioned schemes.

[0143] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0144] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0145] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0146] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described 3D chip layout method, which can solve the technical problem of poor quality of 3D chip physical design results in related technologies. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the 3D chip layout method provided in the above embodiments, and will not be repeated here.

[0147] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A 3D chip layout model, wherein, The 3D chip layout model includes a first sub-model and a second sub-model. The first sub-model includes a function representing the relationship between the net length and the unit coordinates and terminal coordinates. The second sub-model includes an iterative function that integrates the horizontal coordinates, wherein the integrated horizontal coordinates include the horizontal coordinates and terminal coordinates of each unit. The result of the Kth iteration of the first sub-model is used as the iteration input parameter of the Kth iteration of the second sub-model, and the result of the Kth iteration of the second sub-model is used as the iteration input parameter of the (K+1)th iteration of the first sub-model, where K≥1; The first sub-model is used to determine the hierarchical coordinates of each unit based on the shortest line length and the fewest terminal rules, according to the net information and the horizontal coordinates of each unit, wherein the net information includes the unit information constituting the net; The second sub-model is used to perform iterative optimization calculations on the integrated horizontal coordinates based on the hierarchical coordinates of each unit and the network information; In this process, each of the units in the 3D chip layout model is assigned to a wafer, and the 2D layout solution obtained by doubling the memory density threshold is used as the initial horizontal coordinate of each unit.

2. The 3D chip layout model of claim 1, wherein, The first sub-model includes a traversal adjustment module and a first optimization module; The traversal adjustment module is used to traverse and adjust the hierarchical coordinates of each unit; The first optimization module is used to obtain the adjustment benefit parameters of each unit according to a preset evaluation algorithm, and determine the optimization level coordinates of each unit based on the adjustment benefit parameters of each unit. The second sub-model is also used to optimize the horizontal coordinates of each unit in a hierarchical manner based on the optimization level coordinates of each unit.

3. The 3D chip layout model of claim 1, wherein, The 3D chip layout model also includes a third sub-model, which includes a partitioning module and an optimization module. The partitioning module is used to divide the metal layers of the wafer into squares, and to obtain the resources of each square according to the wiring track information and the effective utilization rate of each square, wherein the resources of the square are the number of wiring tracks covered by the square. The optimization module is used to determine the prior probability distribution of each net based on the requirements of each net, determine the congestion region based on the prior probability distribution and the resources of each grid, determine the posterior probability distribution of each net based on the congestion region and the prior probability distribution, use the posterior probability distribution of each net as a resource weight map, and perform routing optimization operations. The requirements of each net are determined based on the length of the right-angle Steiner minimum tree. The routing optimization operation includes merging the resource weight map and the congestion map to generate a routing weight map of the net; determining the next routing distribution based on the routing weight map; updating the congestion map based on the determined routing distribution; and returning to execute the step of merging the resource weight map and the congestion map to generate a routing weight map of the net.

4. The 3D chip layout model of claim 3, wherein, The optimization module is also used to obtain the pin information of each of the wafers, establish a 3D minimum weight Steiner tree based on the pin information and the wiring weight map, and obtain global wiring information.

5. The 3D chip layout model of claim 1, wherein, The 3D chip layout model also includes a fourth sub-model; The fourth sub-model is a terminal allocation model constructed based on the minimum cost weighted bipartite graph matching problem. The fourth sub-model is used to optimize the coordinates of each terminal. The cost is determined by calculating the minimum spanning tree length between the unit pins of the net and the terminal set. Each net has a maximum number of terminals that can be matched.

6. A method of constructing a 3D chip layout model, wherein, The method includes: Based on the line length characteristics in 3D chip layout, the mesh, cell coordinates and terminal coordinates are defined to construct an initial definition model of the 3D chip mesh. The first planning model includes a first objective function and a first constraint function. The first objective function is a function that represents the relationship between the line length of the mesh and the cell coordinates and terminal coordinates. The first constraint function includes a cell area constraint function, a mesh density constraint function and a terminal number constraint function. The coordinate variables in the initial defined model are divided into horizontal coordinate variables and hierarchical coordinate variables to construct a two-level programming model; A 3D chip layout model is constructed based on the two-layer planning model and the horizontal coordinate iterative model, wherein the horizontal coordinate iterative module is an iterative model constructed based on the two-dimensional layout planning method.

7. A 3D chip layout method, wherein, The method includes: Obtain input parameters, wherein the input parameters include mesh information, and the mesh information includes unit information constituting the mesh; The input parameters are input into the 3D chip layout model so that the 3D chip layout model performs iterative calculations until the preset iterative convergence condition is met, wherein the 3D chip layout model is the 3D chip layout model according to any one of claims 1 to 5. Under the condition of satisfying the preset iteration convergence, the target layout information is determined according to the iteration result of the 3D chip layout model. The target layout information includes unit coordinates and the number of terminals.

8. The 3D chip layout method of claim 7, wherein, The iterative convergence condition is that the number of iterations of the 3D chip layout model reaches a preset threshold.

9. A computer device, wherein, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the method for constructing a 3D chip layout model as described in claim 6 or the 3D chip layout method as described in any one of claims 7 to 8.

10. A storage medium, wherein, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. The computer program is configured to implement the steps of the method for constructing a 3D chip layout model as described in claim 6 or the 3D chip layout method as described in any one of claims 7 to 8.

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