Integrated oscillator and manufacturing method therefor

Abstract

The present application relates to the technical field of oscillators, and provides an integrated oscillator and a manufacturing method therefor. In the present application, the method comprises: providing conductive members in a base body; forming a driving circuit structure on a side surface of the base body, wherein the conductive members are electrically connected to the driving circuit structure; and sequentially stacking a bottom electrode layer, a piezoelectric layer, and a top electrode layer to form a beam structure, wherein the bottom electrode layer and the top electrode layer are both electrically connected to the conductive members. The driving circuit structure and the beam structure are integrated on two sides of the base body, such that the overall size of an oscillator is reduced; and the driving circuit structure and the beam structure are electrically connected by means of the conductive members in the base body, realizing electrical interconnection, simplifying the preparation steps, and making the connection more stable than external welding.

Description

An integrated oscillator and its fabrication method

[0001] This application claims priority to Chinese Patent Application No. 202411611517.4, filed on November 12, 2024, entitled "An Integrated Oscillator and a Method for its Fabrication", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of oscillator technology, and more specifically, to an integrated oscillator and its fabrication method. Background Technology

[0003] Micro-Electro-Mechanical Systems (MEMS) are a technology that integrates micro-mechanical structures and electronic functions onto a single chip. Their applications are wide-ranging, including MEMS sensors and MEMS oscillators. MEMS oscillators utilize micro-mechanical resonators to generate high-precision time-frequency signals. MEMS oscillators can be categorized into electrostatically driven and piezoelectrically driven types based on their resonance driving methods.

[0004] In the prior art, piezoelectric driven MEMS oscillators include MEMS resonators and driving circuits. After the MEMS resonator and driving circuits are packaged separately, they are integrated by stacking them on top of each other using packaging technology such as Quad Flat No-leads Package (QFN).

[0005] However, the above structure is relatively large in size. Summary of the Invention

[0006] This application provides an integrated oscillator and its fabrication method to solve the problem of large size in existing oscillator structures.

[0007] To achieve the above objectives, the technical solution of this application is as follows:

[0008] On one hand, this application provides a method for fabricating an integrated oscillator, comprising: setting a conductive element in a substrate; forming a driving circuit structure on the side of the substrate; electrically connecting the conductive element to the driving circuit structure; sequentially stacking a bottom electrode layer, a piezoelectric layer, and a top electrode layer on the substrate to form a beam structure; and electrically connecting both the bottom electrode layer and the top electrode layer to the conductive element.

[0009] In one possible implementation, the fabrication method provided in this application involves sequentially stacking a bottom electrode layer, a piezoelectric layer, and a top electrode layer on a substrate to form a beam structure. The method includes: providing two connection holes on the substrate to expose the end of a conductive element facing away from the driving circuit structure, wherein two conductive elements are provided; depositing a bottom electrode layer within one connection hole onto the substrate; and sequentially stacking a piezoelectric layer and a top electrode layer on the bottom electrode layer, with both the bottom and top electrode layers located on one side of the connection hole, and the top electrode layer extending into the other connection hole to connect with the conductive element.

[0010] In one possible implementation, the fabrication method provided in this application embodiment includes two connection holes on the substrate, comprising: sequentially stacking a top silicon layer, a buried oxide layer, and a substrate silicon to form a substrate; and providing connection holes on the top silicon layer and the buried oxide layer, wherein the conductive element is located on the substrate silicon.

[0011] In one possible implementation, the fabrication method provided in this application embodiment involves sequentially stacking a top silicon layer, a buried oxide layer, and a substrate silicon to form a substrate, including: depositing a buried oxide layer with a thickness of 1 μm to 5 μm on a top silicon layer with a thickness of 2 μm to 20 μm, and depositing a substrate silicon with a thickness of 300 μm to 800 μm on the buried oxide layer, wherein the substrate silicon has a cavity with a depth of 2 μm to 5 μm, and a width and length of 400 μm to 500 μm.

[0012] In one possible implementation, the preparation method provided in this application embodiment, which involves setting a conductive element in a substrate, includes: setting a through hole in the substrate; setting a passivation layer on the surface of the substrate and the surface of the inner wall of the through hole; and setting the conductive element inside the through hole.

[0013] In one possible implementation, the fabrication method provided in this application embodiment involves forming through holes in the substrate, including etching through holes with a diameter of 10µm to 200µm using photolithography and DRIE processes.

[0014] In one possible implementation, the fabrication method provided in this application embodiment involves forming two connection holes on the substrate, including: sequentially etching the top silicon layer and the buried oxide layer through photolithography, DRIE, and RIE processes to form connection holes; the diameter of the connection holes is larger than that of the through holes.

[0015] In one possible implementation, the fabrication method provided in this application embodiment involves sequentially stacking a bottom electrode layer, a piezoelectric layer, and a top electrode layer on a substrate to form a beam structure. The method includes: depositing a piezoelectric layer with a thickness of 500 nm to 2000 nm on a bottom electrode layer 310 with a thickness of 20 nm to 100 nm using a PVD process; depositing a top electrode layer with a thickness of 20 nm to 500 nm on the piezoelectric layer; patterning the bottom electrode layer using photolithography and etching processes; sequentially patterning the piezoelectric layer and the top electrode layer using photolithography, IBE, and ICP etching processes; and removing the top silicon layer using photolithography and DRIE dry etching processes to form the beam structure.

[0016] In one possible implementation, the fabrication method provided in this application embodiment forms a driving circuit structure on the side of a substrate, including: forming the driving circuit structure on the side of the substrate silicon using a CMOS process, 40nm to 180nm process, and passivating the side of the substrate silicon.

[0017] On the other hand, this application also provides an integrated oscillator, which is prepared by the preparation method in any of the above embodiments, including: a substrate, a driving circuit structure and a beam structure; the driving circuit structure and the beam structure are respectively disposed on opposite sides of the substrate, a conductive element is disposed in the substrate, the driving circuit structure and the beam structure are electrically connected through the conductive element, one end of the beam structure is connected to the substrate, and the other end of the beam structure is suspended above the substrate.

[0018] The integrated oscillator and its fabrication method provided in this application involve: placing conductive components within a substrate; forming a drive circuit structure on the side of the substrate; electrically connecting the conductive components to the drive circuit structure; and sequentially stacking a bottom electrode layer, a piezoelectric layer, and a top electrode layer on the substrate to form a beam structure; both the bottom and top electrode layers are electrically connected to the conductive components. By integrating the drive circuit structure and the beam structure on both sides of the substrate, the overall size of the oscillator can be reduced. Furthermore, the electrical connection between the drive circuit structure and the beam structure via the conductive components within the substrate achieves electrical interconnection, simplifying the fabrication process and resulting in a more stable connection compared to external welding. Attached Figure Description

[0019] Figure 1 is a schematic diagram of the integrated oscillator provided in an embodiment of this application;

[0020] Figure 2 is a structural schematic diagram of the integrated oscillator in Figure 1 from another perspective;

[0021] Figure 3 is a schematic diagram of the integrated oscillator fabrication process shown in Figure 1.

[0022] Figure 4 is a schematic diagram of the integrated oscillator fabrication process shown in Figure 1.

[0023] Figure 5 is a schematic diagram of the fabrication process of the integrated oscillator in Figure 1.

[0024] Figure 6 is a schematic diagram of the fabrication process of the integrated oscillator in Figure 1.

[0025] Figure 7 is a schematic diagram of the fabrication process of the integrated oscillator in Figure 1.

[0026] Figure 8 is a schematic diagram of the fabrication process of the integrated oscillator in Figure 1.

[0027] Figure 9 is a schematic diagram of the fabrication process of the integrated oscillator in Figure 1.

[0028] Figure 10 is a schematic diagram of the fabrication process of the integrated oscillator in Figure 1.

[0029] Figure 11 is a schematic diagram of the fabrication process of the integrated oscillator in Figure 1.

[0030] Figure 12 is a schematic diagram of the integrated oscillator fabrication process in Figure 1.

[0031] Figure 13 is a structural schematic diagram of the beam structure in Figure 1;

[0032] Figure 14 is a schematic diagram of the drive circuit structure in Figure 1;

[0033] Figure 15 is a flowchart of the integrated oscillator fabrication method in an embodiment of this application.

[0034] Explanation of reference numerals in the attached figures: 100-Substrate; 110-Conductive component; 120-Cavity; 130-Through hole; 140-Top silicon layer; 150-Buried oxide layer; 160-Substrate silicon; 170-Passivation layer; 200-Drive circuit structure; 210-Electrical connector; 300-Beam structure; 310-Bottom electrode layer; 320-Piezoelectric layer; 330-Top electrode layer.

[0035] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0037] It should be noted that in the description of the embodiments of this application, the terms "upper", "lower", "inner", "outer" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of description, and are not intended to indicate or imply that the device or component must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this application.

[0038] Furthermore, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0039] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "fixation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0040] CMOS technology, short for Complementary Metal-Oxide-Semiconductor (CMOS), is a semiconductor manufacturing technology used to manufacture integrated circuits.

[0041] PECVD deposition, short for Plasma-Enhanced Chemical Vapor Deposition, is a process used to deposit thin films on a substrate.

[0042] PVD (Physical Vapor Deposition) is a thin film deposition technology used to deposit thin films on solid surfaces.

[0043] IBE (ion beam mixing or ion beam doping) is a process that uses ion beam technology to dope or mix semiconductor materials.

[0044] ICP dry etching refers to a dry etching process using inductively coupled plasma (ICP) technology.

[0045] RIE (Reactive Ion Etching) is a dry etching process that uses reactive gases to react with the material surface in a plasma environment to achieve precise etching.

[0046] Micro-Electro-Mechanical Systems (MEMS) are a technology that integrates micro-mechanical structures and electronic functions onto a single chip. Their applications are wide-ranging, including MEMS sensors and MEMS oscillators. MEMS oscillators utilize micro-mechanical resonators to generate high-precision time-frequency signals. MEMS oscillators can be categorized into electrostatically driven and piezoelectrically driven types based on their resonance driving methods.

[0047] In existing technologies, piezoelectrically driven MEMS oscillators include a MEMS resonator and a driving circuit. The MEMS resonator and driving circuit are packaged separately and then integrated using a stacked configuration and packaging technology, such as a Quad Flat No-leads Package (QFN). However, this structure is relatively large.

[0048] In view of this, this application provides an integrated oscillator and its fabrication method, comprising: setting a conductive element within a substrate; forming a driving circuit structure on the side of the substrate; electrically connecting the conductive element to the driving circuit structure; sequentially stacking a bottom electrode layer, a piezoelectric layer, and a top electrode layer on the substrate to form a beam structure; and electrically connecting both the bottom electrode layer and the top electrode layer to the conductive element. By integrating the driving circuit structure and the beam structure on both sides of the substrate, the overall size of the oscillator can be reduced. Furthermore, the driving circuit structure and the beam structure are electrically connected through the conductive element within the substrate, achieving electrical interconnection, simplifying the fabrication steps, and providing a more stable connection compared to external welding.

[0049] This application will be described in conjunction with Figures 1 to 15 and specific embodiments. Figure 1 is a structural schematic diagram of the integrated oscillator provided in the embodiment of this application; Figure 2 is a structural schematic diagram of the integrated oscillator in Figure 1 from another perspective; Figure 3 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 1); Figure 4 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 2); Figure 5 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 3); Figure 6 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 4); Figure 7 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 5); Figure 8 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 6); Figure 9 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 7); Figure 10 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 8); Figure 11 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 9); Figure 12 is a structural schematic diagram of the integrated oscillator in Figure 1 during the fabrication process (Figure 1, 10); Figure 13 is a structural schematic diagram of the beam structure in Figure 1; Figure 14 is a structural schematic diagram of the drive circuit structure in Figure 1.

[0050] On one hand, this application provides a method for fabricating an integrated oscillator, including: S100, setting a conductive element 110 in a substrate 100; S200, forming a driving circuit structure 200 on the side of the substrate 100; S300, electrically connecting the conductive element 110 to the driving circuit structure 200; S400, sequentially stacking a bottom electrode layer 310, a piezoelectric layer 320, and a top electrode layer 330 on the substrate 100 to form a beam structure 300; both the bottom electrode layer 310 and the top electrode layer 330 are electrically connected to the conductive element 110.

[0051] The substrate 100 is a cavity-bonded silicon-on-insulator (C-SOI) wafer. The structure of the substrate 100 is shown in Figure 3. The substrate 100 includes a top silicon layer 140, a buried oxide layer 150, and a substrate silicon 160 stacked sequentially. A cavity 120 is disposed within the substrate silicon 160. This application does not limit the size and structure of the substrate 100. For example, a buried oxide layer 150 with a thickness of 1 μm to 5 μm is disposed on the top silicon layer 140 with a thickness of 2 μm to 20 μm, and a substrate silicon 160 with a thickness of 300 μm to 800 μm is disposed on the buried oxide layer 150. The substrate silicon 160 contains a cavity 120 with a depth of 2 μm to 5 μm, and a width and length of 400 μm to 500 μm. For example, the thickness of the substrate silicon 160 is 500 μm, the thickness of the buried oxide layer 150 is 3 μm, the thickness of the top silicon layer 140 is 5 μm, the cavity 120 has a depth of 3 μm, and the width and length of the cavity 120 are both 500 μm.

[0052] To fabricate a conductive element 110 within the substrate 100, a via 130 needs to be fabricated in the substrate 100 first, as shown in Figure 4. The via 130 is fabricated on the substrate silicon 160 using TSV technology, and etched using photolithography and DRIE processes. The diameter of the via 130 is 10µm to 200µm. Etching stops when the buried oxide layer 150 is reached. The via 130 is fabricated on the substrate silicon 160 of the substrate 100 using TSV technology, and etched using photolithography and DRIE processes. The diameter of the via 130 is 10µm to 200µm. Etching stops when the buried oxide layer 150 is reached, thus forming the via shown in Figure 4.

[0053] A passivation layer 170 is provided on the surface of the substrate 100 and the inner wall of the through hole 130, that is, a SiO2 passivation layer 170 is formed by thermal oxidation process, with a thickness of 0.1um to 2um, as shown in Figure 5.

[0054] A passivation layer 170 is formed on the surface of the substrate 100 and the inner wall of the via 130, and a conductive element 110 is disposed within the via 130. Specifically, an adhesion layer or a barrier layer is grown on the inner wall of the via 130 and the surface of the substrate silicon 160 by magnetron sputtering. The sputtered metal is titanium (Ti), tungsten titanide (TiW), or titanium nitride (TiN), with a thickness of 0.1 μm to 1 μm, as shown in Figure 6.

[0055] The conductive component 110 is made of metallic copper (Cu). Through an electroplating process, the surface of the through hole 130 and the substrate silicon 160 is filled with metallic copper, as shown in Figure 7.

[0056] The copper metal on the surface of the silicon 160 substrate is removed by CMP (Chemical Mechanical Polishing), as shown in Figure 8. CMP is a process used to remove material or smooth a surface.

[0057] A driving circuit structure 200 is set on one side of the substrate 100 using a CMOS process, that is, an ASIC driving circuit is fabricated on the C-SOI wafer substrate using a CMOS process with a 40-180nm process. The substrate surface is then passivated, and silicon oxide or silicon nitride is deposited by PECVD, as shown in Figure 9.

[0058] The area corresponding to the via 130 in the top silicon layer 140 is photolithographically etched. The top silicon layer 140 and the buried oxide layer 150 are then etched sequentially using DRIE and RIE processes to form a connection hole 180, exposing copper leads. This is the end of the conductive element 110 that faces away from the driving circuit structure 200. Specifically, the connection hole 180 is formed on the top silicon layer 140 and the buried oxide layer 150, where the conductive element 110 is located in the via 130 of the substrate silicon 160. The connection hole 180 communicates with the via 130, as shown in Figure 10. It should be noted that the diameter of the connection hole 180 is larger than that of the via 130.

[0059] Two connection holes 180 are provided on the substrate 100 to expose one end of the conductive element 110 away from the drive circuit structure 200, wherein two conductive elements 110 are provided; a bottom electrode layer 310 is provided in one connection hole 180 and on the substrate 100; a piezoelectric layer 320 and a top electrode layer 330 are sequentially stacked on the bottom electrode layer 310, both the bottom electrode layer 310 and the top electrode layer 330 are located on one side of the connection hole 180, and the top electrode layer 330 extends into the other connection hole 180 to connect with the conductive element 110.

[0060] The bottom electrode of the MEMS component is fabricated using metal deposition, employing PVD technology to deposit molybdenum, gold, or platinum with a thickness of 20–100 nm. The bottom electrode layer 310 is patterned using photolithography and etching processes, and the interconnection between the beam structure 300 and the input electrode of the drive circuit structure 200 is achieved, as shown in Figure 11.

[0061] A piezoelectric film, using AlN or PZT, is deposited using PVD technology to a thickness of 500–2000 nm. A top electrode metal, molybdenum, gold, or platinum, is then deposited to a thickness of 20 nm–500 nm. The top metal is removed using photolithography and IBE dry etching to pattern the top electrode. A piezoelectric electrode layer 320 with a thickness of 500 nm–2000 nm is deposited on a bottom electrode layer 310 with a thickness of 20 nm–100 nm using PVD. A top electrode layer 330 with a thickness of 20 nm–500 nm is then deposited on the piezoelectric electrode layer 320. The bottom electrode layer 310 is patterned using photolithography and etching processes. The piezoelectric electrode layer 320 is patterned using photolithography, IBE, and ICP etching processes. The top electrode layer 330 is patterned using photolithography and IBE etching processes. (See Figures 12 and 2.)

[0062] The top silicon layer 140 is removed by photolithography and DRIE dry etching process to form the beam structure 300. Finally, the buried oxide layer 150 is released by RIE dry etching, as shown in Figure 1.

[0063] On the other hand, this application also provides an integrated oscillator, which is prepared by the preparation method in any of the above embodiments, including: a substrate 100, a drive circuit structure 200 and a beam structure 300; the drive circuit structure 200 and the beam structure 300 are respectively disposed on opposite sides of the substrate 100, a conductive element 110 is disposed in the substrate 100, the drive circuit structure 200 and the beam structure 300 are electrically connected through the conductive element 110, one end of the beam structure 300 is connected to the substrate 100, and the other end of the beam structure 300 is suspended above the substrate 100.

[0064] Specifically, the base 100, the drive circuit structure 200, and the beam structure 300 are respectively disposed on opposite sides of the base 100. Two conductive elements 110 and a cavity 120 are disposed within the base 100. The conductive elements 110 are disposed on one side of the cavity 120, and one end of the beam structure 300 is suspended above the cavity 120, while the other end of the beam structure 300 is connected to the base 100. It should be noted that one end of one conductive element 110 is connected to the top electrode of the beam structure 300, and one end of the other conductive element 110 is connected to the bottom electrode of the beam structure 300. The other ends of both conductive elements 110 are connected to the drive circuit structure 200.

[0065] The beam structure 300 includes a first beam, a second beam, and a connecting beam. The first beam and the second beam are arranged opposite to each other and connected by the connecting beam. One end of both the first beam and the second beam is connected to the base 100.

[0066] The substrate 100 includes a top silicon layer 140, a buried oxide layer 150, and a substrate silicon 160 arranged sequentially from bottom to top. A cavity 120 is provided on the side of the substrate silicon 160 facing the buried oxide layer 150. A through-hole 130 sequentially penetrates the top silicon layer 140, the buried oxide layer 150, and the substrate silicon 160. Two through-holes are provided on the substrate 100, and conductive components 110 are connected to each through-hole and embedded in the through-holes. Specifically, the inner wall of the through-hole 130 is provided with silicon oxide.

[0067] The beam structure 300 includes a bottom electrode layer 310, a piezoelectric layer 320, and a top electrode layer 330. The piezoelectric layer 320 is located between the bottom electrode layer 310 and the top electrode layer 330. The piezoelectric layer 320 has a piezoelectric pattern, the top electrode layer 330 has a top electrode pattern, and the bottom electrode layer 310 has a bottom electrode pattern.

[0068] Specifically, the piezoelectric layer 320 is located between the bottom electrode layer 310 and the top electrode layer 330. The piezoelectric layer 320 has a piezoelectric pattern, which is formed by removing the piezoelectric layer through photolithography and ICP dry etching processes. The top electrode layer 330 has a top electrode pattern, which is formed by removing the top metal through photolithography and IBE dry etching processes. The bottom electrode layer 310 has a bottom electrode pattern. In some embodiments, one end of the piezoelectric layer 320 is connected to the top silicon layer 140. In some embodiments, neither end of the piezoelectric layer 320 is connected to the top silicon layer 140.

[0069] In some embodiments, the top electrode layer 330 is arranged sequentially from the conductive member 110 to above the piezoelectric layer 320, and the bottom electrode layer 310 is arranged sequentially from the conductive member 110 to below the piezoelectric layer 320, with the piezoelectric layer 320 sandwiched between the top electrode layer 330 and the bottom electrode layer 310. For example, some of the piezoelectric layers 320 are arranged in parallel, and some of the piezoelectric layers 320 are arranged at an angle.

[0070] At least one side of the drive circuit structure 200 is provided with an electrical connector 210, which is used to connect to the power supply circuit. For example, there are four electrical connectors 210, arranged in pairs opposite each other on both sides of the drive circuit structure 200. The outer frame of the drive circuit structure 200 is square or rectangular; this embodiment does not impose any limitation on this.

[0071] Conductive elements 110 are disposed within the substrate 100 using magnetron sputtering and electroplating processes; a driving circuit structure 200 is disposed on one side of the substrate 100 using CMOS processes; a bottom electrode layer 310, a piezoelectric layer 320, and a top electrode layer 330 are sequentially deposited on the side of the substrate 100 opposite to the driving circuit structure 200, and a beam structure 300 is disposed using photolithography and DRIE dry etching processes; the beam structure 300 is electrically connected to the driving circuit structure 200 via conductive elements 110 through metal deposition so that both the bottom electrode layer 310 and the top electrode layer 330 are electrically connected to the driving circuit structure 200 through conductive elements 110.

[0072] In this application, the position and shape of the via 130 are defined by photolithography, then precise etching is performed using the DRIE process, and finally conductive material is filled into the etched via 130 to establish an electrical connection.

[0073] The substrate 100 is placed on a worktable; vias 130 are etched on the substrate silicon 160 of the substrate 100 using photolithography and DRIE processes; conductive elements 110 are filled in the vias 130 and on one side of the substrate silicon 160 using magnetron sputtering and electroplating processes; a driving circuit structure 200 is set on the substrate silicon 160 using CMOS processes; photolithography is performed in the area of ​​the vias 130 corresponding to the top silicon layer 140, and the top silicon layer and buried oxide layer are etched using DRIE and RIE processes; the bottom electrode layer 310 is electrically connected to the conductive elements 110 by metal deposition; a bottom electrode pattern is set on the bottom electrode layer 310 using photolithography and etching processes; a piezoelectric layer 320 and a top electrode layer 330 are sequentially deposited on the bottom electrode layer 310; the bottom electrode pattern and top electrode pattern are set using photolithography, IBE, and ICP etching processes; the top silicon layer is removed using photolithography and DRIE dry etching processes, and the beam structure 300 is etched.

[0074] TSV stands for Through-Silicon Via, a technique for creating tiny, perpendicular vias in a semiconductor wafer. These vias establish electrical connections between different layers of the wafer. TSV involves the following steps: Etching: Vertical vias are etched into the wafer using etching techniques such as Deep Reactive Ion Etching (DRIE). Filling: The vias are filled with metal or other conductive material to establish electrical connections. Sealing: To protect the vias and the filler material, they are typically sealed.

[0075] Photolithography is a key technology in semiconductor manufacturing used to transfer circuit patterns onto the surface of a wafer. Before creating TSV (Through-Video) holes, photolithography is typically used to define the areas to be etched. In this process, photoresist and a mask are used to define the location and shape of the vias, and then ultraviolet light or other light sources are used to illuminate the pattern on the mask, causing a chemical change in the photoresist in the corresponding areas.

[0076] DRIE (Deep Reactive Ion Etching) is an advanced process for etching semiconductor materials such as silicon. DRIE achieves deep and uniform etching, making it ideal for fabricating TSV (Through-Video) holes because it can precisely etch the required depth and dimensions without damaging the wafer's surface layer.

[0077] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0078] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for fabricating an integrated oscillator, characterized in that, include: A conductive element (110) is disposed within the substrate (100); A drive circuit structure (200) is formed on the side of the substrate (100); the conductive element (110) is electrically connected to the drive circuit structure (200); A bottom electrode layer (310), a piezoelectric layer (320), and a top electrode layer (330) are sequentially stacked on the substrate (100) to form a beam structure (300); Both the bottom electrode layer (310) and the top electrode layer (330) are electrically connected to the conductive element (110).

2. The method for fabricating an integrated oscillator according to claim 1, characterized in that, The method of sequentially stacking a bottom electrode layer (310), a piezoelectric layer (320), and a top electrode layer (330) on the substrate (100) to form a beam structure (300) includes: Two connection holes (180) are provided on the substrate (100) to expose one end of the conductive element (110) away from the driving circuit structure (200), wherein two conductive elements (110) are provided; The bottom electrode layer (310) is disposed within the connection hole (180) and onto the substrate (100); The piezoelectric layer (320) and the top electrode layer (330) are stacked sequentially on the bottom electrode layer (310). The bottom electrode layer (310) and the top electrode layer (330) are both located on one side of the connection hole (180). The top electrode layer (330) extends into another connection hole (180) to connect with the conductive element (110).

3. The method for fabricating the integrated oscillator according to claim 2, characterized in that, The substrate (100) is provided with two connecting holes (180), including: The substrate (100) is formed by sequentially stacking a top silicon layer (140), a buried oxide layer (150), and a substrate silicon layer (160); The connection hole (180) is provided on the top silicon layer (140) and the buried oxide layer (150), wherein the conductive element (110) is located on the substrate silicon (160).

4. The method for fabricating the integrated oscillator according to claim 3, characterized in that, The sequential stacking of a top silicon layer (140), a buried oxide layer (150), and a substrate silicon layer (160) to form the substrate (100) includes: A buried oxide layer (150) with a thickness of 1 μm to 5 μm is disposed on the top silicon layer (140) with a thickness of 2 μm to 20 μm, and a substrate silicon (160) with a thickness of 300 μm to 800 μm is disposed on the buried oxide layer (150). A cavity (120) is provided in the substrate silicon (160), the cavity (120) having a depth of 2 μm to 5 μm, and the width and length of the cavity (120) being 400 μm to 500 μm.

5. The method for fabricating an integrated oscillator according to claim 3, characterized in that, The provision of a conductive element (110) within the substrate (100) includes: A through hole (130) is provided in the substrate (100); A passivation layer (170) is provided on the surface of the substrate (100) and the surface of the inner wall of the through hole (130), and the conductive element (110) is disposed in the through hole (130).

6. The method for fabricating an integrated oscillator according to claim 5, characterized in that, The provision of a through hole (130) in the substrate (100) includes: The vias (130) with diameters of 10µm to 200µm were etched using photolithography and DRIE processes.

7. The method for fabricating an integrated oscillator according to any one of claims 3 to 5, characterized in that, The substrate (100) is provided with two connecting holes (180), including: The top silicon layer (140) and the buried oxide layer (150) are sequentially etched using photolithography, DRIE, and RIE processes to form the connection hole (180); The diameter of the connecting hole (180) is larger than that of the through hole (130).

8. The method for fabricating an integrated oscillator according to any one of claims 1-4, characterized in that, The method of sequentially stacking a bottom electrode layer (310), a piezoelectric layer (320), and a top electrode layer (330) on the substrate (100) to form a beam structure (300) includes: On the bottom electrode layer (310) with a thickness of 20 nm to 100 nm, a pressure electrode layer (320) with a thickness of 500 nm to 2000 nm is deposited by PVD process, and a top electrode layer (330) with a thickness of 20 nm to 500 nm is deposited on the pressure electrode layer (320). The bottom electrode layer (310) is patterned by photolithography and etching processes, the pressure electrode layer (320) is patterned by photolithography and ICP etching processes, and the top electrode layer (330) is patterned by photolithography and IBE processes. The top silicon layer (140) is removed by photolithography and DRIE dry etching process, and the beam structure (300) is formed by etching.

9. The method for fabricating an integrated oscillator according to claim 8, characterized in that, The formation of a drive circuit structure (200) on the side of the substrate (100) includes: The driving circuit structure (200) is formed on the side of the substrate silicon (160) of the substrate (100) by means of CMOS process, 40nm to 180nm process, and the side of the substrate silicon (160) is passivated.

10. An integrated oscillator, characterized in that, The integrated oscillator is prepared by any of the above-mentioned methods, including: The substrate (100), the drive circuit structure (200), and the beam structure (300) are all present. The driving circuit structure (200) and the beam structure (300) are respectively disposed on opposite sides of the base (100). A conductive element (110) is disposed inside the base (100). The driving circuit structure (200) and the beam structure (300) are electrically connected through the conductive element (110). One end of the beam structure (300) is connected to the base (100), and the other end of the beam structure (300) is suspended above the base (100).

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