Partitioned transfer circuit, gate drive circuit, gate driver, control method, and display apparatus
By designing partitioned transmission circuits and gate drive circuits, low power consumption and partitioned refresh of the display device are achieved, solving the problem of balancing power consumption and display effect in the existing technology and meeting the refresh rate requirements of different areas.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
- Filing Date
- 2025-04-07
- Publication Date
- 2026-05-21
AI Technical Summary
How to reduce the power consumption of display devices while maintaining display quality, especially in different scenarios, to achieve high refresh rates in some areas and low refresh rates in others.
By employing a partitioned transmission circuit and a gate drive circuit, and through the combination of a transmission module, a control module, and a refresh adjustment module, the partitioned transmission and control of the drive signal is realized, ensuring that some areas maintain a low refresh rate while other areas refresh normally.
It achieves low power consumption and partitioned refresh in the display device, while maintaining display quality and meeting the display needs of different scenarios.
Smart Images
Figure CN2025087419_21052026_PF_FP_ABST
Abstract
Description
Partition transmission, gate drive circuit and driver, control method and display device
[0001] Cross-references to related applications
[0002] This disclosure claims priority to Chinese Patent Application No. 202411639652X, filed on November 15, 2024, entitled "Partition Transfer, Gate Drive Circuit and Driver, Control Method and Display Device", the entire contents of which are incorporated herein by reference. Technical Field
[0003] This invention relates to the field of display technology, and in particular to a partition transfer, gate driving circuit and driver, control method and display device. Background Technology
[0004] Compared to traditional liquid crystal display devices, organic light-emitting diode (OLED) display devices have advantages such as faster response speed, better color purity and brightness, higher contrast, and wider viewing angle, and therefore have gradually gained increasing attention from display technology developers.
[0005] Among them, the Gate Driver on Array (GOA) technology integrates the gate switching circuit of the thin film transistor (TFT) on the array substrate of the display device to form a gate driver for the display device.
[0006] Figure 1 illustrates a gate driver based on related technology. A gate driver typically consists of multiple cascaded gate drive circuits. Each stage of the gate drive circuit includes a shift register, and the drive signal output terminals of the shift registers are respectively connected to a scan gate line. Furthermore, in two cascaded gate drive circuits, the drive signal of the preceding stage gate drive circuit serves as the input signal for the following stage gate drive circuit.
[0007] During the operation of an OLED display device, the input signal is converted into an on / off drive signal by a shift register through a gate drive circuit. This signal is then applied sequentially to the scanning grid lines of each row of pixels in the OLED display device to select each row of pixels and achieve display refresh.
[0008] As shown in Figure 1, each stage of the gate drive circuit passes down step by step, and the drive signal output by each stage is passed to the AA area in the current row. Therefore, both high and low level signals will be passed to the AA area.
[0009] Currently, reducing the power consumption of display devices is a problem.
[0010] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0011] In view of the problems in the prior art, the purpose of the present invention is to provide partition transmission, gate driving circuit and driver, control method and display device, which overcome the difficulties of the prior art and can take into account the low power consumption and display effect of the display device.
[0012] The first aspect of this disclosure provides a partition transfer circuit for a gate drive circuit, comprising:
[0013] The transmission module connects the drive signal output terminal and the partition signal output terminal of the shift register in the same row, and is used to input the drive signal of the drive signal output terminal to the partition signal output terminal under the control of the first clock signal terminal.
[0014] The first control module is connected to the first level signal terminal and the first node. Under the control of the second clock signal terminal, it inputs the first level signal of the first level signal terminal to the first node. The first clock signal terminal and the second clock signal terminal have the same period and opposite voltage polarities.
[0015] The second control module is connected to the first node and the second level signal terminal. Under the control of the first clock signal terminal, it inputs the second level signal of the second level signal terminal into the first node. The voltage polarity of the second level signal is opposite to that of the first level signal.
[0016] The refresh adjustment module is connected to the second level signal terminal and the partition signal output terminal. It is used to transmit the second level signal of the second level signal terminal to the partition signal output terminal under the control of the first level signal of the first node, and to block the transmission of the second level signal to the partition signal output terminal under the control of the second level signal of the first node.
[0017] In some embodiments, the transmission module includes:
[0018] The first transistor has its gate connected to the first clock signal terminal, its source connected to the drive signal output terminal, and its drain connected to the partition signal output terminal.
[0019] In some embodiments, the first control module includes:
[0020] The second transistor has its gate connected to the second clock signal terminal, its source connected to the first level signal terminal, and its drain connected to the first node.
[0021] In some embodiments, the refresh adjustment module includes:
[0022] The third transistor has its gate connected to the first node, its source connected to the second level signal terminal, and its drain connected to the partition signal output terminal.
[0023] In some embodiments, the second control module includes:
[0024] The fourth transistor has its gate connected to the first clock signal terminal, its source connected to the second level signal terminal, and its drain connected to the first node.
[0025] A second aspect of this disclosure provides a gate driving circuit, comprising:
[0026] Shift register;
[0027] In any of the above embodiments of the partition transfer circuit, the drive signal output terminal of the shift register is connected to the transmission module in the partition transfer circuit.
[0028] In some embodiments, the shift register includes:
[0029] The first input module is connected to the first level signal terminal and the second node, and is used to write the first level signal of the first level signal terminal into the second node under the control of the third clock signal terminal;
[0030] A first output module and a first capacitor, wherein the first output module is connected to the second level signal terminal and the drive signal output terminal, and is used to input the second level signal of the second level signal terminal to the drive signal output terminal under the control of the second node; the first capacitor is connected to the second level signal terminal and the second node.
[0031] The second input module connects the signal input terminal and the third node, and is used to write the input signal from the signal input terminal into the third node under the control of the third clock signal terminal.
[0032] The second output module is connected to the fourth clock signal terminal CKV1 and the drive signal output terminal. It is used to input the fourth clock signal of the fourth clock signal terminal to the drive signal output terminal under the control of the third node. The second capacitor is connected to the third node and the drive signal output terminal. The third clock signal and the fourth clock signal have the same period and opposite voltage polarities.
[0033] The third control module is connected to the third clock signal terminal and the second node, and is used to write the third clock signal of the third clock signal terminal into the second node under the control of the third node.
[0034] The fourth control module, connected to the second level signal terminal and the second node, is used to write the second level signal into the third node under the control of the fourth clock signal terminal and the second node;
[0035] The delay module connects the third node and the fifth node and is used to keep the signal on under the control of the first level signal terminal, delay the input of the signal from the third node to the fifth node, so that the third node controls the second output module through the fifth node.
[0036] A third aspect of this disclosure provides a control method for a gate drive circuit based on any of the above embodiments, comprising:
[0037] During the first time period, when the shift register connected to the partition transmission circuit in the same row executes a positive base frequency refresh rate, the first clock signal terminal controls the transmission module to input the output signal of the signal output terminal into the partition signal output terminal, and controls the second control module to write the second level signal into the first node, so as to control the refresh adjustment module to turn off through the first node;
[0038] During the second time period, the transmission module and the second control signal are turned off by controlling the first clock signal terminal, and the first control module is controlled by controlling the second clock signal terminal to write the first level signal into the first node, so as to control the refresh adjustment module to input the second level signal into the partition signal output terminal.
[0039] A fourth aspect of this disclosure provides a gate driver that includes a plurality of gate driving circuits according to any of the above embodiments;
[0040] The multiple gate drive circuits are electrically coupled in a cascaded manner, wherein the signal input terminal of the shift register in the first-stage gate drive circuit is coupled to the start pulse signal, and except for the last-stage gate drive circuit, the signal output terminal of the shift register in each of the other stages of the gate drive circuit is coupled to the signal input terminal of the shift register in the next stage of the gate drive circuit.
[0041] The fifth aspect of this disclosure provides a display device including the gate driver of the above embodiments.
[0042] As can be seen from the above, using the partition transmission circuit and the gate driving circuit including the partition transmission circuit of this embodiment, the driving signal of the shift register can be transmitted to the partition signal output terminal to maintain the original refresh rate. It can also block the transmission of the driving signal to the partition signal output terminal as needed, and simultaneously input a second-level signal to the partition signal output terminal. In this case, area AA cannot obtain an enable signal and will not refresh the next frame, thus maintaining a low refresh rate. Therefore, using the partition transmission circuit and the gate driving circuit including the partition transmission circuit of this embodiment, partitioned refresh of the display device can be achieved, balancing low power consumption and display effect.
[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0044] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0045] Figure 1 shows a structural diagram of a gate driver that includes cascaded gate drive circuitry in the related art.
[0046] Figure 2 is a circuit structure diagram of the gate driving circuit provided in an embodiment of this disclosure.
[0047] Figure 3 is a circuit structure diagram of the partition transfer circuit in the gate drive circuit shown in Figure 2.
[0048] Figure 4 shows the equivalent circuit diagram of the partitioned transfer circuit shown in Figure 3.
[0049] Figure 5 shows the timing waveforms corresponding to the partitioned transfer circuit shown in Figure 4.
[0050] Figure 6 shows the equivalent circuit diagram of the gate drive circuit shown in Figure 2.
[0051] Figure 7 shows the equivalent circuit diagram of the gate drive circuit shown in Figure 6.
[0052] Figure 8 shows the circuit structure of the gate driver using the gate drive circuit shown in Figure 2.
[0053] Figure 9 shows the timing waveforms corresponding to the gate driver shown in Figure 8.
[0054] Figure 10 shows a schematic diagram of the simulation results of the gate driver shown in Figure 8.
[0055] Figure 11 shows a schematic diagram of the display effect using the gate driver shown in Figure 8.
[0056] Figure 12 shows a flowchart of the control method based on the partitioned transmission circuit shown in Figure 3. Detailed Implementation
[0057] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0058] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0059] Furthermore, the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to define the order of functions performed by these devices, modules or units or their interdependencies.
[0060] Analysis of the gate drivers and display devices related to these technologies reveals that reduced power consumption in display devices depends on lower refresh rates. Some scenarios require high refresh rates, while others require low refresh rates, both of which are currently achievable. However, some application scenarios may not require a high or low refresh rate across the entire screen; instead, a portion of the screen may need a high refresh rate, while other static areas can maintain a low refresh rate.
[0061] This disclosure provides a gate drive circuit for partition refresh.
[0062] As shown in Figure 2, the gate drive circuit includes a shift register SR and a partition transfer circuit 3.
[0063] As shown in Figure 3, the partition transfer circuit 3 for the gate drive circuit includes:
[0064] Transmission module 31 connects the drive signal output terminal Gout and the partition signal output terminal G of the shift register in the same row. Under the control of the first clock signal terminal CLKA, it inputs the drive signal of the drive signal output terminal Gout to the partition signal output terminal G, wherein the partition signal output terminal G is used to connect to the AA (Active Area) area.
[0065] The first control module 32 is connected to the first level signal terminal VEE and the first node n1. Under the control of the second clock signal terminal CLKB, it inputs the first level signal of the first level signal terminal VEE into the first node n1. The first clock signal terminal CLKA and the second clock signal terminal CLKB have the same period and opposite voltage polarities.
[0066] The second control module 33 is connected to the first node n1 and the second level signal terminal VDD. Under the control of the first clock signal terminal CLKA, it inputs the second level signal of the second level signal terminal VDD into the first node n1. The voltage polarity of the second level signal is opposite to that of the first level signal.
[0067] The refresh adjustment module 34 is connected to the second level signal terminal VDD and the partition signal output terminal G. It is used to transmit the second level signal of the second level signal terminal VDD to the partition signal output terminal G under the control of the first level signal of the first node n1, and to block the transmission of the second level signal to the partition signal output terminal G under the control of the second level signal of the first node n1.
[0068] The working principle of the partition transmission circuit shown in Figure 3 is explained below:
[0069] During the first time period, the transmission module 31 and the second control module 33 are turned on under the control of the first clock signal terminal CLKA. The second control module 33 writes the second level signal of the second level signal terminal VDD into the first node n1 to control the refresh adjustment module 34 to turn off. The transmission module 31 directly transmits the drive signal output from the drive signal output terminal Gout to the partition signal output terminal G. The drive signal is normally output to the AA area.
[0070] During the second time period, the transmission module 31 and the second control module 33 are turned off under the control of the first clock signal terminal CLKA, and the drive signal output by the drive signal output terminal Gout is no longer transmitted to the partition signal output terminal G and AA area. The first control module 32 is turned on under the control of the second clock signal terminal CLKB to write the first level signal of the first level signal terminal VEE to the first node n1, triggering the refresh adjustment module 34 to input the second level signal of the second level signal terminal VDD into the partition signal output terminal G and AA area.
[0071] As can be seen from the above, using the partition transmission circuit and the gate driving circuit including the partition transmission circuit of this embodiment, the driving signal of the shift register can be transmitted to the partition signal output terminal to maintain the original refresh rate. It can also block the transmission of the driving signal to the partition signal output terminal as needed, and simultaneously input a second-level signal to the partition signal output terminal. In this case, area AA cannot obtain an enable signal and will not refresh the next frame, thus maintaining a low refresh rate. Therefore, using the partition transmission circuit and the gate driving circuit including the partition transmission circuit of this embodiment, partitioned refresh of the display device can be achieved, balancing low power consumption and display effect.
[0072] As shown in Figure 3, the first level signal terminal VEE outputs a low-level signal, and the second level signal terminal VDD outputs a high-level signal. Taking a Low Temperature Poly-silicon (LTPS) Active-matrix Organic Light-Emitting Diode (AMOLED) as an example, it uses a low-level signal as the enable signal for the pixel driving circuit. When the partition signal output terminal G outputs the aforementioned high-level signal, area AA cannot obtain an enable signal and will not refresh the next frame, thus maintaining a low refresh rate.
[0073] In another embodiment, depending on the application scenario, the first level signal terminal outputs a high-level signal, and the second level signal terminal outputs a low-level signal. Therefore, the voltage polarities of the first level signal and the second level signal are opposite.
[0074] As an equivalent circuit to the partitioned transmission circuit shown in Figure 3, as shown in Figure 4, the transmission module 31 includes:
[0075] The first transistor Ta has its gate connected to the first clock signal terminal CLKA, its source connected to the drive signal output terminal Gout, and its drain connected to the partition signal output terminal G.
[0076] As shown in Figure 4, the first transistor Ta is a PMOS transistor. Therefore, when the first clock signal output from the first clock signal terminal CLKA is a low-level signal, the first transistor Ta is turned on; conversely, when the first clock signal switches to a high-level signal, the first transistor Ta is turned off. In another embodiment, the first transistor can also be an NMOS transistor, which is turned on under the control of a high-level signal and turned off under the control of a low-level signal.
[0077] As shown in Figure 4, the first control module 32 includes:
[0078] The second transistor Tb has its gate connected to the second clock signal terminal CLKB, its source connected to the first level signal terminal VEE, and its drain connected to the first node n1.
[0079] In this embodiment, the second transistor Tb is a PMOS transistor. Therefore, when the second clock signal output from the second clock signal terminal CLKB is a low-level signal, the second transistor Tb is turned on; conversely, when the second clock signal switches to a high-level signal, the second transistor Tb is turned off. In another embodiment, the second transistor can also be an NMOS transistor, which is turned on under the control of a high-level signal and turned off under the control of a low-level signal.
[0080] As shown in Figure 4, the refresh adjustment module 34 includes:
[0081] The third transistor Tc has its gate connected to the first node n1, its source connected to the second level signal terminal VDD, and its drain connected to the partition signal output terminal G.
[0082] In the embodiment shown in Figure 4, the third transistor Tc is a PMOS transistor. Therefore, when a low-level first-level signal is written to the first node n1, the third transistor Tc is turned on; conversely, when a high-level second-level signal is written to the first node n1, the third transistor Tc is turned off. In another embodiment, the third transistor can also be an NMOS transistor, which is turned on under the control of a high-level signal and turned off under the control of a low-level signal.
[0083] As shown in Figure 4, the second control module 33 includes:
[0084] The fourth transistor Td has its gate connected to the first clock signal terminal CLKA, its source connected to the second level signal terminal VDD, and its drain connected to the first node n1.
[0085] In the embodiment shown in Figure 4, the fourth transistor Td is a PMOS transistor. Therefore, when the first clock signal output from the first clock signal terminal CLKA is a low-level signal, the fourth transistor Td is turned on; conversely, when the first clock signal is a high-level signal, the fourth transistor Td is turned off. In another embodiment, the fourth transistor can also be an NMOS transistor, which is turned on under the control of a high-level signal and turned off under the control of a low-level signal.
[0086] Specifically, referring to the timing waveform diagram shown in Figure 5, the working principle of the partitioned transfer circuit shown in Figure 4 is as follows:
[0087] During the first time period t1, when the current row is executing a positive base frequency refresh rate, the first clock signal terminal CLKA is a low-level signal, the first transistor Ta and the fourth transistor Td are turned on, the first node n1 is written with a high-level signal at the second level signal terminal VDD, the third transistor Tc is turned off, and the Gout signal is output to the AA area normally; at this time, the second clock signal terminal CLKB is a high-level signal, and the second transistor Tb is turned off.
[0088] During the second time period t2, when the refresh rate of the current row needs to be changed, the first clock signal terminal CLKA is a high-level signal, the first transistor Ta is turned off, the Gout signal is no longer transmitted to the AA area, the fourth transistor Td is turned off, and the second clock signal terminal CLKB is a low-level signal. The low-level signal of the first level signal terminal VEE is written to the first node n1, the third transistor Tc is turned on, and the high-level signal of the second level signal terminal VDD is input to the AA area. The AA area cannot obtain a low-level enable signal and will no longer refresh the next frame, that is, maintain a lower refresh rate.
[0089] As shown in Figure 5, when the drive signal output by Gout is a low-level signal VGL1, in order for the low-level signal VGL1 of Gout to be output normally to the AA region, the low-level signal of CLKA, VGL2 < VGL1, and VGL2 - VGL1 < Vth_Ta, where Vth_Ta is the gate voltage of the first transistor Ta. For example, if Vth = -2V and VGL1 = -8V for the first transistor Ta, then VGL2 ≤ -10V.
[0090] The first clock signal terminal CLKA changes from low to high before the second clock signal terminal CLKB changes from high to low. Furthermore, the second clock signal terminal CLKB changes from high to low before Gout changes from high to low. This ensures that the high-level signal of the second clock signal terminal VDD is promptly transmitted to area AA when Gout changes from high to low.
[0091] Furthermore, Gout transitions from a low level to a high level before the second clock signal CLKB transitions from a low level to a high level, and the second clock signal CLKB transitions from a low level to a high level before the first clock signal CLKA transitions from a high level to a low level. This ensures that when Gout transitions from a low level to a high level, the partition signal output G still maintains the high level signal of the second clock signal VDD. Then, when the first clock signal CLKA transitions from a high level to a low level, the high level signal of Gout is immediately input to G, achieving a smooth refresh.
[0092] This disclosure also provides a gate driving circuit. FIG6 is an equivalent circuit diagram of the gate driving circuit shown in FIG2. As shown in FIG6, the shift register SR includes:
[0093] The first input module 61 is connected to the first level signal terminal VEE and the second node n2, and is used to write the first level signal of the first level signal terminal VEE into the second node n2 under the control of the third clock signal terminal CKV2.
[0094] The first output module 62 and the first capacitor C1 are connected to the second level signal terminal VDD and the drive signal output terminal Gout. The first output module 62 is used to input the second level signal of the second level signal terminal VDD to the drive signal output terminal Gout under the control of the second node n2. The first capacitor C1 is connected to the second level signal terminal VDD and the second node n2.
[0095] The second input module 63 is connected to the signal input terminal STV / in and the third node n3, and is used to write the input signal of the signal input terminal STV / in into the third node n3 under the control of the third clock signal terminal CKV2.
[0096] The second output module 64 and the second capacitor C2 are connected to the fourth clock signal terminal CKV1 and the drive signal output terminal Gout. The second output module 64 is used to input the fourth clock signal of the fourth clock signal terminal CKV1 to the drive signal output terminal Gout under the control of the third node n3. The second capacitor C2 is connected to the third node n3 and the drive signal output terminal Gout. The third clock signal and the fourth clock signal have the same period and opposite voltage polarities.
[0097] The third control module 65 is connected to the third clock signal terminal CKV2 and the second node n2, and is used to write the third clock signal of the third clock signal terminal CKV2 into the second node n2 under the control of the third node n3.
[0098] The fourth control module 66 is connected to the second level signal terminal VDD and the third node, and is used to write the second level signal into the third node n3 under the control of the fourth clock signal terminal CKV1 and the second node n2.
[0099] In one implementation, the fourth control module 66 includes:
[0100] The fifth transistor T5 is connected to the second level signal terminal VDD and the fourth node n4. It is used to write the second level signal of the second level signal terminal VDD into the fourth node n4 under the control of the first node n1.
[0101] The sixth transistor T6 is connected to the fourth node n4 and the third node n3. It is used to write the second level signal of the fourth node n4 into the third node n3 under the control of the fourth clock signal terminal CKV1.
[0102] In this embodiment, both the fifth transistor T5 and the sixth transistor T6 are PMOS transistors, which are turned on under the control of a low-level signal and turned off under the control of a high-level signal.
[0103] In this embodiment of the disclosure, the shift register further includes:
[0104] The delay module 67 is connected to the third node n3 and the fifth node n5. It is used to keep the signal of the third node n3 on under the control of the first level signal terminal VEE, and to delay the signal of the third node n3 to input the signal of the fifth node n5, so that the third node n3 controls the second output module 64 through the fifth node n5.
[0105] In the above embodiment, Figure 7 is the equivalent circuit of the gate drive circuit shown in Figure 6. As shown in Figure 7, the first input module 61 includes the seventh transistor T7, the first output module 62 includes the eighth transistor T8, the second input module 63 includes the ninth transistor T9 and the tenth transistor T10 with a dual-gate structure, the second output module 64 includes the eleventh transistor T11, and the third control module 65 includes the twelfth transistor T12. These transistors are all PMOS transistors, which are turned on under the control of a low-level signal and turned off under the control of a high-level signal.
[0106] In this embodiment of the disclosure, the delay module 67 includes a thirteenth transistor T13, which is a PMOS transistor that is turned on under the control of a low-level signal and turned off under the control of a high-level signal.
[0107] This disclosure also provides a gate driver, as shown in FIG8, which includes multiple gate driving circuits of the embodiments shown in FIG6 and FIG7. The multiple gate driving circuits are electrically coupled in a cascaded manner. The signal input terminal of the shift register in the first-stage gate driving circuit is coupled to the start pulse signal. Except for the last-stage gate driving circuit, the signal output terminal of the shift register in each of the other stages of the gate driving circuit is coupled to the signal input terminal of the shift register in the next stage of the gate driving circuit.
[0108] Figure 9 shows the timing waveforms corresponding to the gate drivers shown in Figure 8. As shown in Figure 9, the high-level signal of CLKA covers all rows that need to achieve a low refresh rate, and the low-level signal of CLKB covers all rows that need to achieve a low refresh rate.
[0109] CLKA changes from low to high before CLKB changes from high to low; CLKB changes from high to low before Gout[N] changes from high to low; Gout[N+m] changes from low to high before CLKB changes from low to high; and CLKA changes from low to high before CLKB changes from high to low.
[0110] As shown in Figure 10, the simulation results of the gate driver shown in Figure 9 show that, taking the 10-level gate driving circuit as a reference, the 4th to 7th level partition transmission circuit outputs G[4] to G[7] at a high level, that is, the 4 rows are no longer refreshed at the base frequency. The 1st to 3rd level partition transmission circuit outputs G[1] to G[3], and the 8th to 10th level partition transmission circuit outputs G[8] to G
[0010] to output a low-level signal to the AA area normally, that is, normal refresh. Therefore, different refresh rates can be displayed in different areas.
[0111] Figure 11 illustrates a display effect where the top and bottom of the screen are static display areas (X), and the middle area is a dynamic display area (Y). Gray represents a low refresh rate, while the white area in the middle represents a dynamic high refresh rate, achieving zoned refresh. This not only ensures the display quality of the dynamic display area in the middle but also reduces power consumption through the low refresh rate of the static display area.
[0112] This disclosure also provides a control method for the gate drive circuit shown in Figures 6 and 7, as shown in Figure 12. The control method includes the following steps:
[0113] Step 1210, First time period: When the shift register in the same row connected to the partition transmission circuit executes a positive base frequency refresh rate, the first clock signal terminal controls the transmission module to input the output signal of the signal output terminal into the partition signal output terminal, and controls the second control module to write the second level signal into the first node, so as to control the refresh adjustment module to turn off through the first node;
[0114] Step 1220, Second time period: Control the transmission module and the second control signal to shut down through the first clock signal terminal, and control the first control module to write the first level signal to the first node through the second clock signal terminal, so as to control the refresh adjustment module to input the second level signal to the partition signal output terminal.
[0115] This embodiment also provides a display device, including the gate driver described above, and using a gate driving circuit to sequentially activate the gate scan lines in the display device. The display device also includes a source driving circuit for providing data voltage to the corresponding pixels when the gate scan lines are activated.
[0116] In one embodiment, the display device can be a variety of electronic display products, specifically including but not limited to at least one of mobile phones, tablet computers, e-book readers, media players, digital cameras, laptops, in-vehicle computers, desktop computers, set-top boxes, smart TVs, and wearable devices. Furthermore, depending on actual needs, the display device may also include other structures such as a touch-sensitive layer, a polarizing film, and a cover plate.
[0117] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A partition transfer circuit for a gate drive circuit, characterized by, include: The transmission module connects the drive signal output terminal and the partition signal output terminal of the shift register in the same row, and is used to input the drive signal of the drive signal output terminal to the partition signal output terminal under the control of the first clock signal terminal. The first control module is connected to the first level signal terminal and the first node. Under the control of the second clock signal terminal, it inputs the first level signal of the first level signal terminal to the first node. The first clock signal terminal and the second clock signal terminal have the same period and opposite voltage polarities. The second control module is connected to the first node and the second level signal terminal. Under the control of the first clock signal terminal, it inputs the second level signal from the second level signal terminal to the first node. The voltage polarity of the second level signal is opposite to that of the first level signal. The refresh adjustment module is connected to the second level signal terminal and the partition signal output terminal. It is used to transmit the second level signal of the second level signal terminal to the partition signal output terminal under the control of the first level signal of the first node, and to block the transmission of the second level signal to the partition signal output terminal under the control of the second level signal of the first node.
2. The partition transfer circuit for a gate drive circuit according to claim 1, wherein The transmission module includes: The first transistor has its gate connected to the first clock signal terminal, its source connected to the drive signal output terminal, and its drain connected to the partition signal output terminal.
3. The partition transfer circuit for a gate drive circuit according to claim 1, wherein The first control module includes: The second transistor has its gate connected to the second clock signal terminal, its source connected to the first level signal terminal, and its drain connected to the first node.
4. The partition transfer circuit for a gate drive circuit according to claim 1, wherein The refresh adjustment module includes: The third transistor has its gate connected to the first node, its source connected to the second level signal terminal, and its drain connected to the partition signal output terminal.
5. The partition transfer circuit for a gate drive circuit according to claim 1, wherein The second control module includes: The fourth transistor has its gate connected to the first clock signal terminal, its source connected to the second level signal terminal, and its drain connected to the first node.
6. A gate drive circuit characterized by comprising: include: Shift register; In any one of claims 1-5, the drive signal output terminal of the shift register is connected to the transmission module in the partition transfer circuit.
7. The gate drive circuit according to claim 6, characterized in that The shift register includes: The first input module is connected to the first level signal terminal and the second node, and is used to write the first level signal of the first level signal terminal into the second node under the control of the third clock signal terminal; A first output module and a first capacitor, wherein the first output module is connected to the second level signal terminal and the drive signal output terminal, and is used to input the second level signal of the second level signal terminal to the drive signal output terminal under the control of the second node; the first capacitor is connected to the second level signal terminal and the second node. The second input module connects the signal input terminal and the third node, and is used to write the input signal from the signal input terminal into the third node under the control of the third clock signal terminal. The second output module is connected to the fourth clock signal terminal and the drive signal output terminal. Under the control of the third node, the second output module is used to input the fourth clock signal of the fourth clock signal terminal to the drive signal output terminal. The second capacitor is connected to the third node and the drive signal output terminal. The third clock signal and the fourth clock signal have the same period and opposite voltage polarities. The third control module is connected to the third clock signal terminal and the second node, and is used to write the third clock signal of the third clock signal terminal into the second node under the control of the third node. The fourth control module, connected to the second level signal terminal and the second node, is used to write the second level signal into the third node under the control of the fourth clock signal terminal and the second node; The delay module connects the third node and the fifth node and is used to keep the signal on under the control of the first level signal terminal, delay the input of the signal from the third node to the fifth node, so that the third node controls the second output module through the fifth node.
8. A control method of the gate drive circuit according to claim 6 or 7, characterized by, include: During the first time period, when the shift register connected to the partition transmission circuit in the same row executes a positive base frequency refresh rate, the first clock signal terminal controls the transmission module to input the output signal of the signal output terminal into the partition signal output terminal, and controls the second control module to write the second level signal into the first node, so as to control the refresh adjustment module to turn off through the first node; During the second time period, the transmission module and the second control signal are turned off by controlling the first clock signal terminal, and the first control module is controlled by controlling the second clock signal terminal to write the first level signal into the first node, so as to control the refresh adjustment module to input the second level signal into the partition signal output terminal.
9. A gate driver characterized by comprising: Includes multiple gate drive circuits as described in claim 6 or 7; The multiple gate drive circuits are electrically coupled in a cascaded manner, wherein the signal input terminal of the shift register in the first-stage gate drive circuit is coupled to the start pulse signal, and except for the last-stage gate drive circuit, the signal output terminal of the shift register in each of the other stages of the gate drive circuit is coupled to the signal input terminal of the shift register in the next stage of the gate drive circuit.
10. A display device, characterized in that, Includes the gate driver as described in claim 9.