Cable assembly, mating connector, interconnection system and electronic device

Abstract

A cable assembly, a mating connector, an interconnection system and an electronic device. The cable assembly comprises a circuit board and a cable, wherein a gold finger interface, a signal pad and a chip device are disposed on a surface of the circuit board; the gold finger interface is arranged on an edge of a plug-in end of the circuit board and is used for being electrically connected to a terminal of the mating connector; the gold finger interface comprises a signal pin, and the signal pad is electrically connected to the signal pin; the cable comprises a cable core, and an end portion of the cable core is electrically connected to the signal pad; and in a plug-in direction, the signal pad is located on the side of the chip device that is close to the gold finger interface, and the chip device is located on the side of the signal pad that is away from the gold finger interface. In this way, with regard to a signal transmission link formed by the cable assembly, the loss margin of a system signal link can be effectively improved on the basis of rational control over the loss of a link portion inside a board. On the basis of not affecting the requirement for a signal transmission performance, the cable assembly can be applied to a high-speed and long-distance transmission scenario.

Description

Cable assemblies, inter-connectors, interconnect systems and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411644184.5, filed on November 15, 2024, entitled "Cable Assembly, Interconnector, Interconnection System and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of circuit board technology, and more particularly to a cable assembly, inter-connector, interconnection system, and electronic device. Background Technology

[0003] With the increasing application demands of cluster products, interconnecting cables need to be deployed within or between devices to meet the ever-increasing signal transmission rate requirements. In related technologies, a typical interconnecting cable assembly is based on a circuit board assembly. One end of the circuit board has gold finger interfaces and circuit components arranged on its surface. The side of the circuit board away from the gold finger interfaces has pads for soldering cables, and the cables exit from the other end of the circuit board. Both the internal traces of the circuit board and the cables are components of the signal transmission link. Given a fixed system drive capability, the losses generated by the internal traces directly affect the transmission margin of the external cables, creating a technical bottleneck in increasing the physical transmission distance of the interconnecting cables. Summary of the Invention

[0004] This application provides a cable assembly, inter-connector, interconnection system, and electronic device. By optimizing the cable assembly architecture, the impact of on-board link loss is effectively reduced.

[0005] The first aspect of this application provides a cable assembly including a circuit board and a cable. The circuit board has a gold finger interface, signal pads, and a chip device on its surface. The gold finger interface is located at the edge of the circuit board's insertion end for electrical connection with the terminals of a mating connector. The gold finger interface includes signal pins, and the signal pads are electrically connected to the signal pins. The cable includes a cable core, and the end of the cable core is electrically connected to the signal pads. In the insertion direction, the signal pads are located on the side of the chip device closer to the gold finger interface, and the chip device is located on the side of the signal pads away from the gold finger interface. That is, the signal pads are arranged close to the gold finger interface area. By reasonably controlling the circuit board trace length between the signal pads and the gold finger interface, the signal link loss within the board is effectively reduced. Here, "circuit board trace" includes both the case where the signal pads and signal pins are electrically connected via surface traces on the circuit board and the case where the signal pads and signal pins are electrically connected via inner traces on the circuit board.

[0006] This configuration effectively improves the loss margin of the system signal link by reasonably controlling the loss of the link portion within the board, thus forming the signal transmission link. Without affecting signal transmission performance requirements, the cable length can be increased according to interconnection needs, providing technical assurance for reliable applications in high-speed, long-distance transmission scenarios.

[0007] For example, the gold finger interface and cables of the circuit board can be arranged on both sides of the circuit board to increase the interconnection interface density.

[0008] In practical applications, two circuit boards are configured, each connected to one end of the cable.

[0009] Based on the first aspect, this application also provides a first implementation of the first aspect: the circuit board further includes a control circuit, which includes a resistor / capacitor component, located on the side of the signal pad away from the gold finger interface in the insertion direction. This arrangement, placing the resistor / capacitor component and chip device of the control circuit on the side of the signal pad away from the gold finger interface, maximizes the optimization of the board layout.

[0010] In practical applications, the management and control pins in the middle of the standard gold finger interface ensure the effective output of control signals and the normal operation of the control circuit. This way, the control circuit only occupies the middle signal channel of the circuit board, facilitating optimal control of the trace length on the board. For high-speed signal transmission links, these technical advantages are even more significant.

[0011] Based on the first aspect, or the first embodiment of the first aspect, this application also provides a second embodiment of the first aspect: the gold finger interface further includes a ground pin, which is located next to the signal pin; a ground pad is also provided on the surface of the circuit board, which is located next to the signal pad and electrically connected to the ground pin; the cable further includes a shielded cable core, one end of which is connected to the ground pad to form a shielded link. This effectively improves the crosstalk effect between adjacent signals. Furthermore, the ground pad is located next to the signal pad, meaning it is positioned on the side of the chip device closer to the gold finger interface in the insertion direction, facilitating the soldering of each cable core and improving manufacturability.

[0012] For example, the cable may include a shielding cladding, within which two cable cores for transmitting differential signals are disposed, and a shielding cable core is disposed on each side of the two cable cores.

[0013] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, this application also provides a third implementation of the first aspect: the signal pin includes a transmit signal pin and a receive signal pin, both of which are paired and electrically connected to corresponding signal pads. This enables stable transmission of high-speed differential signals.

[0014] Based on the third embodiment of the first aspect, this application also provides a fourth embodiment of the first aspect: a coupling capacitor is further provided on the surface of the circuit board, the coupling capacitor being located between the receiving signal pin and the corresponding signal pad; in the insertion direction, the coupling capacitor is located on the side of the receiving signal pin closer to the gold finger interface. In practical applications, the surface of the circuit board includes a pair of first capacitor pads and second capacitor pads, the two pins of the coupling capacitor being electrically connected to the first capacitor pad and the second capacitor pad respectively; the first capacitor pad is electrically connected to the corresponding receiving signal pin, and the second capacitor pad is electrically connected to the corresponding signal pad. Based on the setting of the coupling capacitor, signal transmission, filtering, and impedance matching can be achieved, meeting the signal integrity requirements of high-speed signal transmission.

[0015] Based on the fourth implementation of the first aspect, this application also provides a fifth implementation of the first aspect: the inner end of the transmitting signal pin is connected to the corresponding signal pad, and the inner end of the receiving signal pin is connected to the corresponding first capacitor pad. This configuration minimizes the physical length of the on-board wiring for the high-speed signal channel, further reducing trace loss.

[0016] For example, the width of the transmit signal pin can be the same as the width of the corresponding signal pad, or they can be configured to have different widths as needed; for other examples, the width of the receive signal pin can be the same as the width of the corresponding capacitor pad, or they can be configured to have different widths as needed.

[0017] In practical applications, the signal pads and corresponding signal pins that interface with the signal pins, as well as the first capacitor pads and corresponding signal pins that interface with the signal pins, can all be formed as a single integrated structure in a single process. In other practical applications, the signal pads and corresponding signal pins that interface with the signal pins can also be formed in different processes.

[0018] Based on the third, fourth, or fifth implementation of the first aspect, this application also provides a sixth implementation of the first aspect: both the transmit signal pins and receive signal pins are configured as multiple pairs, and in the insertion direction, the multiple pairs of transmit signal pins and multiple pairs of receive signal pins are arranged in two rows; wherein, the outer row of signal pins near the insertion end of the circuit board is electrically connected through the inner layer traces of the circuit board; the inner row of signal pins away from the insertion end of the circuit board is electrically connected through the surface layer traces of the circuit board. The overall structure is more compact and reasonable, achieving a high-density layout of signal pins.

[0019] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, this application also provides a seventh implementation of the first aspect: at least a portion of the signal pads are mated to the inner ends of the corresponding signal pins. This minimizes the physical length of on-board wiring for high-speed signal channels, further reducing on-board trace losses.

[0020] A second aspect of this application provides an interlocking connector for insertion into the aforementioned cable assembly. The interlocking connector includes a base and terminals disposed within the base. One end of the base has an insertion port, and a clearance recess is provided along the outer edge of the sidewall of the insertion port to accommodate a cable assembly protruding beyond the sidewall of the insertion port in the height direction. This adapts to the structural characteristics of forward-positioned cable solder joints, effectively controlling trace loss on the board while avoiding structural interference, thus achieving reliable insertion and interlocking with the interlocking connector.

[0021] In practical applications, the clearance recess includes a first clearance recess and a second clearance recess. The first clearance recess can accommodate the cable body solder joint portion close to the signal pad, and the second clearance recess can accommodate the coupling capacitor on the circuit board.

[0022] A third aspect of this application provides an interconnection system, which includes a first device, a second device, and a cable assembly. The first device and the second device are interconnected through the cable assembly, which uses the cable assembly described above to achieve interconnection between input / output (I / O) ports of the devices, such as, but not limited to, interconnection between a single board and a backplane within a device, or interconnection between devices.

[0023] In practical applications, at least one of the first and second devices is provided with the aforementioned mating connector, and the circuit board of the cable assembly is plugged into the mating connector.

[0024] A fourth aspect of this application provides an electronic device, which includes a housing and a first device, a second device, and a cable assembly disposed within the housing. The first device and the second device are interconnected via the cable assembly, which uses the cable assembly described above to interconnect the device I / O ports.

[0025] In practical applications, this electronic device can be a server, computer, or high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, this electronic device can also be a switch, router, or edge device, etc. Attached Figure Description

[0026] Figure 1 is a schematic diagram of an interconnection system architecture provided in an embodiment of this application;

[0027] Figure 2a is a schematic diagram of the first side layout of a circuit board provided in an embodiment of this application;

[0028] Figure 2b is a schematic diagram of the second side layout of a circuit board provided in an embodiment of this application;

[0029] Figure 3a is a schematic diagram of the first side layout of another circuit board provided in an embodiment of this application;

[0030] Figure 3b is a schematic diagram of the second side layout of another circuit board provided in an embodiment of this application;

[0031] Figure 4 is a schematic diagram of an assembly relationship of the cable assembly formed by the circuit boards shown in Figures 3a and 3b;

[0032] Figure 5 is a schematic diagram of one structure of the cable shown in Figure 4;

[0033] Figure 6 is a cross-sectional view of AA in Figure 4;

[0034] Figure 7 is a schematic diagram of the layout of the comparative circuit board;

[0035] Figure 8 is a structural schematic diagram of an interlocking connector provided in an embodiment of this application;

[0036] Figure 9 is a schematic diagram of the assembly relationship between the mating connector and the cable assembly shown in Figure 8;

[0037] Figure 10 is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0038] This application provides a cable assembly implementation scheme to effectively improve the link loss within the board and provide a good technical guarantee for increasing the transmission margin of external cables.

[0039] To facilitate understanding of the technical solutions of the embodiments of this application by those skilled in the art, the application scenarios of the cable assembly are first introduced.

[0040] Cable assemblies are primarily used for interconnecting I / O ports of devices that require connection, such as, but not limited to, interconnecting single boards and backplanes within a device, or interconnecting devices themselves, to construct interconnection systems for different scenarios. A typical interconnect cable assembly is based on a printed circuit board assembly (PCBA). One end of the cable core is electrically connected to the signal pads on the circuit board, and it can connect to the mating connector on the first device side via a gold finger interface located at one end of the circuit board. The other end of the cable core connects to the second device side, realizing signal interconnection between devices.

[0041] The interface between the circuit board and the corresponding mating connector can adopt different interface standards. For example, but not limited to, Small Form-Factor Plugable (SFP), Quad Small Form-Factor Plugable (QSFP), Octal Small Form-Factor Plugable (OSFP), or Four-Port De-serial Differential (QSFP-DD). The gold-plated connector located at one end of the circuit board, also known as the gold-plated connector on the PCB edge, can have its pin arrangement and number designed and defined according to the functional requirements of the interconnect system.

[0042] As transmission rates increase, signal loss during transmission also increases. In high-speed electrical signal transmission, it is necessary to reasonably control signal loss to ensure signal quality. The on-board traces and cables of the cable assembly are components of the signal transmission link. Given a fixed system drive capability, the loss generated by the on-board traces directly affects the transmission margin of the external cables, limiting further increases in the physical transmission distance of the cables and making it impossible to meet the performance requirements of long-distance signal transmission.

[0043] Based on this, this application provides a cable assembly including a circuit board and a cable. The surface of the circuit board is provided with a gold finger interface, signal pads, and a chip device. The gold finger interface is arranged at the edge of the plug-in end of the circuit board for electrical connection with the terminals of a mating connector. The cable includes a cable core, one end of which is electrically connected to the signal pad. The gold finger interface includes a signal pin, and the signal pad is electrically connected to the signal pin. In the plug-in direction, the signal pad is located on the side of the chip device closer to the gold finger interface, and the chip device is located on the side of the signal pad away from the gold finger interface. In this way, by reasonably controlling the circuit board trace length between the low signal pad and the gold finger interface, the loss of the signal link within the board is effectively reduced. Here, "circuit board trace" includes the case where the signal pad and the signal pin are electrically connected through the surface trace of the circuit board, and also the case where the signal pad and the signal pin are electrically connected through the inner trace of the circuit board. With this configuration, for the signal transmission link formed by the cable assembly, the loss margin of the system signal link is effectively improved based on the reasonable control of the loss of the link portion within the board. Without affecting signal transmission performance requirements, the cable length can be increased according to interconnection needs, providing technical support for reliable applications in high-speed, long-distance transmission scenarios.

[0044] To better understand the technical solutions and effects of this application, without loss of generality, specific embodiments will be described in detail below with reference to the accompanying drawings. Please refer to Figure 1, which is a schematic diagram of an interconnection system architecture provided by an embodiment of this application.

[0045] As shown in Figure 1, the interconnection system 100 includes a cable assembly 10, and a first device 20 and a second device 30 interconnected via the cable assembly 10. The cable assembly 10 includes a connected circuit board 1 and a cable 2. The circuit board 1 can be plugged into a connector 3 disposed on the device side to form a signal transmission link. The circuit board 1 side of the cable assembly 10 is equivalent to a male connector, and the connector 3 on the device side is a female connector. The two can be plugged into each other to achieve an electrical connection of the interconnection interface.

[0046] In a specific implementation, both ends of the cable assembly 10 can form interconnection interfaces using circuit boards 1, which are then plugged into connectors 3 provided on the mating device side. In other possible implementations, the cable assembly 10 can also have one end forming an interconnection interface via a circuit board, while the other end uses an interconnection interface with other structural forms, rather than being limited to the configuration shown in Figure 1. This application does not impose limitations on the embodiments.

[0047] Please refer to Figures 2a and 2b together. These two figures respectively illustrate schematic diagrams of the circuit board layout of a cable assembly according to an embodiment of this application. Figure 2a is a schematic diagram of the layout of the first side (bottom side) 101 of the circuit board according to an embodiment of this application, and Figure 2b is a schematic diagram of the layout of the second side (top side) 102 of the circuit board according to an embodiment of this application. For ease of description, the first direction X within the circuit board surface is defined as the insertion extension direction, which is also the pin length extension direction of the gold finger interface, and the second direction Y within the circuit board surface is defined as the pin width extension direction of the gold finger interface.

[0048] The surface of the insertion end of the circuit board 1 is arranged as a gold finger interface, which includes signal pins 11. As shown in the figure, the signal pins 11 include paired differential signal pins (TX, RX). In the second direction Y, the paired transmit signal pins TX are arranged on one side of the gold finger interface, and the paired receive signal pins RX are arranged on the other side of the gold finger interface. That is, the transmit signal pins TX and receive signal pins RX are respectively located close to the two side edges of the circuit board 1 to reduce crosstalk between the transmitting and receiving ends.

[0049] In this embodiment, the surface of circuit board 1 is configured with eight pairs of transmit signal pins TX and eight pairs of receive signal pins RX. Among them, four pairs of transmit signal pins TX (TX1, TX3, TX5 and TX7) and four pairs of receive signal pins RX (RX2, RX4, RX6 and RX8) are located on the first side 101 of circuit board 1, and four pairs of transmit signal pins TX (TX2, TX4, TX6 and TX8) and four pairs of receive signal pins RX (RX1, RX3, RX5 and RX7) are located on the second side 102 of circuit board 1.

[0050] Here, the paired differential signal pins (TX, RX) are arranged in two rows in the first direction X to reduce space occupation in the second direction Y, resulting in better integration. For the gold finger interface with signal pins arranged in two rows, the pins closer to the insertion edge of the circuit board 1 are the outer row of signal pins, and the pins farther away from the insertion edge of the circuit board 1 are the inner row of signal pins. Specifically, on the first surface 101 of the circuit board 1, the outer row of signal pins includes two pairs of transmit signal pins TX (TX5 and TX7) and two pairs of receive signal pins RX (RX6 and RX8), while the inner row of signal pins includes two pairs of transmit signal pins TX (TX1 and TX3) and two pairs of receive signal pins RX (RX2 and RX4). On the second surface 102 of the circuit board 1, the outer row of signal pins includes two pairs of transmit signal pins TX (TX6 and TX8) and two pairs of receive signal pins RX (RX5 and RX7), while the inner row of signal pins includes two pairs of transmit signal pins TX (TX2 and TX4) and two pairs of receive signal pins RX (RX1 and RX3).

[0051] Correspondingly, each signal pad 12 can also be arranged in two rows at intervals in the first direction X, with the first signal pad 121 located relatively close to the gold finger interface and the second signal pad 122 located relatively far from the gold finger interface. Specifically, the transmit signal pins TX1, TX2, TX3, and TX4 are electrically connected to the corresponding first signal pads 121 through the surface traces of the circuit board on their respective sides; the receive signal pins RX1, RX2, RX3, and RX4 are electrically connected to the corresponding first signal pads 121 through the inner layer traces of the circuit board (not shown in the figure).

[0052] In other possible implementations, the signal pins and / or signal pads may also be arranged in a row (not shown in the figure). This application does not limit the scope of the embodiments.

[0053] In a specific implementation, the gold finger interface may further include a ground pin 14 and a management control pin 15. The ground pin 14 is arranged beside the paired signal pins 11 and can be electrically connected to the ground plane of the circuit board 1. The management control pin 15 is connected to the chip device 13 to realize the corresponding management control functions. Further details are omitted in the embodiments of this application.

[0054] For the cable solder joint side, a grounding pad 16 can be provided next to the signal pad 12. In one implementation, the shielded core (not shown in the figure) on the cable side can be electrically connected to the grounding pad 16 to form a reliable shielded link and reduce crosstalk between adjacent signal transmission links.

[0055] In the first direction X, the signal pad 12 is arranged close to the gold finger interface area, and the chip device 13 is located on the side of the signal pad 12 away from the gold finger interface. This moves the cable and the solder joint on the circuit board towards the gold finger interface, that is, the gold finger portion close to the standard pin interface. Referring to Figure 1, this reduces the circuit board trace length L1, thereby reducing trace loss. For the signal transmission link L formed by the cable assembly, the cable length L2 can be increased according to interconnection needs without affecting signal transmission performance requirements.

[0056] In other possible implementations, other resistors and capacitors (not shown in the figure) can also be arranged in the same way as chip device 13, specifically located on the side of signal pad 12 away from the gold finger interface, which can maximize the optimization of the board layout. That is, for the middle pin of the standard gold finger interface defined as the control circuit, the resistors and capacitors of the chip device and the control circuit can be arranged at the tail of the board away from the insertion end. In this way, the control circuit only occupies the middle signal channel of the board, ensuring the effective output of the control signal and the normal operation of the control circuit without affecting the layout space of the high-speed TX and RX signals.

[0057] To improve signal integrity, in the specific implementation, coupling capacitors (not shown in the figure) are respectively provided between the receive signal pin RX and the corresponding signal pad 12. In the first direction X, the coupling capacitor is located on the side of the corresponding receive signal pin RX closer to the gold finger interface. As shown in Figures 2a and 2b, the surface of the circuit board 1 includes a pair of first capacitor pads 171 and second capacitor pads 172. The two pins of the coupling capacitor (not shown in the figure) are soldered to the first capacitor pad 171 and the second capacitor pad 172 respectively. At the same time, the first capacitor pad 171 is electrically connected to the corresponding receive signal pin RX, and the second capacitor pad 172 is electrically connected to the corresponding signal pad 12. Based on the setting of the coupling capacitor, signal transmission, filtering and impedance matching can be achieved, meeting the signal integrity requirements of high-speed signal transmission.

[0058] It should be noted that, for the signal pads 12 located near the gold finger interface area, the insertion end of the circuit board 1 in the first direction X can have a cutoff length that meets standard requirements, ensuring reliable interconnection with the mating connector. In specific implementations, dual-core or multi-core cables can be used to solder to the corresponding signal pads. In other possible implementations, signal transmission paths can also be constructed separately using single-core coaxial cables. This application does not limit the scope of the embodiments.

[0059] In the foregoing embodiments, the signal pads 12 are spaced apart from the corresponding signal pins, maintaining a keep-away length that meets standard requirements. In other specific implementations, the signal pads 12 and the corresponding signal pins can be integrated into one unit. Please refer to Figures 3a and 3b, where Figure 3a is a schematic diagram of the layout of the first side (bottom side) 101 of another circuit board provided in an embodiment of this application, and Figure 3b is a schematic diagram of the layout of the second side (top side) 102 of another circuit board provided in an embodiment of this application. To clearly illustrate the differences and connections between this embodiment and the solutions described in Figures 2a and 2b, the same functional components and structures are indicated by the same reference numerals in the figures.

[0060] Compared to the schemes described in Figures 2a and 2b, the difference in this embodiment is that some signal pads (first signal pad 121) are mated to the inner ends of the corresponding signal pins. Furthermore, the ground pad 16 beside the signal pad 12 can also be mated to the inner ends of the corresponding ground pins. In comparison, this minimizes the physical length of on-board wiring for high-speed signal channels, further reducing trace losses.

[0061] The inner ends of the transmit signal pins TX (TX1, TX2, TX3, and TX4) in the inner row of signal pins are respectively connected to the corresponding first signal pads 121. In specific implementations, the width of the transmit signal pins TX and the width of the first signal pads 121 can be the same, or they can be configured to have different widths as needed. This application embodiment does not limit this. The inner ends of the receive signal pins RX (RX1, RX2, RX3, and RX4) in the inner row of signal pins are respectively connected to the corresponding first capacitor pads 161. In specific implementations, the width of the receive signal pins RX and the width of the first capacitor pads 161 can be the same, or they can be configured to have different widths as needed.

[0062] In addition, for the gold finger interface with signal pins arranged in a row, the inner end of each transmit signal pin TX can be connected to the corresponding first signal pad 121, and the inner end of each receive signal pin RX can be connected to the corresponding first capacitor pad 161.

[0063] Furthermore, in the implementation where no coupling capacitor is provided between the receive signal pin RX and the corresponding signal pad 12, the inner end of the receive signal pin RX is connected to the corresponding signal pad 12. Similarly, the width of the receive signal pin RX and the width of the signal pad 12 can be the same, or they can be configured to have different widths as needed. This application does not limit the scope of the embodiments.

[0064] As shown in the figure, the signal pads and corresponding signal pins that interface with the signal pins, as well as the first capacitor pads and corresponding signal pins that interface with the signal pins, can all be integrally formed in a single process. Of course, in other possible implementations, the signal pads and corresponding signal pins that interface with the signal pins can also be formed in different processes. The specific process can be determined based on the overall product design requirements. This application does not limit the specific implementation.

[0065] Please refer to Figures 4 and 5 together. Figure 4 is a schematic diagram of the assembly relationship of the cable assembly formed by the circuit boards shown in Figures 3a and 3b, and Figure 5 is a schematic diagram of the structure of the cable shown in Figure 4. As shown in Figure 4, the cable 2 includes two signal cores 21 and two shielded cores 22. After assembly, the two signal cores 21 are soldered to the corresponding signal pads 12 on the circuit board 1, and the two shielded cores 22 are soldered to the grounding pads next to the signal pads 12. Each coupling capacitor 18 is located between the receiving signal pin RX and the corresponding signal pad 12, and is soldered to the corresponding first capacitor pad and second capacitor pad, respectively. It is understood that the specific soldering process can be selected as needed, and will not be elaborated here.

[0066] In this embodiment, the gold finger interfaces at the insertion end of circuit board 1 are respectively adapted to each terminal 31 of the mating connector. Please refer to Figure 6, which is the AA cross-sectional view in Figure 4. The gold finger interfaces on both sides of the insertion end of circuit board 1 are adapted to the oppositely arranged terminals 31 of the mating connector. The gold finger interfaces arranged in two rows on the surface of circuit board 1 are adapted to the two rows of terminals 31 of the mating connector. The specific definitions and configurations can be made according to the interconnection system design, which will not be elaborated here.

[0067] It should be noted that the cable 2 shown in Figure 4 and its connection with the circuit board 1, as well as the adaptation relationship between the gold finger interface and the side terminals of the mating connector, can also be applied to the implementation schemes described in Figures 2a and 2b.

[0068] Other functional components and connection methods can be the same as those described in the previous implementation. They will not be repeated here.

[0069] Please refer to Figure 7, which is a schematic diagram of the layout of the comparative circuit board. Figure 7(a) shows the layout of the first side of the circuit board, and Figure 7(b) shows the layout of the second side of the circuit board. In order to clearly show the differences and connections between the comparative example and this embodiment, the same functional components and structures are indicated by the same markings in the figures.

[0070] In the comparative example shown in Figure 7, the signal pad 12 of the cable is located on the side of the chip device 13 away from the gold finger interface, and the chip device 13 is located on the side of the signal pad 12 closer to the gold finger interface. Using the circuit board layout scheme of the cable assembly described in this application embodiment, an insertion loss gain simulation test is performed with the comparative example shown in Figure 4. Specifically, the circuit board substrate is taken as an example of M7-layer TU933 board material, and the corresponding circuit board parameters and total loss are shown in Tables 1-3 below.

[0071] Table 1 shows the parameter structure and total loss of the comparative example described in Figure 4.

[0072] Table 1

[0073] As shown in Table 1, for the comparative scheme shown in Figure 7, the longest TX+RX (TX7+RX7) pin on the outer row has a routing length of nearly 2 inches, and the simulation evaluation shows a total routing loss of -4dB@28GHz; the longest TX+RX (TX1+RX1) pin on the inner row can reach a routing length of 1.4 inches, and the simulation evaluation shows a total routing loss of -2.8dB@28GHz.

[0074] Table 2 shows the parameter structure and total loss of the embodiments described in Figures 2a and 2b.

[0075] Table 2

[0076] Referring to Table 2, in the embodiments shown in Figures 2a and 2b of this application, the longest TX+RX (TX7+RX7) trace length of the outer row pins is 1.1 inches, with a simulation evaluation showing a total trace loss of -4dB@28GHz; the longest TX+RX (TX1+RX1) trace length of the inner row pins is 0.4 inches, with a simulation evaluation showing a total trace loss of -1.1dB@28GHz. Compared to the comparative example, the loss optimization effect can reach an average of 48.555%.

[0077] Table 3 shows the parameter structure and total loss of the embodiments described in Figures 3a and 3b.

[0078] Table 3

[0079] Referring to Table 2, in the embodiments shown in Figures 2a and 2b of this application, the longest TX+RX (TX7+RX7) trace length of the outer row pins is 0.9 inches, with a simulation evaluation showing a total trace loss of -4dB@28GHz; the longest TX+RX (TX1+RX1) trace length of the inner row pins is 0.2 inches, with a simulation evaluation showing a total trace loss of -0.8dB@28GHz. Compared to the comparative example, the loss optimization effect can reach an average of 58.65%.

[0080] Overall, the in-board losses and total losses of each embodiment of this application are effectively reduced.

[0081] Furthermore, based on the circuit board layout of the cable assembly described in Figure 3, in order to ensure compatibility with the mating connector's insertion feasibility, a clearance structure can be provided on the base of the mating connector in a specific implementation. Please refer to Figures 8 and 9 together, where Figure 8 is a structural schematic diagram of a mating connector provided in an embodiment of this application, and Figure 9 is a schematic diagram of the assembly relationship between the mating connector and the cable assembly shown in Figure 8.

[0082] As shown in Figure 8, the mating connector 3 includes a base 32 and a plurality of terminals 31 disposed in the base 32. One end of the base 32 has an insertion port 321, and each terminal 31 is located on opposite sides of the insertion port 321. A clearance recess is provided at the outer edge of the side wall of the insertion port 321 to accommodate the structure of the cable assembly 10 protruding from the side wall of the insertion port 321 in the height direction.

[0083] In a specific implementation, a first clearance recess 3211 and a second clearance recess 3212 are provided at the outer edge of the side wall of the insertion port 321. Both sides of the insertion port 321 have the first clearance recess 3211 and the second clearance recess 3212 to avoid structures with a certain height on both sides of the circuit board 1. The specific details can be determined based on the overall mating relationship; this embodiment does not limit the specific implementation.

[0084] As shown in Figure 9, after the circuit board 1 of the cable assembly 10 is plugged into the mating connector 3, the gold finger interface of its insertion end is adapted to the corresponding terminal 31 to construct the corresponding link. For example, but not limited to, high-speed signal transmission links and management control signal transmission links.

[0085] After the connection is completed, the solder joint portion of the cable 2 on the TX side near the signal pad can be housed in the first clearance recess 3211 on the sidewall of the insertion port 321; correspondingly, the coupling capacitor 18 on the RX side can be housed in the second clearance recess 3212 on the sidewall of the insertion port 321. In this way, based on the clearance recess on the mating connector 3 side, the height of the TX side solder wire and the device height of the RX side coupling capacitor are avoided.

[0086] Specifically, the first and second clearance recesses 3211 and 3212 have assembly gaps with the solder joint and coupling capacitor, which can accommodate fluctuations in the dimensional tolerances of the mating parts and prevent collisions during mating. Here, the first and second clearance recesses 3211 and 3212 can be integrally injection molded; in other words, the clearance recesses can be integrated during the product mold design stage, reducing the thickness of the base plastic material without affecting the overall mating stop. Of course, in other possible implementations, the clearance recesses can also be formed after the base body is manufactured using a material removal process, achieving effective clearance as well. The specific implementation can be determined based on the actual application scenario, and this application does not limit this.

[0087] In addition to the aforementioned cable assemblies and mating connectors, this embodiment also provides an electronic device, as shown in Figure 10, which is a schematic diagram of an electronic device provided in an embodiment of this application.

[0088] As shown in Figure 8, the electronic device 1000 includes a first device 20 and a second device 30 disposed within a housing 40, and the first device 20 and the second device 30 are interconnected via the aforementioned cable assembly 10. In specific implementations, the electronic device can be a server, a computer, or a high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, the electronic device can also be a switch, a router, or an edge device, etc., and this application embodiment does not limit the scope.

[0089] It should be understood that the other main functional components of this electronic device can be implemented using existing technologies, so they will not be described in detail here.

[0090] Furthermore, the ordinal numbers "first" and "second," etc., used herein are only for describing the composition or structure of the same function in the technical solution. It is understood that the use of the aforementioned ordinal numbers does not constitute a limitation on the understanding of the technical solution for which protection is sought in this application.

[0091] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A cable assembly, characterized in that, The cable assembly includes a circuit board and cables; The circuit board has a gold finger interface, signal pads and chip devices on its surface. The gold finger interface is arranged on the edge of the plug end of the circuit board for electrical connection with the terminals of the mating connector. The gold finger interface includes signal pins, and the signal pads are electrically connected to the signal pins. The cable includes a cable core, and the end of the cable core is electrically connected to the signal pads. In the mating direction, the signal pad is located on the side of the chip device closer to the gold finger interface, and the chip device is located on the side of the signal pad away from the gold finger interface.

2. The cable assembly according to claim 1, characterized in that, The circuit board also includes a control circuit, which includes a resistor / capacitor component located on the side of the signal pad away from the gold finger interface in the insertion direction.

3. The cable assembly according to claim 1 or 2, characterized in that, The gold finger interface also includes a ground pin, which is located next to the signal pin. The surface of the circuit board is also provided with a ground pad, which is located next to the signal pad and is electrically connected to the ground pin. The cable also includes a shielded core, one end of which is connected to the grounding pad.

4. The cable assembly according to any one of claims 1 to 3, characterized in that, The signal pins include a transmit signal pin and a receive signal pin. The transmit signal pin and the receive signal pin are arranged in pairs and are electrically connected to the corresponding signal pads respectively.

5. The cable assembly according to claim 4, characterized in that, The surface of the circuit board is also provided with a coupling capacitor, which is located between the receiving signal pin and the corresponding signal pad. In the insertion direction, the coupling capacitor is located on the side of the receiving signal pin closer to the gold finger interface.

6. The cable assembly according to claim 5, characterized in that, The surface of the circuit board includes a pair of first capacitor pads and second capacitor pads, and the two pins of the coupling capacitor are electrically connected to the first capacitor pad and the second capacitor pad, respectively. The first capacitor pad is electrically connected to the corresponding receive signal pin, and the second capacitor pad is electrically connected to the corresponding signal pad.

7. The cable assembly according to claim 6, characterized in that, The inner end of the transmitting signal pin is connected to the corresponding signal pad, and the inner end of the receiving signal pin is connected to the corresponding first capacitor pad.

8. The cable assembly according to any one of claims 4 to 7, characterized in that, Both the transmitting signal pin and the receiving signal pin are configured as multiple pairs, and in the insertion direction, the multiple pairs of transmitting signal pins and the multiple pairs of receiving signal pins are arranged in two rows; The outer signal pins near the insertion end of the circuit board are electrically connected through the inner layer traces of the circuit board; the inner signal pins away from the insertion end of the circuit board are electrically connected through the surface layer traces of the circuit board.

9. The cable assembly according to any one of claims 1 to 3, characterized in that, At least a portion of the signal pads are mated to the inner end of the corresponding signal pins.

10. The cable assembly according to any one of claims 1 to 9, characterized in that, Two circuit boards are configured, each connected to one end of the cable.

11. A mating connector, characterized in that, The interlocking connector is used to connect with the cable assembly according to any one of claims 1 to 10. The interlocking connector includes a base and terminals disposed in the base. One end of the base has an insertion port. An avoidance recess is provided at the outer edge of the side wall of the insertion port to accommodate the structure of the cable assembly protruding from the side wall of the insertion port in the height direction.

12. The interlocking connector according to claim 11, characterized in that, The clearance recess includes a first clearance recess and a second clearance recess. The first clearance recess can accommodate the cable body solder joint portion near the signal pad, and the second clearance recess can accommodate the coupling capacitor on the circuit board.

13. An interconnection system, characterized in that, The interconnection system includes a first device, a second device, and a cable assembly, wherein the first device and the second device are interconnected via the cable assembly, and the cable assembly is the cable assembly of any one of claims 1 to 10.

14. The interconnection system according to claim 13, characterized in that, At least one of the first device and the second device is provided with the interlocking connector as described in claim 11 or 12, and the circuit board of the cable assembly is plugged into the interlocking connector.

15. An electronic device, characterized in that, The electronic device includes a housing and a first device, a second device, and a cable assembly disposed within the housing. The first device and the second device are interconnected via the cable assembly, which is a cable assembly according to any one of claims 1 to 10.

16. The electronic device according to claim 15, characterized in that, At least one of the first device and the second device is provided with the interlocking connector as described in claim 11 or 12, and the circuit board of the cable assembly is plugged into the interlocking connector.

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