Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of memory cell arrays stacked in different layers in a direction perpendicular to a substrate, wherein each memory cell array comprises at least one column of memory cells; a plurality of bit lines (30) extending in the direction perpendicular to the substrate, wherein memory cells at the same position in the different layers are connected to the same bit line (30); and a plurality of word lines (40) extending in a second direction. Each memory cell comprises a transistor. The transistor comprises a first electrode (51) and a semiconductor layer (23) connected to the first electrode (51). The first electrode (51) forms a cylindrical structure having an opening oriented away from the semiconductor layer (23). The semiconductor layers (23) surround the word line (40). The size of the surface of the semiconductor layer (23) on the side facing the bit line (30) in the second direction is larger than the size of the bit line (30) in the second direction. The semiconductor layer (23) covers the surface of the first electrode (51) on the side facing the semiconductor layer (23).

Description

A semiconductor device and its manufacturing method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202411615030.3, filed on November 12, 2024, entitled "A Semiconductor Device and a Method for Manufacturing the Same Thereof, and an Electronic Device", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This application provides a semiconductor device, including: a multilayer array of memory cells stacked along a direction perpendicular to a substrate, the array of memory cells including at least one column of a plurality of memory cells distributed along a second direction;

[0007] Multiple bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; memory cells at the same position in different layers are connected to the same bit line;

[0008] Multiple word lines are distributed in different layers. The word lines and bit lines are distributed along a first direction, and the word lines extend along a second direction. The first direction and the second direction are parallel to the substrate and intersect.

[0009] The memory cell includes a transistor, the transistor including a first electrode and a semiconductor layer connected to the first electrode, the first electrode being disposed on the semiconductor layer away from the bit line, the first electrode forming a cylindrical structure with its opening direction away from the semiconductor layer; multiple semiconductor layers of multiple transistors in the same column surround the same word line, and the multiple semiconductor layers of multiple transistors in the same column are spaced apart along a second direction; the sidewall of the semiconductor layer facing the bit line and perpendicular to the substrate is connected to the bit line, the dimension of the surface of the semiconductor layer facing the bit line along the second direction is larger than the dimension of the bit line along the second direction, and the semiconductor layer covers the surface of the first electrode facing the semiconductor layer.

[0010] In some embodiments, the semiconductor device further includes a seventh insulating layer comprising a first sub-part disposed between adjacent bit lines along a second direction and extending through multiple layers in a direction perpendicular to the substrate, a second sub-part disposed between adjacent first electrodes along the second direction and extending through multiple layers in a direction perpendicular to the substrate, and a third sub-part disposed in a region of the word line facing away from the substrate and not surrounded by the semiconductor layer and a region of the word line facing the substrate and not surrounded by the semiconductor layer, wherein the third sub-part fills the region between adjacent word lines along the direction perpendicular to the substrate that are not surrounded by the semiconductor layer, the first sub-part, the second sub-part, and the third sub-part are connected to form an integral structure, the first sub-part is connected to the side of the word line facing the bit line, and the second sub-part is connected to the side of the word line facing away from the bit line.

[0011] In some embodiments, the semiconductor device further includes a third insulating layer and a fifth insulating layer that fill the regions of adjacent word lines surrounded by the semiconductor layer along a direction perpendicular to the substrate. The third insulating layer and the fifth insulating layer are distributed along a first direction. The third insulating layer is disposed on the side of the fifth insulating layer opposite to the bit line, and the third insulating layer forms a protrusion structure facing the bit line. The fifth insulating layer forms a recess structure on the side opposite to the bit line, and the fifth insulating layer is connected to the bit line.

[0012] In some embodiments, the distance between the two semiconductor layers of two adjacent transistors along the second direction on the side away from the bit line is greater than the distance on the side facing the bit line.

[0013] In some embodiments, the semiconductor device further includes: an eleventh insulating layer disposed between adjacent bit lines along a second direction and extending through multiple layers in a direction perpendicular to the substrate; and an eighth insulating layer disposed between the eleventh insulating layer and the bit lines and extending through multiple layers in a direction perpendicular to the substrate.

[0014] And, a twelfth insulating layer, the twelfth insulating layer comprising a fourth sub-section distributed between adjacent first electrodes along a second direction, extending perpendicular to the substrate direction and penetrating multiple layers, and a fifth sub-section filling the region between adjacent word lines along a perpendicular to the substrate direction that is not surrounded by the semiconductor layer, the fourth sub-section and the fifth sub-section being connected to form an integral structure, the eleventh insulating layer and the twelfth insulating layer being a non-integral structure.

[0015] In some embodiments, the fourth sub-part is distributed on the outer wall of the first electrode extending in a direction perpendicular to the substrate, and extends continuously from the side of the outer wall near the bottom wall of the cylindrical structure to the side away from the bottom wall of the cylindrical structure. The fourth sub-part includes a first part and a second part distributed along a first direction. The second part is disposed on the side of the first part facing the word line, and the size of the second part along the second direction is larger than the size of the first part along the second direction.

[0016] In some embodiments, the distance between two adjacent semiconductor layers along the second direction on the side away from or towards the substrate gradually decreases in the direction toward the bit line.

[0017] In some embodiments, the transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line surrounding the word line, wherein multiple gate insulating layers of multiple transistors distributed in the same column along the second direction in the same layer are connected to form an integral structure on the side facing the substrate and the side away from the substrate, and are disconnected on the side facing the bit line and the side away from the bit line; or, multiple gate insulating layers of multiple transistors distributed in the same column along the second direction in the same layer are connected to form an integral structure on the side facing the substrate, the side away from the substrate, the side facing the bit line, and the side away from the bit line.

[0018] In some embodiments, the memory cell further includes a capacitor, wherein the capacitor and the transistor of the same memory cell are distributed along the first direction, the capacitor includes a dielectric layer and a second capacitor electrode, the dielectric layer is disposed between the first electrode and the second capacitor electrode, the second capacitor electrode fills the cylindrical structure formed by the first electrode and is distributed on the side of the first electrode away from the substrate, the side facing the substrate, and the outer wall perpendicular to the substrate.

[0019] In some embodiments, multiple second capacitor electrodes of multiple capacitors adjacent along a second direction are connected to form an integral structure, and the integral structure formed by connecting multiple second capacitor electrodes fills the region between first electrodes adjacent along the second direction; or, the integral structure formed by connecting multiple second capacitor electrodes forms a groove with an opening direction facing the word line between the first electrodes adjacent along the second direction.

[0020] This disclosure provides a method for manufacturing a semiconductor device, including:

[0021] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0022] A first trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction. Based on the first trench, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral trench. A first isolation layer is formed that fills the first lateral trench, and a second insulating layer is formed that fills the first trench.

[0023] A plurality of first holes are formed penetrating the second insulating layer along a direction perpendicular to the substrate, and a plurality of third holes are formed penetrating the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along a second direction, and the plurality of third holes are spaced apart along the second direction. The third holes are disposed on the side of the first isolation layer opposite to the first trench. The sidewalls of the first holes and the sidewalls of the third holes are exposed in the first isolation layer. The first holes and the third holes are distributed along a first direction. A first dummy layer is formed to fill the first holes and the third holes. The first direction and the second direction are parallel to the substrate and intersect.

[0024] A fourth hole is formed between adjacent third holes along the second direction, penetrating the stacked structure in a direction perpendicular to the substrate. The sidewall of the fourth hole does not expose the first isolation layer, but exposes the first dummy layer. Based on the fourth hole, the first sacrificial layer is etched along a predetermined length parallel to the substrate to form a first lateral groove, and a first electrode is formed covering the inner wall of the first lateral groove.

[0025] Based on the fourth hole, the first insulating layer and the first isolation layer are etched along a direction parallel to the substrate, and a portion of the first isolation layer is retained without exposing the second insulating layer; a plurality of second holes are formed between adjacent first holes along the second direction, penetrating the second insulating layer along a direction perpendicular to the substrate, and the sidewalls of the second holes expose the first isolation layer; based on the second holes, the first isolation layer is etched along a direction parallel to the substrate, such that the first isolation layer is broken into multiple segments spaced apart along the second direction; bit lines are formed to fill the second holes;

[0026] The first dummy layer in the first hole and the third hole is removed by etching. Based on the first hole and the third hole, the first sacrificial layer is etched along the direction parallel to the substrate to form a channel extending along the second direction. A semiconductor structure layer, a gate insulating structure layer and a word line are sequentially formed in the channel. The gate insulating structure layer and the semiconductor structure layer sequentially surround the word line. The word line fills the channel. The semiconductor structure layer is broken into multiple segments on the side facing the bit line and on the side away from the bit line.

[0027] The first isolation layer is removed by etching based on the first hole and the third hole, and the semiconductor structure layer exposed by etching is broken into multiple segments that are spaced apart along the second direction on the side facing the substrate and the side away from the substrate.

[0028] In some embodiments, after etching to expose the semiconductor structure layer on the substrate-facing side and the substrate-removing side, the method further includes:

[0029] The inner wall of the first electrode is exposed, as well as the outer walls of the first electrode facing the substrate and away from the substrate, and the first electrode is perpendicular to the outer wall of the substrate; a first transverse groove is formed to fill the first electrode and to cover the exposed outer walls of the first electrode facing the substrate and away from the substrate, and a second capacitor electrode is formed with the first electrode perpendicular to the outer wall of the substrate.

[0030] This disclosure provides a method for manufacturing a semiconductor device, including:

[0031] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0032] A plurality of fifth holes are formed that penetrate the stacked structure along a direction perpendicular to the substrate and are spaced apart along the second direction;

[0033] A second trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction; the second trench and the fifth hole are spaced apart along a first direction, forming a first barrier layer covering the bottom wall and sidewalls of the fifth hole and a fourth dummy layer filling the fifth hole; the first sacrificial layer is etched along a direction parallel to the substrate based on the second trench to form a second lateral trench; a second isolation layer is formed that fills the second lateral trench, and an eighth insulating layer is formed that fills the second trench; the first direction and the second direction are parallel to the substrate and intersect;

[0034] A third trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction. The third trench is disposed on the side of the fifth hole opposite to the second trench. Based on the third trench, the first sacrificial layer is etched along a direction parallel to the substrate to form a third lateral trench. The third lateral trench includes a first lateral groove disposed between adjacent first barrier layers. A first electrode is formed that covers the inner wall of the first lateral groove.

[0035] A plurality of sixth holes are formed penetrating the eighth insulating layer along a direction perpendicular to the substrate. The plurality of sixth holes are spaced apart along the second direction, and the sidewalls of the six holes expose the second isolation layer. Based on the sixth holes, the second isolation layer is etched along a direction parallel to the substrate, such that the second isolation layer is broken into multiple segments spaced apart along the second direction. Bit lines are formed to fill the sixth holes.

[0036] A plurality of seventh holes are formed between adjacent sixth holes along the second direction, penetrating the eighth insulating layer in a direction perpendicular to the substrate. The sidewalls of the seventh holes expose the second isolation layer but not the bit line. The first sacrificial layer is removed by etching along the direction parallel to the substrate based on the seventh holes, forming a channel extending along the second direction. A semiconductor structure layer, a gate insulating structure layer, and a word line are sequentially formed in the channel. The gate insulating structure layer and the semiconductor structure layer sequentially surround the word line. The word line fills the channel, and the semiconductor structure layer is broken into multiple segments on the side facing the bit line.

[0037] The fourth dummy layer and the first barrier layer are etched to expose the second isolation layer. The second isolation layer is then etched away. The semiconductor structure layer exposed by the etching is separated from the bit line side, the substrate side, and the substrate side, so that the semiconductor structure layer separated from the bit line side, the substrate side, and the substrate side is broken into multiple segments spaced apart along the second direction.

[0038] In some embodiments, after the semiconductor structure layer, the gate insulating structure layer, and the word line are sequentially formed in the channel, before etching the fourth dummy layer and the first barrier layer to expose the second isolation layer, the method further includes:

[0039] The inner wall of the first electrode, the outer wall of the first electrode facing the substrate and the outer wall of the first electrode away from the substrate are exposed, and the first barrier layer is etched while retaining the first barrier layer facing the bit line, exposing the outer wall of the first electrode perpendicular to the substrate.

[0040] A first transverse groove is formed to fill the first electrode and an outer wall covering the exposed side of the first electrode facing the substrate and the side away from the substrate, and a second capacitor electrode is formed whereby the first electrode is perpendicular to the outer wall of the substrate.

[0041] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0042] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0043] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood.

[0044] Overview of the attached figures

[0045] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0046] Figures 1A, 1B, 1C, 1D, 1E, and 1F are schematic cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the AA' and BB' directions parallel to the substrate and the CC', DD', EE', and FF' directions perpendicular to the substrate.

[0047] Figure 2A is a perspective view of the first isolation layer after formation according to some embodiments; Figures 2B and 2C are cross-sectional views along the BB' direction and DD' direction respectively according to some embodiments after the first isolation layer is formed.

[0048] Figure 3A is a perspective view of the first and third holes after formation according to some embodiments; Figures 3B and 3C are cross-sectional views along the BB' and DD' directions respectively after the first and third holes are formed according to some embodiments.

[0049] Figure 4A is a perspective view of the fourth hole and the first transverse groove after forming according to some embodiments. Figures 4B, 4C and 4D are cross-sectional views along the AA' direction, BB' direction and FF' direction, respectively, after forming the fourth hole and the first transverse groove according to some embodiments.

[0050] Figures 5A and 5B are cross-sectional views along the AA' and FF' directions respectively, provided in some embodiments, after the formation of the first capacitor electrode.

[0051] Figures 6A, 6B, 6C, and 6D are cross-sectional views along the AA', BB', EE', and FF' directions respectively, provided in some embodiments after the formation of the third insulating layer and the third dummy layer.

[0052] Figures 7A, 7B, 7C and 7D are cross-sectional views along the AA', BB', CC' and FF' directions respectively, provided in some embodiments after the formation of the second hole and the third transverse groove;

[0053] Figures 8A, 8B, 8C, and 8D are cross-sectional views along the AA', BB', CC', and FF' directions respectively, provided in some embodiments after the bit line and the fifth insulating layer have been formed.

[0054] Figures 9A, 9B, 9C, and 9D are cross-sectional views along the AA', BB', CC', and DD' directions after the first and third holes are exposed, respectively, according to some embodiments.

[0055] Figures 10A, 10B, 10C, and 10D are cross-sectional views along the AA', DD', EE', and FF' directions respectively, provided in some embodiments after the formation of the semiconductor layer, gate insulating layer, and word line.

[0056] Figures 11A, 11B, 11C, 11D, 11E, and 11F are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions, respectively, after disconnecting the semiconductor layers of multiple transistors in the same row according to some embodiments.

[0057] Figures 12A, 12B, 12C, and 12D are cross-sectional views along the AA', BB', DD', and FF' directions respectively, provided in some embodiments after exposing the first capacitor electrode;

[0058] Figure 13A is a perspective view of a semiconductor device provided in some other embodiments. Figures 13B, 13C, 13D, 13E, 13F and 13G are cross-sectional views of the semiconductor device provided in some other embodiments along the AA' direction, BB' direction, CC' direction, DD' direction, EE' direction and FF' direction, respectively.

[0059] Figures 14A and 14B are cross-sectional views along the AA' and DD' directions respectively after the isolation structure is formed according to some embodiments;

[0060] Figures 15A, 15B, and 15C are cross-sectional views along the BB', DD', and FF' directions respectively, provided in some embodiments after the formation of the second trench and the second isolation layer.

[0061] Figures 16A, 16B, and 16C are cross-sectional views along the AA', DD', and FF' directions respectively, provided in some embodiments after the formation of the third trench and the third transverse trench;

[0062] Figures 17A and 17B are cross-sectional views along the AA' and FF' directions respectively, provided in some embodiments, after the formation of the first capacitor electrode.

[0063] Figures 18A, 18B, 18C, 18D, and 18E are cross-sectional views along the AA', BB', CC', EE', and FF' directions respectively, provided in some embodiments after the formation of the sixth hole and the fourth transverse groove.

[0064] Figures 19A, 19B, 19C, 19D, and 19E are cross-sectional views along the AA', BB', CC', EE', and FF' directions after the bit lines are formed, according to some embodiments.

[0065] Figures 20A, 20B, 20C, 20D, 20E, and 20F are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the channel is formed, according to some embodiments.

[0066] Figures 21A, 21B, 21C, and 21D are cross-sectional views along the AA', DD', EE', and FF' directions respectively, provided in some embodiments after the formation of the semiconductor layer, gate insulating layer, and word line.

[0067] Figures 22A, 22B, 22C, and 22D are cross-sectional views along the AA', BB', DD', and FF' directions respectively, provided in some embodiments after exposing the first capacitor electrode;

[0068] Figures 23A, 23B, 23C, and 23D are cross-sectional views along the AA', BB', DD', and FF' directions respectively, provided in some embodiments after the formation of the dielectric layer and the second capacitor electrode.

[0069] Figures 24A, 24B, 24C, and 24D are cross-sectional views along the AA', BB', DD', and EE' directions, respectively, provided in some embodiments after disconnecting multiple semiconductor layers of multiple transistors.

[0070] Detailed Explanation

[0071] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0072] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0073] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0074] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0075] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0076] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0077] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0078] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0079] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0080] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0081] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0082] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0083] Figures 1A to 1F are schematic cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the AA' and BB' directions parallel to substrate 1 and the CC', DD', EE', and FF' directions perpendicular to substrate 1, respectively. Figure 13A is a perspective view of the semiconductor device provided in some other embodiments, and Figures 13B to 13G are schematic cross-sectional views of the semiconductor device provided in some other embodiments along the AA', BB', CC', DD', EE', and FF' directions, respectively. As shown in Figures 1A to 1F and Figures 13A to 13G, the embodiments of this application provide a semiconductor device, including: a multilayer array of memory cells stacked along a direction perpendicular to substrate 1, wherein the memory cell array includes at least one column of multiple memory cells distributed along a second direction Y;

[0084] Multiple bit lines 30 extend through the memory cells in different layers along a direction perpendicular to the substrate 1; memory cells at the same position in different layers are connected to the same bit line 30.

[0085] Multiple word lines 40 are distributed in different layers. The word lines 40 and the bit lines 30 are distributed along a first direction X, and the word lines 40 extend along a second direction Y. The first direction X and the second direction Y are parallel to the substrate 1 and intersect.

[0086] The memory cell includes a transistor, which includes a first electrode 51 and a semiconductor layer 23 connected to the first electrode 51. The first electrode 51 is disposed on the semiconductor layer 23 on the side away from the bit line 30, and the first electrode 51 forms a cylindrical structure with its opening direction away from the semiconductor layer 23. A plurality of semiconductor layers 23 of a plurality of transistors in the same column surround the same word line 40, and the plurality of semiconductor layers 23 of the plurality of transistors in the same column are spaced apart along the second direction Y. The sidewall of the semiconductor layer 23 facing the bit line 30 and perpendicular to the substrate 1 is connected to the bit line 30. The dimension of the surface of the semiconductor layer 23 facing the bit line 30 along the second direction Y is larger than the dimension of the bit line 30 along the second direction Y. The semiconductor layer 23 covers the surface of the first electrode 51 facing the semiconductor layer 23.

[0087] The solution provided in this embodiment of the disclosure is that the semiconductor layer 23 covers the surface of the first electrode 51 facing the semiconductor layer 23 and is larger than the size of the bit line 30 in the second direction Y. The semiconductor layer 23 has a larger size in the second direction Y, thereby increasing the channel width and improving the on-state current of the transistor.

[0088] In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0089] In some embodiments, the memory cell array may include a plurality of memory cells distributed along a first direction X and a second direction Y. Each layer may include a plurality of word lines 40.

[0090] In some embodiments, a bit line 30 may be connected to memory cells in two adjacent vertical columns along the first direction X. A vertical column of memory cells may include multiple memory cells at the same location in multiple layers. However, the embodiments of this disclosure are not limited thereto, and memory cells adjacent along the first direction X may be connected to different bit lines 30.

[0091] In some embodiments, the semiconductor device may further include a seventh insulating layer 17, the seventh insulating layer 17 including a first sub-part 171 disposed between adjacent bit lines 30 along the second direction Y and extending through multiple layers in a direction perpendicular to the substrate 1; a second sub-part 172 disposed between adjacent first electrodes 51 along the second direction Y and extending through multiple layers in a direction perpendicular to the substrate 1; a third sub-part 173 disposed in a region of the word line 40 facing away from the substrate 1 and not surrounded by the semiconductor layer 23 and in a region of the word line 40 facing the substrate 1 and not surrounded by the semiconductor layer 23, and the third sub-part 173 filling adjacent word lines 40 along the direction perpendicular to the substrate 1. The regions between the areas not surrounded by the semiconductor layer 23 (the word line 40 includes regions surrounded by the semiconductor layer 23 and regions not surrounded by the semiconductor layer 23; the third sub-part 173 is distributed on the regions of two adjacent word lines 40 perpendicular to the substrate 1 that are not surrounded by the semiconductor layer 23) can be connected to form an integral structure (i.e., the first sub-part 171, second sub-part 172, and third sub-part 173 are formed in a single manufacturing process). The first sub-part 171 is connected to the word line 40 on the side facing the bit line 30, and the second sub-part 172 is connected to the word line 40 on the side away from the bit line 30. The solution provided by the embodiments of this disclosure simplifies the cutting process by removing the film layer filling the space between adjacent semiconductor layers perpendicular to the substrate direction to cut the semiconductor layer.

[0092] In some embodiments, the semiconductor device may further include a third insulating layer 13 and a fifth insulating layer 15 that fill the regions of adjacent word lines 40 surrounded by the semiconductor layer 23 along a direction perpendicular to the substrate 1. The third insulating layer 13 and the fifth insulating layer 15 are distributed along a first direction X. The third insulating layer 13 is disposed on the side of the fifth insulating layer 15 away from the bit line 30, and the third insulating layer 13 forms a protrusion structure facing the bit line 30. The fifth insulating layer 15 forms a recess structure on the side away from the bit line 30, and the fifth insulating layer 15 is connected to the bit line 30.

[0093] In some embodiments, as shown in FIG1A, the distance between the two semiconductor layers 23 of two adjacent transistors along the second direction Y on the side away from the bit line 30 can be greater than the distance on the side towards the bit line 30.

[0094] In some embodiments, as shown in Figures 13B to 13G, the semiconductor device may further include: an eleventh insulating layer 21 disposed between adjacent bit lines 30 along the second direction Y and extending in a direction perpendicular to the substrate 1, and an eighth insulating layer 18 disposed between the eleventh insulating layer 21 and the bit lines 30 and extending in a direction perpendicular to the substrate 1, extending in a direction perpendicular to the substrate 1.

[0095] Furthermore, a twelfth insulating layer 22 includes a fourth sub-section 221 distributed between adjacent first electrodes 51 along the second direction Y and extending perpendicular to the substrate 1 and penetrating multiple layers, and a fifth sub-section 222 filling the region between adjacent word lines 40 along the perpendicular direction of the substrate 1 that are not surrounded by the semiconductor layer 23. The fourth sub-section 221 and the fifth sub-section 222 are connected to form an integral structure. The eleventh insulating layer 21 and the twelfth insulating layer 22 are not integral structures. The solution provided in this embodiment can achieve semiconductor layer cutting by removing the film layer filling between adjacent semiconductor layers along the perpendicular direction of the substrate, simplifying the cutting process.

[0096] In some embodiments, as shown in Figures 13B and 13C, the fourth sub-part 221 is distributed on the outer sidewall of the first electrode 51 extending in a direction perpendicular to the substrate 1, and extends continuously from the side of the outer sidewall near the bottom wall of the cylindrical structure to the side away from the bottom wall of the cylindrical structure. The fourth sub-part 221 may include a first portion 221a and a second portion 221b distributed along a first direction X. The second portion 221b is disposed on the side of the first portion 221a facing the word line 40, and the maximum dimension of the second portion 221b along the second direction Y is greater than the maximum dimension of the first portion 221a along the second direction Y. That is, the fourth sub-part 221 expands on the side near the bit line 30.

[0097] In some embodiments, the distance between two adjacent semiconductor layers 23 along the second direction Y, either on the side away from or towards the substrate 1, gradually decreases in the direction toward the bit line 30. As shown in FIG13A, the spacing between two adjacent semiconductor layers 23 on the side away from the substrate 1 decreases sequentially in the direction toward the bit line 30. Correspondingly, the dimensions of the semiconductor layers 23 on the side away from the substrate 1 increase sequentially in the direction toward the bit line 30. This structure facilitates the cutting of the isolation layer on one side after forming the isolation layer of transistors of different layers, simplifying the process.

[0098] In some embodiments, the transistor may further include a gate insulating layer 24 disposed between the semiconductor layer 23 and the word line 40, surrounding the word line 40. Multiple gate insulating layers 24 of multiple transistors distributed in the same column along the second direction Y in the same layer are connected on the side facing the substrate 1 and the side away from the substrate 1 to form an integral structure, and are disconnected on the side facing the bit line 30 and the side away from the bit line 30, as shown in Figures 1A and 1E; or, multiple gate insulating layers 24 of multiple transistors distributed in the same column along the second direction Y in the same layer are connected on the side facing the substrate 1, the side away from the substrate 1, the side facing the bit line 30, and the side away from the bit line 30 to form an integral structure, as shown in Figures 13B and 13F.

[0099] In some embodiments, the memory cell may further include a capacitor, with the capacitor and the transistor of the same memory cell distributed along the first direction X. The capacitor may include a dielectric layer 43 and a second capacitor electrode 42. The dielectric layer 43 is disposed between the first electrode 51 and the second capacitor electrode 42. The second capacitor electrode 42 fills the cylindrical structure formed by the first electrode 51 and is distributed on the side of the first electrode 51 away from the substrate 1, the side facing the substrate 1, and the outer wall perpendicular to the substrate 1. That is, the first electrode 51 is multiplexed as the first capacitor electrode 41 of the capacitor.

[0100] In some embodiments, multiple second capacitor electrodes 42 of multiple capacitors adjacent along the second direction Y can be connected to form an integral structure, and the integral structure formed by connecting multiple second capacitor electrodes 42 can fill the area between adjacent first electrodes 51 along the second direction Y, as shown in FIG1B, that is, a solid structure is formed between adjacent first electrodes 51; or, the integral structure formed by connecting multiple second capacitor electrodes 42 forms a groove with an opening direction facing the word line 40 between adjacent first electrodes 51 along the second direction Y, as shown in FIG13C. The groove includes a bottom wall and two sidewalls perpendicular to the substrate 1.

[0101] In some embodiments, the dielectric layers 43 of a plurality of capacitors adjacent to each other along the second direction Y can be connected to form an integral structure.

[0102] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a film pattern is formed through a "patterning process" or a "photolithography process." The "patterning process" includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".

[0103] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0104] 101) Form the first isolation layer 61;

[0105] A substrate 1 is provided, and a first insulating film and a first sacrificial layer film are alternately deposited on the substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0106] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of first trenches T1 penetrating the stacked structure; the first trenches T1 extend along a second direction Y;

[0107] Based on the first trench T1, the first insulating layer 11 is etched laterally (along the direction parallel to the substrate 1) to form the first lateral trench L1;

[0108] A first isolation layer film is deposited, which covers the bottom wall and sidewalls of the first trench T1 and fills the first transverse trench L1. The first isolation layer film in the first trench T1 is then etched away to form a first isolation layer 61 filling the first transverse trench L1. As shown in Figures 2A, 2B and 2C, Figure 2A is a three-dimensional schematic diagram of the first isolation layer 61 after its formation according to some embodiments; Figures 2B and 2C are cross-sectional views along the BB' direction and DD' direction, respectively, of the first isolation layer 61 after its formation according to some embodiments.

[0109] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0110] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to twelfth insulating films are similar and will not be described in detail.

[0111] In some embodiments, the first sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN).

[0112] In some embodiments, the first insulating layer film may be, for example, an aluminum oxide (Al2O3) film layer with an etching selectivity ratio to the first insulating film.

[0113] 102) Form the first hole K1 and the third hole K3;

[0114] The topmost first sacrificial layer 10 is etched away, a second insulating film is deposited and smoothed to form a second insulating layer 12 that fills the first trench T1 and covers the stacked structure.

[0115] The second insulating layer 12 and the stacked structure are etched along a direction perpendicular to the substrate 1 to form a plurality of first holes K1 penetrating the second insulating layer 12 along a direction perpendicular to the substrate 1; and a plurality of third holes K3 penetrating the stacked structure along a direction perpendicular to the substrate 1 are formed; wherein the orthographic projection of the first hole K1 onto the substrate 1 falls within the orthographic projection of the first trench T1 onto the substrate 1, and the sidewalls of the first hole K1 expose a plurality of first insulating layers 61; the plurality of first holes K1 are spaced apart along the second direction Y; the third holes K3 are disposed opposite to the first insulating layers 61. On one side of the first trench T1, the sidewall of the third hole K3 exposes multiple first isolation layers 61. Multiple third holes K3 are distributed at intervals along the second direction Y. The first hole K1 and the third hole K3 correspond to each other. The first hole K1 and the corresponding third hole K3 are distributed along the first direction X. As shown in Figures 3A, 3B and 3C, where Figure 3A is a three-dimensional schematic diagram of the formation of the first hole K1 and the third hole K3 provided in some embodiments; Figures 3B and 3C are cross-sectional views along the BB' direction and the DD' direction respectively after the formation of the first hole K1 and the third hole K3 provided in some embodiments.

[0116] In some embodiments, the dimension of the third hole K3 along the first direction X can be greater than the dimension along the second direction Y.

[0117] In some embodiments, the orthographic projection of the first hole K1 onto the substrate 1 can be square, circular, or the like.

[0118] 103) Form the fourth hole K4 and the first transverse groove A11;

[0119] After depositing the first dummy layer film, it is ground flat to form the first dummy layer 71 that fills the first hole K1 and the third hole K3;

[0120] The second insulating layer 12 and the stacked structure are etched along a direction perpendicular to the substrate 1, and a fourth hole K4 is formed between adjacent third holes K3 along the second direction Y. The sidewall of the fourth hole K4 does not expose the first insulating layer 61, but exposes the first dummy layer 71 in the two adjacent third holes K3; a fourth hole K4 is formed between each pair of adjacent third holes K3.

[0121] Based on the fourth hole K4, the first sacrificial layer 10 is etched laterally to form a first lateral groove A11. The first sacrificial layer 10 can be etched to the area close to the first isolation layer 61, so that the size of the retained first sacrificial layer 10 along the first direction is approximately the same as the size of the first isolation layer 61 along the first direction X, that is, the first sacrificial layer 10 in contact with the first isolation layer 61 is retained. As shown in Figures 4A, 4B, 4C and 4D, wherein Figure 4A is a perspective view of the fourth hole K4 and the first lateral groove A11 after forming according to some embodiments, and Figures 4B, 4C and 4D are cross-sectional views along the AA' direction, BB' direction and FF' direction respectively after forming the fourth hole K4 and the first lateral groove A11 according to some embodiments.

[0122] In some embodiments, the first dummy layer film may be a material with an etching selectivity ratio to the first isolation layer film, the first insulating film, and the first sacrificial layer film, such as polysilicon. The materials of the subsequent second to sixth dummy layer films are similar to those of the first dummy layer film and will not be described further.

[0123] 104) Form the first capacitor electrode 41, i.e., the first electrode 51;

[0124] A first conductive film and a second dummy layer film are deposited sequentially. The first conductive film covers the inner wall of the fourth hole K4 and the inner wall of the first transverse groove A11, and the second dummy layer film fills the first transverse groove A11 and the fourth hole K4.

[0125] The second dummy layer film in the fourth hole K4 is etched away, and the first conductive film on the sidewall of the fourth hole K4 is etched away, while the first conductive film and the second dummy layer film in the first transverse groove A11 are retained, forming the first capacitor electrode 41 and the second dummy layer 72, as shown in Figures 5A and 5B. Figures 5A and 5B are cross-sectional views along the AA' direction and FF' direction after the formation of the first capacitor electrode 41 provided in some embodiments, respectively.

[0126] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0127] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0128] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0129] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0130] The materials for the second to fourth conductive films are similar to those for the first conductive film, and will not be described in detail here.

[0131] 105) Form a third insulating layer 13 and a third dummy layer 73;

[0132] Based on the fourth hole K4, the first insulating layer 11 is etched laterally until the first isolation layer 61 is exposed. The first isolation layer 61 is etched laterally for a preset length, retaining part of the first isolation layer 61, without exposing the second insulating layer 12, and the retained first isolation layer 61 is connected to the first dummy layer 71 to form the second lateral groove A12.

[0133] A third insulating film is deposited to fill the second transverse groove A12 to form a third insulating layer 13; the third insulating layer 13 also covers the inner wall of the fourth hole K4 but does not completely fill the fourth hole K4; the third insulating layer 13 includes a protruding structure facing the bit line 30 (the bit line 30 has not yet been formed).

[0134] A third dummy layer film is deposited and smoothed to form a third dummy layer 73, which fills the fourth hole K4; as shown in Figures 6A, 6B, 6C and 6D, wherein Figures 6A, 6B, 6C and 6D are cross-sectional views along the AA' direction, BB' direction, EE' direction and FF' direction after the formation of the third insulating layer 13 and the third dummy layer 73 provided in some embodiments.

[0135] 106) Form the second hole K2 and the third transverse groove A13;

[0136] A fourth insulating film is deposited to form a fourth insulating layer 14 covering the structure formed above;

[0137] The fourth insulating layer 14 and the second insulating layer 12 are etched along a direction perpendicular to the substrate 1 to form a plurality of second holes K2 disposed between adjacent first holes K1 and penetrating the second insulating layer 12 along a direction perpendicular to the substrate 1. A second hole K2 is disposed between every two adjacent first holes K1. The sidewall of the second hole K2 exposes the first dummy layer 71 in the two adjacent first holes K1 and exposes the first isolation layer 61. Each layer exposes two adjacent first isolation layers 61 along the first direction X.

[0138] Based on the second hole K2, the first isolation layer 61 is laterally etched to form a third lateral groove A13, thereby breaking the first isolation layer 61 into multiple segments spaced apart along the second direction Y. Each segment is a first isolation sublayer, and the first isolation sublayer connects the first dummy layer 71 in the first hole K1 and the third hole K3, as shown in Figures 7A, 7B, 7C, and 7D. Figures 7A, 7B, 7C, and 7D are cross-sectional views along the AA', BB', CC', and FF' directions after the formation of the second hole K2 and the third lateral groove A13, respectively, according to some embodiments. Subsequently, the multiple semiconductor layers 23 can be disconnected by removing the first isolation sublayer to expose the semiconductor thin film.

[0139] 107) Form bit line 30 and fifth insulating layer 15;

[0140] A fifth insulating film is deposited, which fills the third transverse groove A13 and covers the bottom and sidewalls of the second hole K2. The fifth insulating film in the second hole K2 is etched away, while the fifth insulating film in the third transverse groove A13 is retained, forming a fifth insulating layer 15.

[0141] A second conductive film is deposited and the fourth insulating layer 14 is removed by grinding to form a bit line 30 that fills the second hole K2; as shown in Figures 8A, 8B, 8C and 8D, wherein Figures 8A, 8B, 8C and 8D are cross-sectional views along the AA' direction, BB' direction, CC' direction and FF' direction after the bit line 30 and the fifth insulating layer 15 are formed, respectively, according to some embodiments.

[0142] 108) Exposing the first hole K1 and the third hole K3;

[0143] A sixth insulating film is deposited to form a sixth insulating layer 16 covering the structure formed above;

[0144] The sixth insulating layer 16 is etched to expose the first dummy layer 71. The first dummy layer 71 in the first hole K1 and the third hole K3 is removed by etching to expose the first hole K1 and the third hole K3, as shown in Figures 9A, 9B, 9C and 9D. Figures 9A, 9B, 9C and 9D are cross-sectional views along the AA' direction, BB' direction, CC' direction and DD' direction after exposing the first hole K1 and the third hole K3, respectively, according to some embodiments.

[0145] 109) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0146] Based on the first hole K1 and the third hole K3, the first sacrificial layer 10 is removed by lateral etching to form channel B1, which extends along the second direction Y.

[0147] A semiconductor thin film, a gate insulating film, and a third conductive film are deposited sequentially. The semiconductor thin film and the gate insulating film sequentially cover the inner walls of the channel B1, the first hole K1, and the third hole K3. The third conductive film fills the channel B1 and covers the inner walls of the first hole K1 and the third hole K3. The semiconductor thin film, the gate insulating film, and the third conductive film in the first hole K1 and the third hole K3 are etched away, while the semiconductor thin film, the gate insulating film, and the third conductive film in the channel B1 are retained, forming multiple semiconductor layers 23 (referred to as semiconductor structure layers), multiple gate insulating layers 24 (referred to as gate insulating structure layers), and word lines 40 of multiple transistors. As shown in Figures 10A, 10B, 10C, and 10D, Figures 10A, 10B, 10C, and 10D are cross-sectional views along the AA' direction, DD' direction, EE' direction, and FF' direction after the formation of the semiconductor layer 23, the gate insulating layer 24, and the word lines 40 provided in some embodiments. At this time, the semiconductor structure layer is connected on the side away from the substrate 1 and the side facing the substrate 1, and is broken into multiple segments on the side away from the bit line 30 and the side facing the bit line 30.

[0148] In an exemplary embodiment of this disclosure, the material of the semiconductor layer 23 may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0149] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0150] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0151] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0152] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0153] In exemplary embodiments of this disclosure, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0154] 110) Disconnect the semiconductor layer 23 of multiple transistors in the same column;

[0155] Based on the first hole K1 and the third hole K3, the first isolation layer 61 is etched away to expose the semiconductor structure layer connected to the first isolation layer 61.

[0156] Etching removes the semiconductor structure layer connected to the first isolation layer 61, causing the multiple semiconductor layers 23 of the multiple transistors distributed along the second direction Y to be disconnected on the side away from the substrate 1 and the side facing the substrate 1. At this time, the multiple semiconductor layers 23 of the multiple transistors distributed along the second direction Y are disconnected.

[0157] A seventh insulating film is deposited to form a seventh insulating layer 17, which fills the first hole K1 and the third hole K3, as well as the area formed after the first isolation layer 61 is etched.

[0158] The sixth insulating layer 16 is etched away to expose the bit line 30 on the side away from the substrate 1, as shown in Figures 11A, 11B, 11C, 11D, 11E and 11F. Figures 11A to 11F are cross-sectional views along the AA', BB', CC', DD', EE' and FF' directions respectively after disconnecting the semiconductor layer 23 of multiple transistors in the same row according to some embodiments.

[0159] 111) Expose the first capacitor electrode 41;

[0160] Deposit a first hard mask thin film to form a first hard mask layer 81 covering the aforementioned structure;

[0161] The first hard mask layer 81 is etched along a direction perpendicular to the substrate 1 to form an opening; the sidewall of the opening exposes the third dummy layer 73;

[0162] The third dummy layer 73 is removed by the aperture etching, exposing the third insulating layer 13;

[0163] The third insulating layer 13 is etched, and the seventh insulating layer 17 is etched, leaving a portion of the first insulating layer 17, such that most of the outer wall of the first capacitor electrode 41 perpendicular to the substrate 1 (i.e., the two outer walls disposed opposite each other along the second direction Y) is exposed (the area adjacent to the semiconductor layer 23 is not exposed); and the third insulating layer 13 is etched, such that most of the outer wall of the first capacitor electrode 41 facing the substrate 1 and the outer wall facing away from the substrate 1 are exposed (the end connected to the semiconductor layer 23 and the area adjacent to the end are not exposed and are still covered by the third insulating layer 13).

[0164] The second dummy layer 72 is etched away, exposing the inner wall of the first capacitor electrode 41. At this time, the first capacitor electrode 41 forms a suspended structure, as shown in Figures 12A, 12B, 12C, and 12D. Figures 12A to 12D are cross-sectional views along the AA', BB', DD', and FF' directions after the first capacitor electrode 41 is exposed, respectively, according to some embodiments.

[0165] In some embodiments, the first hard mask film may be SiN or the like.

[0166] 112) Forming a dielectric layer 43 and a second capacitor electrode 42;

[0167] A dielectric layer thin film and a fourth conductive thin film are deposited sequentially to form a dielectric layer 43 and a second capacitor electrode 42. The dielectric layer 43 covers the inner wall of the first capacitor electrode 41, the outer wall of the first capacitor electrode 41 facing the substrate 1, the outer wall of the first capacitor electrode 41 away from the substrate 1, and the outer wall of the first capacitor electrode 41 disposed opposite each other along the second direction Y. The second capacitor electrode 42 fills the fourth hole K4 where the first capacitor electrode 41 is located, and fills the region between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1, and the region between adjacent first capacitor electrodes 41 along the second direction Y, as shown in Figures 1A to 1F.

[0168] The second capacitor electrode 42 may include a first sublayer and a second sublayer. The first sublayer may be a conductive thin film with good adhesion, such as TiN, and the second sublayer may be a conductive material with low resistivity, such as tungsten. The first sublayer is distributed on the inner bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1, and on the outer sidewalls disposed opposite each other along the second direction Y. The second sublayer fills the fourth hole K4 where the first capacitor electrode 41 is located, and fills the region between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1, and the region between adjacent first capacitor electrodes 41 along the second direction Y.

[0169] In some embodiments, the dielectric layer 43 may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0170] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0171] 201) Forming an isolation structure;

[0172] A substrate 1 is provided, and a buffer layer thin film is grown on the substrate 1 to form a buffer layer 9; the buffer layer thin film may be silicon germanium (SiGe) or the like, which can protect the substrate 1. In some embodiments, the buffer layer 9 may not be provided.

[0173] A first insulating film and a first sacrificial layer film are alternately deposited on the buffer layer 9 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0174] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of fifth holes K5 penetrating the stacked structure along a direction perpendicular to the substrate 1 (the bottom wall of the fifth hole K5 can expose the buffer layer 9); the plurality of fifth holes K5 are distributed in an array along a first direction X and a second direction Y; the size of the fifth hole K5 along the first direction X can be larger than the size along the second direction Y. For example, the fifth hole K5 can be a rectangular hole, and the size of the fifth hole K5 along the first direction X can be determined according to the size of the capacitor.

[0175] After sequentially depositing the first barrier layer film and the fourth dummy layer film, the layers are smoothed to form the first barrier layer 91 and the fourth dummy layer 74. The first barrier layer 91 covers the bottom wall and sidewalls of the fifth hole K5, and the fourth dummy layer 74 fills the fifth hole K5. As shown in Figures 14A and 14B, Figures 14A and 14B are cross-sectional views along the AA' and DD' directions respectively after the isolation structure is formed according to some embodiments. The first barrier layer 91 and the fourth dummy layer 74 serve as an isolation structure to isolate the subsequently formed first capacitor electrode 41.

[0176] In some embodiments, the first barrier layer film may be a low-K dielectric layer that has an etching selectivity ratio with the first sacrificial layer film, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0177] 202) Forming the second trench T2 and the second isolation layer 62;

[0178] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of second trenches T2 penetrating the stacked structure; the second trenches T2 extend along the second direction Y; a second trench T2 is disposed between two adjacent columns of fifth holes K5; the plurality of second trenches T2 are distributed at intervals along the first direction X (Figures 15A, 15B and 15C show only one second trench T2);

[0179] Based on the second trench T2, the first insulating layer 11 is laterally etched to expose the first barrier layer 91 to form the second lateral trench L2;

[0180] A second isolation layer film is deposited, covering the bottom and sidewalls of the second trench T2 and filling the second lateral trench L2. The second isolation layer film in the second trench T2 is then etched away to form a second isolation layer 62 filling the second lateral trench L2. As shown in Figures 15A, 15B, and 15C, Figures 15A, 15B, and 15C are cross-sectional views along the BB', DD', and FF' directions respectively after the formation of the second trench T2 and the second isolation layer 62 according to some embodiments. In this embodiment, the second isolation layer film in the region formed after the topmost first insulating layer 11 is etched laterally is etched away. The length of the second isolation layer 62 along the first direction X defines the length of the region where the transistor is located along the first direction X.

[0181] In some embodiments, the second isolation layer film may be a film layer that has an etching selectivity ratio with the sacrificial layer film, the first barrier layer film, and the first insulating film, such as polysilicon.

[0182] 203) Forming the third trench T3 and the third transverse trench L3;

[0183] After depositing the eighth insulating film, it is ground flat to form the eighth insulating layer 18, which fills the area formed after the second trench T2 and the top layer of the first insulating layer 11 are laterally etched; the eighth insulating layer 18 is flush with the fourth dummy layer 74 on the side away from the substrate 1.

[0184] The stacked structure is etched along a direction perpendicular to the substrate 1 on the side of the fifth hole K5 away from the second trench T2 to form a third trench T3 that penetrates the stacked structure along a direction perpendicular to the substrate 1. The third trench T3 extends along the second direction Y. Two columns of memory cells are defined between adjacent third trenches T3 along the first direction X, and one column of memory cells is defined between the third trench T3 and the second trench T2.

[0185] Based on the third trench T3, the first sacrificial layer 10 is etched laterally until it approaches the second isolation layer 62, such that the length of the first sacrificial layer 10 retained between the second trench T2 and the third trench T3 along the first direction X is slightly greater than the length of the second isolation layer 62 along the first direction X, forming the third transverse trench L3; as shown in Figures 16A, 16B, and 16C, Figures 16A, 16B, and 16C are cross-sectional views along the AA', DD', and FF' directions after the formation of the third trench T3 and the third transverse trench L3 according to some embodiments. The third transverse trench L3 may include a first transverse groove A11 disposed between adjacent first barrier layers 91.

[0186] 204) Form the first capacitor electrode 41;

[0187] A first conductive film and a fifth dummy layer film are deposited sequentially. The first conductive film covers the inner wall of the third transverse trench L3 and the inner wall of the third trench T3, and the fifth dummy layer film fills the third transverse trench L3.

[0188] The first conductive film and the fifth dummy layer film in the third trench T3 are etched away, and the first conductive film and the fifth dummy layer film in the third transverse trench L3 are etched until the first barrier layer 91 is exposed, forming the first capacitor electrode 41 and the fifth dummy layer 75. At this time, the first capacitor electrodes 41 of the plurality of capacitors are formed in the first transverse groove A11, separated by the first barrier layer 91 and disconnected from each other, and the fifth dummy layer 75 fills the first transverse groove A11. As shown in Figures 17A and 17B, Figures 17A and 17B are cross-sectional views along the AA' direction and FF' direction after the formation of the first capacitor electrode 41 provided in some embodiments.

[0189] 205) Forming the sixth hole K6 and the fourth transverse groove A14;

[0190] After depositing the sixth dummy layer film, it is ground flat to form the sixth dummy layer 76 that fills the third trench T3 and the third transverse trench L3 (the area in the third transverse trench L3 excluding the first transverse groove A11); the side of the sixth dummy layer 76 facing away from the substrate 1 is flush with the side of the fifth dummy layer 75 facing away from the substrate 1.

[0191] A ninth insulating film is deposited to cover the aforementioned structure, forming a ninth insulating layer 19;

[0192] The ninth insulating layer 19 and the eighth insulating layer 18 are etched along a direction perpendicular to the substrate 1 to form a plurality of sixth holes K6. The plurality of sixth holes K6 are spaced apart along the second direction Y. The sidewalls of the sixth holes K6 expose the second isolation layer 62 and expose two adjacent second isolation layers 62 along the first direction X.

[0193] Based on the multiple sixth holes K6, the second isolation layer 62 is laterally etched to expose the first insulating layer 11, forming multiple fourth lateral grooves A14. These fourth lateral grooves A14 space the second isolation layer 62 into multiple segments spaced along the second direction Y. Each segment is called a second isolation sublayer, as shown in Figures 18A, 18B, 18C, 18D, and 18E. Figures 18A to 18E are cross-sectional views along the AA', BB', CC', EE', and FF' directions after forming the sixth holes K6 and the fourth lateral grooves A14 according to some embodiments. The sixth holes K6 are distributed along the second direction Y between the fifth holes K5, and the remaining second isolation sublayers are distributed along the first direction X with the fifth holes K5.

[0194] 206) Formation of bit line 30;

[0195] A tenth insulating film is deposited, which fills the fourth transverse groove A14 and covers the bottom and sidewalls of the sixth hole K6. The tenth insulating film in the sixth hole K6 is etched away, while the tenth insulating film in the fourth transverse groove A14 is retained, forming the tenth insulating layer 20.

[0196] A second conductive film is deposited and smoothed to form a bit line 30 that fills the sixth hole K6; as shown in Figures 19A, 19B, 19C, 19D, and 19E, Figures 19A to 19E are cross-sectional views along the AA', BB', CC', EE', and FF' directions after the bit line 30 is formed, respectively, according to some embodiments.

[0197] 207) Formation of channel B1;

[0198] The ninth insulating layer 19 and the eighth insulating layer 18 are etched along a direction perpendicular to the substrate 1 to form a plurality of seventh holes K7. The seventh holes K7 are disposed between adjacent sixth holes K6 along the second direction Y. A seventh hole K7 is disposed between every two adjacent sixth holes K6. The sidewalls of the seventh holes K7 do not expose the bit line 30 and do not expose the second isolation layer 62.

[0199] Based on the seventh hole K7, the first sacrificial layer 10 is removed by lateral etching to form channel B1, which extends along the second direction Y. As shown in Figures 20A, 20B, 20C, 20D, 20E to 20F, Figures 20A to 20F are cross-sectional views along the AA', BB', CC', DD', EE' and FF' directions after the formation of channel B1 provided in some embodiments.

[0200] 208) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0201] A semiconductor thin film, a gate insulating film, and a third conductive film are sequentially deposited on a substrate 1 on which the aforementioned structure is formed. The semiconductor thin film and the gate insulating film sequentially cover the inner walls of the channel B1 and the seventh hole K7. The third conductive film fills the channel B1 and covers the inner walls of the seventh hole K7. The semiconductor thin film, the gate insulating film, and the third conductive film in the seventh hole K7 are etched away, while the semiconductor thin film, the gate insulating film, and the third conductive film in the channel B1 are retained, forming multiple semiconductor layers 23 (referred to as semiconductor structure layers), multiple gate insulating layers 24 (referred to as gate insulating structure layers), and word lines 40 of multiple transistors. As shown in Figures 21A, 21B, 21C, and 21D, Figures 21A to 21D are cross-sectional views along the AA' direction, DD' direction, EE' direction, and FF' direction after the formation of the semiconductor layer 23, the gate insulating layer 24, and the word lines 40 in some embodiments. At this time, the semiconductor layer 23 of multiple transistors is connected on the side away from the substrate 1, the side facing the substrate 1, and the side away from the bit line 30, and disconnected on the side facing the bit line 30 (disconnected at the location of the seventh hole K7).

[0202] 209) Expose the first capacitor electrode 41;

[0203] An eleventh insulating film is deposited to fill the seventh hole K7, forming an eleventh insulating layer 21;

[0204] A second hard mask layer thin film is deposited to form a second hard mask layer 82 covering the structure formed above;

[0205] The stacked structure is etched along a direction perpendicular to substrate 1 to expose the third trench T3;

[0206] Based on the third trench T3, the sixth dummy layer 76 is etched laterally to expose the inner wall of the first capacitor electrode 41. Based on the third trench T3, the first insulating layer 11 and the first barrier layer 91 are etched laterally, so that most of the outer wall of the first capacitor electrode 41 is exposed (including two outer walls extending perpendicular to the substrate 1 (i.e., two outer walls opposite to each other along the second direction Y), the outer wall facing the substrate 1 and the outer wall away from the substrate 1), and the area adjacent to the semiconductor layer 23 is not exposed, as shown in Figures 22A, 22B, 22C and 22D. Figures 22A to 22D are cross-sectional views along the AA' direction, BB' direction, DD' direction and FF' direction after exposing the first capacitor electrode 41 according to some embodiments.

[0207] In some embodiments, the second hard mask layer thin film may be SiN or the like.

[0208] 210) Forming a dielectric layer 43 and a second capacitor electrode 42;

[0209] A dielectric layer thin film and a fourth conductive thin film are deposited sequentially to form a dielectric layer 43 and a second capacitor electrode 42. The dielectric layer 43 covers the inner wall of the first capacitor electrode 41, the outer wall of the first capacitor electrode 41 facing the substrate 1, the outer wall of the first capacitor electrode 41 away from the substrate 1, and the outer wall of the first capacitor electrode 41 disposed opposite each other along the second direction Y. The second capacitor electrode 42 fills the first transverse groove A11 where the first capacitor electrode 41 is located, and fills the area between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1, and the area between adjacent first capacitor electrodes 41 along the second direction Y, as shown in Figures 23A, 23B, 23C, and 23D. Figures 23A to 23D are cross-sectional views along the AA', BB', DD', and FF' directions after the formation of the dielectric layer 43 and the second capacitor electrode 42 according to some embodiments.

[0210] In some embodiments, the second capacitor electrode 42 may include a first sublayer and a second sublayer. The first sublayer may be a conductive material with good adhesion, such as TiN, and the second sublayer may be a conductive material with low resistivity, such as tungsten. The first sublayer is distributed on the inner bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1, and on the outer sidewalls disposed opposite each other along the second direction Y. The second sublayer fills the first transverse groove A11 where the first capacitor electrode 41 is located, and fills the region between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1, and the region between adjacent first capacitor electrodes 41 along the second direction Y. Figures 23A to 23D do not show the independent first and second sublayers; only the single-layer structure of the second capacitor electrode 42 is shown.

[0211] 211) Disconnect multiple semiconductor layers 23 of multiple transistors;

[0212] The second isolation layer 82 is etched to expose the first barrier layer 91 and the fourth dummy layer 74.

[0213] The fourth dummy layer 74 and the first barrier layer 91 are etched away to expose the second isolation layer 62. The second isolation layer 62 is etched away to expose the semiconductor structure layer on the side facing the substrate 1, the side away from the substrate 1, and the side away from the bit line 30. The exposed semiconductor structure layer is etched away so that the multiple semiconductor layers 23 of the multiple transistors distributed along the second direction Y are disconnected on the side facing the substrate 1, the side away from the substrate 1, and the side away from the bit line 30. At this time, the multiple semiconductor layers 23 of the multiple transistors are disconnected, as shown in Figures 24A, 24B, 24C, and 24D. Figures 24A to 24D are cross-sectional views along the AA' direction, BB' direction, DD' direction, and EE' direction after the multiple semiconductor layers 23 of the multiple transistors are disconnected, respectively, according to some embodiments.

[0214] 212) Form the twelfth insulating layer 22;

[0215] A twelfth insulating film is deposited to form a twelfth insulating layer 22, which fills the cavity formed after etching away the fourth dummy layer 74, the first barrier layer 91 and the second isolation layer 62 in step 211), as shown in Figures 13B to 13G.

[0216] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0217] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, comprising: A multilayer array of memory cells stacked perpendicular to the substrate, the array comprising at least one column of multiple memory cells distributed along a second direction; Multiple bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; memory cells at the same position in different layers are connected to the same bit line; Multiple word lines are distributed in different layers. The word lines and bit lines are distributed along a first direction, and the word lines extend along a second direction. The first direction and the second direction are parallel to the substrate and intersect. The memory cell includes a transistor, the transistor including a first electrode and a semiconductor layer connected to the first electrode, the first electrode being disposed on the semiconductor layer away from the bit line, the first electrode forming a cylindrical structure with its opening direction away from the semiconductor layer; multiple semiconductor layers of multiple transistors in the same column surround the same word line, and the multiple semiconductor layers of multiple transistors in the same column are spaced apart along a second direction; the sidewall of the semiconductor layer facing the bit line and perpendicular to the substrate is connected to the bit line, the dimension of the surface of the semiconductor layer facing the bit line along the second direction is larger than the dimension of the bit line along the second direction, and the semiconductor layer covers the surface of the first electrode facing the semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a seventh insulating layer, the seventh insulating layer comprising a first sub-part disposed between adjacent bit lines along a second direction and extending through multiple layers in a direction perpendicular to the substrate, a second sub-part disposed between adjacent first electrodes along the second direction and extending through multiple layers in a direction perpendicular to the substrate, a third sub-part disposed in a region on the word line facing away from the substrate and not surrounded by the semiconductor layer, and a region on the word line facing the substrate and not surrounded by the semiconductor layer, wherein the third sub-part fills the region between adjacent word lines along the direction perpendicular to the substrate that are not surrounded by the semiconductor layer, the first sub-part, the second sub-part, and the third sub-part are connected to form an integral structure, the first sub-part is connected to the word line on the side facing the bit line, and the second sub-part is connected to the word line on the side facing away from the bit line.

3. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a third insulating layer and a fifth insulating layer that fill the regions of adjacent word lines surrounded by the semiconductor layer along a direction perpendicular to the substrate. The third insulating layer and the fifth insulating layer are distributed along a first direction. The third insulating layer is disposed on the side of the fifth insulating layer opposite to the bit line, and the third insulating layer forms a protrusion structure facing the bit line. The fifth insulating layer forms a recess structure on the side opposite to the bit line, and the fifth insulating layer is connected to the bit line.

4. The semiconductor device according to claim 1, wherein, The distance between the two semiconductor layers of two adjacent transistors along the second direction is greater on the side away from the bit line than on the side facing the bit line.

5. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: an eleventh insulating layer disposed between adjacent bit lines along a second direction and extending in a direction perpendicular to the substrate, penetrating multiple layers; and an eighth insulating layer disposed between the eleventh insulating layer and the bit lines, extending in a direction perpendicular to the substrate, penetrating multiple layers. And, a twelfth insulating layer, the twelfth insulating layer comprising a fourth sub-section distributed between adjacent first electrodes along a second direction and extending along a direction perpendicular to the substrate and penetrating multiple layers, and a fifth sub-section filling the region between regions of adjacent word lines along a direction perpendicular to the substrate that are not surrounded by the semiconductor layer, the fourth sub-section and the fifth sub-section being connected to form an integral structure, the eleventh insulating layer and the twelfth insulating layer being a non-integral structure.

6. The semiconductor device according to claim 5, wherein, The fourth sub-part is distributed on the outer wall of the first electrode extending in a direction perpendicular to the substrate, and extends continuously from the side of the outer wall near the bottom wall of the cylindrical structure to the side away from the bottom wall of the cylindrical structure. The fourth sub-part includes a first part and a second part distributed along a first direction. The second part is disposed on the side of the first part facing the word line, and the maximum size of the second part along the second direction is greater than the maximum size of the first part along the second direction.

7. The semiconductor device according to claim 5, wherein, The distance between two adjacent semiconductor layers along the second direction, either on the side away from the substrate or on the side facing the substrate, gradually decreases in the direction toward the bit line.

8. The semiconductor device according to claim 1, wherein, The transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line surrounding the word line. Multiple gate insulating layers of multiple transistors in the same column distributed along the second direction in the same layer are connected to form an integral structure on the side facing the substrate and the side away from the substrate, and are disconnected on the side facing the bit line and the side away from the bit line. Alternatively, multiple gate insulating layers of multiple transistors distributed in the same column along the second direction on the same layer are connected to form an integral structure on the side facing the substrate, the side away from the substrate, the side facing the bit line, and the side away from the bit line.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The storage cell further includes a capacitor, and the capacitor and the transistor in the same storage cell are distributed along the first direction. The capacitor includes a dielectric layer and a second capacitor electrode. The dielectric layer is disposed between the first electrode and the second capacitor electrode. The second capacitor electrode fills the cylindrical structure formed by the first electrode and is distributed on the side of the first electrode away from the substrate, the side facing the substrate, and the outer wall perpendicular to the substrate.

10. The semiconductor device according to claim 9, wherein, Multiple second capacitor electrodes of multiple capacitors adjacent along the second direction are connected to form an integral structure, and the integral structure formed by connecting multiple second capacitor electrodes fills the area between first electrodes adjacent along the second direction. Alternatively, an integral structure formed by connecting multiple second capacitor electrodes may form a groove with an opening direction facing the word line between adjacent first electrodes along the second direction.

11. A method for manufacturing a semiconductor device, comprising: A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate; A first trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction. Based on the first trench, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral trench. A first insulating layer is formed to fill the first transverse trench, and a second insulating layer is formed to fill the first trench; A plurality of first holes are formed penetrating the second insulating layer along a direction perpendicular to the substrate, and a plurality of third holes are formed penetrating the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along a second direction, and the plurality of third holes are spaced apart along the second direction. The third holes are disposed on the side of the first isolation layer opposite to the first trench. The sidewalls of the first holes and the sidewalls of the third holes are exposed in the first isolation layer. The first holes and the third holes are distributed along a first direction. A first dummy layer is formed to fill the first holes and the third holes. The first direction and the second direction are parallel to the substrate and intersect. A fourth hole is formed between adjacent third holes along the second direction, penetrating the stacked structure in a direction perpendicular to the substrate. The sidewall of the fourth hole does not expose the first isolation layer, but exposes the first dummy layer. Based on the fourth hole, the first sacrificial layer is etched along a predetermined length parallel to the substrate to form a first lateral groove, and a first electrode is formed covering the inner wall of the first lateral groove. Based on the fourth hole, the first insulating layer and the first isolation layer are etched along the direction parallel to the substrate, and a portion of the first isolation layer is retained so as not to expose the second insulating layer; A plurality of second holes are formed between adjacent first holes along the second direction, penetrating the second insulating layer in a direction perpendicular to the substrate. The sidewalls of the second holes expose the first insulating layer. Based on the second holes, the first insulating layer is etched in a direction parallel to the substrate, such that the first insulating layer is broken into multiple segments spaced apart along the second direction; bit lines are formed to fill the second holes. The first dummy layer in the first hole and the third hole is removed by etching. Based on the first hole and the third hole, the first sacrificial layer is etched along the direction parallel to the substrate to form a channel extending along the second direction. A semiconductor structure layer, a gate insulating structure layer and a word line are sequentially formed in the channel. The gate insulating structure layer and the semiconductor structure layer sequentially surround the word line. The word line fills the channel. The semiconductor structure layer is broken into multiple segments on the side facing the bit line and on the side away from the bit line. The first isolation layer is removed by etching based on the first hole and the third hole, and the semiconductor structure layer exposed by etching is broken into multiple segments that are spaced apart along the second direction on the side facing the substrate and the side away from the substrate.

12. The method for manufacturing a semiconductor device according to claim 11, wherein, After etching to expose the semiconductor structure layer on the substrate-facing side and the substrate-removing side, the method further includes: The inner wall of the first electrode is exposed, as well as the outer walls of the first electrode facing the substrate and away from the substrate, and the first electrode is perpendicular to the outer wall of the substrate; a first transverse groove is formed to fill the first electrode and to cover the exposed outer walls of the first electrode facing the substrate and away from the substrate, and a second capacitor electrode is formed with the first electrode perpendicular to the outer wall of the substrate.

13. A method for manufacturing a semiconductor device, comprising: A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate; A plurality of fifth holes are formed that penetrate the stacked structure along a direction perpendicular to the substrate and are spaced apart along the second direction; A second trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction; The second trench and the fifth hole are spaced apart along the first direction to form a first barrier layer covering the bottom wall and sidewall of the fifth hole and a fourth dummy layer filling the fifth hole; the first sacrificial layer is etched along the direction parallel to the substrate based on the second trench to form a second lateral trench; A second isolation layer is formed to fill the second lateral trench, and an eighth insulating layer is formed to fill the second trench; the first direction and the second direction are parallel to the substrate and intersect. A third trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate and extends along a second direction, the third trench being disposed on the side of the fifth hole opposite to the second trench; Based on the third trench, the first sacrificial layer is etched along a direction parallel to the substrate to form a third lateral trench, the third lateral trench including a first lateral groove disposed between adjacent first barrier layers; and a first electrode is formed covering the inner wall of the first lateral groove. A plurality of sixth holes are formed penetrating the eighth insulating layer along a direction perpendicular to the substrate. The plurality of sixth holes are spaced apart along the second direction, and the sidewalls of the six holes expose the second isolation layer. Based on the sixth holes, the second isolation layer is etched along a direction parallel to the substrate, such that the second isolation layer is broken into multiple segments spaced apart along the second direction. Bit lines are formed to fill the sixth holes. A plurality of seventh holes are formed between adjacent sixth holes along the second direction, penetrating the eighth insulating layer in a direction perpendicular to the substrate. The sidewalls of the seventh holes expose the second isolation layer but not the bit line. The first sacrificial layer is removed by etching along the direction parallel to the substrate based on the seventh holes, forming a channel extending along the second direction. A semiconductor structure layer, a gate insulating structure layer, and a word line are sequentially formed in the channel. The gate insulating structure layer and the semiconductor structure layer sequentially surround the word line. The word line fills the channel, and the semiconductor structure layer is broken into multiple segments on the side facing the bit line. The fourth dummy layer and the first barrier layer are etched to expose the second isolation layer. The second isolation layer is then etched away. The semiconductor structure layer exposed by the etching is separated from the bit line side, the substrate side, and the substrate side, so that the semiconductor structure layer separated from the bit line side, the substrate side, and the substrate side is broken into multiple segments spaced apart along the second direction.

14. The method for manufacturing a semiconductor device according to claim 13, wherein, After the semiconductor structure layer, gate insulating structure layer and word line are sequentially formed in the channel, and before etching the fourth dummy layer and the first barrier layer to expose the second isolation layer, the method further includes: The inner wall of the first electrode, the outer wall of the first electrode facing the substrate and the outer wall of the first electrode away from the substrate are exposed, and the first barrier layer is etched while retaining the first barrier layer facing the bit line, exposing the outer wall of the first electrode perpendicular to the substrate. A first transverse groove is formed to fill the first electrode and an outer wall covering the exposed side of the first electrode facing the substrate and the side away from the substrate, and a second capacitor electrode is formed whereby the first electrode is perpendicular to the outer wall of the substrate.

15. An electronic device comprising a semiconductor device as claimed in any one of claims 1 to 10, or a semiconductor device formed by a method of manufacturing a semiconductor device according to any one of claims 11 to 14.

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