Semiconductor device

Abstract

Provided is a semiconductor device with excellent characteristics. This semiconductor device includes a first insulating layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer, and a first conductive layer on the second insulating layer. The first conductive layer and the semiconductor layer overlap each other with the second insulating layer interposed therebetween. The first insulating layer has a first layer and a second layer on the first layer. The second layer contains gallium oxide. The first layer contains one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The second insulating layer has a third layer and a fourth layer on the third layer. The third layer contains gallium oxide. The fourth layer contains one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The semiconductor layer contains indium oxide.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties.

[0003] In recent years, the development of semiconductor devices has progressed, and these devices are mainly used in LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and capacitors) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0004] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0005] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0006] Transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Patent Document 2 also discloses a memory device that uses oxide semiconductors and can retain stored data for a long period of time.

[0007] Furthermore, Non-Patent Document 1 reports on a polycrystalline indium oxide film exhibiting high hole mobility and a transistor using it. Also, Non-Patent Document 2 reports on In ２ O ３ Its use in thin-film transistors has been reported.

[0008] Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, Nature Communications 13, 1078, (2022). Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a transistor with good electrical characteristics. One aspect of the present invention aims to provide a transistor with a large on-current. One aspect of the present invention aims to provide a transistor with low parasitic capacitance. One aspect of the present invention aims to provide a semiconductor device having a transistor with excellent characteristics. One aspect of the present invention aims to provide a semiconductor device with excellent characteristics. One aspect of the present invention aims to provide a highly reliable transistor, semiconductor device, display device, or memory device. One aspect of the present invention aims to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device, display device, or memory device with low power consumption. One aspect of the present invention aims to provide a memory device with a fast operating speed.

[0011] One aspect of the present invention aims to provide a semiconductor device having a novel configuration. Another aspect of the present invention aims to mitigate at least one of the problems of the prior art.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc.

[0013] One aspect of the present invention is a semiconductor device comprising a first insulating layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer, and a first conductive layer on the second insulating layer, wherein the first conductive layer and the semiconductor layer overlap each other with the second insulating layer in between, the first insulating layer comprises a first layer and a second layer on the first layer, the second layer comprises gallium oxide, the first layer comprises one or more selected from hafnium oxide, silicon nitride and silicon oxide, the second insulating layer comprises a third layer and a fourth layer on the third layer, the third layer comprises gallium oxide, the fourth layer comprises one or more selected from hafnium oxide, silicon nitride and silicon oxide, and the semiconductor layer comprises indium oxide.

[0014] Alternatively, one aspect of the present invention is a semiconductor device comprising: a first conductive layer; a first insulating layer on the first conductive layer; a semiconductor layer on the first insulating layer; a second insulating layer on the semiconductor layer; and a second conductive layer on the second insulating layer, wherein the first conductive layer and the semiconductor layer overlap each other with the first insulating layer in between; the second conductive layer and the semiconductor layer overlap each other with the second insulating layer in between; the first insulating layer comprises a first layer and a second layer on the first layer, the second layer comprising gallium oxide; the first layer comprising one or more selected from hafnium oxide, silicon nitride, and silicon oxide; the second insulating layer comprising a third layer and a fourth layer on the third layer, the third layer comprising gallium oxide; the fourth layer comprising one or more selected from hafnium oxide, silicon nitride, and silicon oxide; and the semiconductor layer comprising indium oxide.

[0015] Alternatively, one aspect of the present invention comprises a first conductive layer, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, wherein the first conductive layer and the semiconductor layer overlap each other with the first insulating layer in between, the second conductive layer and the semiconductor layer overlap each other with the second insulating layer in between, and the first insulating layer comprises a first layer, a second layer on the first layer, and a third layer on the second layer, and the third layer The semiconductor device comprises a gallium oxide layer, a second layer having either or both silicon oxide and hafnium oxide, a first layer having silicon nitride, a second insulating layer having a fourth layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer, the fourth layer having gallium oxide, the fifth layer having either or both silicon oxide and hafnium oxide, the sixth layer having silicon nitride, and a semiconductor layer containing indium oxide.

[0016] Furthermore, in the above configuration, it is preferable that the second layer has hafnium oxide, and the fifth layer has a seventh layer and an eighth layer on the seventh layer, with the seventh layer having silicon oxide and the eighth layer having hafnium oxide.

[0017] Alternatively, one aspect of the present invention comprises a first conductive layer, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, wherein the first conductive layer and the semiconductor layer overlap each other with the first insulating layer in between, and the second conductive layer and the semiconductor layer overlap each other with the second insulating layer in between, the first insulating layer comprises a first layer and a second layer on the first layer, the second layer comprises gallium oxide, the first layer comprises one or more selected from hafnium oxide, silicon nitride and silicon oxide, the second insulating layer comprises a third layer and a fourth layer on the third layer, the third layer comprises gallium oxide The semiconductor device has a fourth layer having one or more selected from hafnium oxide, silicon nitride, and silicon oxide, and the semiconductor layer has a first oxide semiconductor layer, a second oxide semiconductor layer on the first oxide semiconductor layer, and a third oxide semiconductor layer on the second oxide semiconductor layer, the second oxide semiconductor layer having indium, and each of the first oxide semiconductor layer and the third oxide semiconductor layer having indium and gallium, and in each of the first oxide semiconductor layer and the third oxide semiconductor layer, the ratio of the number of gallium atoms to the sum of the number of indium and gallium atoms is higher than the ratio in the second oxide semiconductor layer.

[0018] One aspect of the present invention is a semiconductor device comprising an insulating layer and a semiconductor layer on the insulating layer, wherein the semiconductor layer comprises indium and oxygen, the insulating layer comprises an element having a stronger bonding force with oxygen than with indium, and a mixed layer between the insulating layer and the semiconductor layer, wherein the mixed layer comprises indium, oxygen, and the said element.

[0019] Furthermore, in the above embodiment, it is preferable that the semiconductor layer has a crystalline portion whose crystal structure is a bixbyte structure.

[0020] Alternatively, one aspect of the present invention is a semiconductor device having an insulating layer and a semiconductor layer on the insulating layer, wherein the semiconductor layer has indium and oxygen, the insulating layer has gallium or aluminum and oxygen, and there is a mixed layer between the insulating layer and the semiconductor layer, wherein the mixed layer has gallium or aluminum, indium and oxygen.

[0021] Furthermore, in the above embodiment, it is preferable that the semiconductor layer has a crystalline portion whose crystal structure is a bixbyte structure.

[0022] Furthermore, in the above embodiment, it is preferable that the Bigsbite structure has strain.

[0023] Alternatively, one aspect of the present invention is a semiconductor device comprising an insulating layer, a first semiconductor layer on the insulating layer, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, wherein the first to third semiconductor layers each contain indium and oxygen, the insulating layer contains an element with a stronger bonding force with oxygen than indium, and there is a mixed layer between the insulating layer and the first semiconductor layer, the mixed layer contains indium, oxygen, and the said element, and the second semiconductor layer has a lower film density than the first and third semiconductor layers.

[0024] Furthermore, in the above embodiment, the first semiconductor layer preferably has a crystalline portion whose crystal structure is a bixbite structure, and the bixbite structure is strained.

[0025] Furthermore, in the above embodiment, the second semiconductor layer has a lower film density than the first and third semiconductor layers, and the second semiconductor layer has a crystalline portion whose crystal structure is a bixbyte structure, and the bixbyte structure is a semiconductor device having strain.

[0026] In the above embodiment, it is preferable that the sum of the thicknesses of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is 0.1 nm or more and 30 nm or less.

[0027] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-current can be provided. According to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. According to one aspect of the present invention, a semiconductor device having a transistor with excellent characteristics can be provided. According to one aspect of the present invention, a semiconductor device having excellent characteristics can be provided. According to one aspect of the present invention, a highly reliable transistor, semiconductor device, display device, or memory device can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device, display device, or memory device with low power consumption can be provided. According to one aspect of the present invention, a memory device with a fast operating speed can be provided.

[0028] According to one aspect of the present invention, a semiconductor device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be mitigated.

[0029] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0030] Figures 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, and 1J show examples of semiconductor device configurations. Figures 2A, 2B, 2C, and 2D show examples of semiconductor device configurations. Figures 3A, 3B, 3C, 3D, 3E, 3F, and 3G show examples of semiconductor device configurations. Figures 4A, 4B, 4C, and 4D show examples of semiconductor device configurations. Figures 5A, 5B, 5C, 5D, 5E, and 5F show examples of semiconductor device configurations. Figures 6A, 6B, and 6C show examples of semiconductor device configurations. Figures 7A, 7B, 7C, and 7D show examples of semiconductor device configurations. Figures 8A, 8B, and 8C show examples of semiconductor device configurations. Figures 9A, 9B, and 9C show examples of semiconductor device configurations. Figures 10A, 10B, and 10C show examples of semiconductor device configurations. Figure 11 shows an example of semiconductor device configuration. Figures 12A and 12B show examples of semiconductor device configurations. Figures 13A and 13B show examples of semiconductor device configurations. Figures 14A and 14B show examples of semiconductor device configurations. Figures 15A and 15B show examples of semiconductor device configurations. Figures 16A, 16B, and 16C show examples of semiconductor device configurations. Figures 17A, 17B, and 17C show examples of semiconductor device configurations. Figures 18A, 18B, and 18C show examples of semiconductor device configurations. Figures 19A and 19B illustrate the carrier concentration dependence of Hall mobility. Figure 19C is a cross-sectional view illustrating an indium oxide film. Figure 20 shows an example of a memory device configuration. Figures 21A and 21B show examples of memory device configurations. Figures 22A, 22B, 22C, and 22D show examples of memory device configurations. Figure 23 shows an example of memory device configuration. Figures 24A and 24B show examples of display device configurations. Figure 25 shows an example of display device configuration. Figures 26A, 26B, 26C, and 26D show examples of electronic device configurations. Figures 27A, 27B, 27C, 27D, 27E, and 27F show examples of electronic device configurations. Figures 28A, 28B, 28C, 28D, 28E, 28F, and 28G show examples of electronic device configurations. Figures 29A and 29B show examples of electronic component configurations. Figures 30A, 30B, and 30C show examples of large-scale computer configurations. Figures 31A and 31B are perspective views of semiconductor devices. Figure 32 is a perspective view of semiconductor devices.Figures 33A and 33B show the structures used in the calculations. Figure 34 shows the energy calculation results.

[0031] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0032] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0033] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to those figures.

[0034] Furthermore, ordinal numbers such as "the first," "the second," etc., used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0035] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0036] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0037] Furthermore, in this specification, "electrically connected" includes cases where a connection is made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0038] In this specification, cases where two nodes are connected via an insulator, such as the dielectric of a capacitive element, the gate insulating film of a transistor, or an interlayer insulating film, are not included in the definition of "electrical connection."

[0039] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights also match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0040] In this specification, "side edges coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B in a plan view is 10 nm or less, then the side edges also coincide.

[0041] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0042] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0043] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the surface to be formed may be described as "down" and the laminate side as "up."

[0044] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0045] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0046] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0047] In this specification and the like, the content rate of an element in a metal oxide refers to the ratio of the number of atoms of that element to the sum of the number of atoms of the metal elements contained in the metal oxide. For example, if the metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are A Ｘ , A Ｙ , A Ｚ , when the content rate of metal element X is A Ｘ / (A Ｘ + A Ｙ + A Ｚ ). Also, when the ratio of the number of atoms (atom ratio) of metal element X, metal element Y, and metal element Z in the metal oxide is B Ｘ : B Ｙ : B Ｚ , the content rate of metal element X can be expressed as B Ｘ / (B Ｘ + B Ｙ + B Ｚ ). Note that the main component of a metal oxide refers to an element with a content rate of 0.1% or more. Also, an element with a content rate of less than 0.1% may be referred to as an impurity. Note that oxygen is the main component of the metal oxide, but the number of oxygen atoms is not considered in the calculation of the above ratio and the above content rate.

[0048] (Embodiment 1) In this embodiment, a semiconductor device of one aspect of the present invention and a method for manufacturing the same will be described. A semiconductor device of one aspect of the present invention includes a transistor.

[0049] [Configuration example of semiconductor device] FIG. 1A is a schematic cross-sectional view of a semiconductor device. A semiconductor device according to one aspect of the present invention includes a substrate 20, an insulating layer 51, a semiconductor layer 30, an insulating layer 50, and a conductive layer 60.

[0050] Figure 1A shows a configuration in which an insulating layer 51 is provided on a substrate 20, a semiconductor layer 30 is provided on the insulating layer 51, an insulating layer 50 is provided on the semiconductor layer 30, and a conductive layer 60 is provided on the insulating layer 50. In Figure 1A, the semiconductor layer 30, the insulating layer 50, and the conductive layer 60 are shown to be stacked perpendicular to the upper surface of the substrate 20. However, the present invention is not limited to this. For example, the semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can also be stacked parallel to the upper surface of the substrate 20.

[0051] In a transistor according to one aspect of the present invention, the conductive layer 60 functions as a gate electrode, and the insulating layer 50 functions as a gate insulating layer. The semiconductor layer 30 also has a channel formation region. At least a portion of the region of the semiconductor layer 30 that overlaps with the conductive layer 60 via the insulating layer 50 functions as a channel formation region.

[0052] Figure 2A also shows an example in which the semiconductor device has a conductive layer 25 between the substrate 20 and the insulating layer 51. The insulating layer 51 is sandwiched between the conductive layer 25 and the semiconductor layer 30. In the configuration shown in Figure 2A, the semiconductor device also has an insulating layer 52 between the substrate 20 and the insulating layer 51, and the conductive layer 25 is embedded in the insulating layer 52. In addition, the semiconductor device can also be configured such that the conductive layer 25 is embedded in a portion of the insulating layer 51. Specifically, the insulating layer 51 is provided on the conductive layer 25, and the semiconductor layer 30 is provided on the insulating layer 51. The conductive layer 25 has a region that overlaps with the semiconductor layer 30 with the insulating layer 51 in between. Furthermore, the conductive layer 25 has a region that overlaps with the conductive layer 60 with the semiconductor layer 30 in between.

[0053] In the transistor shown in Figure 2A, the conductive layer 60 functions as a first gate electrode, the insulating layer 50 functions as a first gate insulating layer, the conductive layer 25 functions as a second gate electrode, and the insulating layer 51 functions as a second gate insulating layer.

[0054] The transistor shown in Figure 2A can be called a dual-gate transistor, a double-gate transistor, or an S-channel (surrounded channel) transistor. In an S-channel transistor, the channel formation region can be electrically surrounded by the electric field of either or both of the first and second gates. Therefore, by adopting an S-channel structure, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur. Furthermore, since the S-channel structure electrically surrounds the channel formation region, it can be said that it is essentially equivalent to a GAA (Gate All Around) structure. By adopting a GAA structure, it is possible to improve the current density flowing through the transistor, and thus it is expected that the on-current of the transistor or the field-effect mobility of the transistor can be increased.

[0055] By using the conductive layer 25 as a second gate electrode, the on-current can be increased or the threshold voltage can be controlled. For example, by setting the conductive layer 60 and the conductive layer 25 to the same potential and driving them as a double-gate transistor, the on-current can be increased. Alternatively, by applying a different potential to the conductive layer 25 than to the conductive layer 60, the threshold voltage can be controlled. Therefore, by controlling the threshold voltage, it is easy to realize a transistor with normally-off characteristics.

[0056] A transistor according to one aspect of the present invention has a semiconductor layer 30 including a channel-forming region, which contains a metal oxide (also called an oxide semiconductor) that functions as a semiconductor. In other words, this transistor can be called an OS transistor. In this specification, a semiconductor layer having an oxide semiconductor can be referred to as an oxide semiconductor layer.

[0057] For the semiconductor layer 30, it is preferable to use an indium-containing oxide, and particularly preferable to use indium oxide. The band gap of the indium-containing oxide is 2.0 eV or more, or 2.5 eV or more. By using a metal oxide with a large band gap for the semiconductor layer 30, the off-current of the transistor can be reduced. Because the OS transistor has a small off-current, the power consumption of the semiconductor device can be sufficiently reduced. In addition, because the OS transistor has high frequency characteristics, the semiconductor device can be operated at high speed.

[0058] For information on indium oxide that can be used as the semiconductor layer 30, please refer to the description in Embodiment 3. A detailed explanation is omitted here.

[0059] When a metal oxide is used as the semiconductor layer 30, it is preferable that defects such as oxygen vacancies are sufficiently reduced. Oxygen vacancies can be reduced by supplying oxygen to the semiconductor layer 30.

[0060] Furthermore, by surrounding the semiconductor layer 30 with a layer that has barrier properties against oxygen, it is possible to suppress the detachment of oxygen from the semiconductor layer 30 and the formation of oxygen vacancies.

[0061] Therefore, it is preferable that the insulating layer 50 and the insulating layer 51 are insulating layers that have barrier properties against oxygen.

[0062] Also, oxygen deficiency and defects in which hydrogen has entered the oxygen deficiency (V Ｏ Oxygen deficiencies (also called H) can be formed when oxygen is removed from the semiconductor layer. For example, oxygen can be removed from a layer that is in contact with the semiconductor layer 30, or from a layer that is located near the semiconductor layer 30, resulting in oxygen deficiencies in the semiconductor layer 30. Ｏ Point defects such as H may be formed.

[0063] Furthermore, oxygen contained in the semiconductor layer 30 is absorbed by the insulating layer 50, resulting in oxygen deficiencies near the interface between the semiconductor layer 30 and the insulating layer 50. Ｏ Point defects such as H may be formed. Similarly, oxygen contained in the semiconductor layer 30 is taken away by the insulating layer 51, causing oxygen vacancies and V to form near the interface between the semiconductor layer 30 and the insulating layer 51. ＯPoint defects such as H may be formed.

[0064] Furthermore, since the vicinity of the interface between the semiconductor layer 30 and the insulating layer 50 (or insulating layer 51) includes the surface of the semiconductor layer 30 on the insulating layer 50 side (or insulating layer 51 side), these point defects can also be considered surface defects.

[0065] Since carriers tend to flow near the surface of the semiconductor layer 30 on the insulating layer 50 side, there is a concern that carrier conduction may be suppressed due to scattering caused by surface defects (also called surface scattering). Furthermore, especially when a conductive layer 25 is provided in a transistor, the surface of the semiconductor layer 30 on the insulating layer 51 side may also be affected by scattering due to surface defects. Ｏ H acts as a donor, and electrons, which are carriers, can be generated. Therefore, transistors using metal oxides containing oxygen vacancies and a large amount of hydrogen as the semiconductor layer 30 tend to exhibit normally-on characteristics.

[0066] It is preferable that an appropriate amount of oxygen is supplied to the semiconductor layer 30. If an excess of oxygen is supplied, there is a concern that oxygen will be in surplus in and near the semiconductor layer 30, causing a positive shift in the threshold voltage due to the excess oxygen.

[0067] Therefore, it is preferable that at least one of the insulating layer 50 and the insulating layer 51 has an insulator that has barrier properties against oxygen, and it is more preferable that both the insulating layer 50 and the insulating layer 51 have an insulator that has barrier properties against oxygen. With this configuration, the removal of oxygen from the semiconductor layer 30 can be suppressed. This prevents oxygen deficiencies from forming in the semiconductor layer 30. Ｏ The formation of point defects such as H can be suppressed. Therefore, carrier scattering near the surface of the semiconductor layer 30 is reduced, and a transistor with a large on-current can be provided. Also, oxygen vacancies, V Ｏ By suppressing point defects such as H, the carrier concentration in the semiconductor layer 30 can be reduced. In particular, when indium oxide is used as the semiconductor layer 30, the effects of grain boundary scattering can be suppressed. This lowers the carrier concentration, which increases mobility and allows for the provision of transistors with high on-current.

[0068] In insulating layers 50 and 51, it is preferable that the insulator having barrier properties against oxygen is located at the interface with the semiconductor layer 30. For example, it is preferable that the layer containing the insulator having barrier properties against oxygen is in contact with the semiconductor layer 30. As an example of an insulator containing an element with a strong bonding force with oxygen, an oxide will be explained. When the bonding force between the elements constituting the oxide and the oxygen that bonds with those elements is strong, the oxide is highly stable and oxygen is less likely to desorb. Therefore, the oxide can be an oxide with few oxygen vacancies. When the semiconductor layer 30 and the oxide are in contact, the oxide is highly stable and has few oxygen vacancies, so a defect-free interface may be formed between it and the semiconductor layer 30. This can improve the reliability of the semiconductor device. Also, because the oxide has few oxygen vacancies, for example, oxygen supplied from an insulator that has an oxygen supply function is not consumed by the oxide. Therefore, the amount of oxygen supplied to the semiconductor layer 30 can be sufficiently supplied to the semiconductor layer 30 without being consumed by the oxide. Therefore, oxygen vacancies in the semiconductor layer 30 can be reduced.

[0069] In a semiconductor device according to one aspect of the present invention, the insulating layer 50 preferably has an insulator containing an element that has barrier properties against oxygen and a strong bonding force with oxygen. Similarly, the insulating layer 51 preferably has an insulator containing an element that has barrier properties against oxygen and a strong bonding force with oxygen.

[0070] Here, the insulating layer 50 and the insulating layer 51 can each have a laminated structure. By laminating layers having multiple functions, the functions of the insulating layer 50 and the insulating layer 51 can be enhanced, for example, the characteristics and reliability of a transistor according to one aspect of the present invention can be improved. When the insulating layer 50 and the insulating layer 51 have a laminated structure, it is preferable that the layer located at the interface with the semiconductor layer 30 is a layer containing an insulator that has barrier properties against oxygen.

[0071] Furthermore, at least one of the insulating layer 50 and insulating layer 51 may have an insulating layer that has the function of supplying oxygen. This allows oxygen to be supplied from the insulating layer 50 and insulating layer 51 to the semiconductor layer 30. The insulating layer that has the function of supplying oxygen is, for example, an insulating layer that has a region containing oxygen that is desorbed by heating (hereinafter sometimes referred to as excess oxygen). In the manufacturing process of the semiconductor device, when heating is performed, oxygen can be supplied from the insulating layer.

[0072] Furthermore, at least one of the insulating layer 50 and the insulating layer 51 can have an insulating layer with high barrier properties against hydrogen. This makes it possible to suppress, for example, the diffusion of hydrogen from the periphery of the semiconductor layer 30 to the semiconductor layer 30.

[0073] Furthermore, at least one of the insulating layer 50 and the insulating layer 51 may have an insulating layer that has the function of capturing and fixing hydrogen. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 30, particularly in the channel formation region. This makes it possible to make the channel formation region i-type or substantially i-type. Also, by capturing and fixing hydrogen, the semiconductor layer 30 can have a V Ｏ In some cases, it is possible to suppress the formation of H.

[0074] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 50. By using a high-k material as the insulating layer 50, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In addition, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating layer.

[0075] Furthermore, when the transistor has a conductive layer 25 and the insulating layer 51 is used as a second gate insulating layer, it is preferable to use a high dielectric constant material for the insulating layer 51.

[0076] In the configuration shown in Figure 1B, the insulating layer 50 has an insulating layer 50_1 and an insulating layer 50_2 on top of the insulating layer 50_1.

[0077] The insulating layer 50_1 preferably has an insulator that has barrier properties against oxygen. Furthermore, it is preferable that the insulating layer 50_1 has an insulator that contains an element with a strong bonding force with oxygen. More preferably, the insulating layer 50_1 has an insulator that has barrier properties against oxygen and contains an element with a strong bonding force with oxygen.

[0078] Furthermore, it is preferable that the insulating layer 50_1 is in contact with the semiconductor layer 30.

[0079] The insulating layer 50_2 can be a single layer or a configuration in which multiple layers are stacked, and a configuration in which multiple layers are stacked is more preferable.

[0080] The insulating layer 50_2 preferably has one or more selected from an insulating layer having the function of supplying oxygen, an insulating layer with high barrier properties against hydrogen, and an insulating layer having the function of capturing and fixing hydrogen.

[0081] For example, multiple layers with different functions can be laminated together as the insulating layer 50_2. Furthermore, the same layer can be used repeatedly among the multiple layers.

[0082] Figure 1E shows an example in which the insulating layer 50_2 has a laminated structure consisting of an insulating layer 50_2b and an insulating layer 50_2c on top of the insulating layer 50_2b.

[0083] As an example, an insulating layer having the function of capturing and fixing hydrogen is used for insulating layer 50_2b, and an insulating layer with high barrier properties against hydrogen is used for insulating layer 50_2c.

[0084] Figure 1F shows an example in which the insulating layer 50_2 has a laminated structure consisting of insulating layer 50_2a and insulating layer 50_2c on insulating layer 50_2a, and Figure 1G shows an example in which the insulating layer 50_2 has a laminated structure consisting of insulating layer 50_2a, insulating layer 50_2b on insulating layer 50_2a and insulating layer 50_2c on insulating layer 50_2b.

[0085] As an example, in Figures 1E to 1G, an insulating layer having the function of supplying oxygen is used in insulating layer 50_2a, an insulating layer having the function of capturing and fixing hydrogen is used in insulating layer 50_2b, and an insulating layer with high barrier properties against hydrogen is used in insulating layer 50_2c. In addition, in the configuration shown in Figure 1E, insulating layer 50_2a may be provided between insulating layer 50_2b and insulating layer 50_2c.

[0086] If a layer with high hydrogen barrier properties is placed closer to the semiconductor layer 30 than the layer that captures and fixes hydrogen, hydrogen in the semiconductor layer 30 may not be able to pass through the layer with high hydrogen barrier properties and reach the layer that captures and fixes hydrogen. Therefore, it is preferable to place the layer with high hydrogen barrier properties on the side farther from the semiconductor layer 30. It is preferable to use a layer with high hydrogen barrier properties as the insulating layer 50_2c and a layer that captures and fixes hydrogen as the insulating layer 50_2b, as this can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 30.

[0087] Furthermore, the insulating layer 50_2 may have a laminated structure of four or more layers.

[0088] In the configuration shown in Figure 1C, the insulating layer 51 has an insulating layer 51_2 and an insulating layer 51_1 on top of the insulating layer 51_2.

[0089] The insulating layer 51_1 preferably has an insulator that has barrier properties against oxygen. Furthermore, it is preferable that the insulating layer 51_1 has an insulator that contains an element with a strong bonding force with oxygen. More preferably, the insulating layer 51_1 has an insulator that has barrier properties against oxygen and contains an element with a strong bonding force with oxygen.

[0090] Furthermore, it is preferable that the insulating layer 51_1 is in contact with the semiconductor layer 30.

[0091] The insulating layer 51_2 can be a single layer or a configuration in which multiple layers are stacked, and a configuration in which multiple layers are stacked is more preferable.

[0092] The insulating layer 51_2 preferably has one or more selected from an insulating layer having the function of supplying oxygen, an insulating layer with high barrier properties against hydrogen, and an insulating layer having the function of capturing and fixing hydrogen.

[0093] For example, multiple layers with different functions can be laminated together as the insulating layer 51_2. Furthermore, the same layer can be used repeatedly among the multiple layers.

[0094] Figure 1H shows an example in which the insulating layer 51_2 has a laminated structure consisting of insulating layer 51_2b and insulating layer 51_2c beneath insulating layer 51_2b. Figure 1I also shows an example in which the insulating layer 51_2 has a laminated structure consisting of insulating layer 51_2a and insulating layer 51_2c beneath insulating layer 51_2a. Figure 1J also shows an example in which the insulating layer 51_2 has a laminated structure consisting of insulating layer 51_2a, insulating layer 51_2b beneath insulating layer 51_2a, and insulating layer 51_2c beneath insulating layer 51_2b.

[0095] As an example, in Figures 1H to 1J, an insulating layer having the function of supplying oxygen is used in insulating layer 51_2a, an insulating layer having the function of capturing and fixing hydrogen is used in insulating layer 51_2b, and an insulating layer with high barrier properties against hydrogen is used in insulating layer 51_2c. In addition, in the configuration shown in Figure 1H, insulating layer 51_2a may be provided between insulating layer 51_2b and insulating layer 51_2c.

[0096] Furthermore, the insulating layer 51_2 may have a laminated structure of four or more layers.

[0097] The configuration shown in Figure 1B and the configuration shown in Figure 1C can also be combined. In the configuration shown in Figure 1D, the insulating layer 50 has insulating layer 50_1 and insulating layer 50_2 on insulating layer 50_1, and the insulating layer 51 has insulating layer 51_2 and insulating layer 51_1 on insulating layer 51_2.

[0098] Furthermore, Figures 2B, 2C, and 2D show that, in addition to the configurations shown in Figures 1B, 1C, and 1D, the semiconductor device has a conductive layer 25 between the substrate 20 and the insulating layer 51. The insulating layer 51 is sandwiched between the conductive layer 25 and the semiconductor layer 30.

[0099] For the insulating layer 50_1 and insulating layer 51_1, gallium oxide or aluminum oxide can be used as an insulator having barrier properties against oxygen. In one embodiment of the present invention, it is particularly preferable to use gallium oxide. Compared to aluminum, the ionic radius of gallium is close to that of indium. Therefore, when indium oxide is used as the semiconductor layer 30, using gallium oxide as the insulating layer 50_1 makes it possible to bring the surface density of metal atoms in the semiconductor layer 30 closer to the surface density of metal atoms in the insulating layer 50_1. As a result, the frequency of bonding between indium atoms in the semiconductor layer 30 and gallium atoms in the insulating layer 50_1 via oxygen atoms increases, and the occurrence of oxygen vacancies or oxygen with dangling bonds at the interface between the semiconductor layer 30 and the insulating layer 50_1 can be suppressed.

[0100] Furthermore, gallium and aluminum have a stronger bonding force with oxygen than indium. In other words, gallium oxide and aluminum oxide can be considered insulators that have barrier properties against oxygen and contain elements that have a strong bonding force with oxygen.

[0101] Furthermore, gallium oxide and aluminum oxide are insulators with low barrier properties against hydrogen. Therefore, for example, in the configuration shown in Figure 1E, even if gallium oxide or aluminum oxide is used for the insulating layer 50_1 and an insulating layer having the function of capturing and fixing hydrogen is used for the insulating layer 50_2b, hydrogen in the semiconductor layer 30 can permeate through the insulating layer 50_1 and be captured and fixed to the insulating layer 50_2b.

[0102] Furthermore, the semiconductor layer 30 can be formed on the insulating layer 51 using various thin film formation methods (e.g., ALD method, sputtering method, etc.). In forming the semiconductor layer 30, it is preferable that the surface of the insulating layer 51 to be formed is flat. Surface irregularities of the insulating layer 51 can be a factor in the generation of crystal nuclei. Therefore, if the surface irregularities are large, for example, the size of the crystal grains may become smaller. By making the surface flat, the grain boundaries of the semiconductor layer 30 can be reduced and the crystallinity of the semiconductor layer 30 can be improved. In addition, grain boundary scattering is reduced, and a transistor with a large on-current can be provided.

[0103] To flatten the surface of the insulating layer 51, the surface of the insulating layer 51 can be flattened by polishing or other methods. Alternatively, the surface of the insulating layer 51 can be made flat by flattening the surface to which the insulating layer 51 is formed, for example, the conductive layer 25 and the insulating layer 52, by polishing or other methods. For polishing, for example, chemical mechanical polishing (CMP) can be used.

[0104] In view of the above description, in a semiconductor device according to one aspect of the present invention, it is particularly preferable to use gallium oxide as the insulating layer 50_1 and the insulating layer 51_1.

[0105] As an example, it is preferable to use materials with lower electron affinity than the materials used in the channel formation region of the semiconductor layer 30 for insulating layer 50_1 and insulating layer 51_1. This suppresses the effects of scattering at the interface. From this viewpoint as well, gallium oxide can be suitably used as insulating layer 50_1 and insulating layer 51_1.

[0106] This section describes insulating layers that readily form regions containing excess oxygen. Silicon oxide or silicon oxynitride can be suitably used as insulating layers that readily form regions containing excess oxygen. Furthermore, because silicon oxide or silicon oxynitride is structurally stable with respect to heat, it can be suitably used as the material for insulating layers 50 and 51.

[0107] This section describes insulators that have the function of capturing and fixing hydrogen. Examples of insulators that have the function of capturing and fixing hydrogen include metal oxides having an amorphous structure. For example, it is preferable to use metal oxides such as magnesium oxide, aluminum oxide, hafnium oxide, aluminum, and hafnium-containing oxides (hafnium aluminate) as insulators that have the function of capturing and fixing hydrogen. In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing and fixing hydrogen. In other words, amorphous metal oxides can be said to have a high ability to capture and fix hydrogen.

[0108] This section describes insulators that have barrier properties against hydrogen. Examples of insulators that have barrier properties against hydrogen include nitrides such as silicon nitride, and oxides such as tantalum oxide.

[0109] Furthermore, in addition to its function of capturing and fixing hydrogen, hafnium oxide also has the function of capturing and fixing oxygen. Because insulating layers 50_2 and 51_2 contain hafnium oxide, excess oxygen contained in the semiconductor layer 30 can be captured and fixed.

[0110] In particular, by placing the hafnium oxide layer near the semiconductor layer 30, excess oxygen at the interface between the semiconductor layer 30 and the insulating layers 50 and 51 can be reduced. Therefore, for example, it is preferable to use hafnium oxide in the insulating layer 50_2 and insulating layer 51_2 that is closer to the semiconductor layer 30. By reducing excess oxygen at and near the interface, the positive shift in the threshold voltage caused by excess oxygen can be suppressed, and a highly reliable transistor can be provided.

[0111] The presence of hafnium oxide in the insulating layers 50_2 and 51_2 contributes to both reducing excess oxygen in the semiconductor layer 30 and reducing the hydrogen concentration in the channel formation region.

[0112] Furthermore, since aluminum oxide, gallium oxide, hafnium oxide, silicon nitride, etc. are also high-k materials, they can be suitably used as insulating layers 50 and 51. Therefore, in semiconductor devices, it is possible to simultaneously achieve improved reliability, reduced power consumption, and improved circuit operating speed.

[0113] As an example of the laminated structure shown in Figures 1E to 1J, gallium oxide is used for insulating layer 50_1 and insulating layer 51_1, silicon oxide is used for insulating layer 50_2a and insulating layer 51_2a, hafnium oxide is used for insulating layer 50_2b and insulating layer 51_2b, and silicon nitride is used for insulating layer 50_2c and insulating layer 51_2c. Silicon oxide has lower barrier properties against hydrogen compared with silicon nitride. Hydrogen in the semiconductor layer 30 can permeate through the silicon oxide and be captured and fixed to the hafnium oxide. Furthermore, by placing silicon oxide, which has the function of supplying oxygen, closer to the semiconductor layer 30 than hafnium oxide, which has the function of capturing and fixing oxygen, oxygen released from silicon oxide can be supplied to the semiconductor layer 30 without going through hafnium oxide, thereby reducing oxygen vacancies in the semiconductor layer 30 more efficiently.

[0114] Furthermore, it is preferable that the insulating layer 50_1 and insulating layer 51_1 have, for example, barrier properties against oxygen, and moreover, in the semiconductor device manufacturing process, they preferably have a function that allows oxygen to pass through to a moderate extent. Specifically, for example, it is preferable that the oxygen supplied from insulating layer 50_2a and insulating layer 51_2a by heat treatment permeates through insulating layer 50_1 and insulating layer 51_1 and is supplied to the semiconductor layer 30.

[0115] Therefore, for example, it is preferable that at least one of the insulating layer 50_1 and insulating layer 50_2 is thin enough to allow a moderate amount of oxygen to pass through at the temperature at which the heat treatment is performed.

[0116] Furthermore, as shown in the example in Figure 4B, if the insulating layer 50 has an insulating layer 50_2a that has the function of supplying oxygen, and the insulating layer 51 does not have an insulating layer that has the function of supplying oxygen (for example, insulating layer 51_2a), then the thickness of the insulating layer 51_1 can be made thicker than that of the insulating layer 50_1.

[0117] The insulating layer 50 and the insulating layer 51 can each function as gate insulating layers. By setting the thickness of the insulating layer 50 and the insulating layer 51 to 1 nm to 20 nm, preferably 3 nm to 10 nm, the subthreshold swing value (also called the S value), which is one of the transistor characteristics, can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0118] Furthermore, the film thickness of each layer constituting the insulating layer 50 and the insulating layer 51 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting the insulating layer 50 and the insulating layer 51 only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0119] The thickness of insulating layer 50_1 and insulating layer 51_1 can be determined by applying the thickness values ​​of the respective layers that make up insulating layer 50 and insulating layer 51 as described above.

[0120] The thickness of insulating layer 50_1 and insulating layer 51_1 may be different. For example, when applying the configuration of insulating layer 50_1 and insulating layer 50_2 to a transistor described in the embodiment described later, the thickness can be set to a suitable thickness that matches the structure of the transistor.

[0121] As an example, in the transistor shown in Embodiment 2 described later, the configuration of insulating layer 50 can be applied as the gate insulating layer on the first gate side (front gate, top gate), and the configuration of insulating layer 51 can be applied as the gate insulating layer on the second gate side (back gate, bottom gate).

[0122] In the transistors shown in Figures 6A to 13B, the first gate and gate insulating layer are provided so as to be embedded in the opening of the insulating layer 280, and the gate insulating layer is provided so as to cover the side wall of the opening. As transistors become smaller, the diameter of the opening becomes smaller, so it is sometimes preferable that the insulating layer 50 applicable as the gate insulating layer on the first gate side is thinner than the insulating layer 51.

[0123] Therefore, it is sometimes preferable that the insulating layer 50_1 is thinner than the insulating layer 51_1.

[0124] Specifically, it is preferable that the thickness of insulating layer 51_1 is 5 nm or more, and the thickness of insulating layer 50_1 is less than 5 nm. Furthermore, it is more preferable that the thickness of insulating layer 51_1 is 8 nm or more, and the thickness of insulating layer 50_1 is 3 nm or less.

[0125] As an example, gallium oxide is used as the insulating layer 51_1 and insulating layer 50_1, with the thickness of insulating layer 51_1 being 10 nm and the thickness of insulating layer 50_1 being 1 nm.

[0126] The insulating layer 50 and the insulating layer 51 can each function as gate insulating layers of a transistor. If the materials used as insulating layers 50 and 51 are ferroelectric materials, the transistor can function as, for example, an FeFET (Ferroelectric Field Effect Transistor).

[0127] Examples of materials that may possess ferroelectric properties include oxides containing one or both hafnium and zirconium. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Alternatively, as a material that may possess ferroelectric properties, a material may be used in which element J1 (where element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, scandium, yttrium, lanthanum, strontium, gadolinium, etc.) is added to a metal oxide containing one of hafnium and zirconium.

[0128] Incidentally, the crystal structure (properties) of the materials listed above can change not only depending on the film deposition conditions but also on various processes. Therefore, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0129] In this specification, a layered structure of a material capable of ferroelectricity may be referred to as a ferroelectric layer. Furthermore, a device having such a ferroelectric layer may be referred to as a ferroelectric device in this specification.

[0130] The ferroelectric layer is preferably composed of crystals having an orthorhombic crystal structure, as this exhibits ferroelectric properties. The crystal structure of the crystals included in the ferroelectric layer may be one or more selected from tetragonal, orthorhombic, monoclinic, and hexagonal systems. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure comprising both an amorphous and a crystalline structure.

[0131] Furthermore, metal oxides containing one or both of hafnium and zirconium are also insulators that have the function of capturing or fixing hydrogen. Therefore, the transistor can function as an FeFET, and the hydrogen contained in the oxide semiconductor layer can be captured and fixed to the insulating layer that functions as the gate insulating layer, thereby reducing the hydrogen concentration in the channel formation region and making the channel formation region i-type or substantially i-type. When the transistor functions as an FeFET, the insulating layer that functions as the gate insulating layer preferably contains hafnium, zirconium, and oxygen. Hafnium-zirconium oxide is preferred because it readily exhibits ferroelectric properties.

[0132] In one aspect of the present invention, the semiconductor layer 30 can be arranged in a stacked structure of two or more layers.

[0133] Figure 3A shows a configuration in which the semiconductor layer 30 has a semiconductor layer 30_1, a semiconductor layer 30_2 on semiconductor layer 30_1, and a semiconductor layer 30_3 on semiconductor layer 30_2. Figures 3B, 3D, and 3F show examples of applying the configuration shown in Figure 3A to Figures 1B to 1D, respectively, and Figures 3C, 3E, and 3G show examples of applying the configuration shown in Figure 3A to Figures 2B to 2D, respectively.

[0134] Semiconductor layer 30_1 is in contact with insulating layer 51, and semiconductor layer 30_3 is in contact with insulating layer 50. It is preferable to use indium oxide containing a first element that has a stronger bonding force with oxygen than indium for semiconductor layer 30_3 that is in contact with insulating layer 50, and to use indium oxide for semiconductor layer 30_2 that is not in contact with insulating layer 50. With this configuration, oxygen vacancies and V are formed near the interface between semiconductor layer 30_3 and insulating layer 50. Ｏ The formation of H can be suppressed. Therefore, scattering near the surface of the semiconductor layer 30 on the insulating layer 50 side is reduced, and a transistor with a large on-current can be provided.

[0135] For example, one or more elements selected from gallium, aluminum, yttrium, scandium, titanium, tungsten, molybdenum, tin, zirconium, hafnium, and tantalum can be used as the first element of the semiconductor layer 30_3. The first element is preferably one or more elements selected from gallium, aluminum, scandium, and yttrium, more preferably gallium or aluminum, and even more preferably gallium.

[0136] Gallium is suitable because it has a strong bonding affinity with oxygen, and the bond length with oxygen is close to that of indium and oxygen.

[0137] Furthermore, scandium and yttrium are preferable because their oxides can adopt the same bixbite structure as indium oxide, making it easier to maintain their crystalline structure even when increasing their content.

[0138] Gallium, aluminum, yttrium, and scandium primarily exist as trivalent cations, similar to indium atoms. Therefore, by using gallium, aluminum, yttrium, or scandium as the first element, the carrier concentrations in semiconductor layer 30_1 and semiconductor layer 30_3 can be kept low.

[0139] Furthermore, titanium and tungsten have a stronger bonding force with oxygen compared to molybdenum and tin. Therefore, when titanium or tungsten is used as the first element contained in semiconductor layer 30_1 and semiconductor layer 30_3, oxygen vacancies and V are less likely to be present in the semiconductor layer 30 than when molybdenum or tin is used. Ｏ The formation of H can be suppressed. On the other hand, molybdenum and tin have bond lengths with oxygen that are closer to the bond length between indium and oxygen compared to titanium and tungsten. Therefore, when molybdenum or tin is used as the first element, it is easier to maintain the crystal structure of semiconductor layer 30 even if the content of the first element in semiconductor layer 30_1 and semiconductor layer 30_3 is increased compared to when titanium or tungsten is used.

[0140] Preferably, the semiconductor layer 30_1 contains indium, a first element having a stronger bonding force with oxygen than indium, and oxygen. Specific examples of the first element can be found in the description above. The presence of the first element in the semiconductor layer 30_1 prevents oxygen vacancies and V vacancies in the semiconductor layer 30_1 and near the interface between the semiconductor layer 30_1 and the insulating layer 51. Ｏ The formation of H can be suppressed. Therefore, scattering near the surface of the semiconductor layer 30 on the insulating layer 51 side can be suppressed.

[0141] It is preferable that the ratio of the number of atoms of the first element to the sum of the number of atoms of indium and the first element in each of the semiconductor layer 30_1 and semiconductor layer 30_3 is higher than the ratio in semiconductor layer 30_2.

[0142] Oxides containing the first element have a larger band gap than indium oxide. Therefore, the band gap of indium oxide containing the first element may be larger than that of indium oxide. Also, the electron affinity of indium oxide containing the first element may be smaller than that of indium oxide. By making the electron affinity of semiconductor layer 30_1 and semiconductor layer 30_3 smaller than that of semiconductor layer 30_2, the carrier flow path can be moved away from the interface between the insulating layer 50 and the semiconductor layer 30, which may reduce the effects of surface scattering. As a result, it may be possible to increase the on-current or improve reliability. With such a configuration, the transistor can be made into an embedded channel structure.

[0143] The semiconductor layer 30_2 preferably has a crystalline portion or crystalline region. The crystalline structure of indium oxide is a bixbite structure. In other words, the crystalline structure of the crystalline portion of the semiconductor layer 30_2 is a bixbite structure. Note that a layer having a crystalline portion or crystalline region can be rephrased as a layer having crystalline properties.

[0144] While it is particularly preferable to use single-crystal indium oxide as the semiconductor layer 30_2, polycrystalline or microcrystalline indium oxide can also be used. Using single-crystal indium oxide suppresses carrier scattering at grain boundaries, enabling the provision of a transistor with high field-effect mobility. Furthermore, it allows for the provision of a highly reliable transistor.

[0145] When using polycrystalline indium oxide, it is preferable that no grain boundaries are observed in at least the channel-forming region (the region overlapping with the conductive layer 60 via the insulating layer 50). In other words, it is preferable that the region of the semiconductor layer 30_2 that overlaps with the conductive layer 60 via the insulating layer 50 is included in the crystalline portion of the semiconductor layer 30_2. This makes it possible to achieve the same effects as in the case of single crystals, even when using polycrystalline indium oxide.

[0146] The semiconductor layer 30_1 preferably has a crystalline portion or crystalline region. Furthermore, the crystalline structure of the crystalline portion of the semiconductor layer 30_1 is preferably a bixbyte structure. This allows indium oxide to be epitaxially grown on the semiconductor layer 30_1, thereby increasing the crystallinity of the semiconductor layer 30_2.

[0147] Furthermore, by having a crystalline portion or crystalline region in the semiconductor layer 30_2, indium oxide containing the first element can be epitaxially grown on the semiconductor layer 30_2, and the semiconductor layer 30_3 can also have a crystalline portion or crystalline region. In this case, the crystal orientation of the crystalline portion of the semiconductor layer 30_3 and the crystal orientation of the crystalline portion of the semiconductor layer 30_2 coincide.

[0148] Figure 4A shows an example of applying the configurations shown in Figures 1E, 1H, and 3A to Figure 2D.

[0149] Gallium oxide is used for insulating layer 50_1, hafnium oxide for insulating layer 50_2b, and silicon nitride for insulating layer 50_2c. Additionally, gallium oxide is used for insulating layer 51_1, hafnium oxide for insulating layer 51_2b, and silicon nitride for insulating layer 51_2c.

[0150] Figure 4B shows an example of applying the configurations shown in Figures 1G, 1H, and 3A to Figure 2D.

[0151] Gallium oxide is used for insulating layer 50_1, silicon oxide for insulating layer 50_2a, hafnium oxide for insulating layer 50_2b, and silicon nitride for insulating layer 50_2c. Additionally, gallium oxide is used for insulating layer 51_1, hafnium oxide for insulating layer 51_2b, and silicon nitride for insulating layer 51_2c.

[0152] Figure 4C shows an example of applying the configurations shown in Figures 1E, 1J, and 3A to Figure 2D.

[0153] Gallium oxide is used for insulating layer 50_1, hafnium oxide for insulating layer 50_2b, and silicon nitride for insulating layer 50_2c. Additionally, gallium oxide is used for insulating layer 51_1, silicon oxide for insulating layer 51_2a, hafnium oxide for insulating layer 51_2b, and silicon nitride for insulating layer 51_2c.

[0154] Figure 4D shows an example of applying the configurations shown in Figures 1G, 1J, and 3A to Figure 2D.

[0155] Gallium oxide is used for insulating layer 50_1, silicon oxide for insulating layer 50_2a, hafnium oxide for insulating layer 50_2b, and silicon nitride for insulating layer 50_2c. Additionally, gallium oxide is used for insulating layer 51_1, silicon oxide for insulating layer 51_2a, hafnium oxide for insulating layer 51_2b, and silicon nitride for insulating layer 51_2c.

[0156] The configurations shown in Figures 4A to 4D are examples of semiconductor devices, and the configuration of a semiconductor device is not limited thereto.

[0157] Furthermore, as shown in Figure 5A, the first element in the semiconductor layer 30 may have a concentration gradient as indicated by the density of the hatches.

[0158] Furthermore, as shown in Figure 5B, the semiconductor layer 30 can be configured without semiconductor layer 30_3. Also, as shown in Figure 5C, the semiconductor layer 30 can be configured without semiconductor layer 30_1.

[0159] Figures 5D to 5F show examples of applying the configuration of the semiconductor layer 30 shown in Figures 5A to 5C to Figure 2D, respectively.

[0160] In this specification, indium oxide having at least a crystalline portion or crystalline region in a film may be referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO). Examples of Crystal IO or Crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0161] Indium oxide films, compared to, for example, IGZO (In-Ga-Zn oxide) films, are films in which hydrogen and / or oxygen can move more easily. Therefore, indium oxide films can be said to be films in which hydrogen and / or oxygen can be supplied and expelled more easily than, for example, IGZO films. As a result, excess oxygen or hydrogen that can become carriers or fixed charges is less likely to accumulate in the semiconductor layer 30, making it possible to create transistors with good electrical characteristics and reliability.

[0162] In transistors using silicon for the semiconductor layer (also called Si transistors), it is said that reducing the thickness of the semiconductor layer (for example, reducing the thickness to 5 nm or less) changes the wave function in the direction of the thickness, and thus reduces the field-effect mobility. On the other hand, in metal oxides such as indium oxide, the s-orbitals of heavy metals (e.g., indium) mainly contribute to carrier conduction, and because the anisotropy of carrier conduction is small, it is less susceptible to surface scattering due to surface irregularities on the film surface. Therefore, in OS transistors, even when the thickness of the semiconductor layer is reduced, the field-effect mobility does not decrease significantly. Consequently, metal oxides such as indium oxide can be suitably used in transistors with a thin semiconductor layer 30.

[0163] Furthermore, in Si transistors, shortening the channel length (for example, reducing it to 10 nm or less) increases the leakage current due to the tunneling current between the source and drain. The tunneling current between the source and drain depends on the height of the potential barrier between the source and drain, and the potential barrier depends on the band gap of the semiconductor material.

[0164] Because metal oxides such as indium oxide have a larger band gap compared to silicon, OS transistors have a higher potential barrier than Si transistors. Therefore, OS transistors can keep the source-drain tunnel current lower than Si transistors. As a result, they can exhibit good electrical characteristics even when the channel length is shortened. In OS transistors, the channel length can be 1 nm to 15 nm, preferably 3 nm to 15 nm, and more preferably 3 nm to 10 nm.

[0165] [Examples of Manufacturing Methods] Below, we will describe examples of materials applicable to semiconductor layers, insulating layers, conductive layers, etc., that constitute semiconductor devices, as well as examples of manufacturing methods.

[0166] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and other methods. CVD methods include plasma chemical vapor deposition (PECVD or plasma CVD) and thermal CVD. One type of thermal CVD is metal-organic chemical vapor deposition (MOCVD).

[0167] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, or knife coating.

[0168] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by film deposition methods using shielding masks such as metal masks.

[0169] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0170] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it enables extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0171] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0172] As the substrate 20, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, or memory elements.

[0173] The semiconductor film that forms the semiconductor layer 30 can be formed using various methods such as ALD method and sputtering method.

[0174] Furthermore, if the semiconductor layer 30 is a stacked structure, different methods can be used for each layer.

[0175] The first to third semiconductor films, which become semiconductor layers 30_1 to 30_3 as described above, can be formed, for example, using the ALD method. By using the ALD method, which deposits atoms individually, rather than the sputtering method, which involves impacting particles onto the surface to be formed, the formation of crystal nuclei in the film can be suppressed. This prevents unintended polycrystallization of the semiconductor layer 30.

[0176] For the deposition of the first to third semiconductor films, for example, an ALD method using a precursor and an oxidizing agent can be used. When forming a film containing indium as the semiconductor film, an indium-containing precursor can be used. When forming a film containing indium and a first element as the semiconductor film, an indium-containing precursor and a first element-containing precursor can be used. When using an indium-containing precursor, it is preferable to use a thermal ALD method. Alternatively, a plasma-enhanced ALD (PEALD) method can be used.

[0177] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0178] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. Examples of indium-containing inorganic precursors include halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0179] When titanium is used as the first element, for example, titanium tetrachloride, tetrakis(dimethylamide) titanium, or tetraisopropyl titanate can be used as a precursor containing the first element.

[0180] When tungsten is used as the first element, (ethylcyclopentadienyl)dicarbonylnitrosyltungsten, (methylcyclopentadienyl)dicarbonylnitrosyltungsten, bis(tert-butylimide)bis(dimethylamide)tungsten, bis(tert-butylimide)bis(tert-butylamide)tungsten, or hexacarbonyltungsten can be used as a precursor containing the first element.

[0181] When molybdenum is used as the first element, (ethylcyclopentadienyl)dicarbonylnitrosylmolybdenum, (methylcyclopentadienyl)dicarbonylnitrosylmolybdenum, bis(tert-butylimide)bis(dimethylamide)molybdenum, hexacarbonylmolybdenum, or molybdenum dichloride dioxide can be used as precursors containing the first element.

[0182] When tin is used as the first element, for example, tin tetrachloride, tetraethyltin, tetramethyltin, or tetrakis(dimethylamide)tin can be used as a precursor containing the first element.

[0183] When gallium is used as the first element, for example, triethylgallium, trimethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, or diethylchlorogallium can be used as precursors containing the first element.

[0184] When aluminum is used as the first element, for example, aluminum trichloride, trimethylaluminum, triethylaluminum, triisobutylaluminum, dimethylaluminum hydride, tris(dimethylamino)aluminum, or tris(diethylamino)aluminum can be used as a precursor containing the first element.

[0185] When yttrium is used as the first element, a precursor containing the first element can be, for example, tris(methylcyclopentadienyl)yttrium(III)(Y(MeCp) ３ ), Tris(isopropylcyclopentadienyl)yttrium(III)(Y(iPrCp) ３ ), Tris[N,N-bis(trimethylsilyl)amide]yttrium(III)(Y(tmsa) ３ ) and the like can be used.

[0186] When scandium is used as the first element, precursors containing the first element can include, for example, tris(cyclopentadienyl) scandium, bis(ethylcyclopentadienyl)(N,N'-bis(dimethylamino)acetamidinate) scandium, bis(ethylcyclopentadienyl)(di-tert-butyl-triazenide) scandium, bis-methylcyclopentadienyl-scandium chloride, triscyclopentadienyl scandium, and the like.

[0187] In the method for forming the first to third semiconductor films, it is preferable to use a precursor with a low impurity concentration, i.e., a high purity precursor. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, the impurities in the semiconductor layer 30 can be sufficiently reduced.

[0188] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), Nitrogen dioxide (NO) ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) and others can be used, and two or more of these may be used.

[0189] When forming single crystals or polycrystalline materials with large grain sizes, it is preferable to use an oxidizing agent containing hydrogen to suppress the formation of crystal nuclei in the initial stages of film formation. For example, H ２ O, or H２ O ２ It is preferable to use . After forming a film with few crystal nuclei, crystal growth can be achieved by heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with a large grain size. On the other hand, when reducing the hydrogen and nitrogen concentrations in the film, O is used as the oxidizing agent. ２ or O ３ It is preferable to use O ３ It is preferable to use

[0190] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit films with concentration gradients. In addition, it becomes possible to deposit two or more films with different compositions in succession.

[0191] When introducing the precursor into the reaction chamber, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, for example, the substrate heating temperature can be 100°C to 350°C, preferably 150°C to 300°C.

[0192] Furthermore, the first to third semiconductor films, which become semiconductor layers 30_1 to 30_3 as described above, can be formed, for example, by sputtering. When forming a film containing indium, a sputtering target containing indium can be used. For example, when forming an indium oxide film, an indium oxide sputtering target can be used. Also, when forming an oxide film containing indium and a first element, an oxide sputtering target containing indium and the first element can be used.

[0193] When forming an oxide film containing indium and a first element, for example, a sputtering target of indium oxide containing the first element can be prepared. For example, the amount of the first element added to the sputtering target can be set to be the ratio of the number of atoms of the first element to the sum of the number of atoms of indium and the first element in the oxide film to be formed.

[0194] Furthermore, the first to third semiconductor films can also be formed using a co-sputtering method. For example, indium oxide is prepared as the first sputtering target, and an oxide containing the first element is prepared as the second sputtering target. By simultaneously sputtering the first and second sputtering targets, an oxide film containing indium and the first element can be formed. Alternatively, by sputtering the first sputtering target, an indium oxide film can be formed. By using the co-sputtering method, it is also possible to continuously form two or more films with different compositions.

[0195] Furthermore, when forming the semiconductor layer 30 using the sputtering method, the sputtering gas is hydrogen (H ２ It is preferable that the following are included. When forming the semiconductor layer 30 by sputtering, or when introducing hydrogen in the initial stages of formation of the semiconductor layer 30 by sputtering, a semiconductor layer 30 with low crystallinity can be formed. In addition, the generation of crystal nuclei can be suppressed or the disappearance of crystal nuclei can be promoted during the formation of the semiconductor layer 30. Note that a noble gas (typically argon) or a single gas of oxygen, or a mixed gas of a noble gas and oxygen can also be used as the sputtering gas.

[0196] Furthermore, when forming the semiconductor layer 30 using the sputtering method, the substrate temperature during film formation of the semiconductor layer 30 is preferably between room temperature (25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. It is also preferable because it suppresses the generation of crystal nuclei. Alternatively, the semiconductor layer 30 can be formed at room temperature or without heating the substrate.

[0197] Furthermore, it is also possible to form the first to third semiconductor films using different film deposition methods. For example, the first semiconductor film can be formed using the sputtering method, the second semiconductor film using the ALD method, and the third semiconductor film using the sputtering method. By using the sputtering method, a dense film can be formed. By making the first and third semiconductor films dense films, oxygen vacancies and V can be formed near the interface between the semiconductor layer 30_3 and the insulating layer 50, and near the interface between the semiconductor layer 30_1 and the insulating layer 51. Ｏ This allows for the suppression of H formation and provides a transistor with a large on-current.

[0198] Alternatively, for example, the first semiconductor film can be formed using the ALD method, the second semiconductor film can be formed using the sputtering method, and the third semiconductor film can be formed using the ALD method. By forming the first semiconductor film using the ALD method, the formation of a mixed layer at the interface between the substrate and the semiconductor layer 30 can be suppressed, and the crystallinity of the second semiconductor film formed on the first semiconductor film can be increased.

[0199] It is preferable to perform a heat treatment after forming the semiconductor layer 30. Heat treatment makes it possible to improve the crystallinity of the semiconductor layer 30 even if crystallization was insufficient during film formation.

[0200] The above heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed.

[0201] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb (1 × 10⁻¹⁶). −３ Preferably less than ppm, and 0.1 ppb (1 × 10⁻¹⁰ −４ It is more preferable to have a ppm or less, and 0.05 ppb (5 × 10) −５ A concentration of ppm or less is even more preferable. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the semiconductor layer 30 as much as possible.

[0202] There are no special limitations on the heating device used for the heat treatment; it may be a device that heats the object to be treated by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas. Heat treatment can also be performed by irradiation with laser light. For example, an infrared laser, a visible light laser, or an ultraviolet laser can be used as the laser light.

[0203] Here, the heat treatment performed under reduced pressure is referred to as the first treatment, and the heat treatment performed in an atmosphere containing an oxidizing gas is referred to as the second treatment. The temperature of the first treatment is preferably 200°C to 500°C, more preferably 350°C to 450°C. Typically, it can be 400°C. The temperature of the second treatment is preferably 300°C to 700°C, more preferably 450°C to 650°C. Typically, it can be 450°C. As the second treatment, for example, the flow rate ratio of nitrogen gas to oxygen gas can be set to 4:1, and the treatment can be performed at a temperature of 450°C for 1 hour.

[0204] When forming the semiconductor layer 30 using the ALD method, it is preferable to perform the first and second heat treatments in this order. The first treatment can reduce impurities such as carbon, water, and hydrogen in the semiconductor layer 30, and the second treatment can replenish the oxygen removed in the first treatment. Furthermore, it can reduce impurities such as water and hydrogen in the semiconductor layer 30. This can improve the reliability of the transistor.

[0205] When forming the semiconductor layer 30 using the sputtering method, it is preferable to perform the second treatment as the heat treatment described above. Performing the second treatment can promote crystal growth and enlarge the crystal grains in the semiconductor layer 30. Furthermore, performing the second treatment can reduce the amount of hydrogen contained in the semiconductor layer 30. In particular, by forming the insulating layer 51 using an insulating material that has the function of capturing and fixing hydrogen, the amount of hydrogen contained in the semiconductor layer 30 can be further reduced and crystal growth can be promoted. In addition, by using a sputtering target with a reduced carbon concentration, the first treatment can be omitted.

[0206] The insulating layer 50 and the insulating layer 51 can be formed by methods such as ALD, sputtering, CVD, PLD, MBE, and wet methods.

[0207] The insulating layer 50 and the insulating layer 51 can be formed using, for example, the ALD method with a precursor and an oxidizing agent. When forming an aluminum oxide film as the insulating layer 50, an aluminum-containing precursor can be used. Examples of aluminum-containing precursors include aluminum chloride and trimethylaluminum. The oxidizing agent can be any oxidizing agent that can be used for forming the semiconductor layer 30.

[0208] It is preferable to perform a heat treatment after the formation of the insulating layer 50. The heat treatment performed after the formation of the insulating layer 50 is called the third treatment. The temperature of the third treatment is preferably 150°C to 350°C. Typically, it can be set to 250°C. The third treatment can reduce the amount of oxygen and hydrogen contained in the insulating layer 50 and the layer below it.

[0209] In the fabrication of a semiconductor device according to one aspect of the present invention, heat treatment is preferable. For example, by performing heat treatment at a temperature of 100°C to 700°C, oxygen can be supplied from the insulating layer 50 or insulating layer 51 to the semiconductor layer 30. Furthermore, by performing heat treatment, the insulating layer 50 and insulating layer 51 can getter excess hydrogen, excess oxygen, etc., from the semiconductor layer 30.

[0210] The heat treatment is carried out, for example, in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content can be set to about 20%. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment can be carried out again in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed.

[0211] The gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment is preferably 1 ppb (0.001 ppm) or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from being incorporated into each layer constituting the semiconductor device.

[0212] In addition to or instead of heat treatment, microwave plasma treatment can also be performed.

[0213] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0214] In some cases, the impurity concentration in the semiconductor layer 30 can be reduced by performing microwave plasma treatment in an oxygen-containing atmosphere. Examples of impurities include hydrogen and carbon.

[0215] Microwave plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa being preferred, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa. The treatment temperature is preferably room temperature (25°C) to 750°C, more preferably 300°C to 500°C, and can be 400°C to 450°C.

[0216] When performing microwave plasma treatment, it is preferable to heat the substrate. It is preferable to heat the substrate to a temperature of room temperature (e.g., 25°C) or higher, 100°C or higher, 200°C or higher, 300°C or higher, or 400°C or higher, and 500°C or lower, or 450°C or lower.

[0217] Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. Note that the oxygen flow rate ratio (O) in microwave plasma treatment is important. ２ / ( O ２If the oxygen flow rate ratio (O) is too high, the discharge becomes unstable. Therefore, for example, the oxygen flow rate ratio (O) ２ / ( O ２ The oxygen flow rate ratio (O) in microwave plasma processing is preferably greater than 0% and 50% or less, more preferably greater than 0% and 40% or less, and even more preferably greater than 0% and 30% or less. ２ / ( O ２ The value of +Ar) is preferably greater than 0% and 10% or less, preferably between 0.5% and 5%, more preferably between 0.5% and 3%, and typically can be 1%.

[0218] By performing microwave plasma treatment in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and the oxygen radicals generated by the plasma-generated oxygen gas can act on the oxide semiconductor layer. Through the action of plasma, microwaves, oxygen radicals, etc., hydrogen can be added to oxygen vacancies in the oxide semiconductor layer to form defects (hereinafter referred to as V Ｏ V (sometimes called H) can be separated into oxygen vacancies and hydrogen, and the hydrogen impurity can be removed from the oxide semiconductor layer. In this way, the V contained in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen impurity can be removed from the oxide semiconductor layer. Ｏ H can be reduced. In addition, carbon that was bonded to oxygen or hydrogen can sometimes be removed at this time. In this way, impurities such as carbon or hydrogen can be reduced by microwave plasma treatment. Furthermore, by supplying the above oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0219] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0220] (Embodiment 2) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention, and an example of a method for manufacturing the same. Here, a transistor will be described as an example of a semiconductor device. The semiconductor layer of the transistor described below can be the same semiconductor layer as described in Embodiment 1.

[0221] [Example of semiconductor device configuration] Figures 6A to 6C are a top view and a cross-sectional view of the transistor 200. Figure 6A is a top view of the transistor 200, and Figures 6B and 6C are cross-sectional views corresponding to the cutting lines A1-A2 and A3-A4 in Figure 6A, respectively. Figure 6B corresponds to the cross-section of the transistor 200 in the channel length direction, and Figure 6C corresponds to the cross-section in the channel width direction. Figure 7A is an enlarged view of Figure 6B. Note that some components are omitted in Figure 6A.

[0222] The semiconductor device shown in Figures 6A to 6C comprises a substrate 210, an insulating layer 201 provided on the substrate 210, and a transistor 200 provided on the insulating layer 201. The transistor 200 comprises a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. An insulating layer 275 is provided covering the semiconductor layer 230, and an insulating layer 280 is provided on the insulating layer 275. The insulating layer 280 and the insulating layer 275 are provided with openings (also called grooves) that reach the semiconductor layer 230. The insulating layer 250 is provided inside these openings along the surfaces of the insulating layer 280, the insulating layer 275, the semiconductor layer 230, and the insulating layer 201. The conductive layer 260 is provided on the insulating layer 250 so as to fill these openings. Furthermore, insulating layers 282 and 285 are provided in order, covering insulating layer 280, insulating layer 250, and conductive layer 260.

[0223] Openings reaching the semiconductor layer 230 are formed in insulating layers 285, 282, 280, and 275, and conductive layers 242a and 241a are provided within these openings. Insulating layer 241a is provided adjacent to the side wall of the opening, and conductive layer 242a is provided inside insulating layer 241a. Furthermore, openings reaching the semiconductor layer 230 are formed in insulating layers 285, 282, 280, and 275, and conductive layers 242b and 241b are provided within these openings. Insulating layer 241b is provided adjacent to the side wall of the opening, and conductive layer 242b is provided inside insulating layer 241b. Conductive layers 242a and 242b are provided with conductive layer 260 in between. The upper surfaces of conductive layers 242a and 242b are at the same height as the upper surface of insulating layer 285.

[0224] The semiconductor layer 230 functions as the channel formation region of the transistor 200. The conductive layer 260 functions as the gate electrode of the transistor 200. The insulating layer 250 functions as the gate insulating layer of the transistor 200. The conductive layer 242a functions as either the source electrode or the drain electrode of the transistor 200, and the conductive layer 242b functions as the other. The conductive layers 242a and 242b may also function as vias connecting the transistor 200 to wiring or other components provided on the transistor 200. The channel length of the transistor 200 can be rephrased as the width of the conductive layer 260 in a cross-section that includes the shortest distance line connecting the conductive layers 242a and 242b. The width of the conductive layer 260 in a cross-section that includes the shortest distance line connecting the conductive layers 242a and 242b can also be said to be the length of the region of the semiconductor layer 230 that overlaps with the conductive layer 260 in a cross-sectional view in the channel length direction.

[0225] The substrate 210, insulating layer 201, semiconductor layer 230, insulating layer 250, and conductive layer 260 can be respectively applied to the substrate 20, insulating layer 51, semiconductor layer 30, insulating layer 50, and conductive layer 60 as exemplified in Embodiment 1.

[0226] The semiconductor layer 230 has a region 230a that overlaps with the opening where the conductive layer 242a and the insulating layer 241a are provided, a region 230b that overlaps with the opening where the conductive layer 242b and the insulating layer 241b are provided, and a region 230c that overlaps with the conductive layer 260 via the insulating layer 250. Regions 230a and 230b are separated by region 230c. Region 230a is in contact with the conductive layer 242a, and region 230b is in contact with the conductive layer 242b.

[0227] Regions 230a and 230b preferably contain a second element. Examples of the second element include typical nonmetallic elements other than hydrogen and oxygen, typical metallic elements, and transition elements (transition metals). Specifically, examples include boron, phosphorus, magnesium, aluminum, silicon, etc. Regions 230a and 230b may contain one or more of the above elements as the second element.

[0228] The concentration of the second element in region 230a is higher than the concentration of the second element in region 230c. Similarly, the concentration of the second element in region 230b is higher than the concentration of the second element in region 230c. The concentrations of the second element in region 230a and region 230b are, for example, 1 × 10⁻¹⁰. １９ atoms / cm ３ The above 1 x 10 ２３ atoms / cm ３ The following is preferably 5 × 10 １９ atoms / cm ３ The above 5 x 10 ２２ atoms / cm ３ More specifically, 1 x 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ The following applies. Furthermore, if the second element contains multiple of the above elements, it is preferable that the sum of the concentrations of each element falls within the above range.

[0229] Regions 230a and 230b contain the second element, which removes oxygen from these regions, forming an oxygen vacancy. Furthermore, the oxygen vacancy and hydrogen contribute to V ＯH is formed. Therefore, regions 230a and 230b have reduced resistance, allowing region 230a to function as one of the source and drain regions of transistor 200, and region 230b to function as the other. Consequently, the contact resistance between region 230a and conductive layer 242a, and the contact resistance between region 230b and conductive layer 242b can be reduced, and the on-current of transistor 200 can be increased. Furthermore, by increasing the on-current of transistor 200, transistor 200 can obtain high frequency characteristics. Therefore, a semiconductor device with high operating speed can be realized.

[0230] The second element can be supplied to regions 230a and 230b after forming openings, which will later be provided with conductive layer 242b and insulating layer 241b.

[0231] For supplying the second element, ion doping or ion implantation can be suitably used. These methods allow for highly precise control of the concentration profile in the depth direction by controlling the ion acceleration voltage and dose.

[0232] By using an ion implantation method, in which the source gas is ionized and the ions are separated by mass before irradiation, the supply of elements other than the second element to the semiconductor device can be suppressed compared to the ion doping method. On the other hand, by using an ion doping method, in which the source gas is ionized and the ions are irradiated without mass separation, the productivity of the semiconductor device can be increased compared to the ion implantation method.

[0233] When supplying boron as the second element, the raw material gas is B ２ H ６ Gas, BF ３ Gases can be used. Also, when supplying phosphorus as the second element, PH can be used as the raw material gas. ３ Gases can be used. Furthermore, a mixed gas obtained by diluting these raw material gases with hydrogen or a noble gas may also be used.

[0234] Furthermore, the region between region 230a and region 230c, and the region between region 230b and region 230c of the semiconductor layer 230 may also contain the second element. In these regions, for example, the concentration of the second element is lower than in region 230a and region 230b, and higher than in region 230c. In the semiconductor layer 230, having the second element at such concentrations in the region between region 230a and region 230c, and the region between region 230b and region 230c, can suppress the degradation of the transistor's hot carriers.

[0235] It is preferable that the conductive layers 242a and 242b have a laminated structure. For example, as shown in Figure 7A, the conductive layer 242a may have a conductive layer 242a1 formed along the opening and a conductive layer 242a2 formed inside the conductive layer 242a1. The conductive layer 242b may have a conductive layer 242b1 formed along the opening and a conductive layer 242b2 formed inside the conductive layer 242b1.

[0236] The conductive layers 242a1 and 242b1 can be made of conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, conductive metal oxides (also called oxide conductors), or conductive materials that have the function of suppressing oxygen diffusion. This allows conductive layers 242a and 242b to maintain conductivity even if they absorb oxygen. Each of the conductive layers 242a1 and 242b1 contains, for example, indium, a third element, and oxygen. The third element is preferably one or more selected from tin, zinc, tungsten, titanium, and zirconium. Specifically, the conductive layers 242a1 and 242b1 can be made from metal oxides such as indium tin oxide (In-Sn oxide, also known as ITO), silicon-containing indium tin oxide (also known as ITSO), indium zinc oxide (In-Zn oxide, also known as IZO®), tungsten-containing indium tin oxide (In-Sn-W oxide, also known as ITWO), indium titanium oxide (In-Ti oxide), and indium zirconium oxide (In-Zr oxide).

[0237] If the main components of the source electrode and drain electrode are the same as the main components of the semiconductor layer, the work functions of the source electrode and drain electrode can be made to approximately match the lower edge of the conduction band of the semiconductor layer. This reduces the energy barrier between the source electrode and drain electrode and the semiconductor layer. Therefore, the contact resistance between the source electrode and the semiconductor layer, and the contact resistance between the drain electrode and the semiconductor layer can be reduced. For example, the main components of the source electrode and drain electrode, and the main component of the semiconductor layer, can be indium.

[0238] Conductive layers 242a1 and 242b1 may also be made of conductive materials such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, which have the function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated form. By providing conductive layers 242a1 and 242b1, it is possible to suppress the mixing of impurities such as water and hydrogen into the semiconductor layer 230 through conductive layers 242a2 and 242b2.

[0239] It is preferable to use a metal or alloy with higher conductivity than conductive layers 242a1 and 242b1 for conductive layers 242a2 and 242b2. For example, it is preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum. This allows conductive layers 242a and 242b to function as highly conductive electrodes, vias, or wiring.

[0240] Furthermore, materials containing metallic elements such as gold, platinum, palladium, silver, ruthenium, copper, bismuth, lead, tin, nickel, cobalt, cadmium, and iron are conductive materials that are resistant to oxidation, and therefore these materials can also be used for conductive layers 242a1 and 242b1. In addition, since these materials tend to have low resistivity, they can also be used for conductive layers 242a2 and 242b2.

[0241] For example, ITO can be used as conductive layer 242a1 and conductive layer 242b1, and tungsten or nickel can be used as conductive layer 242a2 and conductive layer 242b2.

[0242] The conductive layers 242a and 242b can also be single-layer structures. In this case, the above-mentioned metal oxides such as ITO or ITSO can be used as the conductive layers 242a and 242b.

[0243] A portion of the cross-sectional view shown in Figure 7A is shown in Figure 7B. Figure 7B includes region 230a and its vicinity. Figure 7B shows a configuration in which the conductive layer 242a is in contact with the upper surface of the semiconductor layer 230. However, the configuration in which the conductive layer 242a and the semiconductor layer 230 are in contact is not limited to this.

[0244] For example, as shown in Figure 7C, the semiconductor layer 230 has a recess that overlaps with the conductive layer 242a, and the conductive layer 242a may be in contact with the side wall and bottom of the recess of the semiconductor layer 230. Also, this opening does not overlap with the conductive layer 260. Furthermore, the conductive layer 242a is in contact with the semiconductor layer 230 at the opening. With the above configuration, the contact area between the conductive layer 242a and region 230a is increased, and the contact resistance between the conductive layer 242a and region 230a can be reduced. On the other hand, with the configuration shown in Figure 7B, it is not necessary to form a recess in the semiconductor layer 230, and semiconductor devices can be manufactured in a way that yields a high percentage of the manufacturing cost. Therefore, semiconductor devices with low manufacturing costs can be realized. In addition, the number of manufacturing steps for semiconductor devices can be reduced, and the productivity of semiconductor devices can be increased.

[0245] Furthermore, as shown in Figure 7D, for example, the upper end of the conductive layer 242a1 may be located below the upper surface of the conductive layer 242a2. For example, when the conductive layer 242a1 is formed using the sputtering method, the conductive layer 242a1 may not be formed along the side surface of the insulating layer 241a, and the conductive layer 242a1 may be formed only on the upper surface of region 230a and its vicinity.

[0246] Furthermore, the configuration of the conductive layer 242a shown in Figures 7B to 7D can also be applied to the conductive layer 242b. Therefore, the above-described explanation of the conductive layer 242a can also be applied to the conductive layer 242b.

[0247] The insulating layer 275 preferably has barrier properties against hydrogen. The insulating layer 275 is provided between the insulating layer 280 and the semiconductor layer 230. This configuration suppresses the diffusion of hydrogen contained in the insulating layer 280 into the semiconductor layer 230. Therefore, it is possible to suppress the increase in hydrogen concentration in the semiconductor layer 230, particularly in the channel formation region, due to the hydrogen contained in the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 275.

[0248] Furthermore, in this embodiment, it is preferable to configure the semiconductor device to suppress the mixing of hydrogen into the transistor 200, etc., in addition to the above configuration. For example, it is preferable to provide an insulator having the function of suppressing hydrogen diffusion so as to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, an insulating layer 282 and an insulating layer 283. Note that the insulating layer 283 can be provided between the insulating layer 282 and the insulating layer 285, as shown in Figure 7A. Alternatively, a similar film may be provided under the transistor 200.

[0249] It is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen from above the transistor 200 to the transistor 200. Therefore, it is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen to the transistor 200 from above. ２ O, NO, NO ２ It is preferable to have an insulating material that has the function of suppressing the diffusion of impurities such as copper atoms (i.e., the above-mentioned impurities do not easily permeate). Alternatively, it is preferable to have an insulating material that has the function of suppressing the diffusion of oxygen (i.e., at least one such as oxygen atoms and oxygen molecules) (i.e., the above-mentioned oxygen does not easily permeate).

[0250] The insulating layer 282 and insulating layer 283 preferably have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as the insulating layer 283. Also, for example, it is preferable that the insulating layer 282 has aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulating layer 283 to the transistor 200, etc. Also, it is possible to suppress the diffusion of oxygen contained in the insulating layer 280, etc., upward from the transistor 200, etc. via the insulating layer 282, etc. Furthermore, by providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200, etc.

[0251] As insulating layers 241a and 241b, barrier insulators that can be used for insulating layer 275 and the like can be used. For example, silicon nitride can be used as insulating layer 241a and insulating layer 241b. Insulating layer 241a is provided in contact with the side walls of openings formed in insulating layers 285, 283, 282, and 275, and insulating layer 241b is provided in contact with the side walls of other openings formed in insulating layers 285, 282, and 275. This prevents impurities such as water and hydrogen contained in insulating layer 280 from mixing into semiconductor layer 230 through conductive layer 242a and conductive layer 242b. It also prevents oxygen contained in insulating layer 280 from being absorbed by conductive layer 242a and conductive layer 242b.

[0252] The conductive layer 260 is preferably provided extending in the channel width direction, as shown in Figures 6A and 6C. With this configuration, when multiple transistors are provided, the conductive layer 260 functions as wiring.

[0253] The conductive layer 260 may have a laminated structure. Figure 7A shows an example in which the conductive layer 260 has a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b on the conductive layer 260a. In this case, it is preferable to use a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of suppressing oxygen diffusion, for the conductive layer 260a. It is also preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum for the conductive layer 260b.

[0254] The insulating layer 280 preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulating layer 280 preferably has one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0255] Furthermore, as shown in Figure 8A, it may have a conductive layer 205 that functions as a transistor back gate. The transistor 200 shown in Figure 8A has a conductive layer 205 and an insulating layer 202.

[0256] The conductive layer 205 is provided so as to be embedded in the insulating layer 202. The insulating layer 201 is provided so as to cover the insulating layer 202 and the conductive layer 205.

[0257] The conductive layer 205 functions as the second gate (back gate) of the transistor 200. The conductive layer 205 is located in a region that overlaps with the conductive layer 260 via the semiconductor layer 230. The conductive layer 260 is sometimes referred to as the first gate (front gate). Furthermore, with respect to the substrate, the semiconductor layer 230 can be described as being located above the substrate. In this case, the conductive layer 205 is located below the semiconductor layer 230, and the conductive layer 260 is located above the semiconductor layer 230, so the conductive layer 205 is sometimes referred to as the bottom gate and the conductive layer 260 as the top gate.

[0258] The conductive layer 205 can be made of a material that can be used for the conductive layer 260. Furthermore, the conductive layer 205 may have a laminated structure.

[0259] Furthermore, the conductive layer 205 can also be made of an oxide conductor. Compared to materials composed of metal elements (also called metallic materials), this oxide conductor is more likely to maintain its conductivity even when absorbing oxygen. For example, even when an oxide insulating film is used for the insulating layer 202, the conductive layer 205 can maintain its conductivity, making it suitable. Examples of such oxide conductors include metal oxides such as ITO, ITSO, In-Zn oxide, and In-Ti oxide.

[0260] When the conductive layer 205 functions as the second gate of the transistor 200, the insulating layer 201 functions as the second gate insulating layer.

[0261] <Insulating Layer 250> As described in Embodiment 1, the insulating layer 250 can be a laminated structure of two or more layers. The insulating layer 50 shown in the previous embodiment can be applied to the insulating layer 250. For example, Figures 9A and 8B show an example in which the insulating layer 250 has a laminated structure of insulating layer 250_1 in contact with the semiconductor layer 230, insulating layer 250_2b on insulating layer 250_1, and insulating layer 250_2c on insulating layer 250_2b. Insulating layers 50_1, 50_2b, and 50_2c can be applied to insulating layer 250_1, insulating layer 250_2b, and insulating layer 250_2c, respectively. Figures 9B, 9C, and 8C show an example in which insulating layer 250_2a is provided between insulating layer 250_1 and insulating layer 250_2b. Insulating layer 50_2a can be applied to insulating layer 250_2a.

[0262] The above film configuration can also be understood as a layered structure consisting of a film that can supply oxygen to a film adjacent to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film) on its outer periphery, and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film) on its outer periphery. With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. In addition, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. Furthermore, the presence of the silicon nitride film results in a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, with the above film configuration, the indium oxide film becomes more i-type. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0263] Furthermore, the insulating layer 250 may have an insulating film that has barrier properties against oxygen. Examples of insulators that have barrier properties against oxygen include aluminum oxide and gallium oxide. By having an insulating layer 250 that has barrier properties against oxygen, oxygen contained in the channel formation region of the semiconductor layer 230 and the conductive layer 260 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region. In addition, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260.

[0264] <Insulating Layer 201> The insulating layer 201 can have a laminated structure. For example, Figures 8B, 9A, and 9B show an example in which the insulating layer 201 has a laminated structure consisting of an insulating layer 201_1 in contact with the semiconductor layer 230, an insulating layer 201_2b below the insulating layer 201_1, and an insulating layer 201_2c below the insulating layer 201_2b. Insulating layers 51_1, 51_2b, and 51_2c can be applied to insulating layers 201_1, 201_2b, and 201_2c, respectively. Also, Figure 9C shows an example in which an insulating layer 201_2a is provided between insulating layer 201_1 and insulating layer 201_2b. Insulating layer 51_2a can be applied to insulating layer 201_2a.

[0265] By arranging the insulating layer 201 and the insulating layer 250 in a symmetrical structure in the vertical direction (stacking direction) with respect to the semiconductor layer 230, it may be possible to appropriately control the hydrogen concentration distribution and oxygen concentration distribution in and around the semiconductor layer 230. This may result in good electrical characteristics and high reliability in the transistor.

[0266] <Insulating layer 202> The insulating layer 202 can be made of a silicon oxide film. Alternatively, an insulating film having an oxygen barrier can be provided between the insulating layer 202 and the conductive layer 205. This can suppress oxidation of the conductive layer 205.

[0267] <Semiconductor layer 230 having a stacked structure> The semiconductor layer 230 can also have a stacked structure.

[0268] The configuration example shown in Figure 10A differs from that in Figure 7A in that the semiconductor layer 230 has semiconductor layer 230_1, semiconductor layer 230_2 on semiconductor layer 230_1, and semiconductor layer 230_3 on semiconductor layer 230_2. The semiconductor layers 30_1 to 30_3 exemplified in Embodiment 1 can be applied to semiconductor layers 230_1 to 230_3, respectively.

[0269] For example, as shown in Figure 10B, the semiconductor layer 230 has a recess that overlaps with the conductive layer 242a, and the conductive layer 242a may be in contact with the side wall and bottom of the recess of the semiconductor layer 230. The recess includes an opening in the semiconductor layer 230_3. This opening reaches the semiconductor layer 230_2. This opening does not overlap with the conductive layer 260. The conductive layer 242a is in contact with the semiconductor layer 230_2 at the opening. With this configuration, the contact area between the conductive layer 242a and region 230a is increased, and the contact resistance between the conductive layer 242a and region 230a can be reduced.

[0270] Furthermore, as shown in Figure 10C, for example, the upper end of the conductive layer 242a1 may be located below the upper surface of the conductive layer 242a2. For example, when the conductive layer 242a1 is formed using the sputtering method, the conductive layer 242a1 may not be formed along the side surface of the insulating layer 241a, and the conductive layer 242a1 may be formed only on the upper surface of region 230a and its vicinity.

[0271] Furthermore, Figure 11 shows an example configuration in which, in the configuration shown in Figure 8A, a stacked structure is applied to the semiconductor layer 230, consisting of semiconductor layer 230_1, semiconductor layer 230_2 on semiconductor layer 230_1, and semiconductor layer 230_3 on semiconductor layer 230_2.

[0272] [Example of semiconductor device configuration 2] Below, as an example of the configuration of a semiconductor device, an example in which the semiconductor device has a mixed layer of an insulating layer 51 and a semiconductor layer 30 will be described.

[0273] A semiconductor device may have a mixed layer of an insulating layer 51 and a semiconductor layer 30. The thickness of the mixed layer is, for example, thinner than the thickness of the semiconductor layer 30. When observing the cross-section of the semiconductor device, it may be difficult to confirm the boundary between the mixed layer and the semiconductor layer 30, or it may be difficult to confirm the boundary between the mixed layer and the insulating layer 51.

[0274] If the insulating layer 51 has a laminated structure of insulating layer 51_2 and insulating layer 51_1, and the semiconductor layer 30 has a laminated structure of semiconductor layer 30_1, semiconductor layer 30_2, and semiconductor layer 30_3, then for example, the semiconductor device may have a mixed layer of insulating layer 51_1 and semiconductor layer 30_1.

[0275] The mixed layer described above is formed near the surface of the insulating layer 51_1, at the interface between the insulating layer 51_1 and the semiconductor layer 30_1, or near the surface of the semiconductor layer 30_1 on the insulating layer 51_1 side. The thickness of the mixed layer is preferably thinner than the thickness of the semiconductor layer 30_1.

[0276] Alternatively, the entire semiconductor layer 30_1 may become a mixed layer.

[0277] Indium oxide can be suitably used as the semiconductor layer 30. The crystal structure of indium oxide is, for example, a bixbite structure. The bixbite structure contains structural gaps (structural intermediate positions, which can also be expressed as atomic gaps). The semiconductor layer 30 has a bixbite structure, and this bixbite structure may have distortion. The semiconductor layer 30 has distortion that can be formed, for example, by reducing or eliminating the structural gaps in the bixbite structure. In such distorted indium oxide, for example, the structural gaps in the bixbite structure can be reduced or eliminated. Note that if the bixbite structure is a distorted crystal structure, this crystal structure can also be considered a structure with lattice disorder.

[0278] By forming a mixed layer, a crystal with a strained Bixbite structure can be formed in the semiconductor layer 30. For example, a semiconductor device may have a crystalline portion with a strained Bixbite structure in the semiconductor layer 30_1.

[0279] By having a Bixbite structure crystal with such strain in semiconductor layer 30_1, semiconductor layer 30_2 formed on semiconductor layer 30_1 can grow crystals using semiconductor layer 30_1 as a substrate. As a result, semiconductor layer 30_2 can have regions with small or no structural gaps in the Bixbite structure. By reducing or eliminating structural gaps where impurities may exist, a normally-off transistor can be made. Furthermore, the reliability of the transistor can be improved. In addition, in transistors using a strained semiconductor layer, such as transistors using silicon-containing semiconductors, the field-effect mobility can sometimes be improved.

[0280] Furthermore, the mixed layer may have a structure in which some of the indium in the bixbite structure of indium oxide is replaced by other elements. For example, when an oxide of metallic Me is used as the insulating layer 51, the mixed layer may have a structure in which some of the indium in the bixbite structure of indium oxide is replaced by metallic Me. In this case, it is preferable that the bonding force between metallic Me and oxygen is strong. This can suppress the formation of oxygen vacancies that may form in the mixed layer. As metallic Me, one or more types selected from the first elements described above can be used.

[0281] Therefore, it is preferable to use, for example, gallium oxide or aluminum oxide as the insulating layer 51, and more preferably gallium oxide. Gallium and aluminum have a stronger bonding force with oxygen than indium, and a shorter bonding distance with oxygen than indium. Therefore, the mixed layer or the semiconductor layer 30_1 containing the mixed layer can be made into a hard and dense layer with small structural gaps in the Bixbite structure.

[0282] The mixed layer contains the elements contained in the insulating layer 51 and the elements contained in the semiconductor layer 30. When an oxide of metal Me is used as the insulating layer 51 and an oxide containing indium is used as the semiconductor layer 30, the mixed layer contains metal Me, indium, and oxygen.

[0283] Furthermore, if the insulating layer 51 has a crystalline structure, the ease with which oxygen vacancies are formed in the mixed layer or the semiconductor layer 30_1 containing the mixed layer may differ. For example, if the insulating layer 51 has a hexagonal crystalline structure instead of a bixbite structure, the formation of oxygen vacancies in the mixed layer or the semiconductor layer 30_1 containing the mixed layer can be suppressed. Typical materials having a hexagonal crystalline structure include indium gallium oxide. This indium gallium oxide can be used as a mixed layer. When the insulating layer 51 has a hexagonal crystalline structure, it is preferable that it is c-axis oriented. C-axis orientation can make it easier for the semiconductor layer 30 above it to form a single crystal. It can also make it easier to control the crystal orientation of the semiconductor layer 30.

[0284] Furthermore, it is preferable that semiconductor layer 30_2 has a softer structure than either or both of semiconductor layer 30_1 and semiconductor layer 30_3. Here, a soft structure is a structure with a lower film density than the comparison film, or a structure with a faster wet etching rate. With such a structure, impurities from the upper layer can be blocked by semiconductor layer 30_3 in semiconductor layer 30_2, and impurities from the lower layer can be blocked by semiconductor layer 30_1.

[0285] Furthermore, the semiconductor layer 30_3 formed on the semiconductor layer 30_2 can be grown using the semiconductor layer 30_2 as a substrate. If the semiconductor layer 30_2 is a layer with small structural gaps in the Bixbite structure, for example, the semiconductor layer 30_3 may also have small structural gaps in the Bixbite structure, resulting in a hard and dense layer. This suppresses the incorporation of impurities from the insulating layer 50 into the semiconductor layer 30.

[0286] Furthermore, if the semiconductor layer 30 is too thick, the strain caused by the mixed layer may become smaller in the semiconductor layer 30, or the strain may be reduced in regions of the semiconductor layer 30 that are further away from the mixed layer, thus reducing the effect of the strain in the semiconductor layer 30. Therefore, it is preferable for the semiconductor layer 30 to be thin.

[0287] The thickness of the semiconductor layer 30 is, for example, 0.1 nm or more and 30 nm or less. Preferably, the thickness of the semiconductor layer 30 is 1 nm or more and 20 nm or less, more preferably 2 nm or more and 10 nm or less, and even more preferably 3 nm or more and 8 nm or less, and typically it can be 5 nm or close to that.

[0288] Furthermore, the semiconductor layer 30 preferably has a stacked structure of two or more layers. For example, as mentioned above, it can have a stacked structure of semiconductor layer 30_1, semiconductor layer 30_2, and semiconductor layer 30_3. The thickness of each stacked layer is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0289] The semiconductor layer 30_1 and the semiconductor layer 30_3 can be formed using various thin film formation methods such as sputtering and ALD, with sputtering being more preferable. In sputtering, the mixed layer is more easily formed by impacting particles onto the surface to be formed. Furthermore, in sputtering, the collision energy of the particles can be further increased by using high power and low pressure conditions. This makes it easier to form the mixed layer.

[0290] [Variations] The following describes an example with some configuration differences from the above example. Note that the following explanation omits parts that overlap with the above.

[0291] [Modification 1] The following describes a configuration in which a conductive layer is provided between the semiconductor layer 230 and the conductive layer 242a, and between the semiconductor layer 230 and the conductive layer 242b.

[0292] Figure 12A shows a schematic cross-sectional view of transistor 200. Transistor 200 has a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 205, and an insulating layer 201. The transistor also has a conductive layer 243a between semiconductor layer 230 and conductive layer 242a, and a conductive layer 243b between semiconductor layer 230 and conductive layer 242b.

[0293] The composition and materials of the conductive layer 205, insulating layer 201, semiconductor layer 230, insulating layer 250, and conductive layer 260 can be found in the information described above.

[0294] The conductive layer 243a functions as either the source electrode or the drain electrode of the transistor 200, and the conductive layer 243b functions as the other. In this configuration, the conductive layers 242a and 242b function as vias connecting the transistor 200 to wiring or other components provided on the transistor 200.

[0295] By adopting the configuration shown in Figure 12A, the contact area between the semiconductor layer and the source electrode or drain electrode can be increased compared to the configuration shown in Figure 8A, thereby reducing the contact resistance between the source electrode and the semiconductor layer, and between the drain electrode and the semiconductor layer.

[0296] As conductive layers 243a and 243b, conductive materials applicable to conductive layers 242a1 and 242b1 can be used. For example, an oxide conductor having indium, a third element, and oxygen can be used. As described above, by making the main components of the source electrode and drain electrode common to the main components of the semiconductor layer, the contact resistance between the source electrode and the semiconductor layer, and the contact resistance between the drain electrode and the semiconductor layer can be reduced.

[0297] By making the main component of semiconductor layer 230 the same as the main components of conductive layers 243a and 243b, a reduction in the thickness of semiconductor layer 230 may occur when processing the conductive layers that become conductive layers 243a and 243b. In this case, the film thickness of the portion of semiconductor layer 230 that overlaps with conductive layer 260 becomes thinner than the film thickness of the portion of semiconductor layer 230 that overlaps with conductive layer 243a or conductive layer 243b (see Figure 12A).

[0298] The conductive layers 243a and 243b can be arranged in a laminated structure of two or more layers. For example, as shown in Figure 12B, the conductive layer 243a can be arranged in a laminated structure of a conductive layer 243a1 in contact with the semiconductor layer 230 and a conductive layer 243a2 on top of the conductive layer 243a1. The conductive layer 243b can be arranged in a laminated structure of a conductive layer 243b1 in contact with the semiconductor layer 230 and a conductive layer 243b2 on top of the conductive layer 243b1.

[0299] For conductive layers 243a1 and 243b1, conductive materials applicable to conductive layers 242a1 and 242b1 can be used. For conductive layers 243a2 and 243b2, conductive materials applicable to conductive layers 242a2 and 242b2 can be used. For example, the above-mentioned oxide conductors can be used for conductive layers 243a1 and 243b1, and tungsten can be used for conductive layers 243a2 and 243b2.

[0300] Furthermore, as shown in Figure 12B, an insulating layer 271a can be provided between the conductive layer 242a and the insulating layer 275, and an insulating layer 271b can be provided between the conductive layer 242b and the insulating layer 275. The insulating layers 271a and 271b each function as etching stoppers during processing of the conductive layers 242a and 242b. In other words, the insulating layers 271a and 271b each have the function of protecting the conductive layers 243a and 243b. Also, since the insulating layers 271a and 271b are in contact with the conductive layers 243a and 243b, respectively, it is preferable that the insulating layers 271a and 271b are inorganic insulators that do not easily oxidize the conductive layers 243a and 243b. For example, the insulating layer 271a can also be a laminated structure of a silicon nitride film in contact with the conductive layer 243a and a silicon oxide film on the silicon nitride film. The laminated structure of the insulating layer 271b is similar.

[0301] Furthermore, as shown in Figure 12B, it is possible to provide an insulating layer 255 between the conductive layer 243a2 and the insulating layer 250, and between the conductive layer 243b2 and the insulating layer 250. Since the insulating layer 255 is in contact with the conductive layers 243a2 and 243b2, it is preferable that the insulating layer 255 is an inorganic insulator that does not easily oxidize the conductive layers 243a2 and 243b2. This prevents excessive oxidation of the conductive layers 243a2 and 243b2 by heat treatment, even if a relatively easily oxidized tungsten film or the like is used for the conductive layers 243a2 and 243b2. For example, a silicon nitride film can be used as the insulating layer 255.

[0302] The insulating layer 255 can be formed by creating openings in the insulating layers 280 and 275, removing the portions of the conductive layers that will become the conductive layers 243a2 and 243b2 that overlap with these openings, depositing an insulating film that will become the insulating layer 255, and then processing the insulating film using anisotropic etching. In other words, the insulating layer 255 is formed in a sidewall shape, in contact with the side walls of the openings.

[0303] In the manufacturing process of semiconductor devices, oxygen can be supplied from the insulating layer 250 and insulating layer 201 to the semiconductor layer 230 by heat treatment. In this case, by providing the insulating layer having the function of supplying oxygen by heating only on the insulating layer 250 side, oxygen can be selectively supplied to the channel formation region of the semiconductor layer 230. Therefore, it may not be necessary to provide an insulating layer having the function of supplying oxygen by heating on the insulating layer 201 side.

[0304] For example, the insulating layer 250 may have an insulating layer 250_2a that has the function of supplying oxygen, while the insulating layer 201 may not have an insulating layer 201_2a that has the function of supplying oxygen. Alternatively, for example, the thickness of the insulating layer 201_1 of the insulating layer 201 may be made thicker than the insulating layer 250_1 of the insulating layer 250.

[0305] Furthermore, Figures 13A and 13B show examples of configurations in which a stacked structure is applied as the semiconductor layer 230, in the configuration shown in Figures 12A and 12B, respectively, consisting of semiconductor layer 230_1, semiconductor layer 230_2 on semiconductor layer 230_1, and semiconductor layer 230_3 on semiconductor layer 230_2.

[0306] As explained in Figure 12A, by making the main component of the semiconductor layer 230 common to the main components of the conductive layers 243a and 243b, film thinning of the semiconductor layer 230 may occur when processing the conductive layers that become conductive layers 243a and 243b. In this case, the film thickness of the portion of the semiconductor layer 230 that overlaps with the conductive layer 260 becomes thinner than the film thickness of the portion of the semiconductor layer 230 that overlaps with the conductive layer 243a or conductive layer 243b. In Figure 13A, due to this film thinning, semiconductor layer 230_3 is removed in the portion of the semiconductor layer 230 that overlaps with the insulating layer 250 above and below.

[0307] When applying the configuration of the insulating layer 50 described above to the insulating layer 250, a material can be used that is in contact with the upper surface of the region where semiconductor layer 230_3 has been removed in the semiconductor layer 230 (specifically, the upper surface of semiconductor layer 230_2 in this case) and has a lower electron affinity than that region of semiconductor layer 230.

[0308] [Modification 2] The above describes a configuration in which the gate electrode is embedded in the insulating layer, but the following describes a transistor with a different configuration.

[0309] Figure 14A shows a cross-sectional view of transistor 200a in the channel length direction. Transistor 200a has a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 242a, and a conductive layer 242b.

[0310] An insulating layer 250 is provided covering the semiconductor layer 230, and a conductive layer 260 is provided on the insulating layer 250 at a position overlapping with the semiconductor layer 230. Furthermore, insulating layers 281 and 280 are laminated and provided covering the insulating layer 250 and the conductive layer 260. A pair of openings reaching the semiconductor layer 230 is provided in the insulating layer 281, insulating layer 280, and insulating layer 250, respectively. Conductive layers 242a and 242b are provided on the insulating layer 280 and are in contact with the semiconductor layer 230 at their respective openings.

[0311] As the insulating layer 281, an insulator having barrier properties against hydrogen and oxygen, similar to that of the insulating layer 275, can be used. This suppresses the diffusion of impurities contained in the insulating layer 280 into the semiconductor layer 230, and the diffusion of oxygen contained in the semiconductor layer 230 towards the insulating layer 280.

[0312] The region of the semiconductor layer 230 that overlaps with the conductive layer 260 functions as a channel-forming region. Furthermore, a pair of regions 230n flanking the channel-forming region function as a source region or a drain region. It is preferable that regions 230n have lower resistance than the channel-forming region.

[0313] For example, region 230n preferably contains an element that imparts conductivity to the semiconductor layer 230. Examples of such elements include typical nonmetallic elements other than hydrogen and oxygen, typical metallic elements, and transition elements (transition metals). Specifically, examples include boron, phosphorus, magnesium, aluminum, silicon, etc. These elements can be introduced into a portion of the semiconductor layer 230 by methods such as doping, ion implantation, or thermal diffusion. For example, using the conductive layer 260 as a mask, the above elements can be introduced into a region of the semiconductor layer 230 that does not overlap with the conductive layer 260 via the insulating layer 250 by doping or ion implantation.

[0314] Figure 14B shows an example where the insulating layer 250 is located only in the region overlapping with the conductive layer 260 and is not provided on the region 230n of the semiconductor layer 230. In this case, by using a film containing the above-mentioned elements for the insulating layer 281 in contact with region 230n, the above-mentioned elements can be introduced into region 230n during the formation of the insulating layer 281 or by subsequent heat treatment. For example, it is preferable to use silicon nitride containing hydrogen for the insulating layer 281. Alternatively, an oxide containing a metallic element from among the above-mentioned elements may be used.

[0315] [Modification 3] Figure 15A shows an example in which a conductive layer 205, which functions as a second gate electrode, is provided in the configuration shown in Figure 14A.

[0316] The conductive layer 205 is provided on the substrate 210, and the insulating layer 201 is provided so as to cover the conductive layer 205. The structure, materials, etc. of the conductive layer 205 and the insulating layer 201 can be found in the description above.

[0317] Figure 15B shows an example in which the insulating layer 250 is located only in the region that overlaps with the conductive layer 260 and is not provided on the region 230n of the semiconductor layer 230.

[0318] [Modification 4] The following describes a transistor in which the conductive layer, which functions as a gate electrode, is located below the semiconductor layer.

[0319] Figure 16A shows a cross-sectional view of transistor 200b in the channel length direction. Transistor 200b has a semiconductor layer 230, an insulating layer 201, a conductive layer 205, a conductive layer 242a, and a conductive layer 242b. The conductive layer 205 functions as the gate electrode of transistor 200b. The insulating layer 201 functions as the gate insulating layer of transistor 200b.

[0320] The composition and materials of the substrate 210, conductive layer 205, insulating layer 201, and semiconductor layer 230 can be found in the information described above.

[0321] Each of the conductive layer 242a and conductive layer 242b has a region in contact with the upper surface of the semiconductor layer 230 and a region in contact with the side surface of the semiconductor layer 230. The insulating layer 280 is provided so as to cover the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b.

[0322] Figure 16B shows an example in which an insulating layer 284 is provided in the configuration shown in Figure 16A.

[0323] The insulating layer 284 is provided so as to cover the semiconductor layer 230 and has a first opening and a second opening that reach the semiconductor layer 230. Within the first opening, the conductive layer 242a is in contact with the semiconductor layer 230, and within the second opening, the conductive layer 242b is in contact with the semiconductor layer 230.

[0324] The insulating layer 284 functions as a channel protection film that protects the channel formation region when forming the conductive layers 242a and 242b. The insulating layer 284 is formed on the semiconductor layer 230, a first opening and a second opening are formed in the insulating layer 284, conductive films that will become the conductive layers 242a and 242b are deposited on the insulating layer 284, and the conductive layers 242a and 242b can be formed by processing the conductive films. Since the channel formation region is not exposed during the deposition and processing of the conductive films, damage to the channel formation region can be suppressed. Therefore, a transistor with good electrical characteristics can be made.

[0325] As the insulating layer 284, a material that can be used for the insulating layer 280 can be applied.

[0326] Figure 16C shows an example in the configuration shown in Figure 16A where the side surface of the semiconductor layer 230 is located inward from the side surface of the conductive layer 205. It also shows an example where the conductive layer 205 has a region that does not overlap with the semiconductor layer 230. This reduces the occupied area of ​​the transistor 200b.

[0327] Figure 17A shows an example in the configuration shown in Figure 16A where both the conductive layer 242a and the conductive layer 242b have a two-layer structure. Figure 17B shows an example in the configuration shown in Figure 17A where the side edge of the conductive layer 242a1 coincides with the side edge of the semiconductor layer 230, and the side edge of the conductive layer 242b1 coincides with the side edge of the semiconductor layer 230. By using the configuration shown in Figure 17A or Figure 17B, the contact resistance between the source electrode and the semiconductor layer, and the contact resistance between the drain electrode and the semiconductor layer can be reduced while maintaining conductivity as a wiring.

[0328] In the configuration shown in Figure 17A, the conductive layer 242a1 and the conductive layer 242b1 are in contact with a portion of the upper surface and a portion of the side surface of the semiconductor layer 230, respectively. This increases the contact area between the conductive layer 242a1 and the semiconductor layer 230, and the contact area between the conductive layer 242b1 and the semiconductor layer 230.

[0329] The composition and materials of conductive layers 242a1, 242a2, 242b1, and 242b2 can be found in the description above. For example, metal oxides such as ITO or ITSO can be used for conductive layers 242a1 and 242b1, and tungsten, copper, or nickel can be used for conductive layers 242a2 and 242b2.

[0330] In the configuration shown in Figures 17A and 17B, an insulating layer 281 is provided on the insulating layer 280. As the insulating layer 281, an insulator having barrier properties against hydrogen and oxygen, similar to that of the insulating layer 275, can be used. This suppresses the diffusion of impurities such as water and hydrogen from above the transistor 200b into the semiconductor layer 230.

[0331] In the configuration shown in Figures 17A and 17B, the conductive layer 242a1 and the conductive layer 242b1 are formed by creating conductive layers that will become conductive layer 242a1 and conductive layer 242b1, and then removing a portion of the region of the conductive layer that overlaps with the semiconductor layer 230 by etching. If the etching selectivity ratio of the conductive layer to the semiconductor layer 230 is small, when the conductive layer is etched, a portion of the exposed region of the semiconductor layer 230 is etched, and grooves are formed in the semiconductor layer 230.

[0332] Figure 17C shows an example in which, in the configuration shown in Figure 17A, a conductive layer 260 that functions as a second gate electrode and an insulating layer 250 that functions as a second gate insulating layer are provided.

[0333] The insulating layer 250 is provided on the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b. The conductive layer 260 is provided on the insulating layer 250 such that it has a region overlapping with the semiconductor layer 230. The insulating layer 280 is provided so as to cover the conductive layer 260. The composition, materials, etc., of the conductive layer 260 and the insulating layer 250 can be found in the above description.

[0334] By using the conductive layer 260 as a second gate electrode, the on-current can be increased or the threshold voltage can be controlled. For example, by setting the conductive layer 205 and the conductive layer 260 to the same potential and driving them as a double-gate transistor, the on-current can be increased. Alternatively, by applying a different potential to the conductive layer 260 than to the conductive layer 205, the threshold voltage can be controlled. Therefore, by controlling the threshold voltage, it is easy to realize a transistor with normally-off characteristics.

[0335] [Modification 5] Below, we will describe a vertical transistor in which the source electrode and drain electrode are located at different heights.

[0336] Figure 18A shows a schematic cross-sectional view of transistor 200c. Transistor 200c has a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 245, and a conductive layer 246. Conductive layer 245 functions as either the source electrode or the drain electrode of transistor 200c, and conductive layer 246 functions as the other.

[0337] A conductive layer 245 is provided on an insulating layer 201, and an insulating layer 211 is provided covering the conductive layer 245. A conductive layer 246 is provided on the insulating layer 211. The conductive layer 246 and the insulating layer 211 are provided with openings that reach the conductive layer 245. The semiconductor layer 230 is provided in contact with the upper surface of the conductive layer 246, the side surface of the conductive layer 246 at the opening, the side surface of the insulating layer 211, and the upper surface of the conductive layer 245. The insulating layer 250 is provided covering the semiconductor layer 230 at the opening, and the conductive layer 260 is provided covering the insulating layer 250.

[0338] In transistor 200c, the source electrode and drain electrode are located at different heights, and current flows in the height direction through the semiconductor layer. That is, the channel length direction has a component in the height direction (vertical direction), so transistor 200c can be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel type transistor. In transistor 200c, two or more of the source electrode, semiconductor, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to a so-called planar type transistor (which can also be called a lateral transistor or LFET (Lateral FET)) in which the semiconductor is arranged on a plane.

[0339] Further, since the channel length of the transistor 200c can be precisely controlled by the thickness of the insulating layer 211 that functions as a spacer, the variation in the channel length can be made extremely small compared to planar-type transistors. Furthermore, by making the insulating layer 211 thinner, it is possible to fabricate transistors with an extremely short channel length. For example, transistors with a channel length of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be fabricated. Therefore, it is possible to realize transistors with an extremely short channel length that could not be achieved with exposure apparatuses for mass production. Also, it is possible to realize transistors with a channel length of less than 10 nm without using an extremely expensive exposure apparatus used in the most advanced LSI technology.

[0340] In the transistor 200c, the shape of the opening provided in the insulating layer 211 can be various shapes.

[0341] FIG. 18B shows a perspective view of the insulating layer 211 and the semiconductor layer 230 extracted. Here, an example in which a cylindrical opening 290o is provided in the insulating layer 211 is shown. At this time, the semiconductor layer 230 has a cylindrical portion along the side wall of the opening 290o and flat portions parallel to the substrate surface at the bottom and the top. In the configuration shown in FIG. 18B, the channel width of the transistor approximately coincides with the circumference length of the cylindrical portion. Therefore, in the configuration shown in FIG. 18B, it is easy to reduce the channel length and increase the channel width, and a transistor capable of flowing an extremely large current can be realized.

[0342] On the other hand, FIG. 18C shows an example in which a slit-shaped opening 290s is provided in the insulating layer 211. As shown in FIG. 18C, since a plurality of semiconductor layers 230 can be arranged in the opening 290s, it is suitable for the case of arranging transistors at high density. Although not shown here, the conductive layer 260 that functions as a gate electrode can be provided so as to be embedded in the opening 290s and used as a wiring extending in the extending direction of the opening 290s.

[0343] The substrate 210, the insulating layer 211, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 can be respectively applied with the substrate 20, the insulating layer 51, the semiconductor layer 30, the insulating layer 50, and the conductive layer 60 exemplified in Embodiment 1. An insulating layer may be provided between the insulating layer 211 and the semiconductor layer 230. At this time, the insulating layer 51_1 can be applied to the insulating layer.

[0344] The above is the description of the modified example.

[0345] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments or examples described in this specification.

[0346] (Embodiment 3) In this embodiment, an indium oxide film that can be used for the semiconductor layer of a transistor according to one aspect of the present invention will be described.

[0347] In this specification and the like, indium oxide having at least a crystal part or a crystal region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, as crystal IO or crystalline IO, single-crystalline indium oxide, polycrystalline indium oxide, microcrystalline indium oxide, etc. can be mentioned.

[0348] Indium oxide is a semiconductor material having physical properties completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0349] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO will be described. FIG. 19A is a schematic diagram of the carrier concentration dependence of the hole mobility for silicon (Si) and indium oxide (InO Ｘ ) and FIG. 19B is a schematic diagram of the carrier concentration dependence of the hole mobility for IGZO.

[0350] First, as indicated by the arrows in Figure 19B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 19A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 3). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 19A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 19A.

[0351] In Figure 19A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0352] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0353] On the one hand, in the range R2 with a high carrier concentration, the electrical resistance is low. For example, it can be said that it is a suitable carrier concentration range for the source region and drain region of a transistor, or a resistor, or a transparent conductive film. The range R2 is a range including a carrier concentration value of 1×10 ２０ cm −３ , for example, a range of 1×10 １９ cm −３ or more and 1×10 ２２ cm −３ or less. By sufficiently increasing the carrier concentration, it can be expected that the resistivity can be reduced to 1×10 −４ Ω·cm or less.

[0354] In addition, in indium oxide, the region with a carrier concentration in the range R2 can contain an element that increases the carrier concentration. For example, it is preferable to contain an element common to the source electrode and drain electrode of a transistor. Examples of the element that increases the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, boron, etc. In particular, it is more preferable to use an element whose oxide has conductivity or semiconductor properties. As a method for supplying the element that increases the carrier concentration, a method of forming and diffusing a film containing the element, ion implantation method, ion doping method, plasma immersion ion implantation method, or plasma treatment can be used. In this specification, etc., unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, etc., a method of supplying ions with mass separation is called an ion implantation method, and a method of supplying ions without mass separation is called an ion doping method.

[0355] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be considered an oxide in which valence electron control is possible. Note that in IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 19A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0356] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0357] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 19B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 19A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0358] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic, where Vth is 1nA (1 × 10⁻¹⁰). −９ Let Vsh be the gate voltage (Vg) when A) is true. Also, Vsh is the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0359] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is important in order to make the semiconductor i-type, that is, to achieve Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be made in which a gallium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0360] Furthermore, in the above film configuration, an oxygen-containing film such as a silicon oxide nitride film or a silicon oxide nitride film can be used instead of the silicon oxide film. Also, in the above film configuration, an aluminum oxide film can be used instead of the gallium oxide film. Also, in the above film configuration, a silicon oxide nitride film or a silicon oxide nitride film can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0361] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0362] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0363] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0364] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0365] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0366] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0367] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0368] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0369] Furthermore, the indium oxide film described herein has a high film density. Here, an indium oxide film applicable to one aspect of the present invention (here, In ２ O ３ The membrane density of ) is shown in Table 1.

[0370]

[0371] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the substrate condition for the indium oxide film, where Sample 1 to Sample 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Sample 5 and Sample 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film deposition condition for the indium oxide film, where Sample 1 to Sample 3 are deposited by sputtering (SP), and Sample 4 to Sample 6 are deposited by ALD. Furthermore, condition 3 is the heat treatment condition after indium oxide film deposition. Sample 1, Sample 4, and Sample 5 are without heat treatment (as-depo), Sample 2 is baked at 350°C in a CDA atmosphere, Sample 3 is baked at 650°C in a CDA atmosphere, and Sample 6 is baked at 250°C in a vacuum atmosphere.

[0372] In Table 1, CDA stands for Clean Dry Air. It is preferable that the hydrogen and water content in the atmosphere during the heat treatment after indium oxide film formation (corresponding to condition 3) be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as this atmosphere.

[0373] As shown in Table 1, the indium oxide film shows a tendency that its film density becomes higher when heat treatment is performed, compared with the case where heat treatment is not performed (Sample 1, Sample 4 or Sample 5). This is due to the desorption of impurity elements (such as carbon, nitrogen, hydrogen, argon, etc.) from the film during heat treatment, resulting in the purification of the indium oxide film. Also, as shown in Sample 5 and Sample 6, the indium oxide film on YSZ has a film density exceeding 7.00 g / cm ３ . The theoretical value of the film density of the indium oxide film is 7.18 g / cm ３ . In this specification, etc., the range of the film density of the indium oxide film is 6.70 g / cm ３ or more and 7.18 g / cm ３ or less, preferably 6.90 g / cm ３ or more and 7.18 g / cm ３ or less, more preferably 7.00 g / cm ３ or more and 7.18 g / cm ３ or less.

[0374] Note that for the evaluation of the film density, for example, the Rutherford backscattering method (RBS) or the X-ray reflectivity measurement method (XRR) can be used. The difference in film density may be evaluated by a transmission electron microscope (TEM) image of the cross section. In TEM observation, when the film density is high, the transmission electron (TE: Transmission Electron) image is dark, and when the film density is low, the transmission electron (TE) image is light.

[0375] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, even more preferably 200 cm ２ / (V·s) or more, and even more preferably 250 cm ２ / (V·s) or more.

[0376] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 19C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0377] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0378] Furthermore, as shown in Figure 19C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0379] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0380] Table 2 shows single crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 2, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Furthermore, as shown in Table 2, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0381]

[0382] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0383] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L１ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0384] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0385] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0386] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0387] Here, we compare transistors with crystalline indium oxide films, transistors with IGZO (In, Ga, Zn compound oxide) films, and transistors with silicon (Si) films. This comparison is shown in Table 3.

[0388]

[0389] In Table 3, transistors with a crystalline indium oxide film are explicitly labeled as "Crystal IO (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Crystal IO". Transistors with a Si film are explicitly labeled as "Si (LSI)" for LSI applications. Hereafter, they may simply be referred to as "Si". Transistors with an IGZO film are explicitly labeled as "IGZO (Display)" for Display applications. Hereafter, they may simply be referred to as "IGZO". In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents -1 point. Total is the sum of the points for ◎, ○, △, and × shown in Table 3. A higher point value indicates better performance than a lower point value.

[0390] In Table 3, the first comparison item is minimal off-current, in which crystalline IO and IGZO are superior to Si. The second comparison item is on-current (Ion) characteristics, in which Si, crystalline IO, and IGZO have the highest characteristics. The third comparison item is reliability, in which crystalline IO and Si are superior to IGZO. The fourth comparison item is channel length miniaturization, in which crystalline IO and IGZO are superior to Si. In the channel length miniaturization item, VFET represents a vertical transistor, UFET represents a U-shaped transistor, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, in which crystalline IO and Si are superior to IGZO. The sixth comparison item is improved integration density, in which Si is superior to crystalline IO and IGZO. Furthermore, the seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-stage) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the potential for self-heating, in which crystalline IO and IGZO are superior to Si.

[0391] As shown in Table 3, the total score is 8 points for crystalline IO (LSI), and 4 points each for Si (LSI) and IGZO (Display). Thus, a semiconductor device according to one aspect of the present invention, particularly a semiconductor device having a crystalline indium oxide film, has the potential to replace semiconductor devices using Si.

[0392] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0393] (Embodiment 4) In this embodiment, a memory device according to one aspect of the present invention will be described with reference to Figures 20 to 23. In this embodiment, an example of the configuration of a memory device in which a layer having memory cells is stacked on a layer on which a drive circuit including a sense amplifier is provided will be described.

[0394] The transistors in the memory cells exemplified below can be the same type of transistor (referred to as an OS transistor) exemplified in Embodiment 2, in which a channel is formed in a single-crystal oxide semiconductor.

[0395] <Example of Storage Device Configuration> Figure 20 shows a block diagram illustrating an example of the configuration of a storage device 480 according to one aspect of the present invention. The storage device 480 shown in Figure 20 has a layer 420 and a stacked layer 470.

[0396] Layer 420 is a layer having Si transistors. In layer 470, element layers 430[1] to 430[m] (where m is an integer of 2 or more) are stacked. Element layers 430[1] to 430[m] are layers having OS transistors. Layer 470, in which layers having OS transistors are stacked, can be stacked on top of layer 420.

[0397] The elements in the element layers 430[1] to 430[m], such as OS transistors and capacitive elements, constitute memory cells. Figure 20 shows an example in which the element layers 430[1] to 430[m] have a plurality of memory cells 432 arranged in a matrix of m rows and n columns (where n is an integer of 2 or more).

[0398] In Figure 20, the memory cell 432 in the first row and first column is shown as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is shown as memory cell 432[m,n]. In this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment, the memory cell 432 in the ith row and jth column is shown as memory cell 432[i,j]. In this embodiment, when "i + α" (where α is a positive or negative integer) is used, "i + α" is not less than 1 and not greater than m. Similarly, when "j + α" is used, "j + α" is not less than 1 and not greater than n.

[0399] Figure 20 also illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first wiring WL (first row) is denoted as wiring WL[1], and the mth wiring WL (mth row) is denoted as wiring WL[m]. Similarly, the first wiring PL (first row) is denoted as wiring PL[1], and the mth wiring PL (mth row) is denoted as wiring PL[m]. Similarly, the first wiring BL (first column) is denoted as wiring BL[1], and the nth wiring BL (nth column) is denoted as wiring BL[n]. Note that the number of layers of element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) do not have to be the same.

[0400] Multiple memory cells 432 located in row i are electrically connected to the wiring WL (wiring WL[i]) and wiring PL (wiring PL[i]) in row i. Multiple memory cells 432 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0401] Wiring BL functions as a bit line for writing and reading data. Wiring WL functions as a word line for controlling the on or off state (conductive or non-conductive) of the access transistor, which functions as a switch. Wiring PL functions as a constant potential line connected to the capacitor. A separate wire can be provided to transmit the back gate potential.

[0402] The memory cells 432 in each of the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via wiring BL. The wiring BL can be arranged in the parallel and perpendicular directions to the substrate surface on which layer 420 is provided. By configuring the wiring BL extending from the memory cells 432 in the element layers 430[1] to 430[m] with wiring arranged vertically in addition to wiring arranged horizontally on the substrate surface, the length of the wiring between the element layer 430 and the sense amplifier 446 can be shortened. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thus reducing power consumption and signal delay. As a result, the power consumption and signal delay of the memory device 480 can be reduced. Furthermore, it becomes possible to operate even if the capacitance of the capacitor in the memory cell 432 is reduced. As a result, the memory device 480 can be miniaturized.

[0403] Layer 420 includes a PSW 471 (power switch), a PSW 472, and peripheral circuits 422. Peripheral circuits 422 include a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit in layer 420 is a circuit containing a Si transistor.

[0404] In the storage device 480, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0405] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 473.

[0406] The control circuit 473 is a logic circuit that has the function of controlling the overall operation of the storage device 480. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operating mode is executed.

[0407] The voltage generation circuit 474 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0408] The drive circuit 440 is a circuit for writing and reading data to and from the memory cell 432. The drive circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the aforementioned sense amplifier 446.

[0409] The row decoder 442 and column decoder 444 have the function of decoding the ADDR signal. The row decoder 442 is a circuit for specifying the row to access, and the column decoder 444 is a circuit for specifying the column to access. The row driver 443 has the function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the function of writing data to the memory cell 432, reading data from the memory cell 432, and holding the read data.

[0410] The input circuit 447 has the function of holding the signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) to be written to the memory cell 432. The data (Dout) read by the column driver 445 from the memory cell 432 is output to the output circuit 448. The output circuit 448 has the function of holding Dout. The output circuit 448 also has the function of outputting Dout to the outside of the storage device 480. The data output from the output circuit 448 is the signal RDA.

[0411] PSW 471 has the function of controlling the supply of VDD to the peripheral circuit 422. PSW 472 has the function of controlling the supply of VHM to the row driver 443. Here, the high power supply potential of the storage device 480 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW 471 is controlled by signal PON1, and the on / off state of PSW 472 is controlled by signal PON2. In Figure 20, the number of power supply domains to which VDD is supplied in the peripheral circuit 422 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0412] The element layers 430[1] to 430[m] can be layered on top of layer 420. Figure 21A shows a perspective view of a memory device 480 in which five layers (m=5) of element layers 430[1] to 430[5] are layered on top of layer 420.

[0413] In Figure 21A, the element layer 430 provided as the first layer is shown as element layer 430[1], the element layer 430 provided as the second layer is shown as element layer 430[2], and the element layer 430 provided as the fifth layer is shown as element layer 430[5]. Also in Figure 21A, wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the drive circuit is provided) are shown. Wiring BLB is an inverting bit line. Note that, in order to make the drawing easier to read, some of the wiring WL and wiring PL of each element layer 430 have been omitted from the description.

[0414] Figure 21B shows a schematic diagram illustrating an example configuration of the wiring BL and sense amplifier 446 connected to the wiring BLB shown in Figure 21A, and the memory cells 432 having element layers 430[1] to 430[5] connected to the wiring BL and wiring BLB. A configuration in which multiple memory cells (memory cells 432) are electrically connected to one wiring BL and wiring BLB is also called a "memory string".

[0415] Figure 21B illustrates an example of the circuit configuration of a memory cell 432 connected to wiring BLB. The memory cell 432 has a transistor 437 and a capacitive element 438. The transistor 437, the capacitive element 438, and each wiring (BL, WL, etc.) may also be referred to as wiring BL[1] and wiring WL[1], for example, wiring BL and wiring WL.

[0416] In the memory cell 432, either the source or drain of transistor 437 is connected to wiring BL. The other source or drain of transistor 437 is connected to one electrode of capacitive element 438. The other electrode of capacitive element 438 is connected to wiring PL. The gate of transistor 437 is connected to wiring WL.

[0417] The wiring PL provides a constant potential to maintain the potential of the capacitive element 438. By connecting multiple wiring PLs together and using them as a single wire, the number of wires can be reduced.

[0418] In one aspect of the present invention, OS transistors are stacked, and wiring that functions as bit lines is arranged perpendicular to the substrate surface on which layer 420 is provided. In addition, the transistors 437 and capacitive elements 438 of the memory cell 432 are arranged in a parallel direction perpendicular to the substrate surface on which layer 420 is provided. By providing each element and each wiring perpendicular to the substrate surface, the length of the wiring between element layers can be shortened, and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent memory capacity and reduced power consumption can be obtained.

[0419] [Example Configuration of Memory Cell 432 and Sense Amplifier 446] Figures 22A and 22B show the circuit diagram corresponding to the memory cell 432 described above, and the circuit block diagram corresponding to the said circuit diagram. As shown in Figures 22A and 22B, the memory cell 432 may be represented as a block in drawings, etc. Note that the wiring BL shown in Figures 22A and 22B can be similarly represented when replaced with wiring BLB.

[0420] Furthermore, Figures 22C and 22D show the circuit diagram corresponding to the sense amplifier 446 described above, and the circuit block diagram corresponding to said circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplification circuit 485. In addition to wiring BL and wiring BLB, wiring SA_OUT and wiring SA_OUTB, which output the readout signal, are also shown.

[0421] As shown in Figure 22C, the switch circuit 482 includes, for example, an N-type transistor 482_1 and an N-type transistor 482_2. The N-type transistors 482_1 and 482_2 switch the conduction state of the wiring pair SA_OUT, SA_OUTB and the wiring pair BL, BLB in response to the signal CSEL.

[0422] As shown in Figure 22C, the pre-charge circuit 483 is composed of N-type transistors 483_1 to 483_3. The pre-charge circuit 483 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQ.

[0423] As shown in Figure 22C, the pre-charge circuit 484 is composed of P-type transistors 484_1 to 484_3. The pre-charge circuit 484 is a circuit for pre-charging wiring BL and wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2, in accordance with the signal EQB.

[0424] As shown in Figure 22C, the amplification circuit 485 consists of P-type transistors 485_1, 485_2, N-type transistors 485_3, and 485_4, which are connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is wiring that has the function of providing VDD or VSS. P-type transistors 485_1, 485_2, 485_3, and 485_4 are transistors that constitute an inverter loop.

[0425] Furthermore, Figure 22D shows a circuit block diagram corresponding to the sense amplifier 446 described in Figure 22C, etc. As shown in Figure 22D, the sense amplifier 446 may be represented as a block in drawings, etc.

[0426] Figure 23 is a circuit diagram of the storage device 480 shown in Figure 20. Figure 23 illustrates the circuit blocks described in Figures 22A to 22D.

[0427] As shown in Figure 23, the layer 470, which includes the element layer 430 [m], has memory cells 432. The memory cells 432 shown in Figure 23 are connected, for example, to a pair of wiring BL[1] and wiring BLB[1], or wiring BL[2] and wiring BLB[2]. The memory cells 432 connected to wiring BL are memory cells on which data is written or read.

[0428] Wiring BL[1] and wiring BLB[1] are connected to sense amplifier 446[1], and wiring BL[2] and wiring BLB[2] are connected to sense amplifier 446[2]. Sense amplifiers 446[1] and 446[2] can read data according to the various signals described in Figure 22C.

[0429] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0430] (Embodiment 5) This embodiment describes an example of the configuration of a display device to which a transistor according to one aspect of the present invention can be applied.

[0431] Since the transistor according to one aspect of the present invention can be made extremely small, a display device to which the transistor according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, the display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as VR devices such as head-mounted displays and AR devices such as glasses.

[0432] In one embodiment of the present invention, a display device can be provided with a drive circuit and a pixel circuit stacked on top of each other. In this case, the transistors constituting the pixels can be transistors in which channels are formed in a single-crystal oxide semiconductor, as exemplified in Embodiment 2.

[0433] [Display Module] Figure 24A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590.

[0434] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0435] Figure 24B shows a schematic perspective view illustrating the configuration of the substrate 591. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586, which is composed of multiple wires.

[0436] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 24B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0437] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0438] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0439] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0440] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are superimposed on the lower side of the pixel section 584, thereby making the aperture ratio (effective display area ratio) of the display section 581 extremely high. For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that the pixels 584a in the display section 581 are arranged at a density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0441] Because such a display module 580 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as wristwatches.

[0442] [Display device 500A] The display device 500A shown in Figure 25 has a substrate 301, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 540, a transistor 310, and a transistor 320.

[0443] Transistor 310 is a transistor in which a channel is formed on a single-crystal substrate. Transistor 320 can be a transistor in which a channel is formed on a single-crystal oxide semiconductor, as exemplified in Embodiment 2.

[0444] The transistor 310 is a transistor having a channel-forming region in the substrate 301. The substrate 301 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 310 comprises a portion of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region of the substrate 301 doped with impurities and functions as either a source or a drain. The insulating layer 314 is provided covering the side surface of the conductive layer 311.

[0445] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0446] The transistor 320 has a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 356, and a conductive layer 357.

[0447] An insulating layer 352 is provided on the layer on which the transistor 310 is located, via a wiring layer 316 and an interlayer insulating layer. The insulating layer 352 functions as a barrier layer to prevent impurities from diffusing from the substrate 301 side to the transistor 320, and to prevent oxygen from detaching from the semiconductor layer 351 to the insulating layer 352 side. As the insulating layer 352, for example, a film that is less permeable to hydrogen or oxygen than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0448] A conductive layer 357 is provided on an insulating layer 352, and an insulating layer 356 is provided covering the conductive layer 357. The conductive layer 357 functions as the second gate electrode of the transistor 320, and a portion of the insulating layer 356 functions as the second gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, in at least the region of the insulating layer 356 that is in contact with the semiconductor layer 351. It is preferable that the upper surface of the insulating layer 356 is flattened.

[0449] The semiconductor layer 351 is provided on the insulating layer 356. Preferably, the semiconductor layer 351 has a metal oxide (also called an oxide semiconductor) film that exhibits semiconductor properties. A pair of conductive layers 355 are provided in contact with the semiconductor layer 351 and function as a source electrode and a drain electrode.

[0450] An insulating layer 358 and an insulating layer 350 are provided to cover the top and side surfaces of the pair of conductive layers 355, as well as the side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and to prevent oxygen from detaching from the semiconductor layer 351. An insulating film similar to that used for the insulating layer 352 can be used for the insulating layer 358.

[0451] The insulating layer 358 and the insulating layer 350 are provided with openings that reach the semiconductor layer 351. An insulating layer 353 in contact with the upper surface of the semiconductor layer 351 and a conductive layer 354 are embedded inside these openings. The conductive layer 354 functions as a first gate electrode, and the insulating layer 353 functions as a first gate insulating layer.

[0452] The upper surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are flattened so that their heights are the same, and an insulating layer 359 is provided covering them. The insulating layer 359 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 320. An insulating film similar to that used for the insulating layer 352 can be used for the insulating layer 359.

[0453] The transistor 320 employs a configuration in which a semiconductor layer on which a channel is formed is sandwiched between two gates. The transistor may be driven by connecting the two gates and supplying them with the same signal. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential to control the threshold voltage to one of the two gates and a potential to drive the other gate.

[0454] An insulating layer 564 is provided on the insulating layer 359. The insulating layer 564 functions as an interlayer insulating layer.

[0455] The plug 574, which is electrically connected to one side of the conductive layer 355, is provided so as to be embedded in the insulating layer 564, insulating layer 359, insulating layer 350, and insulating layer 358. Here, it is preferable that the plug 574 has a conductive layer 574a that covers the side surface of the opening in the insulating layer 564, etc., and a part of the upper surface of the conductive layer 355, and a conductive layer 574b that is in contact with the upper surface of the conductive layer 574a. In this case, it is preferable to use a conductive material that does not easily allow oxygen to diffuse as the conductive layer 574a.

[0456] Furthermore, a capacitor 540 is provided on the insulating layer 564. The capacitor 540 has a conductive layer 541, a conductive layer 545, and an insulating layer 543 located between them. The conductive layer 541 functions as one electrode of the capacitor 540, the conductive layer 545 functions as the other electrode of the capacitor 540, and the insulating layer 543 functions as the dielectric of the capacitor 540.

[0457] The conductive layer 541 is embedded in an insulating layer 554 provided on an insulating layer 564. The conductive layer 541 is electrically connected to the conductive layer 355 of the transistor 320 by a plug 574. The insulating layer 543 is provided covering the conductive layer 541. The conductive layer 545 is provided in the region that overlaps with the conductive layer 541 via the insulating layer 543.

[0458] An insulating layer 555a is provided covering the capacitance 540, an insulating layer 555b is provided on top of the insulating layer 555a, and an insulating layer 555c is provided on top of the insulating layer 555b.

[0459] Insulating layers 555a, 555b, and 555c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 555a and 555c, and silicon nitride films for insulating layer 555b. This allows insulating layer 555b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 555c is etched and a recess is formed, but the insulating layer 555c does not necessarily have to have a recess.

[0460] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 555c.

[0461] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting elements 110R, 110G, and 110B.

[0462] The organic layer 112R of the light-emitting element 110R contains at least a luminescent organic compound that emits red light. The organic layer 112G of the light-emitting element 110G contains at least a luminescent organic compound that emits green light. The organic layer 112B of the light-emitting element 110B contains at least a luminescent organic compound that emits blue light. The organic layers 112R, 112G, and 112B can each also be called EL layers and each contains at least a luminescent substance (luminescent layer).

[0463] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 112R, 112G, and 112B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0464] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0465] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 355 of the transistor 320 by plugs 556 embedded in insulating layers 555a, 555b, and 555c, a conductive layer 541 embedded in insulating layer 554, and plugs 574. The height of the upper surface of insulating layer 555c and the height of the upper surface of plug 556 are the same. Various conductive materials can be used for the plugs.

[0466] Furthermore, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. The substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0467] There is no insulating layer covering the upper edge of the pixel electrode 111 between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0468] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0469] (Embodiment 6) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 26A to 28G.

[0470] The electronic device of this embodiment has a display panel (display device) to which a transistor according to one aspect of the present invention is applied in the display unit. The display device according to one aspect of the present invention can be easily made high-definition and high-resolution, and can achieve high display quality. Therefore, it can be used in the display unit of various electronic devices.

[0471] Examples of electronic devices include television sets, desktop or laptop computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0472] In particular, a display panel according to one embodiment of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0473] A display panel according to one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display panel according to one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display panel having either high resolution or high detail, or both, it becomes possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display panel in one embodiment of the present invention. For example, the display panel can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0474] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0475] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0476] Figures 26A to 26D illustrate an example of a wearable device that can be worn on the head. These wearable devices have one or both functions: the ability to display AR content and / or VR content. In addition to AR and VR, these wearable devices may also have functions to display SR or MR content. By having an electronic device that has the ability to display at least one of the following content types, such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0477] The electronic device 700A shown in Figure 26A and the electronic device 700B shown in Figure 26B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0478] A display panel according to one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created.

[0479] Electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical element 753. Because the optical element 753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 753. Therefore, electronic devices 700A and 700B are electronic devices capable of AR display.

[0480] Electronic devices 700A and 700B may be equipped with cameras capable of capturing images of the area in front of them as imaging units. Furthermore, electronic devices 700A and 700B may each be equipped with acceleration sensors such as gyro sensors to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.

[0481] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0482] Furthermore, electronic devices 700A and 700B are equipped with batteries (not shown) that can be charged wirelessly, wired, or both.

[0483] The housing 721 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0484] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0485] When using an optical touch sensor, a photoelectric conversion device (also called a photoelectric element) can be used as the light-receiving device (also called a photoelectric element). The active layer of the photoelectric conversion device can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0486] The electronic device 800A shown in Figure 26C and the electronic device 800B shown in Figure 26D each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0487] A display panel according to one embodiment of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0488] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can be achieved.

[0489] Electronic devices 800A and 800B can each be described as electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0490] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0491] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 26C and other figures as resembling the temples (or arms) of eyeglasses, it is not limited to this. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0492] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0493] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0494] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This allows users to enjoy video and audio simply by wearing the electronic device 800A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0495] Electronic devices 800A and 800B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided in the electronic devices.

[0496] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 26A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 26C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0497] Furthermore, the electronic device may have an earphone section. The electronic device 700B shown in Figure 26B has an earphone section 727. For example, the earphone section 727 and the control unit can be connected to each other by wire. Part of the wiring connecting the earphone section 727 and the control unit may be located inside the housing 721 or the mounting section 723.

[0498] Similarly, the electronic device 800B shown in Figure 26D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have magnets. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it facilitates storage.

[0499] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0500] Thus, as one embodiment of the present invention, both eyeglass-type (electronic devices 700A and 700B, etc.) and goggle-type (electronic devices 800A and 800B, etc.) are preferred as electronic devices.

[0501] The electronic device 6500 shown in Figure 27A is a portable information terminal that can be used as a smartphone.

[0502] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The display unit 6502 has a touch panel function. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 6502, the control device 6509, etc. Using a semiconductor device according to one aspect of the present invention as the control device 6509 is preferable because it can reduce power consumption.

[0503] A display panel according to one embodiment of the present invention can be applied to the display unit 6502.

[0504] Figure 27B is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0505] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0506] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0507] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0508] A display device according to one embodiment of the present invention can be applied to the display panel 6511. As a result, an extremely lightweight electronic device can be realized. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel section, an electronic device with a narrow bezel can be realized.

[0509] Figure 27C shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown to be supported by a stand 7103.

[0510] The television device 7100 shown in Figure 27C can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0511] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0512] Figure 27D shows an example of a notebook computer. The notebook computer 7200 includes a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is incorporated into the casing 7211. The control device 7216 has one or more components selected from, for example, a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 7000, the control device 7216, etc. Using a semiconductor device according to one aspect of the present invention as the control device 7216 is preferable because it can reduce power consumption.

[0513] Figures 27E and 27F show examples of digital signage.

[0514] The digital signage 7300 shown in Figure 27E includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0515] Figure 27F shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0516] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0517] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0518] Furthermore, as shown in Figures 27E and 27F, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. Also, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0519] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0520] In Figures 27C to 27F, a display panel according to one embodiment of the present invention can be applied to the display unit 7000.

[0521] The electronic device shown in Figures 28A to 28G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, a sensor 9007 (including a function to detect, identify, or measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, and the like.

[0522] The electronic devices shown in Figures 28A to 28G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0523] Details of the electronic equipment shown in Figures 28A to 28G will be explained below.

[0524] Figure 28A is a perspective view showing a personal digital information terminal (PDI) 9101. The PDI 9101 can be used, for example, as a smartphone. The PDI 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. Furthermore, the PDI 9101 can display text and image information on multiple surfaces. Figure 28A shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, and phone calls, the subject of an email or SNS message, the sender's name, date and time, battery level, and signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0525] Figure 28B is a perspective view showing a personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0526] Figure 28C is a perspective view showing the tablet terminal 9103. The tablet terminal 9103 can run various applications, such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000. The left side of the housing 9000 has operation keys 9005 as buttons for operation, and the bottom has connection terminals 9006.

[0527] Figure 28D is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. The charging operation may be performed by wireless power supply.

[0528] Figures 28E to 28G are perspective views showing a foldable portable information terminal 9201. Figure 28E shows the portable information terminal 9201 in an unfolded state, Figure 28G shows it in a folded state, and Figure 28F shows a perspective view of the state in between, transitioning from one of Figures 28E or 28G to the other. The portable information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm to 150 mm.

[0529] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0530] (Embodiment 7) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention. A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as Data Centers: DCs). Electronic components, electronic devices, large computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective in achieving high performance, such as low power consumption.

[0531] Electronic components and the like to which a semiconductor device according to one embodiment of the present invention is applied can be applied to the electronic device exemplified in Embodiment 6.

[0532] [Electronic Components] Figure 29A shows a perspective view of a substrate (mounted substrate 704) on which electronic components 700 are mounted. The electronic component 700 shown in Figure 29A has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 29A to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 via a wire 714. The electronic component 700 is mounted on a printed circuit board 702, for example. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted substrate 704.

[0533] Furthermore, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 715 and the storage layer 716 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the storage layer 716, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0534] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0535] Furthermore, it is preferable to form the multiple memory cell arrays in the memory layer 716 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 716, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0536] Furthermore, the semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0537] Next, a perspective view of the electronic component 730 is shown in Figure 29B. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0538] Electronic component 730 shows an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs (Graphics Processing Units), or FPGAs (Field Programmable Gate Arrays).

[0539] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0540] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0541] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0542] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0543] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0544] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 735.

[0545] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 29B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0546] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0547] [Large-scale computer] Figure 30A shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 houses multiple rack-mount type computers 5620 in rack 5610. The large-scale computer 5600 may also be referred to as a supercomputer.

[0548] Figure 30B shows a perspective view of an example of the computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0549] Figure 30C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, GPU, and memory device. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic component 5626, electronic component 5627, electronic component 5628, and connection terminal 5629 mounted on the board 5622. Note that Figure 30C shows components other than electronic component 5626, electronic component 5627, and electronic component 5628.

[0550] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0551] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0552] The electronic component 5626 has terminals (not shown) for inputting and outputting signals, and by inserting these terminals into a socket (not shown) on the board 5622, the electronic component 5626 and the board 5622 can be electrically connected.

[0553] Electronic components 5627 and 5628 have multiple terminals, and these terminals can be mounted to the wiring provided on board 5622 by, for example, reflow soldering. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. For example, electronic component 730 can be used as electronic component 5627. Examples of electronic component 5628 include memory devices. For example, electronic component 700 can be used as electronic component 5628.

[0554] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0555] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0556] (Embodiment 8) A semiconductor device according to one aspect of the present invention will be described. Figure 31A is a schematic perspective view of a semiconductor device 10 according to one aspect of the present invention. Figure 31B is a schematic perspective view of a part of the semiconductor device 10. Figure 32 is a schematic perspective view illustrating the configuration of the semiconductor device 10.

[0557] In Figures 31A, 31B, and 32, the semiconductor device 10 has an element layer 70 below an element layer 80 which includes a substrate 22 that is a semiconductor substrate, and a support substrate 40 above the element layer 80 via an insulating layer 41. The element layer 80 has a plurality of transistors 21 which constitute a functional circuit 11. The element layer 70 has a plurality of transistors 71 which constitute a switch circuit 15. The transistors 71 function as switches to control the conduction and non-conductivity between an external power supply line and a conductive layer 72 which functions as a power line.

[0558] The transistor exemplified in Embodiment 1 can be used for transistor 71.

[0559] The transistor 21 in the element layer 80 is formed on the front surface (also called the "first surface") of the substrate 22. The element layer 70 is formed on the back surface (the surface opposite to the front surface, also called the "second surface") of the substrate 22. Therefore, the transistor 71 in the element layer 70 is formed on the second surface of the substrate 22.

[0560] Figure 32 illustrates a functional circuit 11 consisting of a CPU 12, a GPU 13, and a memory 14.

[0561] Furthermore, the functional circuit 11 is not limited to the CPU 12, GPU 13, and memory 14, and one or more of these can be used. It is also possible to include circuits with other functions.

[0562] To improve the operating speed, mounting density, and power consumption of the semiconductor device 10, the functional circuit 11 requires miniaturization and thinning of transistors, wiring, etc., and reduction of the power supply potential. The switch circuit 15 can control the supply of voltage supplied from an external source to each circuit of the functional circuit 11, and to stop the supply. This makes it possible to stop the supply of power potential to circuits in standby mode, thereby reducing power consumption.

[0563] Furthermore, the transistors constituting the switch circuit 15 require high dielectric strength. One effective way to increase the dielectric strength of the transistors is to thicken the gate insulating film. Thus, transistors 21 and 71 require different performance characteristics. Therefore, different measures are needed to improve the characteristics of transistors 21 and 71.

[0564] Furthermore, miniaturization and thinning are required for the functional circuit 11. Therefore, if the switch circuit 15 is constructed using the same process node as the functional circuit 11, not only the routing wiring but also the wiring for supplying power (power lines) will become thinner, making it impossible to supply sufficient power to the functional circuit 11. In addition, if the wiring resistance increases due to miniaturization, voltage drop is likely to cause unevenness in the power supply potential within the functional circuit 11. To stably supply power to the functional circuit 11, it is preferable that the wiring constituting the switch circuit 15 has a lower wiring resistance than the wiring constituting the functional circuit 11. In particular, it is preferable that the wiring that functions as a power line has a lower wiring resistance than the wiring constituting the functional circuit 11. One means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, in order to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase one or both of the width and height of the conductive layer. Thus, it is preferable to use different process nodes for the functional circuit 11 and the switch circuit 15.

[0565] In a semiconductor device 10 according to one aspect of the present invention, by providing the functional circuit 11 and the switch circuit 15 on different element layers, different improvement measures can be implemented in the functional circuit 11 and the switch circuit 15. Furthermore, the functional circuit 11 and the switch circuit 15 can be formed at different process nodes.

[0566] In one aspect of the present invention, a plurality of conductive layers 72 that function as power lines and a switch circuit 15 can be arranged below the functional circuit 11, thereby reducing the occupied area of ​​the semiconductor device 10. Furthermore, it is preferable that the element layer 70, which is superimposed on the element layer 80, is formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 71 included in the element layer 70 is preferably a thin-film transistor.

[0567] At least a portion of the multiple conductive layers 72 of the element layer 70 can function as power lines. Furthermore, if the element layer 70 has a clock signal generation circuit, at least a portion of the multiple conductive layers 72 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 11 of the element layer 80 via at least a portion of the multiple conductive layers 72.

[0568] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 11 and a die containing the switch circuit 15 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving the alignment accuracy is difficult because the two are bonded together mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary parts of the functional circuit 11.

[0569] According to one aspect of the present invention, an element layer 70 including a switch circuit 15 is formed on the back side of the substrate 22 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 10 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0570] By forming the element layer 70 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 11 over extremely short distances. Therefore, the necessary voltage of power can be supplied to the necessary locations of the functional circuit 11. In addition, in the semiconductor device 10 according to one aspect of the present invention, since the connection distance between the switch circuit 15 and the functional circuit 11 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0571] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0572] In this embodiment, the energy required to desorb oxygen was estimated in a layer applicable to a semiconductor layer, an insulating layer, or a mixed layer of a semiconductor layer and an insulating layer in a semiconductor device according to one aspect of the present invention. It is believed that the greater the energy required to desorb oxygen, the less likely oxygen vacancies are to form.

[0573] [Energy Calculation] The energy required to remove oxygen from indium oxide, indium oxide containing gallium, and gallium oxide was calculated.

[0574] First, using molecular dynamics, the melt-quench calculation was performed, In ２ O ３ and In ３１ Ga １ O ４８ Models of the amorphous structures were created for each. QuantumATK, an atomic-scale simulation software from Synopsys, was used for the calculations. The machine learning potential force field (QuantumATK_MTP_InGaZnOH_2023_09) built into QuantumATK was used for the force field. After annealing with an NVT ensemble for 50 ps at 2000 K, quenching was performed with an NPT ensemble for 500 ps at a cooling rate of -3.4 K / ps and a pressure of 1 bar.

[0575] Next, first-principles calculations were performed to optimize the structure (also known as optimization calculations). These optimization calculations focused on optimizing the size and shape of the cells, as well as the arrangement of atoms within them.

[0576] Indium oxide has a bixbite structure. ２ O ３ A crystalline model and amorphous In ２ O ３ Calculations were performed on the amorphous structure model. Figure 33A shows amorphous In ２ O ３ The model is shown below. Each cell contains 32 In cells and 48 O cells.

[0577] Indium oxide containing gallium was prepared using molecular dynamics.３１ Ga １ O ４８ Calculations were performed on the model. Figure 33B shows amorphous In ３１ Ga １ O ４８ The model is shown below. Each cell contains 31 In, 1 Ga, and 48 O.

[0578] Gallium oxide is β-Ga ２ O ３ We performed calculations on the crystal model.

[0579] For this optimization calculation, the VASP (Vienna ab-initio simulation package), a plane wave basis first-principles calculation software based on density functional theory, was used. The potential generated by the Projector Augmented Wave (PAW) method was used for the electronic state pseudopotential, and the GGA-PBE (Generalized-Gradient-Approximation-Perdew-Burke-Ernzerhof) functional was used. Furthermore, the calculation was performed to satisfy a density of 0.03 / Å at the k-point. The plane wave cutoff energy was set to 600 eV.

[0580] Optimized amorphous In ２ O ３ The amorphous structure model showed that it has oxygen coordinated with four inions (four-coordinate oxygen) and oxygen coordinated with three inions (three-coordinate oxygen). ３１ Ga １ O ４８ The amorphous structure model showed that it has oxygen coordinated with one Ga and three In (four-coordinate oxygen) and oxygen coordinated with one Ga and two In (three-coordinate oxygen).

[0581] Next, optimization calculations were performed for the structures of indium oxide (crystalline and amorphous), indium oxide containing gallium (amorphous), and gallium oxide (crystalline) after oxygen was removed. These optimization calculations were performed using the first-principles calculation method described above.

[0582] The structures used in the calculations are shown in Figures 33A and 33B. Figure 33A shows amorphous In ２ O３ The model is shown, and Figure 33B shows amorphous In ３１ Ga １ O ４８ The model is shown. Note that amorphous In ２ O ３ In this model, four In atoms are coordinated with O (specifically, V shown in Figure 33A). ｏ When O at position 1 is detached, and O coordinated with three In (specifically V shown in Figure 33A) ｏ Optimization calculations were performed for the case where O) at position 2 is removed. Furthermore, amorphous In ３１ Ga １ O ４８ In this model, one Ga and three In are coordinated with O (specifically, V shown in Figure 33B). ｏ When the O at position 3 is detached, and the O (specifically, the V shown in Figure 33B) that is coordinated with one Ga and two In atoms ｏ An optimization calculation was performed for the case where O) at position 4 is removed.

[0583] Next, according to equation (1) below, the energy E required to remove oxygen (O) is... ＶＯ The calculation was performed. The large amount of energy required to remove oxygen indicates that the energy required to form an oxygen vacancy is large, and the energy E ＶＯ The larger the value, the less likely it is that oxygen deficiency will form. The energy E shown in equation (1) ａ E' is the total energy of the model optimized for the structure before oxygen desorption. ａ μ is the total energy of the model optimized for the structure after oxygen desorption, where μ is the energy. ０ This represents the chemical potential of oxygen. The chemical potential of oxygen is assumed to be 0.5 times the energy of the oxygen molecule.

[0584] E ＶＯ = E' ａ +μ ０ -E ａ (1)

[0585] Energy E calculated for each structure ＶＯ This is shown in Figure 34.

[0586] As shown in Figure 34, the energy E ＶＯ is amorphous In ２ O ３ In V ｏ When removing O at position 1 (described as a_IO_Vo1) and V ｏ When the O at position 2 was detached (indicated as a_IO_Vo2), the values ​​were 3.23 eV and 3.60 eV, respectively. ｏ The average bond distance between O at position 1 and the four In atoms is 2.19 Å, V ｏ The average bond distance between the oxygen atom at position 2 and the three in molecules was 2.17 Å.

[0587] Also, as shown in Figure 34, the energy E ＶＯ is amorphous In ３１ Ga １ O ４８ In V ｏ When removing O at position 3 (indicated as a_IGO_Vo3) and V ｏ When the O at position 4 was detached (indicated as a_IGO_Vo4), the values ​​were 3.80 eV and 3.81 eV, respectively. ｏ The bond distance between O at position 3 and Ga is 1.91 Å, V ｏ The bond distance between O at position 4 and Ga was 1.90 Å.

[0588] Also, as shown in Figure 34, the energy E ＶＯ In ２ O ３ The crystalline sample (denoted as c_IO) had a voltage of 3.27 eV. The bond distance between In and O was 2.18 Å.

[0589] Also, as shown in Figure 34, the energy E ＶＯ Ga ２ O ３ The crystalline sample (denoted as c_GO) had a voltage of 3.76 eV. The bond distance between Ga and the oxygen atom tetrahedral to Ga was 1.87 Å.

[0590] As shown in Figure 34, amorphous In ３１ Ga １ O ４８ (V ｏ 3 or V ｏ (When removing O at position 4) and Ga２ O ３ Crystal energy E ＶＯ is amorphous In ２ O ３ (V ｏ 1 or V ｏ (When removing O at position 2) and In ２ O ３ Crystal energy E ＶＯ This result was significantly larger compared to the previous result. Furthermore, the bond distance between Ga and O was calculated to be shorter than the bond distance between In and O.

[0591] Considering the results described above, it is suggested that the formation of oxygen vacancies within a layer composed of gallium-doped indium oxide, or a layer containing gallium-doped indium oxide, is suppressed. It can also be expressed as suggesting that adding gallium to indium oxide suppresses the formation of oxygen vacancies. Furthermore, it is suggested that gallium oxide is a material that is less prone to oxygen vacancy formation compared to indium oxide.

[0592] The results described above can be applied to and considered, for example, the semiconductor layer 30, insulating layer 51, insulating layer 50, mixed layer of semiconductor layer 30 and insulating layer 51, mixed layer of semiconductor layer 30 and insulating layer 50, etc., as shown in Figures 1A to 5F of Embodiment 1. Furthermore, the results can be applied to and considered, for example, the semiconductor layer 230, insulating layer 201, insulating layer 250, mixed layer of semiconductor layer 230 and insulating layer 201, mixed layer of semiconductor layer 230 and insulating layer 250, etc., of the transistor shown in Embodiment 2.

[0593] As an example, applying the above results to the semiconductor layer 30 suggests that the presence of gallium as the first element in the semiconductor layer 30 suppresses the formation of oxygen vacancies in the semiconductor layer 30.

[0594] Furthermore, if the semiconductor layer 30 consists of three layers, at least one of semiconductor layer 30_1 and semiconductor layer 30_3 contains gallium as the first element, which may suppress the formation of oxygen vacancies in semiconductor layer 30_2 sandwiched between these layers. For example, since semiconductor layer 30_1 and semiconductor layer 30_3 are layers with few oxygen vacancies, oxygen can be supplied to semiconductor layer 30_2 more efficiently. In addition, an amorphous indium oxide layer containing gallium may have excellent oxygen barrier properties. Therefore, it may be possible to suppress the diffusion of oxygen from semiconductor layer 30_2 to the layers above and below it. As a result, semiconductor layer 30_2 can be made into a layer with few oxygen vacancies.

[0595] As another example, if we apply the above results to a mixed layer of semiconductor layer 30 and insulating layer 51, and consider that the insulating layer 51 contains gallium and the semiconductor layer 30 contains indium and oxygen, a gallium-doped indium oxide layer can be formed as a mixed layer between the semiconductor layer 30 (semiconductor layer 30_1 if there are three semiconductor layers 30) and the insulating layer 51. In this mixed layer, for example, it is suggested that the formation of oxygen vacancies is suppressed. Similarly, if the insulating layer 50 contains gallium and the semiconductor layer 30 contains indium and oxygen, a gallium-doped indium oxide layer can be formed as a mixed layer between the semiconductor layer 30 (semiconductor layer 30_3 if there are three semiconductor layers 30) and the insulating layer 50. In this mixed layer, for example, it is suggested that the formation of oxygen vacancies is suppressed. When the mixed layer is formed thickly, it may be possible to observe the mixed layer by cross-sectional observation using an electron microscope and elemental analysis. When the mixed layer is thin, it may not be clearly observed by cross-sectional observation, etc.

[0596] Furthermore, it is thought that oxygen vacancies occur in the semiconductor layer 30, for example, at the interface with the upper layer or the interface with the lower layer, causing the oxygen supplied to the semiconductor layer 30 to be consumed by these oxygen vacancies at the interface. By configuring the semiconductor layer 30 so that at least one of its upper and lower surfaces is in contact with the aforementioned mixed layer, vacancies at the interface with the upper layer or the interface with the lower layer can be reduced, and oxygen can be supplied to the semiconductor layer 30 more efficiently.

[0597] Furthermore, the aforementioned mixed layer may have excellent oxygen barrier properties. Therefore, by providing the mixed layer above and below the semiconductor layer 30, it may be possible to suppress the diffusion of oxygen from the semiconductor layer 30 to the layers above and below it. This makes the semiconductor layer 30 a layer with fewer oxygen vacancies.

[0598] As another example, if we apply the above results to insulating layer 51 and insulating layer 50 and consider the results, it is suggested that when gallium oxide is used as insulating layer 51 and insulating layer 50, the formation of oxygen vacancies in the insulating layer is suppressed.

[0599] This embodiment can be implemented in appropriate combination with at least a portion of the embodiments described herein.

[0600] ADDR: signal, BL[1]: wiring, BL[2]: wiring, BL[j]: wiring, BL[n]: wiring, BL: wiring, BLB[1]: wiring, BLB[2]: wiring, BLB: wiring, BW: signal, CE: signal, CLK: signal, CSEL: signal, EQ: signal, EQB: signal, GW: signal, PL[1]: Wiring, PL[i]: Wiring, PL[m]: Wiring, PL: Wiring, RDA: Signal, SA_OUT: Wiring, SA_OUTB: Wiring, SAN: Wiring, SAP: Wiring, VPRE: Intermediate potential, WAKE: Signal, WDA: Signal, WL[1]: Wiring, WL[i]: Wiring, WL[m]: Wiring, WL: Wiring, 10: Semiconductor equipment, 11: Functional circuit, 12: CPU, 13: GPU, 14: Memory, 15: Switch circuit, 20: Substrate, 21: Transistor, 22: Substrate, 25: Conductive layer, 30: Semiconductor layer, 30_1: Semiconductor layer, 30_2: Semiconductor layer, 30_3: Semiconductor layer, 40: Support substrate, 41: Insulating layer, 50: Insulating layer, 50_1: Insulating layer, 50_2: Insulating layer, 50_2a: Insulating layer, 50_2b: Insulating layer, 50_2c: Insulating layer, 51: Insulating layer, 51_1: Insulating layer, 51_2: Insulating layer, 51_2a: Insulating layer, 51_2b: Insulating layer, 51_2c: Insulating layer 52: insulating layer, 60: conductive layer, 70: element layer, 71: transistor, 72: conductive layer, 80: element layer, 110B: light-emitting element, 110G: light-emitting element, 110R: light-emitting element, 111: pixel electrode, 111B: pixel electrode, 111G: pixel electrode, 111R: pixel electrode, 112B: organic layer, 112G: organic layer, 112R: organic layer, 113: common electrode, 114: common layer, 121: protective layer, 125: insulating layer, 126: resin layer, 128: layer, 170: substrate, 171: adhesive layer, 200: transistor, 200a: transistor, 200b: transistor, 200c: transistor Zista, 201: insulating layer, 201_1: insulating layer, 201_2a: insulating layer, 201_2b: insulating layer, 201_2c: insulating layer, 202: insulating layer, 205: conductive layer, 210: substrate, 211: insulating layer, 230: semiconductor layer, 230_1: semiconductor layer, 230_2: semiconductor layer, 230_3: semiconductor layer, 230a: region, 230b: region, 230c: region, 230n: region, 241a: insulating layer, 241b: insulating layer, 242a: conductive layer, 242b: conductive layer, 243a: conductive layer, 243b: conductive layer, 245: conductive layer, 246: conductive layer, 250: insulating layer, 250_1: insulating layer,250_2a: insulating layer, 250_2b: insulating layer, 250_2c: insulating layer, 255: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 271a: insulating layer, 271b: insulating layer, 275: insulating layer, 280: insulating layer, 281: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 285: insulating layer, 290o: opening, 290s: opening, 301: substrate, 310: transistor, 311: conductive layer, 312: low resistance region, 313: insulating layer, 314: insulating layer, 315: element isolation layer, 316: wiring layer, 320: transistor, 350: insulating layer, 35 1: Semiconductor layer, 352: Insulating layer, 353: Insulating layer, 354: Conductive layer, 355: Conductive layer, 356: Insulating layer, 357: Conductive layer, 358: Insulating layer, 359: Insulating layer, 420: Layer, 422: Peripheral circuit, 430: Element layer, 432: Memory cell, 437: Transistor, 438: Capacitive element, 440: Drive circuit, 442: Row decoder, 443: Row driver, 444: Column decoder, 445: Column driver, 446[1]: Sense amplifier, 446[2]: Sense amplifier, 446: Sense amplifier, 447: Input circuit, 448: Output circuit, 470: Layer, 471: PSW, 472: PS W, 473: Control circuit, 474: Voltage generation circuit, 480: Memory device, 482: Switch circuit, 482_1: N-type transistor, 482_2: N-type transistor, 483: Pre-charge circuit, 483_1: N-type transistor, 483_3: N-type transistor, 484: Pre-charge circuit, 484_1: P-type transistor, 484_3: P-type transistor, 485: Amplifier circuit, 485_1: P-type transistor, 485_2: P-type transistor, 485_3: N-type transistor, 485_4: N-type transistor, 500A: Display device, 540: Capacitance, 54 1: conductive layer, 543: insulating layer, 545: conductive layer, 554: insulating layer, 555a: insulating layer, 555b: insulating layer, 555c: insulating layer, 556: plug, 564: insulating layer, 574: plug, 574a: conductive layer, 574b: conductive layer, 580: display module, 581: display unit, 582: circuit unit, 583: pixel circuit unit, 583a: pixel circuit, 584: pixel unit, 584a: pixel, 585: terminal unit, 586: wiring unit, 590: FPC, 591: substrate, 592: substrate, 700: electronic component, 700A: electronic equipment, 700B: electronic equipment, 702: printed circuit board, 704: mounted board,710: Semiconductor equipment, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 715: Drive circuit layer, 716: Memory layer, 721: Housing, 723: Mounting part, 727: Earphone part, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor equipment, 750: Earphone, 751: Display panel, 753: Optical component, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic equipment, 800B: Electronic equipment, 820: Display part, 821: Housing, 822: Communication part, 823: Mounting part, 824: Control unit, 825: Imaging unit, 827: Earphone unit, 832: Lens, 5600: Large computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic equipment, 6501: Enclosure, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 65 08: Light source, 6509: Control device, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television device, 7101: Enclosure, 7103: Stand, 7111: Remote control unit, 7200: Notebook computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7216: Control device, 7300: Digital signage, 730 1: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Enclosure, 9001: Display unit, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9103: Tablet terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

The first insulating layer, The semiconductor layer on the first insulating layer, A second insulating layer on the semiconductor layer, The first conductive layer is located on the second insulating layer, The first conductive layer and the semiconductor layer overlap each other with the second insulating layer in between. The first insulating layer comprises a first layer and a second layer on the first layer. The second layer has gallium oxide, The first layer comprises one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The aforementioned second insulating layer comprises a third layer and a fourth layer on the third layer. The third layer comprises gallium oxide, The fourth layer comprises one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The semiconductor device comprises a semiconductor layer containing indium oxide. 　 A first conductive layer and The first insulating layer on the first conductive layer, The semiconductor layer on the first insulating layer, A second insulating layer on the semiconductor layer, The present invention comprises a second conductive layer on the second insulating layer, The first conductive layer and the semiconductor layer overlap each other with the first insulating layer in between. The second conductive layer and the semiconductor layer overlap each other with the second insulating layer in between. The first insulating layer comprises a first layer and a second layer on the first layer. The second layer has gallium oxide, The first layer comprises one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The aforementioned second insulating layer comprises a third layer and a fourth layer on the third layer. The third layer comprises gallium oxide, The fourth layer comprises one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The semiconductor device comprises a semiconductor layer containing indium oxide. 　 A first conductive layer and The first insulating layer on the first conductive layer, The semiconductor layer on the first insulating layer, A second insulating layer on the semiconductor layer, The present invention comprises a second conductive layer on the second insulating layer, The first conductive layer and the semiconductor layer overlap each other with the first insulating layer in between. The second conductive layer and the semiconductor layer overlap each other with the second insulating layer in between. The first insulating layer comprises a first layer, a second layer on the first layer, and a third layer on the second layer. The third layer comprises gallium oxide, The second layer comprises one or both of silicon oxide and hafnium oxide. The first layer has silicon nitride, The second insulating layer comprises a fourth layer, a fifth layer on the fourth layer, and a sixth layer on the fifth layer. The fourth layer has gallium oxide, The fifth layer comprises one or both of silicon oxide and hafnium oxide. The sixth layer has silicon nitride, The semiconductor device comprises a semiconductor layer containing indium oxide. 　 In claim 3, The second layer comprises hafnium oxide, The fifth layer comprises a seventh layer and an eighth layer on the seventh layer. The seventh layer has silicon oxide, A semiconductor device having hafnium oxide as the eighth layer. 　 A first conductive layer and The first insulating layer on the first conductive layer, The semiconductor layer on the first insulating layer, A second insulating layer on the semiconductor layer, The present invention comprises a second conductive layer on the second insulating layer, The first conductive layer and the semiconductor layer overlap each other with the first insulating layer in between. The second conductive layer and the semiconductor layer overlap each other with the second insulating layer in between. The first insulating layer comprises a first layer and a second layer on the first layer. The second layer has gallium oxide, The first layer comprises one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The aforementioned second insulating layer comprises a third layer and a fourth layer on the third layer. The third layer comprises gallium oxide, The fourth layer comprises one or more selected from hafnium oxide, silicon nitride, and silicon oxide. The semiconductor layer comprises a first oxide semiconductor layer, a second oxide semiconductor layer on the first oxide semiconductor layer, and a third oxide semiconductor layer on the second oxide semiconductor layer. The second oxide semiconductor layer contains indium, Each of the first oxide semiconductor layer and the third oxide semiconductor layer comprises indium and gallium, A semiconductor device wherein, in each of the first oxide semiconductor layer and the third oxide semiconductor layer, the ratio of the number of gallium atoms to the sum of the number of indium and gallium atoms is higher than the ratio in the second oxide semiconductor layer. 　 Insulating layer and, The semiconductor layer on the insulating layer, It has a mixed layer, The semiconductor layer comprises indium and oxygen. The insulating layer has an element that has a stronger bonding force with oxygen than indium. The mixed layer is located between the insulating layer and the semiconductor layer. The aforementioned mixed layer comprises indium, oxygen, and the aforementioned element, wherein the semiconductor device is a semiconductor device. 　 In claim 6, The semiconductor device comprises a semiconductor layer having a crystalline portion whose crystal structure is a bixbyte structure. 　 Insulating layer and, The semiconductor layer on the insulating layer, It has a mixed layer, The semiconductor layer comprises indium and oxygen. The insulating layer comprises gallium or aluminum and oxygen. The mixed layer is located between the insulating layer and the semiconductor layer. The aforementioned mixed layer comprises gallium or aluminum, indium, and oxygen, in a semiconductor device. 　 In claim 8, The semiconductor device comprises a semiconductor layer having a crystalline portion whose crystal structure is a bixbyte structure. 　 In claim 7 or claim 9, The aforementioned Bixbite structure is a semiconductor device having strain. 　 Insulating layer and, The first semiconductor layer on the insulating layer, The second semiconductor layer on the first semiconductor layer, A third semiconductor layer on the second semiconductor layer, It has a mixed layer, Each of the first to third semiconductor layers comprises indium and oxygen, The insulating layer has an element that has a stronger bonding force with oxygen than indium. The mixed layer is located between the insulating layer and the first semiconductor layer. The mixed layer comprises indium, oxygen, and the aforementioned element. A semiconductor device wherein the second semiconductor layer has a lower film density than the first semiconductor layer and the third semiconductor layer. 　 In claim 11, The first semiconductor layer has a crystalline portion whose crystal structure is a bixbyte structure. The aforementioned Bixbite structure is a semiconductor device having strain. 　 In claim 11, The second semiconductor layer has a crystalline portion whose crystal structure is a bixbyte structure. The aforementioned Bixbite structure is a semiconductor device having strain. 　 In any one of claims 11 to 13, A semiconductor device in which the sum of the thicknesses of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer is 0.1 nm or more and 30 nm or less.

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