Phase synchronization circuit and semiconductor integrated circuit
The phase-synchronous circuit stabilizes PLL gain by controlling current flow through a first current path and adjusting internal characteristics during calibration, addressing performance variations caused by manufacturing variations in semiconductor integrated circuits.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SOCIONEXT INC
- Filing Date
- 2024-11-12
- Publication Date
- 2026-05-21
Smart Images
Figure JP2024040099_21052026_PF_FP_ABST
Abstract
Description
Phase synchronization circuit and semiconductor integrated circuit
[0001] The present invention relates to a phase synchronization circuit and a semiconductor integrated circuit.
[0002] There is known a phase synchronization circuit (PLL: Phase Locked Loop) having a sampling phase detector including a switch capacitor circuit and generating an output signal synchronized with the phase of an input signal. This type of phase synchronization circuit, for example, inputs a slope signal generated by supplying an output signal to a slope buffer and a non-overlap clock generated from an input signal to a switch capacitor circuit, and samples the slope signal by the switch capacitor circuit to generate an input voltage of a voltage controlled oscillator.
[0003] U.S. Patent Application Publication No. 2020 / 0028515, U.S. Patent Application Publication No. 2019 / 0214976
[0004] Seok Min Jung et al., "Design of Low Jitter Phase-Locked Loop with Closed Loop Voltage Controlled Oscillator"
[0005] A transfer function for determining the phase noise of a phase synchronization circuit includes a so-called PLL gain, and one of the elements for determining the PLL gain is a slope output current supplied from a slope buffer to a switch capacitor circuit. The PLL gain varies due to manufacturing variations of the semiconductor integrated circuit on which the phase synchronization circuit is mounted. Variations in the PLL gain may cause performance variations, for example, among a plurality of systems each having a phase synchronization circuit. Alternatively, when a plurality of phase synchronization circuits are mounted on one semiconductor integrated circuit, the PLL gain may vary depending on the position of the phase synchronization circuit on the semiconductor integrated circuit. Therefore, it is preferable to avoid variations in the PLL gain due to manufacturing variations of the semiconductor integrated circuit.
[0006] The present invention has been made in view of the above points, and aims to suppress fluctuations in PLL gain by suppressing variations caused by manufacturing variations in the current flowing from the slope voltage generation circuit that generates the slope voltage signal to the filter circuit.
[0007] In one aspect of the present invention, the phase-synchronous circuit is a phase-synchronous circuit having a sampling phase comparison circuit that compares the phases of a reference clock and a feedback clock and generates an oscillation control signal, an oscillation circuit that generates an output clock based on the oscillation control signal, and a feedback circuit that generates the feedback clock based on the output clock, wherein the sampling phase comparison circuit includes a slope voltage generation circuit that generates a slope voltage signal based on a first input signal which is either the reference clock or the feedback clock, and a filter circuit that generates the oscillation control signal based on a slope output current that flows in accordance with the slope voltage signal, and the slope voltage generation circuit includes a first current path that can control whether or not to generate a through-current flowing between a first power supply voltage line to which a first power supply voltage is supplied and a second power supply voltage line to which a second power supply voltage lower than the first power supply voltage is supplied via an output node to which the slope voltage signal is output.
[0008] According to the disclosed technology, fluctuations in the PLL gain can be suppressed by suppressing variations caused by manufacturing variations in the current flowing from the slope voltage generation circuit, which generates the slope voltage signal, to the filter circuit.
[0009] This is a block diagram showing an example of a semiconductor integrated circuit equipped with a phase-locked circuit in the first embodiment. This is a circuit block diagram showing an example of the phase-locked circuit in Figure 1. This is a circuit diagram showing an example of the slope voltage generation circuit in Figure 2. This is an explanatory diagram showing an example of the state of the slope voltage generation circuit set so that the slope output current is relatively large in the normal operating mode of the phase-locked circuit in Figure 2. This is a timing diagram showing an example of the operation of the phase-locked circuit in the normal operating mode of Figure 2. This is an explanatory diagram showing an example of the state of the slope voltage generation circuit in the calibration mode of the phase-locked circuit in Figure 2. This is an explanatory diagram showing another example of the state of the slope voltage generation circuit in the calibration mode of the phase-locked circuit in Figure 2. This is an explanatory diagram showing yet another example of the state of the slope voltage generation circuit in the calibration mode of the phase-locked circuit in Figure 2. This is an explanatory diagram showing an example of a correspondence table of various currents measured and calculated for each gate voltage pattern of transistors P11-P1n in the calibration mode of the phase-locked circuit in Figure 2. This is a flowchart showing an example of the operation of the phase-locked circuit in the calibration mode of Figure 2. This is a flowchart continuing from Figure 10.
[0010] Embodiments will be described below with reference to the drawings. In the following, the symbols indicating signals are also used to indicate signal lines, signal terminals, or signal nodes. The symbols indicating voltage are also used to indicate voltage lines, voltage terminals, or voltage nodes. A signal line shown as a single line may indicate a signal line with multiple bits.
[0011] Figure 1 shows an example of a semiconductor integrated circuit in which the phase-locked circuit in the first embodiment is mounted. For example, the semiconductor integrated circuit 200 shown in Figure 1 has a phase-locked circuit 100, a receiving circuit 210, a processing circuit 220, and a transmitting circuit 230, and operates by receiving a power supply voltage VDD and a ground voltage VSS. For example, the semiconductor integrated circuit 200 has the form of a chip such as a SoC (System on Chip). In the normal operating mode, the phase-locked circuit 100 generates an output clock Fout by multiplying the frequency of a reference clock REF received from outside the semiconductor integrated circuit 200, and outputs the generated output clock Fout to the processing circuit 220.
[0012] During calibration mode to correct gain variations, the phase-locked circuit 100 changes its internal characteristic values in response to an externally received control signal CNTL, and sets the internal characteristic values to fixed values using an externally received program signal PGM. For example, the control signal CNTL and the program signal PGM are generated by a test device 300, such as an LSI (Large-Scale Integration) tester, which tests the semiconductor integrated circuit 200.
[0013] The test device 300 sets the semiconductor integrated circuit 200 to calibration mode and outputs a control signal CNTL to measure the amount of deviation between the characteristic value and the expected value of the phase-locked circuit 100. Subsequently, the test device 300 outputs a program signal PGM to fix the characteristic value to a value with a small deviation from the expected value. The semiconductor integrated circuit 200 may also have a test circuit with functions equivalent to those of the test device 300. In this case, the test circuit has the function of outputting the control signal CNTL and the program signal PGM to the phase-locked circuit 100 during calibration mode, measuring the amount of deviation between the characteristic value and the expected value of the phase-locked circuit 100, and fixing the characteristic value to a value with a small deviation from the expected value.
[0014] The receiving circuit 210 receives the receiving signal to be processed from outside the semiconductor integrated circuit 200 and outputs it to the processing circuit 220. The processing circuit 220 receives the receiving signal based on the output clock Foot and processes the received signal. The processing circuit 220 also outputs the signal generated based on the processing of the received signal as a transmission signal to the transmitting circuit 230 based on the output clock Foot. The transmitting circuit 230 transmits the transmission signal received from the processing circuit 220 to the outside of the semiconductor integrated circuit 200.
[0015] Figure 2 shows an example of the phase-locked circuit 100 shown in Figure 1. The phase-locked circuit 100 shown in Figure 2 includes a sampling phase comparison circuit 110 which includes a slope voltage generation circuit 112, a filter circuit 114, and an inverter IV, a voltage-controlled oscillator (VCO), a non-overlap signal generation circuit 120, a feedback circuit 130, and a register 140. The phase-locked circuit 100 generates an output clock Fout which is a multiplication of the frequency of the reference clock REF. The voltage-controlled oscillator (VCO) is an example of an oscillator circuit.
[0016] The sampling phase comparison circuit 110 compares the phases of the reference clock REF and the feedback clock / DIV and generates an oscillation control signal VCONT. The slope voltage generation circuit 112 generates a slope voltage signal Vx at the output node Vx based on the feedback clock / DIV obtained by inverting the logic value of the feedback clock DIV received from the feedback circuit 130 with inverter IV, thereby outputting a slope output current Icp to the filter circuit 114. The feedback clock / DIV is an example of a first input signal. An example of the slope voltage generation circuit 112 is shown in Figure 3.
[0017] The filter circuit 114 has switches SW1 and SW2 connected in series between node Vx and node VCONT via node Va. Node VCONT is connected to the input of the voltage-controlled oscillator VCO. The filter circuit 114 also has a capacitor C1 located between node Va and the ground wire VSS, and a capacitor C2 located between node VCONT and the ground wire VSS.
[0018] Switch SW1 turns on when the switching control signal S1 is at an effective level and turns off when the switching control signal S1 is at an inactive level. Switch SW2 turns on when the switching control signal S2 is at an effective level and turns off when the switching control signal S2 is at an inactive level. For example, switch SW1 may be a transistor that receives the switching control signal S1 at its gate, and switch SW2 may be a transistor that receives the switching control signal S2 at its gate. Transistors that receive the switching control signals S1 and S2 at their gates are examples of a third type of transistor.
[0019] The non-overlap signal generation circuit 120 generates switching control signals S1 and S2 whose effective level periods do not overlap, based on the transition edges of the reference clock REF, and outputs the generated switching control signals S1 and S2 to the control terminals (e.g., the gates of the transistors) of switches SW1 and SW2, respectively. The non-overlap signal generation circuit 120 is an example of a switching control circuit.
[0020] The filter circuit 114 operates as a switched-capacitor circuit that, via exclusively switched-on switches SW1 and SW2, sequentially transfers the charge generated at node Vx by the slope output current Icp to capacitors C1 and C2, thereby generating the control voltage of the voltage-controlled oscillator VCO at node VCONT.
[0021] The voltage-controlled oscillator (VCO) generates an output clock (FOT) having a frequency corresponding to the voltage of the oscillation control signal (FOT) generated at node VCONT. For example, the output clock (FOT) is supplied as an operating clock to a processing circuit (not shown) that performs signal processing, data processing, etc.
[0022] The feedback circuit 130 divides the frequency of the output clock Fout and generates a feedback clock DIV that is supplied to the slope voltage generation circuit 112.
[0023] Register 140 has multiple memory units, each holding the logical values of n sets of 2-bit switch control signals SWP1-SWPn and the logical value of a 1-bit switch control signal SWN. Register 140 outputs the switch control signals SWP1-SWPn and SWN to the slope voltage generation circuit 112. The logical values held in each memory unit of Register 140 can be rewritten by the control signal CNTL from outside the phase synchronization circuit 100. In addition, the logical values held in each memory unit of Register 140 can be fixed in an unrewritable state by the program signal PGM.
[0024] For example, the register 140 has a rewritable latch circuit corresponding to each storage unit and a program element that fixes the state of the latch circuit. Each storage unit of the register 140 may be formed using an electrically rewritable non-volatile memory such as flash memory.
[0025] The switch control signal SWN is an example of a first switch control signal, and a portion of the register 140 that generates the switch control signal SWN is an example of a first control circuit. Each of the switch control signals SWP1-SWPn is an example of a second switch control signal, and another portion of the register 140 that generates the switch control signals SWP1-SWPn is an example of a second control circuit.
[0026] The register 140 may have multiple volatile memory units, such as latch circuits. In this case, before the phase-synchronous circuit 100 starts operating, data to set the logical values of the switch control signals SWP1-SWPn and the switch control signal SWN is written to each memory unit of the register 140 from outside the phase-synchronous circuit 100 using a control signal CNTL or the like.
[0027] Figure 2 shows an example in which the reference clock REF is supplied to the non-overlap signal generation circuit 120 and the feedback clock DIV is supplied to the slope voltage generation circuit 112. However, even if the feedback clock DIV is supplied to the non-overlap signal generation circuit 120 and the reference clock REF is supplied to the slope voltage generation circuit 112, the phase-locking circuit 100 can generate an output clock Fout by multiplying the frequency of the reference clock REF. In this case, the reference clock REF supplied to the slope voltage generation circuit 112 becomes an example of the first input signal.
[0028] Figure 3 shows an example of the slope voltage generation circuit 112 shown in Figure 2. The slope voltage generation circuit 112 includes PMOS (P-channel Metal Oxide Semiconductor) transistors P0, P1, P01, P11, P02, P12, ..., P0n, P1n, an NMOS (N-channel Metal Oxide Semiconductor) transistor N0, selector circuits SELP1, SELP2, ..., SELPn, SELN, and a current source circuit CS. For example, the sizes of the PMOS transistors P0, P01, P02, ..., P0n are the same, and the sizes of the PMOS transistors P1, P11, P12, ..., P1n are the same. Hereafter, PMOS transistors and NMOS transistors will be simply referred to as transistors.
[0029] Transistors P0 and P1 and the current source circuit CS are connected in series between the power line VDD and the ground line VSS. The gate of transistor P1 is connected to the ground line VSS. Transistors P01 and P11 are connected in series between the power line VDD and node Vx. Transistors P02 and P12 are connected in series between the power line VDD and node Vx. Transistors P0n and P1n are connected in series between the power line VDD and node Vx.
[0030] Other transistors not shown (e.g., P03, P13) are also connected in series between the power line VDD and node Vx. Transistor N0 is connected between node Vx and the ground line VSS. Node Vx is an example of a second intermediate node. Each pair of transistors P01, P11, P02, P12, ..., P0n, P1n is an example of a third current path circuit connected in parallel between the power line VDD and node Vx.
[0031] Transistor N0 is an example of a first transistor. Each of transistors P11-P1n is an example of a second transistor. Transistors P01-P0n, connected in series with each of transistors P11-P1n, are examples of a fourth transistor. Transistor P0 is an example of a fifth transistor.
[0032] The gates of transistors P0, P01, P02, ..., P0n are connected to the drain of transistor P0. This causes the slope voltage generation circuit 112 to operate as a current mirror circuit, for example, by passing equal currents between the sources and drains of each of transistors P0, P01, P02, ..., P0n. The drain of transistor P0 is an example of a first intermediate node.
[0033] A current path that can control whether or not a through-current flows between the power line VDD and the ground line VSS in each of the rows of transistors P01, P11, N0, P02, P12, N0, ..., P0n, P1n, N0 is an example of a first current path. Transistor P0 is an example of a first current path circuit. Transistor N0 and the selector circuit SELN are examples of a second current path circuit.
[0034] n selector circuits SELP1-SELPn operate according to the respective logic values of the switch control signals SWP1-SWPn. Selector circuit SELP1 connects the gate of transistor P11 to either the power line VDD, the ground line VSS, or the node / DIV, according to the logic value of the switch control signal SWP1. Selector circuit SELP2 connects the gate of transistor P12 to either the power line VDD, the ground line VSS, or the node / DIV, according to the logic value of the switch control signal SWP2.
[0035] The selector circuit SELPn connects the gate of transistor P1n to either the power line VDD, the ground line VSS, or the node / DIV, depending on the logic value of the switch control signal SWPn. Other selector circuits SELP3-SELP(n-1), not shown, also connect the gate of the corresponding transistor P13-P1(n-1) to either the power line VDD, the ground line VSS, or the node / DIV, depending on the logic value of the corresponding switch control signal SWP3-SWP(n-1).
[0036] The pairs of selector circuit SELP1 and transistor P11, selector circuit SELP2 and transistor P12, ..., selector circuit SELPn and transistor P1n are examples of second switch circuits connected to constitute a second part of the first current path. Each of the selector circuits SELP1-SELPn is an example of a second selector circuit. The power supply voltage VDD, ground voltage VSS, or feedback clock / DIV voltage that each of the selector circuits SELP1-SELPn outputs to the gates of the corresponding transistors P11-P1n are examples of second gate control signals.
[0037] Each of the transistors P11, P12, ..., P1n is always on when receiving a ground voltage VSS at its gate, always off when receiving a power supply voltage VDD at its gate, and on or off depending on the logic value of the feedback clock / DIV when receiving a feedback clock / DIV at its gate. For example, each of the transistors P11, P12, ..., P1n is on when receiving a low level of feedback clock / DIV and off when receiving a high level of feedback clock / DIV.
[0038] The selector circuit SELN and transistor N0 are an example of a first switch circuit connected to constitute a first part of a first current path. The selector circuit SELN is an example of a first selector circuit. The selector circuit SELN connects the gate of transistor N0 to either node / DIV or power line VDD according to the logic value of the switch control signal SWN. The node / DIV voltage or power supply voltage VDD output by the selector circuit SELN to the gate of transistor N0 is an example of a first gate control signal.
[0039] The power line VDD is an example of one of the first power voltage line and the second power voltage line, and the grounding line VSS is an example of the other of the first power voltage line and the second power voltage line. The power voltage VDD is an example of one of the first power voltage and the second power voltage, and the grounding voltage VSS is an example of the other of the first power voltage and the second power voltage.
[0040] The power line VDD and ground line VSS are the power line VDD and ground line VSS of the semiconductor integrated circuit 200 on which the phase-lock circuit 100 is mounted. For example, during a calibration mode to calibrate the gain variation of the phase-lock circuit 100, the power supply current is measured using a current measurement circuit 310 provided in the test apparatus 300 of Figure 1 or a current measurement circuit 310 provided in the test circuit mounted on the semiconductor integrated circuit 200. The current measurement circuit 310 is located between the power supply PS and the power line VDD.
[0041] Since the power supply line VDD is commonly wired to various circuits within the semiconductor integrated circuit 200, the current measurement circuit 310 measures not only the power supply current flowing through the slope voltage generation circuit 112 but also the overall power supply current of the semiconductor integrated circuit 200. For example, during the calibration mode of the phase-locked loop circuit 100, the semiconductor integrated circuit 200 stops the operation of circuits other than the phase-locked loop circuit 100. Then, the current measurement circuit 310 measures the power supply current of the phase-locked loop circuit 100 and the standby current of circuits other than the phase-locked loop circuit 100.
[0042] Also, the current measurement circuit 310 measures the power supply current (including the standby current) that includes the current flowing when any one of the pairs of transistors P01, P11, the pairs of transistors P02, P12,..., the pairs of transistors P0n, P1n and the transistor N0 are turned on. Then, for example, by subtracting the standby current from each measured power supply current using a test circuit such as an LSI tester that includes the current measurement circuit 310, the slope output current Icp flowing through each of the pairs of transistors P02, P12,..., the pairs of transistors P0n, P1n can be accurately obtained.
[0043] Note that it becomes possible to measure the slope output current Icp by connecting a monitor terminal to the output node Vx and connecting an ammeter to the monitor terminal. However, when connecting a monitor terminal to the output node Vx, there is a risk of problems such as the phase-locked loop circuit 100 becoming difficult to lock due to the influence of disturbance (noise) from the monitor terminal.
[0044] The phase-locked loop circuit 100 shown in FIG. 3 shows an example of the state of the slope voltage generation circuit 112 set so that the slope output current Icp is relatively small in the normal operation mode of generating the output clock Fout. The slope output current Icp becomes smaller as the number of transistors P11 - P1n that turn on or off according to the logical value of the node / DIV is smaller, and becomes larger as the number of transistors P11 - P1n that turn on is larger.
[0045] In the example shown in Figure 3, a switch control signal SWP1 connecting the gate of transistor P11 to node / DIV is supplied to selector circuit SELP1, and transistor P11 is turned on or off according to the logic value of node / DIV. Switch control signals SWP2-SWPn connecting the gates of transistors P12-P1n to power line VDD are supplied to selector circuits SELP2-SELPn respectively, and transistors P12-P1n are turned off. A switch control signal SWN connecting the gate of transistor N0 to node / DIV is supplied to selector circuit SELN, and transistor N0 is turned on or off according to the logic value of node / DIV.
[0046] As a result, the slope voltage generation circuit 112 flows a slope output current Icp from the power line VDD to node Vx via transistors P01 and P11 when the feedback clock / DIV is at a low level. The slope voltage generation circuit 112 sets node Vx to a low level when the feedback clock / DIV is at a high level. Then, during the low-level period of the feedback clock / DIV, the slope voltage generation circuit 112 generates a slope voltage signal Vx using a pair of transistors P01 and P11, and outputs the slope output current Icp to the filter circuit 114 as shown by the dashed arrow.
[0047] Figure 4 shows an example of the state of the slope voltage generation circuit 112 in the normal operating mode of the phase-locked circuit 100 in Figure 2, where the slope output current Icp is set to be relatively large. In Figure 5, in addition to the state shown in Figure 3, a switch control signal SWP2 connecting the gate of transistor P12 to node / DIV is supplied to the selector circuit SELP2. As a result, transistors P11 and P12 are turned on or off according to the logic value of node / DIV, and if transistors P11 and P12 are the same size, when transistors P11 and P12 are on, twice the slope output current Icp flows compared to Figure 3. The number of transistors P11-P1n that are turned on in the normal operating mode is set by programming register 140 based on the evaluation in calibration mode. The evaluation in calibration mode is shown in Figures 10 and 11.
[0048] FIG. 5 shows an example of the operation timing in the normal operation mode of the phase synchronization circuit 100 of FIG. 2. In the example shown in FIG. 5, the phase synchronization circuit 100 receives a reference clock REF of 38.4 MHz or 100 MHz and generates an output clock Fout of 4 GHz (FIGS. 5(a) and 5(b)). The feedback circuit 130 divides the frequency of the output clock Fout by 104 or 40 to generate a feedback clock DIV of 38.4 MHz or 100 MHz (FIG. 5(c)). The inverter IV of the slope voltage generation circuit 112 inverts the logical value of the feedback clock DIV to generate a feedback clock / DIV (FIG. 5(d)).
[0049] The non-overlap signal generation circuit 120 sets the switching control signal S1 to the low level in synchronization with the rising edge of the reference clock REF, and sets the switching control signal S2 to the high level with a predetermined time delay from the rising edge of the reference clock REF (FIGS. 5(e) and 5(f)). Further, the non-overlap signal generation circuit 120 sets the switching control signal S2 to the low level at a timing with a predetermined time delay from the falling edge of the reference clock REF, and sets the switching control signal S1 to the high level at a timing with a further predetermined time delay from the rising edge of the reference clock REF (FIGS. 5(g) and 5(h)).
[0050] As a result, switching control signals S1 and S2 whose high-level periods do not overlap with each other are generated. The high-level periods of the switching control signals S1 and S2 are the valid-level periods. The switching control signals S1 and S2 are respectively output to the control terminals of the switches SW1 and SW2 of the filter circuit 114. For example, the non-overlap period NOP1 from the falling edge of the switching control signal S1 to the rising edge of the switching control signal S2 and the non-overlap period NOP2 from the falling edge of the switching control signal S2 to the rising edge of the switching control signal S1 are substantially equal.
[0051] During the period when the feedback clock / DIV is at a high level, transistors P11-P1n are off, transistor N0 is on, and node Vx is fixed at a low level (=0V) (Figure 5(i)). When the feedback clock / DIV changes to a low level, transistor N0 is turned off, and when the transistors among transistors P11-P1n whose gates are connected to node / DIV are turned on, the voltage at node Vx gradually rises due to the slope output current Icp, which is the current supplied from the power line VDD (Figure 5(j)). The slope, which indicates the incline of the voltage rise at node Vx, is shown by dividing the slope output current Icp by the capacitance value of capacitor C1 of the filter circuit 114.
[0052] During the period when the feedback clock / DIV is at a low level and the switching control signal S1 is at a high level, the voltage at node Va rises along with the voltage at node Vx (Figure 5(k)). The change in the switching control signal S1 to a low level turns off switch SW1. The filter circuit 114 samples the voltage at node Vx at the time switch SW1 is turned off and places it at node Va (Figure 5(l)). Furthermore, when switch SW1 is turned off, the supply of slope output current Icp to the filter circuit 114 stops, and the voltage at node Vx rises to the power supply voltage VDD (Figure 5(m)).
[0053] When the switching control signal S2 changes to a high level after a non-overlap period NOP1 following a change in the switching control signal S1 to a low level, the switch SW2 is turned on. The charge held at node Va moves to node VCONT, and the voltage at node VCONT increases by value V1 (Figure 5(n)). The voltage-controlled oscillator VCO generates an output clock Fout with a frequency corresponding to the voltage at node VCONT.
[0054] Subsequently, when the feedback clock DIV changes to a low level and the feedback clock / DIV changes to a high level, transistors P11-P1n turn off, transistor N0 turns on, and the voltage at node Vx drops to 0V (Figure 5(o)). When switch SW2 turns off due to the change in the low level of the switching control signal S2, the voltage at node VCONT is held for the period until switch SW2 is turned on again (Figure 5(p)).
[0055] When the switching control signal S1 changes to a high level after the non-overlap period NOP2 following the change in the switching control signal S2 to a low level, switch SW1 is turned on. Node Va is electrically connected to node Vx, the charge stored in capacitor C1 is discharged, and the voltage at node Va becomes 0V (Figure 5(q)).
[0056] When the feedback clock / DIV changes to a low level, transistor N0 turns off, and the transistors P11-P1n whose gates are connected to node / DIV turn on, the voltage at node Vx gradually rises due to the slope output current Icp while switch SW1 is on (Figure 5(r)). The voltage at node Va rises along with the voltage at node Vx (Figure 5(s)). When the switching control signal S1 changes to a low level, switch SW1 turns off, and the voltage at node Vx is sampled as the voltage at node Va (Figure 5(t)). With switch SW1 turned off, the voltage at node Vx rises to the power supply voltage VDD (Figure 5(u)).
[0057] When the switch SW2 is turned on by a change in the switching control signal S2 to a high level, the charge held at node Va moves to node VCONT, and the voltage at node VCONT increases by value V2 (Figure 5(v)).
[0058] The voltage-controlled oscillator VCO generates an output clock Fout with a frequency corresponding to the voltage at node VCONT. For example, when the voltage difference V2 at node VCONT is smaller than the voltage difference V1, it indicates that the voltage at node VCONT is converging toward a predetermined value. When the voltage at node VCONT converges to an appropriate voltage and the phase-lock circuit 100 locks, the reference clock REF and the feedback clock DIV have a predetermined phase difference. For example, the phase-lock circuit 100 locks with the phase of the feedback clock DIV leading the phase of the reference clock REF by a predetermined angle.
[0059] Figure 6 shows an example of the state of the slope voltage generation circuit 112 in calibration mode of the phase-locked circuit 100 in Figure 2. In calibration mode, a switch control signal SWN that connects the gate of transistor N0 to the power line VDD is supplied to the selector circuit SELN, and transistor N0 is turned on. Also in calibration mode, the non-overlap signal generation circuit 120 outputs a switching control signal S1 at an invalid level, turning off switch SW1. Note that in calibration mode, for example, in the semiconductor integrated circuit 200, the operation of all circuits except the phase-locked circuit 100 is stopped, and all other circuits enter standby mode or sleep mode.
[0060] In Figure 6, similar to Figure 3, a switch control signal SWP1 connecting the gate of transistor P11 to the ground line VSS is supplied to the selector circuit SELP1, and switch control signals SWP2-SWPn connecting the gates of transistors P12-P1n to the power line VDD are supplied to the selector circuits SELP2-SELPn respectively. As a result, only transistor P11 is turned on, and transistors P12-P1n are turned off. Transistor N0 is turned on. This generates a through-current flowing between the power line VDD and the ground line VSS via transistors P01, P11, and N0, and a slope output current Icp flows from the power line VDD to the ground line VSS. The current measurement circuit 310 measures the power supply current in this state. The power supply current includes the slope output current Icp, as well as the leakage current (standby current) flowing through circuits other than the phase-locking circuit 100 in the semiconductor integrated circuit 200.
[0061] Figure 7 shows another example of the state of the slope voltage generation circuit 112 in calibration mode of the phase-locked circuit 100 in Figure 2. In Figure 7, a switch control signal SWP2 that connects the gate of transistor P12 to the ground line VSS is supplied to the selector circuit SELP2, and switch control signals SWP1 and SWP3-SWPn that connect the gates of transistors P11, P13-P1n to the power line VDD are supplied to the selector circuits SELP1 and SELP3-SELPn, respectively, and only transistor P12 of transistors P11-P1n is turned on. Transistor N0 is turned on. As a result, a through-current flows between the power line VDD and the ground line VSS via transistors P02, P12, and N0, and a slope output current Icp flows from the power line VDD to the ground line VSS. The current measurement circuit 310 measures the power supply current in this state. The power supply current includes the slope output current Icp, as well as the leakage current flowing through circuits other than the phase-locking circuit 100 in the semiconductor integrated circuit 200.
[0062] Figure 8 shows yet another example of the state of the slope voltage generation circuit 112 in calibration mode of the phase-locked circuit 100 in Figure 2. In Figure 8, switch control signals SWP1-SWPn, which connect the gates of transistors P11-P1n to the power line VDD, are supplied to selector circuits SELP1-SELPn, respectively, and all transistors P11-P1n are turned off. Transistor N0 is turned on. As a result, in each of the rows of transistors P01, P11, N0, P02, P12, N0, ..., P0n, P1n, N0, no through-current flows between the power line VDD and the ground line VSS through the transistors in each row. In this state, the current measurement circuit 310 measures the sum of the leakage current flowing through the slope voltage generation circuit 112 and the leakage current flowing through other circuits in the semiconductor integrated circuit 200 other than the phase-locked circuit 100 as the power supply current.
[0063] Therefore, for example, by subtracting the power supply current measured in the state shown in Figure 8 from the power supply current measured in the state shown in Figure 6, it is possible to measure only the slope output current Icp flowing from the power line VDD to the ground line VSS via transistors P01, P11, and N0 as the power supply current. Also, by subtracting the power supply current measured in the state shown in Figure 8 from the power supply current measured in the state shown in Figure 7, it is possible to measure only the slope output current Icp flowing from the power line VDD to the ground line VSS via transistors P02, P12, and N0 as the power supply current.
[0064] Figure 9 shows an example of a correspondence table of various currents measured and calculated for each gate voltage pattern of transistors P11-P1n in the calibration mode of the phase-locked circuit 100 in Figure 2. The gate voltage patterns of transistors P11-P1n differ for each variable k. The gate voltage of transistors P11-P1n is set by changing the switch control signals SWP1-SWPn to predetermined logic values by rewriting the setting value of register 140 with the control signal CNTL.
[0065] For example, setting the gate voltages of transistors P11-P1n and measuring and calculating various currents are performed by a test device 300 (Figure 1), such as an LSI tester, for testing the semiconductor integrated circuit 200. Alternatively, setting the gate voltages of transistors P11-P1n and measuring and calculating various current values may be performed by a test circuit, such as a BIST (Built-In Self Test) circuit, mounted on the semiconductor integrated circuit 200. Hereinafter, an LSI tester or test circuit that measures and calculates various currents will be referred to as a measurement circuit.
[0066] When the variable k = 0, the switch control signals SWP1-SWPn connect the gates of all transistors P11-P1n to the power line VDD, turning off all transistors P11-P1n. Although not shown in the diagram, when the variable k = 0 to n, the switch control signal SWN turns on transistor N0.
[0067] When the variable k = 0, the gates of all transistors P11-P1n are connected to the power line VDD. As a result, the power supply current IVDD(0) is measured with all transistors P11-P1n permanently off (second state). From the variable k = 1 to k = n, only the gate of transistor P1k is connected to the ground line VSS, and the gates of the other transistors are connected to the power line VDD. As a result, the power supply currents IVDD(1)-IVVDD(n) are measured with only one transistor P1k permanently on in sequence (first state).
[0068] The measurement circuit sets the gate voltage of transistors P11-P1n for each state of variable k = 0 to n, and stores the measured power supply current IVDD (IVVDD(0) to IVDD(n)) in the area of the correspondence table corresponding to variable k. That is, for variable k = 1 to n, the power supply current IVDD is measured by turning on transistors P11-P1n one by one. Note that each element of the correspondence table may be stored, for example, in a memory unit mounted on the measurement circuit.
[0069] Here, the power supply current IVDD includes the slope output current Icp generated by the slope voltage generation circuit 112. When measuring the power supply current IVDD with multiple transistors P11-P1n turned on, the more transistors P11-P1n are turned on, the larger the slope output current Icp flowing through transistor N0 becomes, and the on-resistance component of transistor N0 can no longer be ignored. By measuring the power supply current IVDD with transistors P11-P1n turned on one by one, the on-resistance component of transistor N0 can be ignored, and the accurate slope output current Icp can be determined.
[0070] The measurement circuit stores the output current IOUT(k) as the value obtained by subtracting the power supply current IVDD(0) from each power supply current IVDD(k) for variables k=1 to n in the area corresponding to variable k in the correspondence table. Note that the output current IOUT(0) is 0. For variables k=1 to n, the output current IOUT(k) corresponds to the slope output current Icp measured by turning on transistors P11-P1n one by one.
[0071] The measurement circuit stores the total output current ITOTAL(0) = 0 in the area corresponding to variable k = 0 in the correspondence table. For variables k = 1 to n, the measurement circuit stores the total output current ITOTAL(k) obtained by adding the total output current ITOTAL(k-1) to each output current IOUT(k) in the area corresponding to variable k in the correspondence table. The total output current ITOTAL corresponds to the slope output current Icp measured when transistors P11-P1n are turned on at a rate of 1 or more. For variables k = 1 to n, the measurement circuit stores the current difference IERR(k) obtained by subtracting the target current ITARGET from each total output current ITOTAL(k) in the area corresponding to variable k in the correspondence table. Here, the target current ITARGET is the slope output current Icp for optimizing the PLL gain, and can be determined, for example, by circuit simulation during the design of the phase-locked circuit 100.
[0072] The measurement circuit then programs the register 140 with the logic values of the switch control signals SWP1-SWPn that turn on the k transistors P1-Pk, based on the variable k that minimizes the current difference IERR(k). This allows the slope output current Icp to be matched to the target current ITARGET even when the electrical characteristics of the semiconductor integrated circuit 200 on which the phase-locked circuit 100 is mounted fluctuate due to manufacturing variations, thereby suppressing fluctuations in the PLL gain due to manufacturing variations.
[0073] Figures 10 and 11 show an example of the operation of the phase-locked circuit 100 in Figure 2 in calibration mode. For example, the operation shown in Figures 10 and 11 is performed by operating an LSI tester that tests the semiconductor integrated circuit 200 or a test circuit of the phase-locked circuit 100 mounted on the semiconductor integrated circuit 200 as the measurement circuit described in Figure 9.
[0074] The measurement circuit outputs the control signal CNTL to register 140, thereby rewriting the value set in register 140 and setting the logic of the switch control signals SWP1-SWPn and SWN. The measurement circuit stores the various currents that have been measured and calculated in the correspondence table shown in Figure 9.
[0075] The measurement circuit then determines the number of transistors P11-P1n that can be turned on to minimize the variation in PLL gain caused by variations in the slope output current Icp due to process variations during the manufacturing of the semiconductor integrated circuit 200. After this, the measurement circuit outputs a program signal PGM to the register 140, programming the logic values of the switch control signals SWP1-SWPn, which turn on the determined number of transistors P11-P1n, into a state where they cannot be rewritten.
[0076] First, in step S10, the measurement circuit sets the variable k to 0. Next, in step S12, the measurement circuit outputs the control signal CNTL to register 140 and the switch control signal SWN, which connects the gate of transistor N0 to the power line VDD, to register 140. As a result, transistor N0 is turned on.
[0077] Next, in step S14, the measurement circuit outputs the control signal CNTL to the register 140 and, according to the correspondence table in Figure 9, turns off all transistors P11-P1n or turns on one of transistors P11-P1n depending on the value of variable k. Next, in step S16, the measurement circuit measures the power supply current IVDD(k) using the current measurement circuit 310 and stores the measurement result in the correspondence table.
[0078] Next, in step S18, if the value of variable k is less than the number n of transistors P11-P1n, the measurement circuit proceeds to step S20 because there are unmeasured power supply currents IVDD(k). When the value of variable k reaches the number n, the measurement circuit proceeds to step S22 because the measurement of all power supply currents IVDD(k) has been completed. In step S20, the measurement circuit increments variable k by 1 and returns to step S14 to measure the next power supply current IVDD(k).
[0079] In step S22, the measurement circuit sets the variable k to 1. Next, in step S24, the measurement circuit subtracts the power supply current IVDD(0) from the power supply current IVDD(k) and stores the resulting value as the output current IOUT(k) in the correspondence table.
[0080] Next, in step S26, if the value of variable k is less than n, the measurement circuit proceeds to step S28 because there are uncalculated output currents IOUT(k). When the value of variable k becomes n, the measurement circuit proceeds to step S30 in Figure 11 because the calculation of all output currents IOUT(k) has been completed. In step S28, the measurement circuit increments variable k by 1 and returns to step S24 to calculate the next output current IOUT(k).
[0081] In step S30 of Figure 11, the measurement circuit sets the total output current ITOTAL(0) to 0 and the variable k to 1. Next, in step S32, the measurement circuit stores the value obtained by adding the total output current ITOTAL(k-1) to the output current IOUT(k) as the total output current ITOTAL(k) in the correspondence table. Next, in step S34, the measurement circuit stores the value obtained by subtracting the target current ITARGET from the total output current ITOTAL(k) as the output current difference IERR(k) in the correspondence table.
[0082] Next, in step S36, if the value of variable k is less than n, the measurement circuit proceeds to step S38 because there is an uncalculated current difference IERR(k). When the value of variable k becomes n, the measurement circuit proceeds to step S40 because the calculation of all current differences IERR(k) has been completed. In step S38, the measurement circuit increments variable k by 1 and returns to step S34 to calculate the next current difference IERR(k).
[0083] In step S40, the measurement circuit refers to the correspondence table and selects the variable k that minimizes the absolute value of the current difference IERR(k). If there are multiple current differences IERR(k) that minimize the absolute value, the measurement circuit selects the variable k with the smallest value. Next, in step S42, based on the variable k selected in step S40, the measurement circuit decides to turn on k transistors from P11 to P1n in ascending order of their last digits. For example, if the k selected in step S40 is 2, the measurement circuit decides to turn on transistors P11 and P12.
[0084] Next, in step S44, the measurement circuit outputs a program signal PGM to register 140, programs the logical values of the switch control signals SWP1-SWPn that turn on the determined k transistors into register 140, and ends the operation in calibration mode as shown in Figures 10 and 11.
[0085] In this embodiment, the slope voltage generation circuit 112 is provided with a current path that can control whether or not to generate a through-current, and the difference in the power supply current IVDD between when a through-current is generated and when it is not generated in calibration mode is measured as the slope output current Icp. As a result, for example, compared to the case where a monitor terminal for the slope output current Icp is provided at the output node Vx, variations in the slope output current Icp caused by manufacturing variations of the semiconductor integrated circuit 200 can be suppressed without being affected by disturbances. As a result, fluctuations in the PLL gain in normal operation mode can be suppressed.
[0086] In calibration mode, the measurement circuit calculates the output current IOUT (i.e., slope output current Icp) by subtracting the power supply current IVDD when all transistors P11-P1n are turned off from the power supply current IVDD when each of transistors P11-P1n is turned on one by one.
[0087] As a result, when measuring the power supply current IVDD using the current measurement circuit 310 connected to the power supply line VDD, it is possible to cancel out current components flowing in the semiconductor integrated circuit 200 other than the phase-locking circuit 100 and calculate an accurate slope output current Icp. As a result, it is possible to accurately determine the number of on-states of transistors P11-P1n that can generate the slope output current Icp closest to the target current ITARGET, and to suppress variations in the slope output current Icp caused by manufacturing variations in the semiconductor integrated circuit 200.
[0088] In calibration mode, by turning on transistors P11-P1n one by one and measuring the power supply current IVDD, the on-resistance component of transistor N0 can be ignored, and the accurate slope output current Icp can be determined.
[0089] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application.
[0090] 100 Phase-Locked Circuit 110 Sampling Phase Comparison Circuit 112 Slope Voltage Generation Circuit 114 Filter Circuit 120 Non-Overlap Signal Generation Circuit 130 Feedback Circuit 140 Register 200 Semiconductor Integrated Circuit 210 Receiving Circuit 220 Processing Circuit 230 Transmitting Circuit 300 Test Equipment 310 Current Measurement Circuit C1, C2 Capacitors CNTL Control Signal CS Current Source Circuit DIV Feedback Clock Foot Output Clock Icp Slope Output Current IERR Current Difference IOUT Output Current IV Inverter IVDD Power Supply Current N0 Transistor NOP1, NOP2 Non-Overlap Period P0, P01-P0n PMOS Transistor P1, P11-P1n PMOS Transistor PGM Program Signal PS Power Supply REF Reference Clock S1, S2 Switching control signal SELN Selector circuit SELP1-SELPn Selector circuit SW1, SW2 Switch SWN Switch control signal SWP1-SWPn Switch control signal Va Node VCO Voltage-controlled oscillator VCONT Oscillator control signal VDD Power line VSS Ground line Vx Node, slope voltage signal
Claims
1. A phase-synchronous circuit comprising: a sampling phase comparison circuit that compares the phases of a reference clock and a feedback clock and generates an oscillation control signal; an oscillation circuit that generates an output clock based on the oscillation control signal; and a feedback circuit that generates a feedback clock based on the output clock, wherein the sampling phase comparison circuit includes: a slope voltage generation circuit that generates a slope voltage signal based on a first input signal which is either the reference clock or the feedback clock; and a filter circuit that generates the oscillation control signal based on a slope output current that flows in accordance with the slope voltage signal, wherein the slope voltage generation circuit includes a first current path capable of controlling whether or not to generate a through-current flowing between a first power supply voltage line to which a first power supply voltage is supplied and a second power supply voltage line to which a second power supply voltage lower than the first power supply voltage is supplied via an output node to which the slope voltage signal is output.
2. The phase-locked circuit according to claim 1, wherein the slope voltage generating circuit is connected to constitute a first portion of the first current path and includes a first switch circuit whose on / off state is controlled in response to a first switch control signal.
3. The phase-locked circuit according to claim 2, wherein the first switch circuit includes a first selector circuit that outputs a first gate control signal in response to the first switch control signal, and a first transistor provided between one of the first power supply voltage line and the second power supply voltage line and the output node, and whose on / off state is controlled in response to the first gate control signal supplied to the gate.
4. The phase-locked circuit according to claim 3, wherein the first selector circuit selects either a voltage signal that keeps the first transistor constantly on, or the first input signal, in response to the first switch control signal, and outputs it as the first gate control signal.
5. The phase-locked circuit according to claim 2, comprising a first control circuit for generating the first switch control signal.
6. The phase-locked circuit according to claim 2, wherein the slope voltage generating circuit includes a plurality of second switch circuits connected to constitute a second portion of the first current path, and whose on / off state is controlled in accordance with a plurality of second switch control signals.
7. The phase-locked circuit according to claim 6, wherein the plurality of second switch circuits are provided in parallel with each other between one of the first power supply voltage lines and the second power supply voltage lines and the output node, and each of the plurality of second switch circuits includes a second selector circuit that outputs a second gate control signal in accordance with a corresponding second switch control signal, and a second transistor provided between one of the first power supply voltage lines and the second power supply voltage lines and the output node, and whose on / off state is controlled in accordance with a second gate control signal supplied to the gate.
8. The phase-locked circuit according to claim 7, wherein the second selector circuit selects one of the following in response to the second switch control signal: a voltage signal that keeps the second transistor constantly on, a voltage signal that keeps the second transistor constantly off, and the first input signal, and outputs it as the second gate control signal.
9. The phase-locked circuit according to claim 7, comprising a second control circuit for generating the plurality of second switch control signals.
10. The phase-locked circuit according to claim 6, wherein in a first state of calibration mode, the slope voltage generation circuit generates a through-current between the first power supply voltage line and the second power supply voltage line via the first current path by having the first switch circuit always on and at least one of the plurality of second switch circuits always on.
11. The phase-locked circuit according to claim 10, wherein the slope voltage generation circuit generates a through-current flowing between the first power supply voltage line and the second power supply voltage line via the first current path by sequentially changing the status of the second switch circuit that is always on among the plurality of second switch circuits in the first state of the calibration mode.
12. The phase-locked circuit according to claim 10, wherein in the second state of the calibration mode, the slope voltage generation circuit does not generate a through-current flowing between the first power supply voltage line and the second power supply voltage line via the first current path, by keeping the first switch circuit always on and all of the plurality of second switch circuits always off.
13. The phase-locked circuit according to claim 1, comprising a current measuring circuit connected to the first power supply voltage line or the second power supply voltage line.
14. The phase-locked circuit according to claim 1, wherein the filter circuit includes a switched-capacitor circuit having a plurality of capacitors and a plurality of third transistors, and the phase-locked circuit includes a switching control circuit that generates a switching control signal for controlling the on / off state of the plurality of third transistors.
15. The phase-synchronous circuit according to claim 14, wherein the slope voltage generation circuit generates the slope voltage signal based on the feedback clock, and the switching control circuit generates the switching control signal based on the reference clock.
16. The slope voltage generating circuit includes: a current source circuit connected between one of the first power supply voltage line and the second power supply voltage line and a first intermediate node; a first current path circuit connected between the first intermediate node and the other of the first power supply voltage line and the second power supply voltage line; a second current path circuit connected between one of the first power supply voltage line and the second power supply voltage line and the second intermediate node; and a plurality of third current path circuits connected in parallel between the second intermediate node and the other of the first power supply voltage line and the second power supply voltage line, wherein the second current path circuit includes a first switch circuit arranged to constitute a first part of the first current path and whose on / off control is controlled in accordance with a first switch control signal; each of the plurality of third current path circuits includes a second switch circuit connected to constitute a second part of the first current path and whose on / off control is controlled in accordance with a corresponding second switch control signal; and a fourth transistor connected in series with the second switch circuit. The phase-locked circuit according to claim 1, wherein the first current path circuit includes a fifth transistor whose gate and drain are connected and whose gate is connected to the gate of the fourth transistor.
17. The phase-locked circuit according to claim 16, wherein the first switch circuit includes a first selector circuit that outputs a first gate control signal in response to the first switch control signal, and a first transistor whose on / off state is controlled in response to the first gate control signal supplied to the gate, and the second switch circuit includes a second selector circuit that outputs a second gate control signal in response to the corresponding second switch control signal, and a second transistor whose on / off state is controlled in response to the second gate control signal supplied to the gate.
18. A semiconductor integrated circuit having a phase-locked circuit according to any one of claims 1 to 17, and a processing circuit that performs processing based on the output clock.