Display device and method for driving same

Abstract

The present application discloses a foldable display device capable of sufficiently reducing power consumption when one of two display regions having a folding portion interposed therebetween is brought into a non-display state. A display panel 6 has a first display region and a second display region with a folding portion as the boundary. An EM driver serving as a light emission control circuit is separated into an upper-stage EM driver that drives a light emission control line in the first display region on the basis of a first start pulse signal ESP1, and a lower-stage EM driver that drives a light emission control line in the second display region 120 on the basis of a second start pulse signal ESP2. In a full-screen display mode, the first and second start pulse signals ESP1, ESP2 are generated such that the entire EM driver operates as one shift register. In a half-screen display mode, the first start pulse signal ESP1 is generated such that the upper-stage EM driver operates as a shift register, and the second start pulse signal ESP2 is fixed in an inactive state.

Description

Display device and its driving method

[0001] The following disclosure relates to a display device, and more particularly to a display device configured to be foldable between two display areas.

[0002] In recent years, organic EL display devices including pixel circuits containing organic EL elements have been put into practical use. Organic EL elements are also called OLEDs (Organic Light-Emitting Diodes), and are self-emitting display elements that emit light with a luminance corresponding to the current flowing through them. Since such organic EL elements are self-emitting display elements, organic EL display devices can be easily made thinner, consume less power, and have higher brightness compared to liquid crystal display devices that require backlights and color filters.

[0003] On the other hand, in recent years, the development of foldable (foldable) display devices with excellent portability and storage has been progressing. In such a display device, two display areas are provided so as to sandwich the folding position.

[0004] In relation to the present application, Japanese Patent Application Laid-Open No. JP2019-102130 discloses an organic EL display device including an organic EL display that can be folded and used at a preset folding portion having flexibility. In this organic EL display, a plurality of wirings are disconnected at the folding portion along a plurality of scanning lines, and scanning circuits for supplying scanning signals to the corresponding plurality of scanning lines are formed on both sides of the folding portion (see Claims 1 and 4, Paragraph 0025, and FIG. 3 of the same document).

[0005] Furthermore, International Publication No. 2020 / 194492 discloses a foldable organic EL display device comprising a display unit 200 having a first display area 210 and a second display area 220 sandwiching a folding portion 250 (see Figure 3 of the same document). The scanning signal lines of the first display area 210 are driven by a first gate driver 300a, the scanning signal lines of the second display area 220 are driven by a second gate driver 300b, the light emission control lines of the first display area 210 are driven by a first emission driver 300a, and the light emission control lines of the second display area 220 are driven by a second emission driver 300b (see Figure 13). Each data signal line consists of a first data signal line for the first display area 210 and a second data line signal for the second display area 220. An analog switch 252 provided in the bending portion 250 can control the electrical connection state between the first data signal line and the second data signal line that constitute each data signal line (see Figure 1). With this configuration, power consumption can be reduced in a foldable organic EL display device compared to conventional devices.

[0006] Japanese Patent Publication No. 2019-102130, International Publication No. 2020 / 194492, Pamphlet

[0007] In a foldable organic EL display device, one of the two display areas separated by the folding portion can be made invisible in order to place a keyboard there. This invisible function can be achieved by driving the data signal lines and scan signal lines so that the display area where the keyboard is to be placed becomes black.

[0008] For example, such a function can be realized in the organic EL display device disclosed in Japanese Patent Publication No. 2019-102130. However, in this display device, the signal lines (data signal lines) for transmitting signals corresponding to the grayscale value to the pixels are separated at the bent portion, and two drive circuits are required, one drive circuit for driving the signal lines in one of the two display areas and another drive circuit for driving the signal lines in the other. For this reason, regardless of whether one of the two display areas is displayed in black or as a normal image, more power than usual is required to drive the signal lines.

[0009] Furthermore, the above functions can also be realized in the organic EL display device disclosed in International Publication No. 2020 / 194492. However, it is necessary to provide control signals to the first gate driver 300a and the second gate driver 300b, which correspond to the first display area 210 and the second display area 220, respectively, that are provided on either side of the folding portion, and also to provide control signals to the first emission driver 400a and the second emission driver 400b, respectively, that correspond to the first display area and the second display area, respectively. As a result, the area of ​​the bezel region on the display panel becomes larger. In addition, even though one of the two display areas 210 and 220 that sandwich the folding portion is displayed in black, the same amount of power is required to drive the data signal lines and scan signal lines as when displaying a normal image in each of the two display areas 210 and 220.

[0010] Therefore, in a foldable organic EL display device, when one of the two display areas flanking the folding portion is not displayed, it is desirable that power consumption be significantly reduced compared to when a normal image is displayed in each of the two display areas.

[0011] A display device according to several embodiments of the present invention is a foldable display device comprising: a display unit including a plurality of pixel circuits, a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, and a plurality of light emission control lines corresponding to each of the plurality of scan signal lines; a data signal line drive circuit for driving the plurality of data signal lines; a scan signal line drive circuit for driving the plurality of scan signal lines; and a light emission control circuit for driving the plurality of light emission control lines, wherein each of the plurality of pixel circuits includes a light-emitting element driven by current, a holding capacitor, a drive transistor that controls the amount of current supplied to the light-emitting element according to the voltage written to the holding capacitor, a write control switching element having a control terminal connected to one of the plurality of scan signal lines for controlling whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor, and a light emission control switching element having a control terminal connected to one of the plurality of light emission control lines and provided in series with the light-emitting element and the drive transistor, wherein the display unit has a first display area and a second display area separated by a folding portion for folding the display device, The light emission control circuit includes a first light emission control circuit that drives a plurality of first light emission control lines which are light emission control lines arranged in the first display area from among the plurality of light emission control lines, and a second light emission control circuit that drives a plurality of second light emission control lines which are light emission control lines arranged in the second display area from among the plurality of light emission control lines, wherein the first light emission control circuit has a plurality of stages for driving the plurality of first light emission control lines and is configured to operate as a shift register based on a first light emission control start pulse signal and a predetermined clock signal provided to the first stage, wherein the second light emission control start pulse signal can be generated as a signal independent of the first light emission control start pulse signal,The second light emission control circuit deactivates the plurality of second light emission control lines when the second light emission control start pulse signal is fixed in an inactive state.

[0012] A driving method according to several embodiments of the present invention is a driving method for a foldable display device having a display unit including a plurality of pixel circuits, a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, and a plurality of light emission control lines corresponding to each of the plurality of scan signal lines, comprising: a data signal line driving step for driving the plurality of data signal lines; a scan signal line driving step for driving the plurality of scan signal lines; and a light emission control line driving step for driving the plurality of light emission control lines, wherein each of the plurality of pixel circuits includes a light-emitting element driven by current, a holding capacitor, a driving transistor that controls the amount of current supplied to the light-emitting element according to a voltage written to the holding capacitor, a write control switching element having a control terminal connected to one of the plurality of scan signal lines that controls whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor, and a light emission control switching element having a control terminal connected to one of the plurality of light emission control lines that is provided in series with the light-emitting element and the driving transistor, The display unit has a first display area and a second display area separated by a folding portion for folding the display device, and the light emission control line driving step includes a first light emission control line driving step which sequentially drives a plurality of first light emission control lines which are light emission control lines arranged in the first display area from among the plurality of light emission control lines, based on a first light emission control start pulse signal and a predetermined clock signal, and a second light emission control line driving step which sequentially drives a plurality of second light emission control lines which are light emission control lines arranged in the second display area from among the plurality of light emission control lines, based on a second light emission control start pulse signal and a predetermined clock signal, the second light emission control line driving step which deactivates the plurality of second light emission control lines when the second light emission control start pulse signal is fixed in an inactive state.

[0013] According to some embodiments of the present disclosure, in a foldable display device, the display unit has a first display area and a second display area separated by a folding portion for folding the display device, and the display unit is provided with a plurality of data signal lines and a plurality of scan signal lines, in addition to a plurality of light emission control lines corresponding to each of the plurality of scan signal lines. Each pixel circuit in the display unit includes a light-emitting element, a holding capacitor and a drive transistor, etc., as well as a light emission control switching element provided in series with the light-emitting element and the drive transistor, and the control terminal of the light emission control switching element is connected to one of the plurality of light emission control lines. The plurality of first light emission control lines, which are light emission control lines in the first display area, are driven sequentially based on a first light emission control start pulse signal and a predetermined clock signal, and the plurality of second light emission control lines, which are light emission control lines in the second display area, are driven sequentially based on a second light emission control start pulse signal and a predetermined clock signal. In this configuration, when displaying a normal image in the first and second display areas, the timing of the first light emission control start pulse signal and the second light emission control start pulse signal can be set so that the multiple light emission control lines are driven sequentially along with the multiple data signal lines and the multiple scan signal lines. On the other hand, by sequentially driving the multiple first light emission control lines based on the first light emission control start pulse signal and a predetermined clock signal, and fixing the second light emission control start pulse signal to an inactive state, the multiple second light emission control lines can be deactivated, thereby displaying an image in the first display area while keeping the second display area hidden (black display state). By keeping the second display area hidden in this way, a function for placing a keyboard can be realized as needed. When the second display area is kept hidden, the light-emitting elements in each pixel circuit in the second display area are turned off, reducing not only the power consumption in each pixel circuit but also the power consumption for driving the multiple second light emission control lines. Therefore, when one of the two display areas flanking the folding portion is hidden, power consumption can be significantly reduced compared to when a normal image is displayed in each of the two display areas.

[0014] This is a block diagram showing the functional configuration of an organic EL display device according to the first embodiment. This is a diagram showing the configuration of the display panel of the organic EL display device according to the first embodiment. This is a timing chart for explaining the operation of the display panel according to the first embodiment. This is a circuit diagram showing the configuration of the pixel circuit in the first embodiment. This is a timing chart for explaining the operation of the pixel circuit in the first embodiment. This is a perspective view of the organic EL display device according to the first embodiment. This is a block diagram for explaining the configuration of the scanning-side drive circuit in the first embodiment. This is a block diagram showing the configuration of the EM driver as a light emission control circuit in the first embodiment. This is a timing chart for explaining the operation of the EM driver in full-screen display mode in the first embodiment. This is a timing chart for explaining the operation of the EM driver in half-screen display mode in the first embodiment. This is a circuit diagram showing an example of the configuration of a unit circuit of the EM driver in the first embodiment. This is a signal waveform diagram for explaining the operation of a unit circuit of the EM driver in the first embodiment. This is a diagram for explaining the operation of the display panel in half-screen display mode in the first embodiment. This is a block diagram showing the configuration of the EM driver in a modified example of the first embodiment. This is a block diagram for explaining the configuration of the scanning-side drive circuit in an organic EL display device according to the second embodiment. This is a block diagram showing the configuration of the SC driver as a write control circuit in the second embodiment. This is a timing chart for explaining the operation of the SC driver in full-screen mode in the second embodiment described above. This is a timing chart for explaining the operation of the SC driver in half-screen mode in the second embodiment described above. This is a circuit diagram showing an example of the configuration of the unit circuit of the SC driver in the second embodiment described above. This is a signal waveform diagram for explaining the operation of the unit circuit of the SC driver in the second embodiment described above. This is a block diagram showing an example of the configuration of the DIS driver as an initialization control circuit in the second embodiment described above. This is a signal waveform diagram for explaining the operation of the DIS driver in full-screen mode in the second embodiment described above. This is a signal waveform diagram for explaining the operation of the DIS driver in half-screen mode in the second embodiment described above.This is a signal waveform diagram illustrating the operation of the first example of the unit circuit of the DIS driver in the second embodiment described above. This is a signal waveform diagram illustrating the operation of the second example of the unit circuit of the DIS driver in the second embodiment described above, in particular the operation of the first stage unit circuit. This is a signal waveform diagram illustrating the operation of the second example of the unit circuit of the DIS driver in the second embodiment described above, in particular the operation of unit circuits other than the first stage. This is a signal waveform diagram illustrating the operation of the third example of the unit circuit of the DIS driver in the second embodiment described above. This is a signal waveform diagram illustrating the operation of the EM driver in half-screen display mode in the first modified example. This is a signal waveform diagram illustrating the operation of the EM driver in half-screen display mode in the second modified example.

[0015] The embodiments will be described below with reference to the attached drawings. In each of the transistors mentioned below, the gate terminal corresponds to the control terminal, one of the drain terminal and the source terminal corresponds to the first conduction terminal, and the other corresponds to the second conduction terminal. Furthermore, the transistors in each of the embodiments below are thin-film transistors having a channel layer formed of, for example, low-temperature polysilicon (hereinafter referred to as "LTPS-TFT"), but the present invention is not limited thereto, and some or all of the transistors used may be N-channel thin-film transistors having a channel layer formed of, for example, an oxide semiconductor containing indium, gallium, zinc, and oxygen (hereinafter referred to as "IGZO-TFT"). Moreover, in this specification, "connection" means "electrical connection" unless otherwise specified, and to the extent that it does not depart from the gist of the present invention, it includes not only direct connections but also indirect connections via other elements.

[0016] <1. First Embodiment> <1.1 Outline Configuration> Figure 1 is a block diagram showing the functional configuration of an organic EL display device according to the first embodiment. As shown in Figure 1, this organic EL display device comprises a display unit 10, a scanning-side drive circuit 20, a data signal line drive circuit (hereinafter also referred to as "data driver") 30 as a data-side drive circuit, and a display control circuit 40. In this embodiment, the scanning-side drive circuit 20 and the data driver 30 are included within a display panel 6 having the display unit 10. The scanning-side drive circuit 20 is typically monolithic; that is, the scanning-side drive circuit 20 is directly formed on a substrate on which the pixel circuit in the display unit 10 is formed. The data driver 30 may also be monolithic or not. Furthermore, the data driver 30 may be directly provided on the display panel 6, or it may be composed of a circuit within an IC chip mounted on the display panel 6.

[0017] Figure 2 shows the configuration of the display panel 6 of the organic EL display device according to this embodiment, and illustrates the connection relationships between the pixel circuits 15 and various wirings. As shown in Figure 2, the display unit 10 is provided with m data signal lines D1, D2, ..., Dm (where m is an integer of 2 or more) and n scan signal lines SC1, SC2, ..., SCn (where n is an integer of 2 or more) that intersect these lines as write control lines. m × n pixel circuits 15 are arranged in a matrix along the m data signal lines D1 to Dm and the n scan signal lines SC1 to SCn. Each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n scan signal lines SC1 to SCn (hereinafter, when distinguishing each pixel circuit 15, the pixel circuit corresponding to the i-th scan signal line SCi and the j-th data signal line Dj will be referred to as the "i-th row, j-th column pixel circuit" and will be denoted by the symbol "Pix(i,j)"). Furthermore, the display unit 10 is provided with n light emission control lines EM1, EM2, ..., EMn arranged along n scan signal lines SC1, SC2, ..., SCn, and n+1 initialization control lines DIS0, DIS1, DIS2, ..., DISn. The first initialization control line DIS0 is arranged along the first row of pixel circuits Pix(1,1) to Pix(1,m), the i-th initialization control line DISi of the n-1 initialization control lines DIS1 to DISn-1 is arranged along the i-th row of pixel circuits Pix(i,1) to Pix(i,m) and along the i+1-th row of pixel circuits Pix(i+1,1) to Pix(i+1,m) (i=1 to n-1), and the n-th initialization control line DISn is arranged along the n-th row of pixel circuits Pix(n,1) to Pix(n,m). Each pixel circuit 15 corresponds to one of the n light emission control lines EM1 to EMn, and also to one of the n initialization control lines DIS1 to DISn.

[0018] The display unit 10 is further equipped with power lines common to multiple pixel circuits. More specifically, it is equipped with power lines that supply a high-level power supply voltage ELVDD for driving the organic EL elements (hereinafter referred to as "high-level power lines," and denoted by the same symbol "ELLVDD" as the high-level power supply voltage), power lines that supply a low-level power supply voltage ELVSS for driving the organic EL elements (hereinafter referred to as "low-level power lines," and denoted by the same symbol "ELVSS" as the low-level power supply voltage), and power lines that supply an initialization voltage Vini (hereinafter referred to as "initialization voltage lines," and denoted by the same symbol "Vini" as the initialization voltage). Furthermore, in the frame area of ​​the display panel 6, which includes the display unit 10, where the scanning drive circuit 20 is located, a power line is provided to supply a gate high-level voltage VGH, which is a high-level fixed voltage, to the scanning drive circuit 20 (hereinafter referred to as the "gate high-level voltage line," and is indicated by the same symbol "VGH" as the gate high-level voltage), and a power line is provided to supply a gate low-level voltage VGL, which is a low-level fixed voltage, to the scanning drive circuit 20 (hereinafter referred to as the "gate low-level voltage line," and is indicated by the same symbol "VGL" as the gate low-level voltage).

[0019] <1.2 General Operation> The display control circuit 40 receives an input signal Sin from outside the display device according to this embodiment, which includes image information representing the image to be displayed and timing control information for image display. Based on this input signal Sin, it generates a data-side control signal Scd, a digital video signal DV, and a scanning-side control signal Scs. It outputs the data-side control signal Scd and the digital video signal DV to the data signal line drive circuit 30, and outputs the scanning-side control signal Scs to the scanning-side drive circuit 20.

[0020] The data signal line drive circuit 30 drives the plurality of data signal lines based on the data-side control signal Scd and the digital video signal DV from the display control circuit 40. The scanning-side drive circuit 20 receives the scanning-side control signal Scs from the display control circuit 40. This scanning-side control signal Scs includes a drive control signal SCCTL for scanning signal lines consisting of a write control start pulse signal GSPa and write control clock signals GCK1a and GCK2a, a drive control signal DISCTL for initialization control lines consisting of an initialization control start pulse signal GSPb and initialization control clock signals GCK1b and GCK2b, and a drive control signal EMCTL for light emission control lines consisting of a first light emission control start pulse signal ESP1, a second light emission control start pulse signal ESP2, and light emission control clock signals ECK1 and ECK2. The scanning drive circuit 20 drives the plurality of initialization control lines based on the initialization control line drive control signal DISCTL, drives the plurality of scanning signal lines based on the scanning signal line drive control signal SCCTL, and drives the plurality of light emission control lines based on the light emission control line drive control signal EMCTL.

[0021] By driving the data signal lines, initialization control lines, scan signal lines, and light emission control lines as described above, a data voltage corresponding to the value of each pixel in the image represented by the digital video signal DV is written to the pixel circuit corresponding to that pixel, and each pixel circuit emits light with a brightness corresponding to the data voltage written thereto.

[0022] <1.3 Operation of the Display Panel> Figure 3 is a timing chart for explaining the operation of the display panel 6 according to this embodiment. The data signal lines D1 to Dm are driven by the application of data signals D(1) to D(m) as shown in Figure 3 from the data signal line drive circuit 30. The scanning drive circuit 20 includes a DIS driver 211 as an initialization control circuit, an SC driver 212 as a write control circuit, and an EM driver (emission driver) 213 as a light emission control circuit. The initialization control lines DIS0 to DISn are driven by the application of initialization control signals DIS(0) to DIS(n) as shown in Figure 3 from the DIS driver 211 based on the initialization control start pulse signal GSPb and the initialization control clock signals GCK1b and GCK2b. The scanning signal lines SC1 to SCn are driven by the application of scanning signals SC(1) to SC(n) as write control signals, as shown in Figure 3, from the SC driver 212, based on the write control start pulse signal GSPa and the write control clock signals GCK1a and GCK2a. The light emission control lines EM1 to EMn are driven by the application of light emission control signals EM(1) to EM(n) as shown in Figure 3, from the EM driver 213, based on the first light emission control start pulse signal ESP1, the second light emission control start pulse signal ESP2, and the light emission control clock signals ECK1 and ECK2. The initialization control line DISi is active when its voltage level is at the level of an inactive signal (high level in this embodiment) and active when its voltage level is at the level of an active signal (low level in this embodiment) (i = 0 to n). The same applies to the light emission control line EMI and the scanning signal line SCi (i = 1 to n).

[0023] <1.4 Pixel Circuit Configuration and Operation> Figure 4 is a circuit diagram showing the configuration of the pixel circuit 15 in this embodiment, and more specifically, it is a circuit diagram showing the configuration of the pixel circuit 15 corresponding to the i-th scan signal line SCi and the j-th data signal line Dj, i.e., the i-th row and j-th column pixel circuit Pix(i,j) (1≦i≦n, 1≦j≦m). This pixel circuit 15 includes one organic EL element OL, which is a light-emitting element that functions as a display element, seven transistors T1 to T7 (hereinafter referred to as "first initialization transistor T1", "threshold compensation transistor T2", "write control transistor T3", "drive transistor T4", "power supply control transistor T5", "light emission control transistor T6", and "second initialization transistor T7"), and one holding capacitor Cst. The holding capacitor Cst is a capacitive element having two electrodes consisting of a first electrode and a second electrode. Transistors T1 to T7 are all P-channel type and are thin-film transistors (LTPS-TFTs) having a channel layer formed of, for example, low-temperature polysilicon. In the pixel circuit 15, transistors T1 to T3 and T5 to T7, other than the drive transistor T4, function as switching elements.

[0024] As shown in Figure 4, the pixel circuit Pix(i,j) is connected to the corresponding scan signal line SCi, the corresponding initialization control line DISi, the initialization control line immediately preceding the initialization control line DISi, i.e., the i-1th initialization control line DISi-1 (hereinafter, in explanations focusing on the pixel circuit, this will also be simply called the "previous initialization control line"), the corresponding light emission control line EMI, the corresponding data signal line Dj, the initialization voltage line Vini, the high-level power supply line ELVDD, and the low-level power supply line ELVSS.

[0025] The drive transistor T4 has a gate terminal connected to the high-level power line ELVDD via a holding capacitor Cst and to the initialization voltage line Vini via a first initialization transistor T1, a source terminal connected to the data signal line Dj via a write control transistor T3 and to the high-level power line ELVDD via a power supply control transistor T5, and a drain terminal connected to the gate terminal via a threshold compensation transistor T2 and to the anode of the organic EL element OL via a light emission control transistor T6. The anode of the organic EL element OL is connected to the initialization voltage line Vini via a second initialization transistor T7, and the cathode of the organic EL element OL is connected to the low-level power line ELVSS. The gate terminals of the write control transistor T3 and the threshold compensation transistor T2 are connected to the scan signal line SCi, the gate terminals of the power supply control transistor T5 and the light emission control transistor T6 are connected to the light emission control line EMI, the gate terminal of the first initialization transistor T1 is connected to the pre-initialization control line DISi-1, and the gate terminal of the second initialization transistor T7 is connected to the initialization control line DISi.

[0026] Next, the operation of the pixel circuit 15 will be explained. Figure 5 is a timing chart for explaining the operation of the pixel circuit 15 shown in Figure 4. In this timing chart, the period before time t01 and the period after time t06 are the light emission period, and the period from time t01 to t06 is the non-light emission period.

[0027] Immediately before time t01, the scan signal SC(i) and initialization control signals DIS(i-1) and DIS(i) are at a high level (H level), and the light emission control signal EM(i) is at a low level (L level). At this time, the write control transistor T3, the first initialization transistor T1, and the second initialization transistor T7 are in the off state, the power supply control transistor T5 and the light emission control transistor T6 are in the on state, and the organic EL element OL is emitting light with a brightness corresponding to the amount of drive current.

[0028] At time t01, the light emission control signal EM(i) supplied to the pixel circuit Pix(i,j) via the light emission control line EMI changes from L level to H level at time t01. As a result, both the power supply control transistor T5 and the light emission control transistor T6 are turned off. Consequently, the supply of current to the organic EL element OL is cut off, and the organic EL element OL turns off.

[0029] Subsequently, at time t02, the initialization control signal DIS(i-1), which is supplied to the pixel circuit Pix(i,j) via the pre-initialization control line DISi-1 (hereinafter referred to as the "pre-initialization control signal"), changes to the L level. As a result, the first initialization transistor T1 turns on. Consequently, the voltage Vg at the gate terminal of the drive transistor T4 is initialized to the initialization voltage Vini. Next, at time t03, the initialization control signal DIS(i) changes to the L level. As a result, the second initialization transistor T7 turns on. Consequently, the voltage Va at the anode of the organic EL element OL is initialized to the initialization voltage Vini.

[0030] Subsequently, at time t04, the pre-initialization control signal DIS(i-1) changes from L level to H level. This turns off the first initialization transistor T1. Also at time t04, the scan signal SC(i) changes from H level to L level. This turns on both the write control transistor T3 and the threshold compensation transistor T2. As a result, the data signal D(j) is supplied from the data signal line Dj to the first electrode of the holding capacitor Cst via the write control transistor T3, the drive transistor T4, and the threshold compensation transistor T2. This charges the holding capacitor Cst, and a voltage is written to the holding capacitor that is the data voltage Vdata, which is the voltage of the data signal D(j), with threshold compensation applied by the threshold voltage Vth of the drive transistor T4.

[0031] Subsequently, at time t05, the scan signal SC(i) changes from L level to H level. As a result, both the write control transistor T3 and the threshold compensation transistor T2 turn off. Also at time t05, the initialization control signal DIS(i) changes from L level to H level. As a result, the second initialization transistor T7 turns off.

[0032] Subsequently, at time t06, the light emission control signal EM(i) changes from the H level to the L level. As a result, both the power supply control transistor T5 and the light emission control transistor T6 are turned on, and a drive current corresponding to the holding voltage of the holding capacitor Cst, i.e., a drive current corresponding to the threshold-compensated data voltage, is supplied to the organic EL element OL. As a result, the organic EL element OL emits light with a brightness corresponding to the amount of this drive current. From then on, the organic EL element OL maintains its light emission state until the next time the light emission control signal EM(i) changes from the L level to the H level.

[0033] <1.5 Foldable Configuration and Partial Concealment Function> Next, with reference to Figures 6 and 7, the foldable configuration in this embodiment and the partial concealment function based on this configuration will be described.

[0034] Figure 6 is a perspective view of the organic EL display device according to this embodiment. As shown in Figure 6, the display unit 10 is provided with a folding portion 150, and the display unit 10 has a first display area 110 and a second display area 120 separated by the folding portion 150. This makes it possible to fold the display panel 6 so that the front of the first display area 110 and the front of the second display area 120 face each other, or so that the back of the first display area 110 and the back of the second display area 120 face each other. In addition, a frame area 60 is provided so as to surround the first display area 110 and the second display area 120.

[0035] Figure 7 is a block diagram illustrating the configuration of the scanning drive circuit 20 in the display panel 6 in this embodiment. As shown in Figure 7, the scanning drive circuit 20 is provided in the frame area 60 of the display panel 6 that corresponds to one end of the scanning signal lines SC1 to SCn, initialization control lines DIS0 to DISn, and light emission control lines EM1 to En (the right-hand frame area in the figure). This scanning drive circuit 20 includes a DIS driver 211 as an initialization control circuit, an SC driver 212 as a write control circuit (scanning signal line drive circuit), and an emission driver (EM driver) as a light emission control circuit.

[0036] Of these drivers, the EM driver 213 is separated into an upper EM driver 213U as a first light emission control circuit and a lower EM driver 213L as a second light emission control circuit, with the boundary being the position corresponding to the folding portion 150 in the display panel 6. The upper EM driver 213U and the lower EM driver 213L are each configured to operate as independent shift registers. That is, the upper EM driver 213U and the lower EM driver 213L are supplied with a common two-phase clock signal for light emission control (hereinafter simply referred to as the "light emission control clock signal") ECK1, ECK, but the start pulse signal ESP1 to be supplied to the first stage of the upper EM driver 213U and the start pulse signal ESP2 to be supplied to the first stage of the lower EM driver 213L are configured to be supplied as independent signals. The upper EM driver 213U operates as a shift register based on the first light emission control start pulse signal ESP1 and the light emission control clock signals ECK1 and ECK2, and drives the light emission control lines EM1 to EMna in the first display area (upper display area) 110. The lower EM driver 213L operates as a shift register based on the second light emission control start pulse signal ESP2 and the light emission control clock signals ECK1 and ECK2, and drives the light emission control lines EMna+1 to EMn in the second display area 120.

[0037] The SC driver 212 operates as a single shift register based on the write control start pulse signal GSPa and the write control two-phase clock signals GCK1a and GCK2a, and drives the scan signal lines SC1 to SCn in the first display area 110 and the second display area 120. The DIS driver 211 also operates as a single shift register based on the initialization control start pulse signal GSPb and the initialization control two-phase clock signals GCK1b and GCK2b, and drives the initialization control lines DIS0 to DISn in the first display area 110 and the second display area 120.

[0038] <1.5.1 Configuration and Operation of Emission Driver> Figure 8 is a block diagram showing the configuration of the EM driver 213. This EM driver 213 includes a shift register that implements the upper EM driver 213U and a shift register that implements the lower EM driver 213L.

[0039] Each stage unit circuit 24(i) in the upper EM driver 213U and the lower EM driver 213L includes input terminals for receiving the shift signal S, the first input clock signal CK1, the second input clock signal CK2, the gate high-level voltage VGH, the gate low-level voltage VGL, and the reset signal INITB, respectively, and an output terminal for outputting the light emission control signal EM(i) as the output signal OUT. The reset signal INITB is kept at an L level for a predetermined period of time, such as when the display device is started up, to initialize each unit circuit 24(1) to 24(N) of the EM driver 213, and is then maintained at an H level.

[0040] In the first stage unit circuit 24(1) of the upper EM driver 213U, the first light emission control start pulse signal ESP1 is provided as a shift signal S, the first light emission control clock signal ECK1 is provided as the first input clock signal CK1, and the second light emission control clock signal ECK2 is provided as the second input clock signal CK2. On the other hand, in the first stage unit circuit 24(na+1) of the lower EM driver 213L, the second light emission control start pulse signal ESP2 is provided as a shift signal S, the first light emission control clock signal ECK1 is provided as the first input clock signal CK1, and the second light emission control clock signal ECK2 is provided as the second input clock signal CK2. However, na is assumed to be an even number. Furthermore, in the upper EM driver 213U and the lower EM driver 213L, the odd-numbered unit circuits 24 (iod) are supplied with the first light emission control clock signal ECK1 as the first input clock signal CK1 and the second light emission control clock signal ECK2 as the second input clock signal CK2, while the even-numbered unit circuits 24 (iev) are supplied with the second light emission control clock signal ECK2 as the first input clock signal CK1 and the first light emission control clock signal ECK1 as the second input clock signal CK2. The output signal OUT from each unit circuit 24(i) in the EM driver 213 is applied to the light emission control line EMI as the light emission control signal EM(i) (1 ≤ i ≤ n), and the output signal OUT from each unit circuit 24(k), excluding the final stage unit circuits 24(na) and 24(n) of the upper EM driver 213U and the lower EM driver 213L, is given to the next stage unit circuit 24(k+1) as a shift signal S (1 ≤ k ≤ na-1 or na+1 ≤ k ≤ n-1).

[0041] In an EM driver 213 configured as described above, the EM driver 213 can be operated as a single shift register by appropriately setting the timing of the first light emission control start pulse signal ESP1 relative to the second light emission control start pulse signal ESP2. For example, if na = 1280, and light emission control lines EM1 to EM1280 are arranged in the first display area 110, and light emission control lines EM1281 and later are arranged in the second display area 120, then by supplying the first light emission control start pulse signal ESP1 and the second light emission control start pulse signal ESP2 and light emission control clock signals ECK1 and ECK2 to the EM driver 213 as shown in Figure 9A, the EM driver 213 can be operated as a single shift register.

[0042] The organic EL display device according to this embodiment has a full-screen display mode as a first operating mode in which an image is displayed in both the first display area (area corresponding to the upper screen) 110 and the second display area (area corresponding to the lower screen) 120 of the display unit 10, and a half-screen display mode as a second operating mode in which an image is displayed in one of the first display area 110 and the second display area 120 of the display unit 10 and the other is hidden. For the sake of explanation, in the following, in the half-screen display mode, an image is displayed in the first display area 110 and the second display area is hidden (displayed in black).

[0043] The display mode, whether full-screen or half-screen, is specified by mode information based on a predetermined user operation or by mode information included in an external input signal Sin. The display control circuit 40 controls the scanning drive circuit 20 according to the specified display mode. Figure 9A is a timing chart illustrating the operation of the EM driver 213 in full-screen mode, and Figure 9B is a timing chart illustrating the operation of the EM driver 213 in half-screen mode. The operation of the EM driver 213 with the configuration shown in Figure 8 will be described below with reference to Figures 9A and 9B. In the following, the number of stages in the upper EM driver 213U and the lower EM driver 213L will be set to 1280, and the number of light emission control lines EMI will be set to 1280 × 2 = 2560.

[0044] In the full-screen display mode, the first light emission control start pulse signal ESP1 and the second light emission control start pulse signal ESP2 shown in FIG. 9A are respectively supplied to the upper EM driver 213U and the lower EM driver 213L as shown in FIG. 8, and the first light emission control clock signal ECK1 and the second light emission control clock signal ECK2 shown in FIG. 9A are supplied to the upper EM driver 213U and the lower EM driver 213L as shown in FIG. 8. By such light emission control start pulse signals ESP1, ESP2 and light emission control clock signals ECK1, ECK2, the upper EM driver 213U and the lower EM driver 213L operate as one shift register, and the EM driver 213 outputs light emission control signals EM(1) to EM(n) that sequentially become the H level (inactive state) at predetermined intervals as shown in FIG. 9A, and applies them to the light emission control lines EM1 to EMn respectively.

[0045] The SC driver 212 generates scanning signals SC(1) to SC(n) as shown in FIG. 3 based on the writing control start pulse signal GSPa and the writing control clock signals GCK1a, GCK2a with the same configuration as the conventional one, and applies them to the scanning signal lines SC1 to SCn respectively. Also, the DIS driver 211 generates initialization control signals DIS(0) to DIS(n) based on the initialization control start pulse signal GSPb and the initialization control clock signals GCK1b, GCK2b with the same configuration as the conventional one, and applies them to the initialization control lines DIS0 to DISn respectively. Further, the data signal line driving circuit 30 generates data signals D(1) to D(m) representing the image to be displayed at the timing as shown in FIG. 3 based on the data-side control signal Scd and the digital video signal DV with the same configuration as the conventional one, and applies them to the data signal lines D1 to Dm respectively.

[0046] In half-screen display mode, the same first light emission control start pulse signal ESP1 as in full-screen display mode is supplied to the upper EM driver 213U, but the second light emission control start pulse signal ESP2 supplied to the lower EM driver 213L is fixed at the H level (inactive state) as shown in Figure 9B. As a result, the upper EM driver 213U operates as a single shift register with the first light emission control start pulse signal ESP1 and the light emission control clock signals ECK1 and ECK2, and outputs light emission control signals EM(1) to EM(na) that are sequentially at the H level for predetermined periods, as shown in Figure 9B, and applies them to the light emission control lines EM1 to EMna in the first display area 110, respectively (na = 1280). In contrast, the lower EM driver 213L outputs light emission control signals EM(na+1) to EM(n) fixed at the H level, as shown in Figure 9B, and applies them to the light emission control lines EMna+1 to EMn in the second display area 120, respectively (na+1 = 1281, n = 2560). In the configuration shown in Figure 8, each unit circuit 24(1) to 24(n) is configured such that the output signals EM(1) to EM(n) as OUT are at the H level in the initial state (initialized by the reset signal INITB) (see, for example, Figure 10 described later).

[0047] As shown in Figure 9B, in this embodiment, in half-screen display mode, the light emission control clock signals ECK1 and ECK2, which are supplied in common to the upper EM driver 213U and the lower EM driver 213L, are stopped for periods other than those necessary for driving the light emission control lines EM1 to EMna in the first display area 110 where the image should be displayed. On the other hand, the SC driver 212, the DIS driver 211, and the data signal line drive circuit 30 operate in half-screen display mode in the same way as in full-screen display mode. However, since the second display area 120 is in a non-display state, the data signal line drive circuit 30 may set the data signals D(1) to D(m) to a fixed level (for example, the level of the data voltage for black display) or a high impedance state during the period when it should output the data signals D(1) to D(m) to the data signal lines D1 to Dm to write to the pixel circuit 15 in the second display area 120.

[0048] In the half-screen display mode as described above, since the emission control signals EM(na + 1) to EM(n) fixed at the H level are respectively applied to the emission control lines EMna+1 to EMn in the second display area 120 by the lower EM driver 213L (na + 1 = 1281, n = 2560), the emission control transistors T6 and the power supply control transistors T5 included in each pixel circuit 15 in the second display area 120 are maintained in the off state (see FIG. 3). As a result, the second display area becomes a non-display state (non-emission state), that is, black display.

[0049] <1.5.2 Configuration and Operation of Unit Circuits in Emission Driver> FIG. 10 is a circuit diagram showing a configuration example of unit circuits 24 in each stage of the upper EM driver 213U and the lower EM driver 213L operating as a shift register in the present embodiment. As such unit circuits 24(i) (i = 1 to n), the unit circuits 24 as shown in FIG. 10 can be used.

[0050] As shown in FIG. 10, this unit circuit 24 includes 13 transistors M1 to M13 and 3 capacitors C1 to C3. These transistors M1 to M13 are P-channel type LTPS-TFTs, and all of them function substantially as switching elements. Note that the transistor M12 has a dual-gate structure. This unit circuit 24 also has an input terminal connected to a gate high-level voltage line VGH for supplying a gate high-level voltage VGH and an input terminal connected to a gate low-level voltage line for supplying a gate low-level voltage VGL, in addition to an input terminal 51 for receiving a shift signal S, an input terminal 52 for receiving a first input clock signal C K1, an input terminal 53 for receiving a second input clock signal C K2, and an input terminal 54 for receiving a reset signal INITB, and has an output terminal 59 for outputting an emission control signal EM(i) as an output signal OUT.

[0051] This unit circuit 24 includes a first internal node N1 connected to the gate low-level voltage line VGL via transistor M2 and to the gate terminal of transistor M6 via transistor M3; a second internal node N2 connected to the gate terminal of transistor M9 and to the gate high-level voltage line VGH via first capacitor C1; a third internal node N3 connected to the input terminal 51 of the shift signal S via transistor M1; and a fourth internal node N4 connected to the gate terminal of transistor M10 and to the third internal node N3 via transistor M11. In this unit circuit 24, the first internal node N1 is connected to the input terminal 52 of the first input clock signal via transistor M12 and to the gate terminal of transistor M4. The second internal node N2 is connected to the input terminal 53 of the second input clock signal CK2 via transistors M7 and M6 in order, the source terminal of transistor M6 is connected to the gate terminal of transistor M6 via capacitor C2, and the gate terminal of transistor M7 is connected to the input terminal 53 of the second input clock signal CK2. Furthermore, the second internal node N2 is connected to the gate high-level voltage line VGH via transistor M8 and to the gate low-level voltage line VGL via transistor M13, with the gate terminal of transistor M13 connected to the input terminal 54 of the reset signal INITB. The third internal node N3 is connected to the gate terminal of transistor M8 and to the gate terminal of transistor M12, and is also connected to the gate high-level voltage line VGH via transistors M5 and M4 in order, with the gate terminal of transistor M5 connected to the input terminal 53 of the second input clock signal CK2. The fourth internal node N4 is connected to the input terminal 53 of the second input clock signal CK2 via capacitor C3.

[0052] The output terminal 59 of this unit circuit 24 has its gate terminal connected to the gate high-level voltage line VGH via transistor M9 connected to the second internal node N2, and its gate terminal connected to the gate low-level voltage line VGL via transistor M10 connected to the fourth internal node N4.

[0053] Figure 11 is a signal waveform diagram illustrating the operation of the unit circuit 24 configured as described above. When the unit circuit 24 is supplied with a shift signal S, a first input clock signal CK1, and a second input clock signal CK2, respectively, with waveforms as shown in Figure 11, the voltage levels of the first internal node N1 to the fourth internal node N4 change as shown in Figure 11, and an output signal OUT with a waveform as shown in Figure 11 is output from the output terminal 59. That is, as shown in Figure 11, when the shift signal S is a signal that is at a high level for a period t12 to t14 including two pulses p1 and p3 in the first input clock signal CK1 and one pulse p2 in the second input clock signal CK2, an output signal OUT is output that is at a high level for a period t13 to t15 including one pulse p3 in the first input clock signal CK1 and two pulses p2 and p4 in the second input clock signal CK2.

[0054] The EM driver 213 in this embodiment is realized by using the unit circuit 24 in Figure 10, which operates in this manner, as each unit circuit 24(i) (i=1 to n) of the EM driver 213 configured in Figure 8. That is, in the EM driver 213 using the unit circuit 24 in Figure 10, when the first stage unit circuit 24(1) of the upper EM driver 213U is given a first light emission control start pulse signal ESP1 as shown in Figure 9A, and the first stage unit circuit 24(na+1) of the lower EM driver 213L is given a second light emission control start pulse signal ESP2 as shown in Figure 9A, light emission control signals EM(1) to EM(n) as shown in Figure 9A are obtained as the output signals OUT of the unit circuits 24(1) to 24(n) (n=2560, na=1280). This realizes the function of the EM driver 213 in the full-screen display mode of this embodiment.

[0055] On the other hand, in the half-screen display mode of this embodiment, in the EM driver 213 using the unit circuit 24 of Figure 10, the first stage unit circuit 24(1) of the upper EM driver 213U is supplied with a first light emission control start pulse signal ESP1 as shown in Figure 9B, and the second light emission control start pulse signal ESP2 supplied to the lower EM driver 213L is fixed to an H level as shown in Figure 9B. Thus, the upper EM driver 213U operates as a single shift register with the first light emission control start pulse signal ESP1 and the light emission control clock signals ECK1 and ECK2, and, similar to the operation shown in Figure 9A, light emission control signals EM(1) to EM(na) as shown in Figure 9B are obtained as the output signals OUT of the unit circuits 24(1) to 24(na) (na = 1280). In response, the lower EM driver 213L outputs light emission control signals EM(na+1) to EM(n) fixed to the H level, as shown in Figure 9B (ma+1 = 1281, n = 2560). Since each unit circuit 24(i) is configured as shown in Figure 10, when initialized by the reset signal INITB and the start pulse signal ESP2 for second light emission control is fixed to the H level, the output signal OUT(EM(i)) of each unit circuit 24(i) is maintained at the H level. As a result, as shown in Figure 12, an image can be displayed in the first display area 110 on the display panel 6 while the second display area 120 is hidden (displayed in black).

[0056] <1.6 Effects> According to the above embodiment, in a foldable organic EL display device, in full-screen display mode, the first light emission control start pulse signal ESP1 and the second light emission control start pulse signal ESP2, as shown in Figure 9A, are supplied to the upper EM driver 213U and the lower EM driver 213L, respectively. As a result, the upper EM driver 213U and the lower EM driver 213L operate as a single shift register to drive the light emission control lines EM1 to EMn, and an image is displayed in both the first display area 110 and the second display area 120, which are separated by the position of the folding part 150 in the display unit 10. On the other hand, in half-screen display mode, as shown in Figure 9B, the first light emission control start pulse signal ESP1 is supplied to the upper EM driver 213U in the same way as in full-screen display mode, but the second light emission control start pulse signal ESP2 is fixed at the H level. As a result, the light emission control signals EM(na+1) to EM(n) in the second display area 120 are fixed at the H level, and each pixel circuit 15 in the second display area 120 is kept off. Consequently, the second display area 120 is kept in a non-display state (black display). The second display area 120, thus in a non-display state, is used to place a keyboard. In other words, according to this embodiment, in a foldable organic EL display device, the function of placing a keyboard is realized by the above-described half-screen display mode.

[0057] In a foldable organic EL display device, it is conceivable to use a scanning-side drive circuit (EM driver, SC driver, DIS driver) with the same configuration as conventional devices to write a black display data voltage to each pixel circuit 15 in one of the first display area 110 and the second display area 120 (the second display area 120 in the above example) in order to place a keyboard. In this case, since the second display area 120 is also driven in the same way as normal image display, the power consumption of the black display (off state) pixel circuit 15 is reduced, but the power consumption of the drive circuit becomes the same as when displaying an image on the entire screen. In contrast, according to this embodiment, in half-screen display mode, the operation of the lower EM driver 231L is substantially stopped, so in addition to reducing the power consumption of the off state pixel circuit 15, the power consumption of the drive circuit is also reduced. Furthermore, according to this embodiment, as shown in Figure 9B, in half-screen display mode, the light emission control clock signals ECK1 and ECK2, which are supplied in common to the upper EM driver 213U and the lower EM driver 213L, are stopped for periods other than those necessary for driving the light emission control lines EMna+1 to EMn in the first display area 110 where the image should be displayed. This also reduces power consumption due to charging and discharging based on the light emission control clock signals ECK1 and ECK2.

[0058] Furthermore, in this embodiment, as shown in Figures 7 and 8, compared to the conventional configuration of the EM driver, only a configuration for supplying the second light emission control start pulse signal ESP2 to the lower EM driver 213L is added, and the signal line for the second light emission control start pulse signal ESP2 can be realized with wiring of about 5 μm in width. Therefore, the EM driver 213 in this embodiment, as shown in Figure 8, can be realized without significantly increasing the circuit area for arranging the scanning side drive circuit 20 in the frame area of ​​the display panel 6.

[0059] <1.7 Modification of the First Embodiment> In the first embodiment described above, the EM driver 213 is configured such that the first light emission control start pulse signal ESP1 and the second light emission control start pulse signal ESP2 are supplied as shift signals S to the first stage unit circuits 24(1) and 24(na) of the upper EM driver 213U and the lower EM driver 213L, respectively, as independent signals, as shown in Figure 8. This makes it possible to appropriately switch the operating mode of the foldable display device between full-screen display mode and half-screen display mode by changing the change timing and level of the second light emission control start pulse signal ESP2 (see Figures 9A and 9B).

[0060] Alternatively, the EM driver 213 may be configured such that the light emission control start pulse signal ESP is supplied as a shift signal S only to the first stage of the upper EM driver 213U, and the signal to be supplied as a shift signal S to the first stage of the lower EM driver 213L is switched between the output signal OUT of the final stage of the upper EM driver 213U and an inactive level (H level) voltage. Hereinafter, an organic EL display device equipped with an EM driver 213 configured in this way will be described as a modification of the first embodiment. Since the other configurations in this modification are the same as in the first embodiment, the same or corresponding parts are denoted by the same reference numerals and detailed descriptions are omitted.

[0061] Figure 13 is a block diagram showing the configuration of the EM driver 213b in this modified example. As shown in Figure 13, this EM driver 213b is also composed of an upper EM driver 213bU and a lower EM driver 213bL, similar to the EM driver 213 in the first embodiment described above. The drive control signal EMCTL for the light emission control line generated by the display control circuit 40 consists of one light emission control start pulse signal ESP and light emission control clock signals ECK1 and ECK2. The light emission control start pulse signal ESP is provided as a shift signal S to the first stage unit circuit 24(1) of the upper EM driver 213bU, and the light emission control clock signals ECK1 and ECK2 are provided to each unit circuit 24(1) to 24(n) of the EM driver 213b.

[0062] In this modified example, the display control circuit 40 includes a switching circuit 28 for switching the connection destination of the input terminal of the shift signal S of the first-stage unit circuit 24(na+1) in the lower-stage EM driver 213bL between the output terminal 59 of the final-stage unit circuit 24(na) in the upper-stage EM driver 213bU and the gate high-level voltage line VGH. This allows the second light emission control start pulse signal ESP2, which should be given as the shift signal S to the first stage of the lower-stage EM driver 213bL, to be switched between the output signal OUT of the final stage of the upper-stage EM driver 213U and the gate high-level voltage VGH. The switching control signal Msw, which is the control signal of this switching circuit 28, is generated in the display control circuit 40 and provided from the display control circuit 40 to the switching circuit 28. This switching control signal Msw causes the input terminal of the shift signal S of the first-stage unit circuit 24(na+1) in the lower-stage EM driver 213bL to be connected to the output terminal of the final-stage unit circuit 24(na) of the upper-stage EM driver 213bU in full-screen display mode, and to the gate high-level voltage line VGH in half-screen display mode. Therefore, in full-screen display mode, the output signal OUT(EM(na)) of the final-stage unit circuit 24(na) of the upper-stage EM driver 213bU is applied to the input terminal of the shift signal S of the first-stage unit circuit 24(na+1) in the lower-stage EM driver 213bL, and in half-screen display mode, the gate high-level voltage VGH as an inactive level voltage is applied.

[0063] In this modified example, the EM driver 213b generates light emission control signals EM(1) to EM(n) as shown in Figure 9A in full-screen display mode, and generates light emission control signals EM(1) to EM(n) as shown in Figure 9B in half-screen display mode. Therefore, the same effects as in the first embodiment can be obtained in this modified example as well.

[0064] In the first embodiment described above, the pulses in the light emission control start pulse signals ESP1 and ESP2, i.e., the start pulses, are provided as shift signals S to the first stage of the upper EM driver 213U and the first stage of the lower EM driver 213L. The start pulse in this shift signal S is a pulse with a time width that includes two pulses p1 and p3 from the first input clock signal CK1 and one pulse p2 from the second input clock signal CK2 (see Figure 11). However, the start pulse is not limited to such a time width, and light emission control start pulse signals ESP1 and ESP2 that include a start pulse with a longer time width may also be used.

[0065] <2. Second Embodiment> Next, a second embodiment will be described. The same reference numerals will be used for parts of the second embodiment that are the same as or correspond to those of the first embodiment described above, and below, only the differences from the first embodiment will be described.

[0066] Figure 14 is a block diagram illustrating the configuration of the scanning drive circuit 20 provided in the display panel 6 in this embodiment. In this embodiment as well as in the first embodiment described above, the scanning drive circuit 20 is provided in the frame region 60 of the display panel 6, which corresponds to one end of the scanning signal lines SC1 to SCn, the initialization control lines DIS0 to DISn, and the light emission control lines EM1 to En. This scanning drive circuit 20 includes a DIS driver 211 as an initialization control circuit, an SC driver 212 as a write control circuit (scanning signal line drive circuit), and an EM driver as a light emission control circuit. As shown in Figure 14, in this embodiment, unlike the first embodiment, the EM driver 213 is separated into an upper EM driver 213U and a lower EM driver 213L at a position corresponding to the bent portion 150 in the display panel 6. In addition, the SC driver 212 is separated into an upper SC driver 212U as a first scan signal line drive circuit and a lower SC driver 212L as a second scan signal line drive circuit at a position corresponding to the bent portion 150. Similarly, the DIS driver 211 is separated into an upper DIS driver 211U as a first initialization control circuit and a lower DIS driver 211L as a second initialization control circuit at a position corresponding to the bent portion 150. In this embodiment, both the SC driver 212 and the DIS driver 211 are separated into upper and lower drivers. However, in this embodiment, only one of the SC driver 212 or the DIS driver 211 may be separated into an upper and lower driver, and the other may be a driver with the same configuration as in the conventional example.

[0067] The EM driver 213 in this embodiment is configured as shown in Figure 8, similar to the first embodiment, and operates in the same manner as the EM driver 213 in the first embodiment (see Figures 9A and 9B).

[0068] <2.1 SC Driver as a Write Control Circuit> Figure 15 is a block diagram showing the configuration of a shift register that realizes the SC driver 212 in this embodiment. As shown in Figure 15, the upper SC driver 212U is configured by unit circuits 24a(1) to 24a(na), and the lower SC driver 212L is configured by unit circuits 24a(na+1) to 24a(n). The first stage unit circuit 24a(1) of the upper SC driver 212U is supplied with a shift signal S, which is the first write control start and pulse signal GSP1a. The first stage unit circuit 24a(na+1) of the lower SC driver 212L is supplied with a shift signal S, which is the second write control start pulse signal GSP2a. All unit circuits 24a(1) to 24a(n) are supplied with a two-phase clock signal for write control (hereinafter simply referred to as "write control clock signal") GCK1a and GCK2a, which are the first input clock signal CK1 and second input clock signal CK2, respectively. The output signal OUT of each stage unit circuit 24a(i) of the SC driver 212 is applied to the scan signal line SCi as a scan signal SC(i) (i=1 to n).

[0069] As can be seen by comparing Figure 15 with Figure 8, this SC driver 212 has substantially the same configuration as the EM driver 213. However, the first write control start pulse signal GSP1a and the second write control start pulse signal GSP2a are different from the first light emission control start pulse signal ESP1 and the second light emission control start pulse signal ESP2, and the configuration of the unit circuit 24a(i) in this embodiment is also different from the configuration of the unit circuit 24(i) in the first embodiment described above. For this reason, scan signals SC(1) to SC(n) with waveforms different from the light emission control signals EM(1) to EM(n) are generated.

[0070] Figure 16A is a timing chart illustrating the operation of the SC driver 212 in full-screen mode as shown in Figure 15, and Figure 16B is a timing chart illustrating the operation of the SC driver 212 in half-screen mode as shown in Figure 15. The operation of the SC driver 212 with the configuration shown in Figure 15 will be explained below with reference to Figures 16A and 16B. In the following explanation, the number of stages na for the upper SC driver 212U and the lower SC driver 212L will be set to 1280, and the number of light emission control lines EMI will be set to 1280 × 2 = 2560.

[0071] In full-screen mode, the first write control start pulse signal GSP1a and the second write control start pulse signal GSP2a shown in Figure 16A are supplied to the upper SC driver 212U and the lower EM driver 213L respectively as shown in Figure 15, and the first write control clock signal GCK1a and the second write control clock signal GCK2a shown in Figure 16A are supplied to the upper SC driver 212U and the lower SC driver 212L as shown in Figure 15. With these write control start pulse signals GSP1a, GSP2a and write control clock signals GCK1a, GCK2a, the upper SC driver 212U and the lower SC driver 212L operate as a single shift register. As shown in Figure 16A, the SC driver 212 outputs scan signals SC(1) to SC(n) that are sequentially L level (active state) for predetermined periods as write control signals, and applies them to scan signal lines SC1 to SCn respectively (n = 2560).

[0072] In half-screen display mode, the same first write control start pulse signal GSP1a as in full-screen display mode is supplied to the upper SC driver 212U, but the second write control start pulse signal GSP2a supplied to the lower SC driver 212L is fixed to the H level as shown in Figure 16B. As a result, the upper SC driver 212U operates as a single shift register with the first write control start pulse signal GSP1a and the write control clock signals GCK1a and GCK2a, and outputs scan signals SC(1) to SC(na) that are sequentially at the L level (active state) for a predetermined period of time as write control signals, as shown in Figure 16B, and applies them to the scan signal lines SC1 to SCna in the first display area 110, respectively (na = 1280). In contrast, the lower SC driver 212L outputs scanning signals SC(na+1) to SC(n) fixed at the H level (inactive state), as shown in Figure 16B, and applies them to the scanning signal lines SCna+1 to SCn in the second display area 120, respectively (na+1 = 1281, n = 2560). Note that each unit circuit 24a(na+1) to 24a(n) of the lower SC driver 212L is configured such that the output signals SC(1) to SC(n) as OUT are at the H level in the initial state (initialized by the reset signal INITB) (see, for example, Figure 17 described later).

[0073] As shown in Figure 16B, in this embodiment, in half-screen display mode, the write control clock signals GCK1a and GCK2a, which are supplied in common to the upper SC driver 212U and the lower SC driver 212L, are stopped during periods other than those necessary for driving the scan signal lines SC1 to SCna in the first display area 110 where the image should be displayed.

[0074] <2.2 Configuration and Operation of Unit Circuits in SC Drivers> Figure 17 is a circuit diagram showing an example of the configuration of unit circuits 24a corresponding to each stage in the upper SC driver 212U and lower SC driver 212L that operate as shift registers in this embodiment. As unit circuits 24a(i) (i=1 to n) that constitute the upper SC driver 212U and lower SC driver 212L as described above, the unit circuits 24a shown in Figure 17 can be used.

[0075] As shown in Figure 17, this unit circuit 24a comprises nine transistors M21 to M29, two capacitors C21 and C22, and one resistor R1. Transistors M21 to M29 are P-channel type LTPS-TFTs, and all of them function substantially as switching elements. In addition to an input terminal connected to the gate high-level voltage line VGH that supplies the gate high-level voltage VGH and an input terminal connected to the gate low-level voltage line that supplies the gate low-level voltage VGL, this unit circuit 24a also has an input terminal 61 for receiving a shift signal S, an input terminal 62 for receiving a first input clock signal CK1, an input terminal 63 for receiving a second input clock signal CK2, and an input terminal 64 for receiving a reset signal INITB, and an output terminal 69 for outputting a scan signal SC(i) as an output signal OUT.

[0076] This unit circuit 24a includes a first internal node N21 connected to the gate low-level voltage line VGL via transistor M22, a second internal node N22 connected to the gate terminal of transistor M28 and also connected to the first internal node N21 via transistor M26, and a third internal node N23 connected to the gate terminal of transistor M27 and also connected to the first terminal of resistor R1, the second terminal of resistor R1 being connected to the gate low-level voltage line VGL via transistor M5. Furthermore, the first internal node N21 is connected to the gate high-level voltage line VGH via transistor M24, and the second internal node N22 is connected to the output terminal 69 via capacitor C22. Furthermore, the third internal node N23 is connected to the gate high-level voltage line VGH via transistor M21 and also to the gate high-level voltage line VGH via transistor M23, and is connected to the gate low-level voltage line VGL via transistor M29, and is connected to the gate terminal of transistor M24, and is connected to the gate high-level voltage line VGH via capacitor C21.

[0077] Figure 18 is a signal waveform diagram illustrating the operation of the unit circuit 24a of Figure 17 configured as described above. When signals S, CK1, and CK2, with waveforms as shown in Figure 18, are applied to this unit circuit 24a as a shift signal S, a first input clock signal CK1, and a second input clock signal CK2, the voltage levels of the first internal node N21 to the third internal node N23 in the unit circuit 24a change as shown in Figure 18, and an output signal OUT with a waveform as shown in Figure 18 is output from the output terminal 69. That is, as shown in Figure 18, when a signal including a pulse corresponding to one pulse p21 in the first input clock signal CK1 is applied as the shift signal S, a signal including one pulse p22 in the second input clock signal CK2 is output as the output signal OUT.

[0078] By using the unit circuit 24a in Figure 17, which operates in this manner, as each unit circuit 24a(i) (i=1 to n) of the SC driver 212 configured in Figure 15, the SC driver 212 in this embodiment, which operates as shown in Figures 16A and 16B, is realized (n=2560, na=1280).

[0079] <2.3 DIS Driver as Initialization Control Circuit> Figure 19 is a block diagram showing the configuration of a shift register that realizes the DIS driver 211 as an initialization control circuit in this embodiment.

[0080] The DIS driver 211 in this embodiment is also implemented with a configuration substantially similar to that of the SC driver 212, namely the configuration shown in Figure 19. However, when the pixel circuit 15 with an internal compensation method as shown in Figure 4 is used, the period of the active state (L level) of the initialization control signal DIS(i) (i=0 to n) is set to be longer than the period of the active state (L level) of the scan signal SC(i) (i=1 to n) as a write control signal. For this reason, at least the initialization control clock signals GCK1b and GCK2b are different from the write control clock signals GCK1a and GCK2a, or the initialization control start pulse signals GSP1b and GSP2b are different from the write control start pulse signals GSP1a and GSP2a. Furthermore, the configuration of the unit circuit 24b in the DIS driver 211 may be different from the configuration of the unit circuit 24a in the SC driver 212 (Figure 17).

[0081] Figure 20A is a timing chart illustrating the operation of the DIS driver 211 in full-screen mode as shown in Figure 19, and Figure 20B is a timing chart illustrating the operation of the DIS driver 211 in half-screen mode as shown in Figure 19. The operation of the DIS driver 211 with the configuration shown in Figure 19 will be explained below with reference to Figures 20A and 20B. In the following explanation, the number of stages of the upper DIS driver 211U will be 1281, the number of stages of the lower DIS driver 211L will be 1280, and the number of initialization control lines DISi will be 1281 + 1280 = 2561.

[0082] In full-screen mode, the first initialization control start pulse signal GSP1b and the second initialization control start pulse signal GSP2b shown in Figure 20A are supplied to the upper DIS driver 211U and the lower DIS driver 211L respectively as shown in Figure 19, and the first initialization control clock signal GCK1b and the second initialization control clock signal GCK2b shown in Figure 20A are supplied to the upper DIS driver 211U and the lower DIS driver 211L as shown in Figure 20A. With these initialization control start pulse signals GSP1b, GSP2b and initialization control clock signals GCK1b, GCK2b, the upper DIS driver 211U and the lower DIS driver 211L operate as a single shift register. As shown in Figure 20A, the DIS driver 211 outputs initialization control signals DIS(0) to DIS(n) that are sequentially L level (active state) for predetermined periods and apply them to the initialization control lines DIS0 to DISn respectively (n = 2561).

[0083] In half-screen display mode, the same first initialization control start pulse signal GSP1b as in full-screen display mode is supplied to the upper DIS driver 211U, but the second initialization control start pulse signal GSP2b supplied to the lower DIS driver 211L is fixed to the H level as shown in Figure 20B. As a result, the upper DIS driver 211U operates as a single shift register with the first initialization control start pulse signal GSP1b and the initialization control clock signals GCK1b and GCK2b, and outputs initialization control signals DIS(0) to DIS(na) that are sequentially at the L level (active state) for predetermined periods as shown in Figure 20B, and applies them to the upper initialization control lines DIS0 to DISna respectively (na = 1280). In contrast, the lower SC driver 212L outputs initialization control signals DIS(na+1) to DIS(n) fixed to the H level (inactive state), as shown in Figure 20B, and applies them to the lower initialization control lines DISna+1 to DISn respectively (n = 2561). Note that each unit circuit 24b(na+1) to 24b(n) of the lower DIS driver 211L is configured such that the output signals DIS(na+1) to DIS(n) are at the H level in the initial state (initialized by the reset signal INITB) (see, for example, Figures 10 and 17).

[0084] As shown in Figure 20B, in this embodiment, in half-screen display mode, the initialization control clock signals GCK1b and GCK2b, which are supplied in common to the upper DIS driver 211U and the lower DIS driver 211L, are stopped for periods other than those necessary for driving the initialization control lines DIS0 to DISna in the first display area 110 where the image should be displayed.

[0085] <2.4 Configuration and Operation of Unit Circuits in DIS Drivers> In this embodiment, the unit circuit 24a with the configuration described above, as shown in Figure 17, can be used as the unit circuit 24b corresponding to each stage in the upper DIS driver 211U and lower DIS driver 211L, which operate as shift registers. In this case, the duty cycle of the initialization control clock signals GCK1b and GCK2b is set so that the period of the initialization control clock signals GCK1b and GCK2b is the same length as the period of the write control clock signals GCK1a and GCK2b, while the period of the L level (pulse width) in the initialization control clock signals GCK1b and GCK2b is longer than the period of the L level (pulse width) in the write control clock signals GCK1a and GCK2b. Figure 21 is a signal waveform diagram showing the operation of the unit circuit 24b in this case. As shown in Figure 21, in the unit circuit 24b, an output signal OUT is generated that has an active state (L level) period longer than the active state (L level) period of the output signal OUT shown in Figure 18, and is output as an initialization control signal DIS(i).

[0086] Furthermore, in this embodiment, the unit circuit 24a shown in Figure 17 may be adopted as the unit circuit 24b, and while using initialization control clock signals GCK1b and GCK2b similar to the write control clock signals GCK1a and GCK2a, the start pulse signal GSP, which has a longer L-level period (pulse width) than the write control start pulse signals GSP1b and GSP2a, may be used as the initialization control start pulse signals GSP1b and GSP2b to be supplied to the first stage unit circuits of the upper DIS driver 211U and lower DIS driver 211L, respectively. Figure 22A is a signal waveform diagram illustrating the operation of the first stage unit circuits 24b of the upper DIS driver 211U and lower DIS driver 211L in this case. In this case, when the first-stage unit circuit 24b is supplied with signals S, CK1, and CK2, which have waveforms as shown in Figure 22A, as the shift signal S (which is the start pulse signal GSP), the first input clock signal CK1, and the second input clock signal CK2, the voltage levels of the first internal node N21 to the third internal node N23 in the first-stage unit circuit 24b change as shown in Figure 22A, and an output signal OUT consisting of two pulses as shown in Figure 22A is generated. The number of pulses included in this output signal OUT corresponds to the pulse width of the start pulse signal GSP given as the shift signal S (in the example shown in Figure 22A, there are two pulses, but it is possible to have three or more pulses by changing the pulse width of the start pulse signal GSP), and such an output signal OUT is output as initialization control signals DIS(0) and DIS(na+1) (see Figure 19). Figure 22B is a signal waveform diagram to explain the operation of the unit circuits 24b other than the first stage in this case. In this case, the output signal OUT of the preceding stage is input to the unit circuit 24b other than the first stage as a shift signal S, and signals CK1 and CK2, with waveforms as shown in Figure 22B, are provided as the first input clock signal CK1 and the second input clock signal CK2.As a result, the voltage levels of the first internal nodes N21 to the third internal nodes N23 in the unit circuits 24b other than the first stage change as shown in Figure 22B, and an output signal OUT consisting of two pulses as shown in Figure 22B is generated (it is also possible to have three or more pulses in the output signal OUT by changing the pulse width in the start pulse signal GSP as described above). Such an output signal OUT is output as an initialization control signal DIS(i) from the unit circuits 24b other than the first stage (see Figure 19). In this way, by adopting the unit circuit 24a of Figure 17 as the unit circuit 24b in this embodiment and operating it as shown in Figures 22A and 22B, the period of the active state (L level) of the initialization control signal DIS(i) can be made substantially longer than the period of the active state (L level) of the scan signal SC(i) as a write control signal.

[0087] Furthermore, in this embodiment, instead of the unit circuit 24a shown in Figure 17, the unit circuit 24 with the previously described configuration shown in Figure 10 can be used as the unit circuit 24b. Figure 23 is a signal waveform diagram showing the operation of the unit circuit 24b in this case. In this case, when the unit circuit 24b is supplied with signals S, CK1, and CK2 as a shift signal S, a first input clock signal CK1, and a second input clock signal CK2, respectively, the voltage levels of the first internal node N1 to the fourth internal node N4 in the unit circuit 24b change as shown in Figure 23, and an output signal OUT with a waveform as shown in Figure 23 is generated. The pulse width included in this output signal OUT (the length of the active state period t21 to t26) is the length corresponding to the pulse width of the signal given as the shift signal S, and such an output signal OUT is output as an initialization control signal DIS(i).

[0088] By using the unit circuit 24 in Figure 10, which operates in this manner, as each unit circuit 24b(i) (i=0 to n) of the DIS driver 211 configured in Figure 19, the DIS driver 211 in this embodiment, which operates as shown in Figures 20A and 20B, is realized (na=1280, n=2561).

[0089] <2.5 Effects> According to this embodiment as described above, in a foldable organic EL display device, the configuration and operation of the EM driver 213 are the same as in the first embodiment, and therefore the same effects as in the first embodiment can be obtained.

[0090] In addition, in this embodiment, not only the EM driver 213 but also the SC driver 212 and the DIS driver 211 are configured to be separated into an upper driver and a lower driver, corresponding to the first display area 110 and the second display area 120 of the display unit 10, separated by the position of the folding portion 150 (see Figure 6) (see Figure 14). Based on this configuration, in half-screen display mode, not only the operation of the lower EM driver 231L but also the operation of the lower SC driver 212 and the lower DIS driver 211 are substantially stopped (see Figures 16B and 20B), so the power consumption for driving the scanning signal lines SC1 to SCn and the initialization control lines DIS0 to DISn is reduced, and as a result the power consumption in the drive circuit is further reduced compared to the first embodiment described above.

[0091] <3. Modifications> The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the scope of the present invention. For example, the following modifications are possible.

[0092] <3.1 First Modification> In each of the above embodiments, in half-screen display mode, an image is displayed in the first display area 110 and the second display area 120 is hidden (see Figures 9B and 12). However, by changing the start pulse signal and clock signal supplied from the display control circuit 40 to the scanning drive circuit 20, it is also possible to hide the first display area 110 and display an image in the second display area 120. In this case, the start pulse signals ESP1 and ESP2 for light emission control and the clock signals ECK1 and ECK2 for light emission control shown in Figure 24 should be supplied to the scanning drive circuit 20. In this way, as shown in Figure 24, the upper EM driver 213U outputs light emission control signals EM(1) to EM(na) fixed at the H level and applies them to the light emission control lines EM1 to EMna in the first display area 110, respectively (na = 1280), and the lower EM driver 213L outputs light emission control signals EM(na+1) to EM(n) that are sequentially at the H level for predetermined periods of time and applies them to the light emission control lines EMna+1 to EMn in the second display area 120, respectively (n = 1280).

[0093] <3.2 Second Modification> In the half-screen display mode of each of the above embodiments, the light emission control clock signals ECK1 and ECK2 are stopped for periods other than those necessary for driving the light emission control lines EM1 to EMna in the first display area 110 where the image should be displayed (see Figure 9B). Also, in the half-screen display mode of the second embodiment, the write control clock signals GCK1a and GCK2a are stopped for periods other than those necessary for driving the scan signal lines SC1 to SCna in the first display area 110 where the image should be displayed, and the initialization control clock signals GCK1b and GCK2b are stopped for periods other than those necessary for driving the initialization control lines DIS1 to DISna in the first display area 110 where the image should be displayed (see Figures 16B and 20B). However, even in the half-screen display mode, these clock signals EMCK1, EMCK2, GCK1a, GCK2a, GCK1b, and GCK2b may be kept from being stopped. In this case, as shown in Figure 25, it is preferable to configure the first light emission control start pulse signal ESP1 to be supplied to the upper EM driver 213U so that a start pulse appears every 1 / 2 frame period (1 / 2 vertical scanning period). In this case, the first write control start pulse signal GSP1a to be supplied to the upper SC driver 212U and the first initialization control start pulse signal GSP1b to be supplied to the upper DIS driver 211U are similarly configured so that a start pulse appears every 1 / 2 frame period (1 / 2 vertical scanning period), and the data signal line drive circuit 30 is controlled so that the data signal lines D1 to Dm are driven according to the modified drive cycle of the scanning-side drive circuit 20. In the half-screen display mode, by configuring the display control circuit 40 so that such configurations of start pulse signals ESP1, GSP1a, and GSP1b and control of the data signal line drive circuit 30 are realized, it is possible to display an image in the first display area 110 better than in each of the above embodiments while keeping the second display area 120 hidden.

[0094] <3.3 Third Modification> In the EM driver 213 in the modification of the first embodiment described above, as shown in Figure 13, instead of providing the second light emission control start pulse signal ESP2 as a shift signal S to the first stage unit circuit 24(na+1) of the lower EM driver 213L, a switching circuit 28 is provided to switch the shift signal S to be provided to the first stage unit circuit 24(na+1) between the output signal OUT of the final stage unit circuit 24(na) of the upper EM driver 213U and the gate high-level voltage VGH. This configuration shown in Figure 13 can also be adopted in the EM driver 213, SC driver 212, and DIS driver 211 of the second embodiment described above, and even if such a configuration is adopted, the same effects as in the second embodiment described above can be obtained.

[0095] <3.4 Fourth Modification> In each of the above embodiments, the light emission control clock signals ECK1, ECK2, the write control clock signals GCK1a, GCK2a, and the initialization control clock signals GCK1b, GCK2b are assumed to have the same period length, but this is not limited to this. For example, in order to lengthen the non-light emission period, the period of the light emission control clock signals ECK1, ECK2 may be set to twice the length of the period of the write control clock signals GCK1a, GCK2a. In this case, the EM driver 213 generates half the number of light emission control lines EM1 to EMn, numbered EMo(1) to EMo(n / 2) (where n is an even number), and applies each EMo(k) to the two light emission control lines EM2k-1, EM2k as the light emission control signals EM(2k-1), EM(2k) in each of the above embodiments (k = 1 to n / 2). Even when using such an EM driver 213, the same effects as in the first embodiment can be obtained by separating the EM driver 213 into an upper EM driver 213U and a lower EM driver 213L, similar to the embodiments described above (see Figures 7 and 8, etc.).

[0096] <3.5 Other Modifications> In each of the above embodiments, a DIS driver 211, an SC driver 212, and an EM driver 213 are provided as the scanning drive circuit 20 (see Figures 2, 7, and 14). However, in configurations that do not use an internal compensation type pixel circuit, or in configurations where the size of the display unit 10 is relatively small and a large driving capability is not required for the initialization of the retaining capacitor Cst etc. in the pixel circuit 15, the DIS driver 211 may be omitted, and both the scanning signal lines SC1 to SCn and the initialization control lines DIS0 to DISn may be driven by the SC driver 212.

[0097] In each of the above embodiments, the scanning drive circuit 20 is provided in the frame area 60 of the display panel 6 that corresponds to one end of the scanning signal lines SC1 to SCn, initialization control lines DIS0 to DISn, and light emission control lines EM1 to En (see Figures 2, 7, and 14). However, one scanning drive circuit 20 may be provided in each of the frame areas 60 of the display panel 6 that corresponds to one end and the other end of the scanning signal lines SC1 to SCn, initialization control lines DIS0 to DISn, and light emission control lines EM1 to En. In this case, by configuring the system to drive each scanning signal line SCi, each initialization control line DISii, and each light emission control line EMI (i=1 to n, ii=0 to n) from one end and the other, images can be displayed well on a larger display unit 10. Alternatively, for example, the initialization control lines DIS0 to DISn may be divided into two sets (for example, a set consisting of odd-numbered initialization control lines DIS1, DIS3, DIS5, ... and a set consisting of even-numbered initialization control lines DIS0, DIS2, DIS4, ...), with one of the two DIS drivers 211 driving the initialization control lines of one set and the other DIS driver 211 driving the initialization control lines of the other set. The same applies to the SC driver 212 and the EM driver 213.

[0098] In each of the above embodiments, the transistors T1 to T7 included in the pixel circuit 15 are all P-channel type transistors (e.g., LTPS), and considering the monolithic design of the scanning-side drive circuit 20, the EM driver 213, SC driver 212, and DIS driver 211 are described using configuration examples in which the transistors included in them are all P-channel type transistors (Figures 10 and 17). However, the invention is not limited to this, and the transistors included in the pixel circuit may all be N-channel type transistors (e.g., IGZO-TFT), and correspondingly, the transistors included in the EM driver 213, SC driver 212, and DIS driver 211 may all be N-channel type transistors. Furthermore, the pixel circuit may include both P-channel type transistors and N-channel type transistors, and the EM driver 213, SC driver 212, and DIS driver 211 may also include both P-channel type transistors and N-channel type transistors. In each of the above embodiments, an internally compensated pixel circuit 15 is used (see Figure 4), but the invention is not limited to this, and any pixel circuit that can control light emission by the light emission control line EMI may be used.

[0099] In the above, each embodiment has been described using an organic EL display device as an example, but the present invention is not limited to organic EL display devices, and is applicable to any display device that uses an electric current-driven light-emitting element as a display element. Examples of display elements that can be used here include organic EL elements, i.e., organic light-emitting diodes (OLEDs), as well as inorganic light-emitting diodes and quantum dot light-emitting diodes (QLEDs).

[0100] Furthermore, the features of the display devices described above can be arbitrarily combined in a manner that does not contradict their properties and does not depart from the spirit of the present invention, thereby constructing a display device that combines some of the features of the above embodiments and modifications.

[0101] 6...Display panel 10...Display unit 15...Pixel circuit 20...Scanning drive circuit 30...Data signal line drive circuit 40...Display control circuit 60...Border area 110...First display area 120...Second display area 150...Folding part 211...DIS driver (initialization control circuit) 211U...Upper DIS driver 211L...Lower DIS driver 212...SC driver (write control circuit) 212U...Upper SC driver 212L...Lower SC driver 213...EM driver (light emission control circuit) 213U...Upper EM driver (first light emission control circuit) 213L...Lower EM driver (second light emission control circuit) 24(1) to 24(n)...Unit circuits (of the EM driver) 24a(1) to 24a(n)...Unit circuits (of the SC driver) 24b(i), 24b(i)... Unit circuit (of the DIS driver) OL... Organic EL element EM1 to EMn... Light emission control lines SC1 to SCn... Scan signal lines (write control lines) DIS0 to DISn... Initialization control lines

Claims

1. A foldable display device comprising: a display unit including a plurality of pixel circuits, a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, and a plurality of light emission control lines corresponding to each of the plurality of scan signal lines; a data signal line drive circuit for driving the plurality of data signal lines; a scan signal line drive circuit for driving the plurality of scan signal lines; and a light emission control circuit for driving the plurality of light emission control lines, wherein each of the plurality of pixel circuits includes: a light-emitting element driven by current; a holding capacitor; a drive transistor for controlling the amount of current supplied to the light-emitting element according to the voltage written to the holding capacitor; a write control switching element having a control terminal connected to one of the plurality of scan signal lines for controlling whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor; and a light emission control switching element having a control terminal connected to one of the plurality of light emission control lines, and provided in series with the light-emitting element and the drive transistor, The display unit has a first display area and a second display area separated by a folding portion for folding the display device, the light emission control circuit includes a first light emission control circuit that drives a plurality of first light emission control lines which are light emission control lines arranged in the first display area, and a second light emission control circuit that drives a plurality of second light emission control lines which are light emission control lines arranged in the second display area, the first light emission control circuit has a plurality of stages for driving the plurality of first light emission control lines and is configured to operate as a shift register based on a first light emission control start pulse signal and a predetermined clock signal provided to the first stage, the second light emission control circuit has a plurality of stages for driving the plurality of second light emission control lines and is configured to operate as a shift register based on a second light emission control start pulse signal and a predetermined clock signal provided to the first stage, the second light emission control start pulse signal can be generated as a signal independent of the first light emission control start pulse signal.The second light emission control circuit is a display device that deactivates the plurality of second light emission control lines when the second light emission control start pulse signal is fixed in an inactive state.

2. The display device according to claim 1, having a first operating mode and a second operating mode, further comprising a data signal line drive circuit, a scan signal line drive circuit, and a display control circuit for controlling the light emission control circuit, wherein in the first operating mode, the display control circuit provides the first light emission control start pulse signal and the second light emission control start pulse signal to the first light emission control circuit and the second light emission control circuit, respectively, so that the first light emission control circuit and the second light emission control circuit operate as a single shift register, and in the second operating mode, the display control circuit provides the first light emission control start pulse signal to the first light emission control circuit so that the first light emission control circuit operates as a shift register, and fixes the second light emission control start pulse signal in an inactive state.

3. The display device according to claim 2, further comprising a switching circuit that receives a switching control signal and switches the start pulse signal for the second light emission control between a first final stage output signal, which is the output signal of the final stage of the first light emission control circuit, and an inactive voltage, which is a fixed voltage at an inactive level, based on the switching control signal, wherein the display control circuit generates and provides the switching control signal to the switching circuit such that in the first operating mode the first final stage output signal is provided to the first stage of the second light emission control circuit as a start pulse signal for the second light emission control, and in the second operating mode the inactive voltage is provided to the first stage of the second light emission control circuit as a start pulse signal for the second light emission control.

4. The display device according to claim 2, wherein the first light emission control circuit and the second light emission control circuit are configured to operate as a shift register based on a common clock signal, and the display control circuit stops the common clock signal during periods other than those necessary for driving the plurality of first light emission control lines in the second operating mode.

5. The scanning signal line driving circuit includes a first scanning signal line driving circuit that drives a plurality of first scanning signal lines which are scanning signal lines arranged in the first display area from among the plurality of scanning signal lines, and a second scanning signal line driving circuit that drives a plurality of second scanning signal lines which are scanning signal lines arranged in the second display area from among the plurality of scanning signal lines, wherein the first scanning signal line driving circuit has a plurality of stages that drive each of the plurality of first scanning signal lines and is configured to operate as a shift register based on a first write control start pulse signal and a predetermined clock signal provided to the first stage, wherein the second scanning signal line driving circuit has a plurality of stages that drive each of the plurality of second scanning signal lines and is configured to operate as a shift register based on a second write control start pulse signal and a predetermined clock signal provided to the first stage, and the display control circuit is, The display device according to claim 2, wherein in the first operating mode, the first write control start pulse signal and the second write control start pulse signal are supplied to the first scan signal line drive circuit and the second scan signal line drive circuit, respectively, so that the first scan signal line drive circuit and the second scan signal line drive circuit operate as a single shift register, and in the second operating mode, the first write control start pulse signal is supplied to the first scan signal line drive circuit so that the first scan signal line drive circuit operates as a shift register, and the second write control start pulse signal is fixed in an inactive state.

6. The display device according to claim 5, wherein the first scan signal line drive circuit and the second scan signal line drive circuit are configured to operate as a shift register based on a common clock signal, and the display control circuit stops the common clock signal during periods other than those necessary for driving the plurality of first scan signal lines in the second operating mode.

7. The display device according to any one of claims 1 to 6, wherein the light emission control circuit and the scanning signal line driving circuit are formed directly on the substrate on which the plurality of pixel circuits are formed.

8. Further comprising an initialization control circuit, the display unit further includes a plurality of initialization control lines provided along the plurality of scan signal lines, each of the plurality of pixel circuits further includes an initialization switching element having a control terminal connected to one of the plurality of initialization control lines for initializing the holding capacitor, the initialization control circuit includes a first initialization control circuit for driving a plurality of first initialization control lines which are initialization control lines arranged in the first display area, and a second initialization control circuit for driving a plurality of second initialization control lines which are initialization control lines arranged in the second display area, the first initialization control circuit has a plurality of stages for driving each of the plurality of first scan signal lines and is configured to operate as a shift register based on a first initialization control start pulse signal and a predetermined clock signal provided to the first stage, the second initialization control circuit has a plurality of stages for driving each of the plurality of second initialization control lines and is configured to operate as a shift register based on a second initialization control start pulse signal and a predetermined clock signal provided to the first stage, the display control circuit is, The display device according to claim 2, wherein in the first operating mode, the first initialization control circuit and the second initialization control circuit are supplied with a first initialization control start pulse signal and a second initialization control start pulse signal, respectively, so that they operate as a single shift register, and in the second operating mode, the first initialization control circuit is supplied with a first initialization control start pulse signal so that the first initialization control circuit operates as a shift register, and the second initialization control start pulse signal is fixed in an inactive state.

9. The display device according to claim 8, wherein the first initialization control circuit and the second initialization control circuit are configured to operate as a shift register based on a common clock signal, and the display control circuit stops the common clock signal during periods other than those necessary for driving the plurality of first initialization control lines in the second operating mode.

10. The display device according to claim 8 or 9, wherein the light emission control circuit, the scanning signal line drive circuit, and the initialization control circuit are formed directly on the substrate on which the plurality of pixel circuits are formed.

11. A method for driving a foldable display device having a display unit including a plurality of pixel circuits, a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, and a plurality of light emission control lines corresponding to each of the plurality of scan signal lines, comprising: a data signal line driving step for driving the plurality of data signal lines; a scan signal line driving step for driving the plurality of scan signal lines; and a light emission control line driving step for driving the plurality of light emission control lines, wherein each of the plurality of pixel circuits includes: a light-emitting element driven by current; a holding capacitor; a drive transistor that controls the amount of current supplied to the light-emitting element according to the voltage written to the holding capacitor; a write control switching element having a control terminal connected to one of the plurality of scan signal lines and controlling whether or not to write the voltage of one of the plurality of data signal lines as a data voltage to the holding capacitor; and a light emission control switching element having a control terminal connected to one of the plurality of light emission control lines and provided in series with the light-emitting element and the drive transistor, The display unit has a first display area and a second display area separated by a folding portion for folding the display device, and the light emission control line driving step includes a first light emission control line driving step of sequentially driving a plurality of first light emission control lines which are light emission control lines arranged in the first display area from among the plurality of light emission control lines, based on a first light emission control start pulse signal and a predetermined clock signal, and a second light emission control line driving step of sequentially driving a plurality of second light emission control lines which are light emission control lines arranged in the second display area from among the plurality of light emission control lines, based on a second light emission control start pulse signal and a predetermined clock signal, the second light emission control start pulse signal can be generated as a signal independent of the first light emission control start pulse signal, and the driving method wherein the second light emission control line driving step deactivates the plurality of second light emission control lines when the second light emission control start pulse signal is fixed in an inactive state.

12. The driving method according to claim 11, having a first operating mode and a second operating mode, further comprising a display control step for controlling the data signal line driving step, the scan signal line driving step, and the light emission control line driving step, wherein the display control step supplies a first light emission control start pulse signal to the first light emission control line driving step and a second light emission control start pulse signal to the second light emission control line driving step so that the plurality of light emission control lines are sequentially deactivated, and supplies a first light emission control start pulse signal to the first light emission control line driving step and fixes the second light emission control start pulse signal to an inactive state.

13. The scan signal line driving step includes a first scan signal line driving step that sequentially drives a plurality of first scan signal lines, which are scan signal lines arranged in the first display area, from among the plurality of scan signal lines, based on a first write control start pulse signal and a predetermined clock signal; and a second scan signal line driving step that sequentially drives a plurality of second scan signal lines, which are scan signal lines arranged in the second display area, from among the plurality of scan signal lines, based on a second write control start pulse signal and a predetermined clock signal, wherein the second scan signal line driving step deactivates the plurality of second scan signal lines when the second write control start pulse signal is fixed in an inactive state; and the display control step supplies the first write control start pulse signal to the first scan signal line driving step and the second write control start pulse signal to the second scan signal line driving step so that the plurality of scan signal lines are sequentially activated in the first operation mode. The driving method according to claim 12, wherein in the second operating mode, the first write control start pulse signal is supplied to the first scan signal line driving step so that the plurality of first scan signal lines are sequentially activated, and the second write control start pulse signal is fixed in an inactive state.

14. Further comprising an initialization control line driving step, the display unit further includes a plurality of initialization control lines provided along the plurality of scan signal lines, each of the plurality of pixel circuits further includes an initialization switching element having a control terminal connected to one of the plurality of initialization control lines for initializing the holding capacitor, the initialization control line driving step includes a first initialization control line driving step that sequentially drives a plurality of first initialization control lines which are initialization control lines arranged in the first display area from among the plurality of initialization control lines, based on a first initialization control start pulse signal and a predetermined clock signal, and a second initialization control line driving step that sequentially drives a plurality of second initialization control lines which are initialization control lines arranged in the second display area from among the plurality of initialization control lines, based on a second initialization control start pulse signal and a predetermined clock signal, the second initialization control line driving step deactivates the plurality of second initialization control lines when the second initialization control start pulse signal is fixed in an inactive state, and the display control step is The driving method according to claim 12, wherein in the first operating mode, the first initialization control start pulse signal is supplied to the first initialization control line driving step and the second initialization control start pulse signal is supplied to the second initialization control line driving step so that the plurality of initialization control lines are sequentially activated, and in the second operating mode, the first initialization control start pulse signal is supplied to the first initialization control line driving step so that the first initialization control lines are sequentially activated, and the second initialization control start pulse signal is fixed in an inactive state.

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