Circuit board and semiconductor package comprising same

Abstract

Disclosed is a circuit board according to an embodiment of the present invention comprising: a first insulation layer; a second insulation layer disposed on the first insulation layer; a capacitor structure disposed between the first and second insulation layers; a first via electrode penetrating the first insulation layer; and a second via electrode disposed between the upper surface of the first insulating layer and upper surface of the second insulation layer, wherein the first and second via electrodes differ in taper angles.

Description

Circuit board and semiconductor package including the same

[0001] An embodiment according to the present invention relates to a circuit board and a semiconductor package.

[0002] As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or package board consists of a processor package housing a processor chip and a memory package housing a memory chip, connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, such package boards offer the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these benefits, such package boards are widely applied in mobile devices and the like.

[0004] Meanwhile, recently, the size of packages has been increasing due to the high specifications of electronic devices such as mobile devices and the adoption of High Bandwidth Memory (HBM). In addition, as the functions required of application processors increase, there is a demand for circuit boards capable of mounting these processor chips, which are configured as separate processor chips for each function. At this time, even when the application processor is separated into two processor chips for each function, the number of terminals (Input / Output) provided on each processor chip is increasing.

[0005] In addition, due to recent factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on processor chips is gradually increasing as the number of power and signals grows. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. However, increasing the area and thickness of a circuit board can lead to difficulties in miniaturizing products, as well as issues such as reliability problems like board warping and increased product costs. Therefore, rather than increasing the area and thickness of the circuit board, increasing the circuit pattern density is more advantageous in terms of product cost, reliability (such as warping), and miniaturization. Consequently, miniaturization of circuit patterns and through-electrodes is required.

[0006] An embodiment of the present invention implements an easy-to-use circuit board having first and second insulating layers of different inclination angles to improve the reliability of a capacitor structure, and a semiconductor package including the same.

[0007] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, wherein additional pads are placed on the capacitor structure to prevent connection between each via land by vias and to ensure the reliability of the capacitor structure.

[0008] In addition, the embodiment can realize a circuit board and a semiconductor package including the same, which facilitates miniaturization by reducing the thickness of the insulating layer while the capacitor structure is located within the insulating layer.

[0009] In addition, the embodiment can realize a circuit board and a semiconductor package including the same, in which the alignment of vias can be more accurately achieved through an insulating layer with a thin thickness compared to the lower insulating layer.

[0010] In addition, the embodiment can realize a circuit board with improved process efficiency and reliability through sub-electrodes of various lengths in an insulating layer covered with a capacitor structure, and a semiconductor package including the same.

[0011] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, in which integration density is improved, input / output counts are increased, and signal loss is reduced through an embedded capacitor structure.

[0012] The problems intended to be solved in the embodiments are not limited thereto, and may also include objectives or effects that can be identified from the means of solving the problems or the embodiments described below.

[0013] A circuit board according to an embodiment of the present invention comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer; a capacitor structure disposed between the first insulating layer and the second insulating layer; a first via electrode penetrating the first insulating layer; and a second via electrode disposed between the upper surface of the first insulating layer and the upper surface of the second insulating layer; wherein the first via electrode and the second via electrode have different inclination angles.

[0014] It may include a first wiring portion disposed on the first insulating layer.

[0015] The first wiring section above can be overlapped horizontally with the capacitor structure.

[0016] The width of the first wiring portion above may correspond to the width of the second via electrode above.

[0017] The first wiring section may include a first layer and a second layer disposed on the first layer.

[0018] The first layer may include a protrusion protruding toward the second insulating layer and an outer portion disposed on the outside of the protrusion.

[0019] A capacitor structure may include a first via land, a dielectric layer, and a second via land sequentially stacked on the first insulating layer.

[0020] The second via electrode may include a first sub-electrode disposed between the second via land and the upper surface of the second insulating layer; and a second sub-electrode disposed between the first via land and the upper surface of the second insulating layer.

[0021] The first sub-electrode may overlap in a vertical direction with the capacitor structure, and the second sub-electrode may be offset in a vertical direction with the second via-land and overlap in a vertical direction with the first via-land.

[0022] The length in the vertical direction of the first sub-electrode may be smaller than the length in the vertical direction of the second sub-electrode.

[0023] It includes a first wiring portion disposed on the first insulating layer; and the second via electrode may include a third sub-electrode disposed between the first wiring portion and the upper surface of the second insulating layer.

[0024] The length of the third sub-electrode may be smaller than the length of the second sub-electrode.

[0025] The width of the third sub-electrode may be smaller than the width of at least one of the second sub-electrode and the first sub-electrode.

[0026] It may further include a third insulating layer disposed below the first insulating layer; and a third via electrode penetrating the third insulating layer.

[0027] The width of the first via electrode may decrease as it moves from the upper surface of the first insulating layer toward the lower surface of the first insulating layer.

[0028] The width of the third via electrode may increase as it moves from the upper surface of the first insulating layer toward the lower surface of the first insulating layer.

[0029] The first insulating layer, the second insulating layer, and the third insulating layer may be made of different materials.

[0030] The first insulating layer may be RCC, the second insulating layer may be ABF, and the third insulating layer may be PPG.

[0031] A circuit board according to an embodiment comprises: a first insulating layer; a second insulating layer disposed on the first insulating layer; and a capacitor structure comprising a first metal layer disposed on the upper surface of the second insulating layer, a second metal layer disposed on the first metal layer, and a dielectric layer disposed between the first metal layer and the second metal layer, wherein the thickness of the second insulating layer is thinner than the thickness of the first insulating layer.

[0032] The apparatus further comprises: a third insulating layer disposed on the second insulating layer; a first wiring portion and a first via electrode disposed on the first insulating layer; a second wiring portion and a second via electrode disposed on the second insulating layer; and a third wiring portion and a third via electrode disposed on the third insulating layer; wherein the second via electrode penetrates the second insulating layer, and the second wiring portion may be disposed on the upper surface of the second insulating layer.

[0033] The thickness of the second wiring section above may be greater than the thickness of the capacitor structure above.

[0034] The second wiring section above can be overlapped horizontally with the capacitor structure.

[0035] The width of the second via electrode and the width of the third via electrode may increase along the stacking direction, and the width of the first via electrode may decrease along the stacking direction.

[0036] A capacitor structure may include a first metal layer, a dielectric layer, and a second metal layer sequentially stacked on the second insulating layer.

[0037] The length from the upper surface of the second metal layer to the upper surface of the third insulating layer may be greater than the total thickness of the capacitor structure.

[0038] The length from the upper surface of the second metal layer to the upper surface of the third insulating layer may be smaller than the thickness of the third wiring portion or the first wiring portion.

[0039] The length from the upper surface of the first metal layer to the upper surface of the third insulating layer may be greater than the total thickness of the capacitor structure.

[0040] The length from the lower surface of the first wiring section to the lower surface of the first insulating layer may be greater than the length from the upper surface of the first metal layer to the upper surface of the third insulating layer.

[0041] The third wiring portion is disposed on the upper surface of the third insulating layer, and the third via electrode penetrates the third insulating layer, and the first wiring portion is disposed on the lower surface of the second insulating layer, and the first via electrode can penetrate the first insulating layer.

[0042] The third via electrode may include a third-1 via electrode penetrating the third insulating layer; and a third-2 via electrode penetrating the second insulating layer and the third insulating layer.

[0043] The above third via electrode may include a third via electrode in contact with the capacitor structure.

[0044] The thickness of the above 3-3 via electrode may be greater than the thickness of the above 3-1 via electrode.

[0045] The thickness of the above 3-2 via electrode may be greater than the thickness of the above 1 via electrode.

[0046] The thickness of the above 3-2 via electrode may be smaller than the thickness of the above 1 insulating layer.

[0047] The second via electrode may include a second-1 via electrode in contact with the capacitor structure; and a second-2 via electrode in contact with the second wiring portion.

[0048] The thickness of the second insulating layer and the third insulating layer may be smaller than the thickness of the first insulating layer.

[0049] At least some of the second insulating layer, the third insulating layer, and the first insulating layer may be made of different materials.

[0050] The first insulating layer comprises glass fiber and resin, and the second insulating layer and the third insulating layer may comprise resin.

[0051] An embodiment of the present invention provides an easy circuit board having first and second insulating layers of different inclination angles to improve the reliability of a capacitor structure, and a semiconductor package including the same.

[0052] In addition, the embodiment may provide a circuit board and a semiconductor package including the same, wherein additional pads are placed on a capacitor structure to prevent connection between each via land by vias and to ensure reliability of the capacitor structure.

[0053] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which facilitates miniaturization by reducing the thickness of the insulating layer while the capacitor structure is located within the insulating layer.

[0054] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which the alignment of vias can be more accurately achieved through an insulating layer with a thin thickness compared to the lower insulating layer.

[0055] In addition, the embodiment can provide a circuit board with improved process efficiency and reliability through sub-electrodes of various lengths in an insulating layer covered with a capacitor structure, and a semiconductor package including the same.

[0056] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which integration density is improved, input / output count is increased, and signal loss is reduced through an embedded capacitor structure.

[0057] The various and beneficial advantages and effects of the present invention are not limited to those described above and may be more easily understood in the process of explaining specific embodiments of the present invention.

[0058] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, and

[0059] FIG. 2 is an enlarged view of the K1 portion in FIG. 1, and

[0060] FIG. 3 is a partial enlarged view of the K1 portion in FIG. 1, and

[0061] FIG. 4 is a plan view of a sub-electrode first via land and a second via land in a circuit board according to an embodiment, and

[0062] Figure 5 is an enlarged view of the K2 portion in Figure 1, and

[0063] FIGS. 6a to 6o are drawings illustrating a method for manufacturing a circuit board according to a first embodiment, and

[0064] FIG. 7 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and

[0065] Fig. 8 is an enlarged view of the K3 portion in Fig. 7, and

[0066] FIG. 9 is an enlarged view of the K4 portion in FIG. 7, and

[0067] FIGS. 10a to 10l are drawings illustrating a method for manufacturing a circuit board according to a second embodiment, and

[0068] FIG. 11 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, and

[0069] FIG. 12 is an enlarged view of the K5 portion in FIG. 11, and

[0070] FIG. 13 is an enlarged view of the K6 portion in FIG. 11, and

[0071] FIG. 14 is an enlarged view of the K7 portion in FIG. 11, and

[0072] FIG. 15 is a modified example of FIG. 13, and

[0073] FIG. 16 is another variation of FIG. 13, and

[0074] FIG. 17 is another variation of FIG. 13, and

[0075] FIG. 18 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, and

[0076] FIG. 19 is an enlarged view of the K8 portion in FIG. 18, and

[0077] FIG. 20 is a variation of FIG. 19, and

[0078] FIG. 21 is an SEM image of a circuit board according to an embodiment, and

[0079] FIG. 22 is an enlarged view of the K9 portion in FIG. 21, and

[0080] FIG. 23 is a cross-sectional view showing a semiconductor package according to a first embodiment, and

[0081] FIG. 24 is a cross-sectional view showing a semiconductor package according to a second embodiment, and

[0082] FIG. 25 is a cross-sectional view showing a semiconductor package according to a third embodiment, and

[0083] FIG. 26 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0084] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0085] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0086] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0087] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0088] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a meaning that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0089] Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “and at least one of B and C (or more than one),” it may include one or more of all combinations that can be combined with A, B, and C.

[0090] Terms including ordinal numbers, such as second, first, etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of multiple related described items or any of the multiple related described items. Such terms are intended only to distinguish the component from other components and are not limited by the essence, order, sequence, etc. of the component.

[0091] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0092] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0093] Furthermore, when described as being formed or placed "above or below" each component, "above or below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0094] In addition, the expression that configuration A is positioned between configuration B and configuration C must include the meaning that configuration A is positioned such that at least a portion of it overlaps with configurations B and C in the horizontal and / or vertical directions.

[0095] Expressions referring to directions include horizontal directions and vertical directions, and the horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. For example, according to the Cartesian coordinate system, this is referred to as the first horizontal direction (x-axis), the second horizontal direction (y-axis), and the vertical direction (z-axis), and the meaning of being superimposed along the horizontal direction must include the meaning of being superimposed along the first horizontal direction and / or superimposed along the second horizontal direction.

[0096] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration A is covered by at least a portion of Configuration C.

[0097] Furthermore, when it is stated that Component A 'contacts' Component B, this may include not only cases where the component 'contacts' the other component directly, but also cases where it 'contacts' due to another component located between the component and the other component. Therefore, if Component A is to be understood only as 'directly contacting' Component B, it is described as 'directly contacting'.

[0098] In addition, when it is stated that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part intended for the function and purpose to be resolved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0099] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0100] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements disposed on the circuit board, and a connecting member that electrically connects the plurality of semiconductor elements.

[0101] The circuit board may include a plurality of stacked insulating layers, wiring or circuit patterns disposed within each of the stacked insulating layers, and via electrodes for connecting the wiring or circuit patterns disposed within each insulating layer.

[0102] The semiconductor device may be mounted on a circuit board and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive components are integrated into a single chip. For example, it may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip comprising at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, or it may be an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or it may be a chip set comprising a specific combination of those listed above. Additionally, the semiconductor device may be a memory device such as High Bandwidth Memory (HBM).

[0103] A connecting member is a component that functions to electrically connect multiple semiconductor devices, and can be placed between a semiconductor device and a circuit board. For example, the connecting member may be embedded within the circuit board or placed on the circuit board. When embedded within the circuit board, it may have the advantage of being able to thin the thickness of the semiconductor package. The connecting member may be provided with silicon, but is not limited thereto and may be provided with an organic material, and may be referred to as a bridge because it functions to electrically interconnect multiple semiconductor devices.

[0104] Additionally, the connecting member may be placed on a circuit board. When placed on a circuit board, the connecting member may be covered by a molding member, and the circuit board, the semiconductor device, and the connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Furthermore, a redistribution layer may be additionally placed between the molding member and the semiconductor device.

[0105] Meanwhile, the product family to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0106] In addition, electronic devices may include smartphones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, automotive devices, etc. However, they are not limited to these, and it goes without saying that they may be any other electronic devices that process data in addition to these.

[0107] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of portion K1 in FIG. 1, FIG. 3 is a partial enlarged view of portion K1 in FIG. 1, FIG. 4 is a plan view of a sub-electrode first via land and a second via land in a circuit board according to an embodiment, and FIG. 5 is an enlarged view of portion K2 in FIG. 1.

[0108] Referring to FIG. 1, a circuit board (100) according to the first embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100) may further include a core layer which is a protective layer disposed on the electrode portion (120) or an insulating layer disposed within the insulating layer (110).

[0109] The insulating layer (110) may be composed of a plurality of layers. The insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), a third insulating layer (113), and a fourth insulating layer (114).

[0110] The fourth insulating layer (114), the third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) may be positioned sequentially along the stacking direction or the vertical direction (the first direction or the X-axis direction). In other words, the fourth insulating layer (114), the third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) may be stacked sequentially. Furthermore, the insulating layer (110) on the circuit board may consist of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113). Additionally, the insulating layer (110) may further include an additional insulating layer in addition to the fourth insulating layer (114).

[0111] The insulating layer (110) may include a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. Additionally, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be a glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0112] For example, the insulating layer (110) may be provided with any insulating resin, such as a thermosetting and / or photocurable resin. As a thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and materials such as prepreg (PPG) containing glass fibers may be used. As a photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin may be used. The aforementioned any insulating resin may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and may include inorganic fillers such as silica. When an insulating resin is used as a core, it may include a reinforcing material provided with glass fibers or aramid fibers. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric Resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0113] Each insulating layer may be made of the same or different materials. For example, in the embodiment, the third insulating layer (113) and the fourth insulating layer (114) may be made of PPG. The first insulating layer (111) may be made of RCC (resin-coated copper foil). The second insulating layer (112) may be made of ABF or RCC. As such, each insulating layer may be made of the same or different materials as other insulating layers. A detailed explanation of this will be provided later.

[0114] Additionally, a protective layer may be further disposed at the top or bottom of the insulating layer (110). The protective layer (not shown) may function to protect the pad from external moisture or contaminants, and to prevent short circuit problems when bonding between the semiconductor device and / or main board and the circuit board, the protective layer (not shown) may, for example, be provided with a solder resist. Specifically, the semiconductor device and / or main board, etc., have a plurality of terminals to be connected to the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pad of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals with high density, so to solve this short circuit problem, a solder resist with poor wettability with the solder may be disposed. In addition, the protective layer (not shown) may be made of a material that has insulating properties for electrical connections. Accordingly, the protective layer (not shown) may be called an 'insulating layer' and may be a component of the insulating layer described above. The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (not shown) may include any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0115] In addition, an insulating layer or protective layer (not shown) located on the outer side of the circuit board may have an opening. It may be electrically connected to other semiconductor devices or circuit boards through the opening.

[0116] The electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. In the following description, the electrode portion (120) is described as including a wiring portion (or wiring electrode) and a via electrode. Accordingly, the wiring portion may include a circuit pattern and a pad. And the circuit pattern may correspond to an 'electrode pattern', 'pattern', 'line', 'wiring', etc.

[0117] In an example, the wiring portion (or wiring electrode) in the electrode portion (120) may include wiring (or circuit pattern, pattern) and pads disposed on the insulating layer. In the electrode portion (120), the via electrode may be located within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Electrical connection may be implemented within the insulating layer or above or below the insulating layer through the via electrode.

[0118] The electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), a third electrode portion (123), and a fourth electrode portion (124). Each electrode portion may include a wiring portion and a via electrode as described above.

[0119] The first electrode portion (121) may be located on the first insulating layer (111). The second electrode portion (122) may be located on the second insulating layer (112). The third electrode portion (123) may be located on the third insulating layer (113). Additionally, the fourth electrode portion (124) may be located on the fourth insulating layer (114). Furthermore, additional electrode portions may be disposed on each insulating layer. A detailed explanation thereof will be provided later.

[0120] And the first electrode part (121) may include a first via electrode (121b) and a first wiring part (121a). Also, the second electrode part (122) may include a second via electrode (122b) and a second wiring part (122a). The third electrode part (123) may include a third via electrode (123b) and a third wiring part (123a). Also, the fourth electrode part (124) may include a fourth via electrode (124b) and a fourth wiring part (124a).

[0121] The first wiring section (121a) may be placed on the upper surface (US1) of the first insulating layer (111). The first via electrode (121b) may penetrate the first insulating layer (111). The second wiring section (122a) may be placed on the upper surface (US2) of the second insulating layer (112). The second via electrode (122b) may penetrate the second insulating layer (112). The third wiring section (123a) may be located on the lower surface of the first insulating layer (111) or on the third insulating layer (113). The third via electrode (123b) may penetrate the third insulating layer (113). The fourth wiring section (124a) may be located on the fourth insulating layer (114) or on the lower surface of the third insulating layer (113). The fourth via electrode (124b) can penetrate the fourth insulating layer (114). Additionally, an electrode portion (e.g., a wiring portion) may be further disposed on the lower surface of the fourth insulating layer (114).

[0122] Additionally, the outer pad of the electrode portion (120) can be bonded to a semiconductor device, substrate, board, etc. using solder, wire, conductive adhesive, etc., and can be positioned with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, it is not limited to this, and can have a width equal to the width of the circuit pattern depending on the technical limitations of the bonding process.

[0123] In addition, the pad placed on the inner side functions to connect the via electrode and the circuit pattern. When the via electrode is placed with a width wider than the circuit pattern, a pad with a width wider than the circuit pattern is provided to ensure positional alignment during the manufacturing process of the via electrode to be placed on each circuit pattern. Accordingly, each via electrode may have an upper surface located on the same plane as the lower surface of the upper pad directly in contact with the via electrode, and a lower surface located on the same plane as the upper surface of the lower pad directly in contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that concave or convex surfaces that may appear depending on various processes may also be present.

[0124] Additionally, semiconductor devices may be mounted on or on top of a circuit board. The semiconductor devices may be logic chips, memory chips, etc.

[0125] A capacitor structure (CAS) may be located on a first insulating layer (111). A capacitor structure (CAS) may be located between the first insulating layer (111) and the second insulating layer (112). Alternatively, a capacitor structure (CAS) may be located between the upper surface (US1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). Alternatively, a capacitor structure (CAS) may be placed on the second insulating layer (112). Alternatively, a capacitor structure (CAS) may be located on the upper surface (US1) of the first insulating layer (111) or on the lower surface (BS2) of the second insulating layer (112). Additionally, a capacitor structure (CAS) may be covered by the second insulating layer (112).

[0126] A capacitor structure (CAS) according to an embodiment may include a first via land (VL1), a dielectric layer (DL), and a second via land (VL2). In the capacitor structure (CAS), the first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may be stacked or positioned sequentially along a vertical direction (X-axis direction). The second via land (VL2) may be located on top of the first via land (VL1) and the dielectric layer (DL). For example, the second via land (VL2) may be located between the first via land (VL1') and the upper surface (US2) of the second insulating layer (112). The first via land (VL1) and the second via land (VL2) may be directly connected to via electrodes. Through the first via land (VL1) and the second via land (VL2), functions such as securing the positional alignment of the via electrode and the functions of the circuit electrically connected to the via electrode can be implemented. In addition, the via land here refers to an electrode, for example, one electrode (layer) and another electrode (layer) of a capacitor structure that performs the role of a capacitor. Furthermore, although the via electrodes connected to the first via land and the second via land of the capacitor are shown as a single number, they may be connected in a single or multiple numbers depending on the circuit connection. Also, the dielectric layer (DL) may be located on the first via land (VL1). Additionally, the dielectric layer (DL) may be located between the first via land (VL1) and the second via land (VL2).

[0127] Furthermore, as the processor of an electronic device or package substrate continues to draw more power, first droop and power transfer noise can be obstacles. Specifically, first droop can occur as the circuit inside the die or semiconductor device pulls power. To improve this first droop, a capacitor can be added to the circuit board on which the die or semiconductor device is provided, as in the embodiment. In particular, it may be desirable to add the capacitor near the die or semiconductor device that is the source of the droop. In this case, if the capacitor is placed on the die side or the side land of the substrate, the electrical path between the die and the side land (or die side) capacitor becomes longer, and the additional effect of the capacitor may be reduced due to the addition of parasitic inductance, etc. Additionally, interference with the interface of the circuit board or package substrate may occur due to the side land capacitor.

[0128] Therefore, as in the embodiment, by embedding the capacitor structure within the circuit board beneath the die, droop and power transfer noise generation can be suppressed. In addition, a high dielectric constant dielectric layer (DL) can be applied to form a large capacitance. Furthermore, in the embodiment, the capacitor structure may have any suitable shape and dimensions. For example, the capacitor structure may have a planar rectangular or circular shape. Also, the capacitor structure may be placed at any location within the circuit board. For example, to reduce the electrical path, the capacitor structure may be located in a layer adjacent to the upper die within the circuit board. Thus, the capacitor structure is located in an area adjacent to the die within the insulating layer, thereby suppressing electrical performance degradation.

[0129] Referring further to FIG. 2, in a circuit board (100) according to an embodiment, a first wiring portion (121a) may be located on a first insulating layer (111). The first wiring portion (121a) may overlap with a capacitor structure (CAS) in a horizontal direction or a second direction (Y-axis direction). The horizontal direction or the second direction (Y-axis direction) may be a direction perpendicular to the vertical direction (or the first direction, X-axis direction).

[0130] In the embodiment, the first wiring section (121a) may have a greater thickness or length in the first direction (X-axis direction) compared to the second wiring section, the third wiring section, and the fourth wiring section during the process, as described below. For example, the thickness (T4) of the first wiring section (121a) may be greater than the thickness of each of the second wiring section, the third wiring section, and the fourth wiring section. With this configuration, the process is simplified and the occurrence of electrical short circuits between via lands during via processing for the capacitor structure (CAS) can be suppressed. That is, the electrical reliability of the circuit board can be improved.

[0131] In addition, in the embodiment, the second via electrode (122b) may include a plurality of sub-electrodes. In particular, the first wiring portion (121a) may have the same width as at least one sub-electrode of the second via electrode (122b). For example, the width (W1) of the first wiring portion (121a) may correspond to the widths (W2, W3) of the second via electrode (122b).

[0132] Specifically, the second via electrode (122b) can penetrate the second insulating layer (112). The second via electrode (122b) can be located between the upper surface (US1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112).

[0133] In the embodiment, the second via electrode (122b) may include a first sub-electrode (122ba), a second sub-electrode (122bb), and a third sub-electrode (122bc).

[0134] The first sub-electrode (122ba) may be positioned between the second via land (VL2) and the upper surface (US2) of the second insulating layer (112). The first sub-electrode (122ba) may be in contact with the second via land (VL2). The first sub-electrode (122ba) may be in contact with the upper surface of the second via land (VL2). The first sub-electrode (122ba) may overlap with the capacitor structure (CAS). In particular, the first sub-electrode (122ba) may overlap with the first via land (VL1), the dielectric layer (DL), and the second via land (VL2) in the capacitor structure (CAS) in a first direction (X-axis direction).

[0135] The second sub-electrode (122bb) may be positioned between the first via land (VL1) and the upper surface (US2) of the second insulating layer (112). The second sub-electrode (122bb) may be in contact with the first via land (VL1). The second sub-electrode (122bb) may be in contact with the upper surface of the first via land (VL1). The second sub-electrode (122bb) may be spaced apart from the first sub-electrode (122ba) in the horizontal direction (Y-axis direction). The second sub-electrode (122bb) may overlap with the capacitor structure (CAS) in the horizontal direction (Y-axis direction). For example, the second sub-electrode (122bb) may overlap with the dielectric layer (DL) and the second via land (VL2) in the capacitor structure (CAS) in the horizontal direction (Y-axis direction).

[0136] Additionally, the second sub-electrode (122bb) may overlap with a part of the capacitor structure (CAS) in the first direction (X-axis direction). The second sub-electrode (122bb) may overlap with the first via land (VL1) of the capacitor structure (CAS) in a vertical direction. The second sub-electrode (122bb) may be positioned offset from the dielectric layer (DL) and the second via land (VL2) of the capacitor structure (CAS) without overlapping in a vertical direction. For example, the second sub-electrode (122bb) may be spaced apart from the dielectric layer (DL) and the second via land (VL2) of the capacitor structure (CAS) in the horizontal direction (Y-axis direction).

[0137] The third sub-electrode (122bc) may be positioned between the first wiring section (121a) and the upper surface (US2) of the second insulating layer (112). The third sub-electrode (122bc) may be in contact with the first wiring section (121a). The third sub-electrode (122bc) may be in contact with the upper surface of the first wiring section (121a). The third sub-electrode (122bc) may be spaced apart from the first sub-electrode (122ba) and the second sub-electrode (122bb). Additionally, the third sub-electrode (122bc) may also be spaced apart from the capacitor structure (CAS) in the horizontal direction (Y-axis direction). Accordingly, the third sub-electrode (122bc) may be positioned offset from the capacitor structure (CAS) in the vertical direction (Y-axis direction). Additionally, the third sub-electrode (122bc) may be positioned so as to be offset in the vertical direction (X-axis direction) from the first sub-electrode (122ba) and the second sub-electrode (122bb). Accordingly, the third sub-electrode (122bc) may not overlap in the vertical direction (X-axis direction) with the capacitor structure (CAS), the first sub-electrode (122ba), and the second sub-electrode (122bb). The third sub-electrode (122bc) may not overlap with the capacitor structure (CAS) in the horizontal direction.

[0138] In various examples, the third sub-electrode (122bc) may overlap horizontally with at least a portion of the capacitor structure (CAS) depending on the degree of etching or plating during the process. For example, depending on the thickness (T4) of the first wiring portion (121a), the third sub-electrode (122bc) may overlap horizontally with the second via land (VL2). Additionally, the third sub-electrode (122bc) may overlap horizontally with the second via land (VL2) and the dielectric layer (DL). Additionally, the third sub-electrode (122bc) may overlap horizontally with the first via land (VL1), the dielectric layer (DL), and at least a portion of the first via land (VL1).

[0139] In addition, the second via electrode (122b) penetrating the second insulating layer (112) according to the embodiment may be multiple and may have different lengths in the vertical direction. That is, the multiple sub-electrodes (122ba, 122bb, 122bc) of the second via electrode (122b) may have different lengths in the vertical direction (X-axis direction). In some cases, at least some of the multiple sub-electrodes may have the same length in the vertical direction. Furthermore, each sub-electrode may also be at least one.

[0140] The width (W4) of the third sub-electrode (122bc) may be smaller than the width of at least one of the first sub-electrode (122ba) and the second sub-electrode (122ba). For example, the width (W4) of the third sub-electrode (122bc) may be smaller than the width (W2) of the first sub-electrode (122ba). Or the width (W4) of the third sub-electrode (122bc) may be smaller than the width (W3) of the second sub-electrode (122bb). Or the width (W4) of the third sub-electrode (122bc) may be smaller than the width (W2) of the first sub-electrode (122ba) and the width (W3) of the second sub-electrode (122bb). With this configuration, electrical resistance on the electrical path connected to the capacitor structure (CAS) may be reduced, and heat dissipation, etc., may be improved. Furthermore, stress or warping due to thermal expansion, etc. can be relatively reduced by the third sub-electrode (122bc) having the longest length among the second via electrodes (122b). In addition, the circuit board according to the embodiment can effectively provide improved process efficiency.

[0141] Additionally, the length (T1) in the vertical direction or first direction (X-axis direction) of the first sub-electrode (122ba) may be smaller than the length (T2) in the vertical direction or first direction (X-axis direction) of the second sub-electrode (122bb).

[0142] And the length (T3) in the vertical direction or the first direction (X-axis direction) of the third sub-electrode (122bc) may be smaller than the length (T2) in the vertical direction or the first direction (X-axis direction) of the second sub-electrode (122bb).

[0143] Additionally, the length (T3) in the vertical direction or the first direction (X-axis direction) of the third sub-electrode (122bc) may be the same as or different from the length (T1) in the vertical direction or the first direction (X-axis direction) of the first sub-electrode (122ba).

[0144] As described above, corresponding to the thickness (T4) of the first wiring portion (121a), the third sub-electrode (122bc) may be the same as or different from the thickness (T1) of the first sub-electrode (122ba). For example, if the thickness (T4) of the first wiring portion (121a) is smaller than the thickness of the capacitor structure (CAS), the third sub-electrode (122bc) may be larger than the thickness (T1) of the first sub-electrode (122ba).

[0145] Thus, the lengths of the multiple sub-electrodes in the vertical direction or the first direction (X-axis direction) are all different, so they can be formed in the second insulating layer (112) of via holes or via electrodes of various sizes. Accordingly, the circuit board according to the embodiment can provide the effect of optimizing the signal transmission path and improving the signal transmission speed.

[0146] Additionally, in the embodiment, the first wiring portion (121a) may include a first layer (LY1) and a second layer (LY2). The first layer (LY1) and the second layer (LY2) may overlap at least partially in a vertical direction (X-axis direction) with the first sub-electrode (122ba).

[0147] And the first layer (LY1) can correspond to chemical copper in the first wiring section (121a). The second layer (LY2) can correspond to electrolytic copper, etc. in the first wiring section (121a). Accordingly, the first layer (LY1) and the second layer (LY2) can form a boundary surface with each other.

[0148] Furthermore, the first layer (LY1) may include a protrusion (PR) protruding toward the upper surface of the second layer (LY2) or the second insulating layer (112), and an outer portion (EG) outside the protrusion (PR). The protrusion (PR) may overlap with the first sub-electrode (122ba) in a vertical direction (X-axis direction). The outer portion (EG) may not overlap with the first sub-electrode (122ba) in a vertical direction and may be adjacent to the protrusion (PR).

[0149] Corresponding to this first layer (LY1), the second layer (LY2) may have a groove corresponding to the protrusion (PR) of the first layer (LY1). Thus, the thickness (h1) of the second layer (LY2) in the region overlapping vertically with the first sub-electrode (122ba) may be smaller than the thickness (h2) in the region offset vertically from the first sub-electrode (122ba). Additionally, the length (h1) of the second layer (LY2) in the vertical direction (X-axis direction) from the center may be smaller than the length (h2) in the vertical direction (X-axis direction) from the outside.

[0150] With this configuration, the bonding strength between chemical copper and electrolytic copper is strengthened, thereby improving the mechanical reliability of the first wiring section. Furthermore, the reliability of the electrical connection in the first wiring section can also be improved.

[0151] Furthermore, the first layer (LY1) may have a structure that protrudes upward from the upper surface (US2) of the second insulating layer (112). That is, on the second via electrode (122b), the first layer (LY1) may have a structure that extends or protrudes upward from the upper surface (US2) of the second insulating layer (112).

[0152] Referring further to FIGS. 3 and FIGS. 4, a capacitor structure (CAS) may be placed on a first insulating layer (111) and located on a second insulating layer (112). Depending on various processes, at least a portion of the capacitor structure (CAS) may be embedded in the first insulating layer (111). Additionally, at least a portion of the capacitor structure (CAS) may be embedded in the second insulating layer (112).

[0153] As described above, the capacitor structure (CAS) may include a first via land (VL1), a dielectric layer (DL), and a second via land (VL2). Additionally, a dielectric layer (DL) may be placed between the first via land (VL1) and the second via land (VL2) to form a storage capacity or capacitance. That is, the capacitor structure (CAS) can function as a 'capacitor'. There is a need for such a capacitor structure or capacitor to be further reduced in size to meet the requirements of substrates and semiconductor devices that demand increased integration density. Furthermore, as a method to improve the storage capacity of such a capacitor, one may consider increasing the effective area of ​​the first and second via lands (electrodes), reducing the thickness of the dielectric film (corresponding to the dielectric layer), or using a high dielectric constant material as the dielectric film. In particular, when the high dielectric constant material is used as a dielectric film, the leakage current that frequently occurs between the first via land, which is the lower electrode, and the second via land, which is the upper electrode, can be sufficiently reduced while maintaining a thin equivalent oxide thickness. In the embodiments, a high dielectric constant material may be used as a dielectric film. For example, the high dielectric constant material may include, for example, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, etc.

[0154] In addition, when a high-capacity capacitor is mounted on the circuit board according to the embodiment, as described above, problems such as reduced circuit board integration density and input / output count due to the volume of the capacitor can be resolved. In other words, through the capacitor structure according to the embodiment, it is possible to increase the circuit board integration density and input / output count while simultaneously providing improved storage capacity.

[0155] In an embodiment, the second via electrode (122b) may be superimposed on the capacitor structure (CAS) in a vertical direction (X-axis direction). In particular, the first sub-electrode (122ba) and the second sub-electrode (122bb) may be connected to the capacitor structure (CAS).

[0156] For example, the first sub-electrode (122ba) may be electrically connected to the capacitor structure (CAS). The second sub-electrode (122bb) may be electrically connected to the capacitor structure (CAS). Furthermore, the first sub-electrode (122ba) and the second sub-electrode (122bb) may be spaced apart in the horizontal direction (Y-axis direction) and may overlap at least partially in the horizontal direction (Y-axis direction). Accordingly, the capacitor structure (CAS) may be positioned between the die or chip mounted on the upper part of the circuit board (100), so that a capacitor may be placed between the die (or chip) and the main circuit board.

[0157] Additionally, there may be at least one capacitor structure (CAS) on the circuit board (100). In an embodiment, the capacitor structure (CAS) may be a plurality of capacitor structures, including a first capacitor structure and a second capacitor structure. The first capacitor structure and the second capacitor structure may be spaced apart from each other. Alternatively, a plurality of capacitor structures may be formed on the same first via land (VL1) with spaced-apart second via lands (VL2) and dielectric layers (DL).

[0158] Additionally, as described above, at least a portion of the capacitor structure (CAS) may be embedded within the first insulating layer (111). More specifically, the upper surface (US1) of the first insulating layer (111) (or the lower surface, BS2, of the second insulating layer) may be positioned offset from the upper or lower surface of the first via land (VL1). Furthermore, the upper surface (US1) of the first insulating layer (111) may not form a plane with the upper surface of the first via land (VL1). For example, the upper surface (US1) of the first insulating layer (111) may not form a plane with the upper surface of the first via land (VL1). Accordingly, the upper surface (US1) of the first insulating layer (111) may also form a step with the lower surface of the dielectric layer (DL).

[0159] Furthermore, since the first capacitor structure and the second capacitor structure are spaced apart from each other and overlap in the horizontal direction, the first via land (VL1) of the first capacitor structure and the first via land (VL1) of the second capacitor structure may overlap at least partially in the horizontal direction. For example, the upper surface of the first via land (VL1) in the first capacitor structure and the upper surface of the first via land (VL1) in the second capacitor structure may form the same plane. Also, as another example, the upper surface of the first via land (VL1) in the first capacitor structure and the upper surface of the first via land (VL1) in the second capacitor structure may be misaligned from each other. For example, the upper surface of the first via land (VL1) in the first capacitor structure and the upper surface of the first via land (VL1) in the second capacitor structure may have a vertical separation distance.

[0160] In an embodiment, the width or area (SS1) of the first via land (VL1) may be larger than the width or area (SS3) of the second via land (VL2). For example, the width or area (SS1) of the upper surface of the first via land (VL1) may be larger than the area (SS3) of the upper surface of the second via land (VL2). Additionally, the width or area (SS1) of the lower surface of the first via land (VL1) may be larger than the width or area (SS3) of the lower surface of the second via land (VL2). Furthermore, the area (SS1) of the first via land (VL1) may overlap with the width or area (SS3) of the second via land (VL2) in the vertical direction (X-axis direction). With this configuration, capacitance deviation and error generation can be suppressed depending on the difference in the overlapping area.

[0161] Additionally, the planar width or area of ​​the dielectric layer (DL) may be smaller than the width or area (SS1) of the first via land (VL1). For example, the width or area (SS1) of the first via land (VL1) may be larger than the width or area (SS2) of the dielectric layer (DL). Additionally, the width or area (SS2) of the dielectric layer (DL) may be larger than the width or area (SS3) of the second via land (VL2). Accordingly, a reduction in the size of the capacitance due to the dielectric layer can be prevented.

[0162] In addition, the thickness of the first via land (VL1) may be the same as or different from the thickness of the second via land (VL2).

[0163] Referring further to FIG. 5, in the embodiment, the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may be made of different materials. In particular, based on the upper surface of the first insulating layer (111) where the capacitor structure (CAS) is located, the upper second insulating layer (1112) and the lower third insulating layer (113) may be made of different materials. For example, the first insulating layer (111) may be made of RCC, the second insulating layer (112) may be made of ABF, and the third insulating layer (113) (and the fourth insulating layer) may be PPG. After the third insulating layer (113) and the fourth insulating layer (114) below the third insulating layer (113) are formed, the first insulating layer (111) may be formed on the third insulating layer (113). Then, the second insulating layer (112) may be formed on the first insulating layer (111). Accordingly, in the embodiments, the width of the via electrodes formed in each insulating layer may differ at least partially.

[0164] In addition, to prevent damage or disconnection of the capacitor structure (CAS) located on the upper surface (US1) of the first insulating layer (111) when forming via holes or via electrodes, the second insulating layer (112) may have a material different from that of the first insulating layer (111) or may have different via holes. In the embodiment, the inclination angle (θ) of the first via electrode (121b) may be different from the inclination angle (θ) of the second via electrode (122b). For example, the inclination angle (θ) of the first via electrode (121b) may be different from the inclination angle (θ) of the third sub-electrode (122bc). In the following, the inclination angle may be an angle formed based on the upper or lower surface of the insulating layer that each via electrode contacts.

[0165] The inclination angle (θ) of the first via electrode (121b) may be less than 90 degrees. In contrast, the inclination angle (θ) of the third sub-electrode (122bc) may be 90 degrees or less than 10% of 90 degrees.

[0166] And the angle of inclination (θ) of the third via electrode (123b) may also be different from the angle of inclination (θ) of the second via electrode (122b). The angle of inclination (θ) of the second via electrode (122b) may be greater than the angle of inclination (θ) of the third via electrode (123b).

[0167] And the width (W5) of the first via electrode (121b) may increase along the vertical direction or the first direction (X-axis direction). For example, the width of the first via electrode (121b) on the upper surface of the first insulating layer (111) may be greater than the width on the lower surface of the first insulating layer (111). Additionally, the width (W5) of the first via electrode (121b) may decrease as it moves from the upper surface of the first insulating layer (111) toward the lower surface of the first insulating layer (111).

[0168] In contrast, the second via electrode (122b) may have the same or different width (W4) along the vertical direction or the first direction (X-axis direction).

[0169] And the width (W6) of the third via electrode (123b) may decrease along the vertical direction or the first direction (X-axis direction). The width of the third via electrode (123b) on the upper surface of the third insulating layer (113) may be smaller than the width on the lower surface of the third insulating layer (113). Additionally, the width (W6) of the third via electrode (123b) may increase as it moves from the upper surface of the first insulating layer (111) (or the third insulating layer) toward the lower surface of the first insulating layer (111) (or the third insulating layer).

[0170] FIGS. 6a to 6o are drawings illustrating a method for manufacturing a circuit board according to a first embodiment.

[0171] Referring to FIG. 6a, in the embodiment, a first insulating layer (111) and a capacitor structure layer on the first insulating layer (111) may be formed on a structure in which a fourth insulating layer (114) and a third insulating layer (113) are stacked. The capacitor structure layer may be formed by etching as described below. The capacitor structure layer may have a first electrode layer, a dielectric layer, and a second electrode layer stacked sequentially. The first electrode layer may correspond to the first via land described above. The second electrode layer may correspond to the second via land described above. Additionally, the dielectric layer may correspond to the dielectric layer described above. Accordingly, hereinafter, the capacitor structure layer is denoted as 'CAS' corresponding to the capacitor structure described above, the first electrode layer as 'VL1' corresponding to the first via land described above, the dielectric layer as 'DL' corresponding to the dielectric layer described above, and the second electrode layer as 'VL2' corresponding to the second via land described above.

[0172] Here, the third insulating layer (113) may have a third electrode portion (123) formed thereon. Additionally, the fourth insulating layer (114) may have a fourth electrode portion (124) formed thereon.

[0173] For example, a third insulating layer (113) may be formed on a carrier board, and a third electrode portion (123) may be formed on the third insulating layer (113) in various ways. For example, the third electrode portion (123) may be formed on the third insulating layer (113) using the Embedded Trace Substrate (ETS) method. Furthermore, a fourth insulating layer (114) may be formed on the third insulating layer (113). And a fourth electrode portion (124) may be formed on the fourth insulating layer (114). Subsequently, the carrier board is removed, and a first insulating layer (111) may be formed on the third insulating layer (113). And a capacitor structure layer may be formed on the upper surface of the first insulating layer (111). In addition to the carrier board, the third insulating layer (113), the fourth insulating layer (114), the third electrode portion (123), and the fourth electrode portion (124) can be formed through various methods. For example, various manufacturing methods used for producing coreless circuit boards may be applied.

[0174] Referring to FIGS. 6b and 6c, in the embodiment, a mask such as a dry film may be formed on a carrier metal layer. At this time, after the dry film covers the entire capacitor structure layer, an opening or pattern that exposes the surface of the capacitor structure layer may be formed by exposure and development. The opening may be formed corresponding to the area where the first via land (VL1), the second via land (VL2), and the dielectric layer (DL) are to be formed on the capacitor structure layer. In this step, the opening of the mask may be formed corresponding to the area where the second via land (VL2) and the dielectric layer (DL2) are to be formed.

[0175] For example, a second via land (VL2) can be formed by etching. That is, regions other than the second via land (VL2) in the capacitor structure layer can be removed by etching.

[0176] And a dielectric layer (DL) can be formed by etching (e.g., plasma etching). That is, regions other than the dielectric layer (DL) in the capacitor structure layer can be removed by etching.

[0177] Referring to FIG. 6d, vias can be formed in the first insulating layer (111) by various methods. In the first insulating layer (111), vias can be formed corresponding to the first via electrode. For example, vias can be formed in an area corresponding to the first via electrode by laser drilling, etc.

[0178] Referring to FIG. 6e, a first mask (M1) may be formed on a capacitor structure layer. The first mask (M1) may form an opening (PT1) patterned by exposure or the like. The opening (PT1) may be formed in an area other than the first via land in the capacitor structure layer. That is, the first mask (M1) may be located on the first via land (VL1). The opening (PT1) may be formed corresponding to the location where the first wiring portion is formed.

[0179] Referring to FIG. 6f, a plating layer can be formed. For example, a plating layer for chemical plating can be formed. However, in addition to this plating process, various methods can be applied to form the electrode portion. In the embodiment, electrolytic copper can be formed on the plating layer.

[0180] Referring to FIG. 6g, in order to remove a portion of the first electrode layer from the capacitor structure layer (CAS) at the bottom of the chemically plated copper, a portion of the first mask (M1) can be removed, or a corresponding mask can be formed. The remaining first mask (M1') can correspond to the first via land.

[0181] Referring to FIG. 6h, etching can be performed on an area exposed by a first mask (M1') remaining on a first electrode layer located on the upper surface of the first insulating layer (111). At this time, the area exposed by the first mask (M1') may include the first electrode layer and an electroplated portion formed by electroplating on a chemical copper. Accordingly, a capacitor structure can be formed on the first insulating layer. Furthermore, a first wiring portion (121a) of the first electrode portion (121) can also be formed on the first insulating layer.

[0182] Referring to FIG. 6i, the remaining first mask (M1') can be removed. The capacitor structure can be exposed by peeling off the first mask (M1').

[0183] Referring to FIG. 6j, a second mask (M2) may be formed on the first insulating layer (111), the capacitor structure (CAS), and the first wiring portion (121a). Then, a patterned opening (PT2) may be formed on the second mask (M2) by exposure or etching.

[0184] At least a portion of the second via land (VL2), the first via land (VL1), and the first wiring portion (121a) of the capacitor structure (CAS) may be exposed by the opening (PT2).

[0185] Referring to FIG. 6k, plating can be performed on the opening (PT2) of the second mask (M2). A post can be formed by the plating. As previously mentioned, the plating can be performed with various metals. For example, the plating can be formed with copper.

[0186] Referring to FIG. 6L, the second mask (M2) can be removed. As the second mask (M2) peels off, the plated posts may remain on the second via land (VL2), the first via land (VL1), and the first wiring portion (121a) on the capacitor structure.

[0187] Referring to FIG. 6m, a second insulating layer (112) may be formed on a post, a second via land (VL2), a first via land (VL1), and a first wiring section (121a). For example, ABF may be applied to cover the second via land (VL2), the first via land (VL1), and the first wiring section (121a) on the plated post and capacitor structure. For example, heat and pressure may be applied, and the second insulating layer may be cured.

[0188] Referring to FIG. 6n, a thinning process to reduce the thickness of the second insulating layer (1) can be performed. For example, the thickness of the second insulating layer (112) can be reduced by polishing (e.g., CMP) or chemical treatment (e.g., etching). Accordingly, the thickness of the insulating layer is reduced, and the electrical distance can be reduced. Thus, it becomes possible to apply it to a high-performance semiconductor package, and in particular, miniaturized electronic devices such as mobile devices or wearable devices can be realized.

[0189] At least a portion of the post may be exposed by thinning. The post may correspond to the aforementioned sub-electrode. That is, the first sub-electrode, the second sub-electrode, and the third sub-electrode may be exposed by thinning. For example, at least a portion of the post may be a structure protruding above the upper surface of the second insulating layer (112).

[0190] Referring to FIG. 6o, a second wiring portion (122a) can be formed on the second insulating layer (112). That is, a circuit pattern can be formed. The circuit pattern can be formed by a plating process using a mask having a patterned opening as described above. As described above, chemical plating and electroplating can be performed on the exposed post corresponding to the second wiring portion.

[0191] FIG. 7 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, FIG. 8 is an enlarged view of portion K3 in FIG. 7, and FIG. 9 is an enlarged view of portion K4 in FIG. 7.

[0192] Referring to FIG. 7, a circuit board (100A) according to a second embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100) may further include a core layer which is a protective layer disposed on the electrode portion (120) or an insulating layer disposed within the insulating layer (110). Furthermore, the configuration described in the embodiments of the present invention may be applied identically, except for the details described below.

[0193] In particular, in this embodiment, additional pads (BP1, BP2) may be further disposed in the capacitor structure (CAS). The additional pads may include a first pad (BP1) and a second pad (BP2).

[0194] The first pad (BP1) may be located on the second via land (VL2). The first pad (BP1) may be in contact with the first via land (VL2). Additionally, the first pad (BP1) may be in contact with the first sub-electrode (122ba). Furthermore, the first pad (BP1) may overlap the first sub-electrode (122ba) in a vertical direction or in a first direction (X-axis direction). Also, the first pad (BP1) may overlap at least partially with the third sub-electrode (122bc) in a horizontal direction.

[0195] The second pad (BP2) may be positioned on the first via land (VL1). The second pad (BP2) may be spaced apart horizontally from the first pad (BP1). The second pad (BP2) may be in contact with the first via land (VL1) and may also be in contact with the second sub-electrode (122bb). Accordingly, the second pad (BP2) may overlap with the second sub-electrode (122bb) in a vertical direction or in a first direction (X-axis direction).

[0196] And the second pad (BP2) can also be horizontally overlapped with the dielectric layer (DL) and the second via land (VL2). Additionally, the second pad (BP2) can be horizontally overlapped (Y-axis direction) at least partially with the third sub-electrode (122bc). The second pad (BP2) can also be horizontally overlapped with the first pad (BP1).

[0197] And the third sub-electrode (122bc) may overlap with at least a portion of the first pad (BP1) and the second pad (BP2). Additionally, the first wiring portion (121a) may also overlap horizontally with at least a portion of the first pad (BP1) and the second pad (BP2).

[0198] In this way, when vias are formed on the capacitor structure (CAS) by the first pad (BP1) and the second pad (BP2), a disconnection between the first via land (VL1) and the second via land (VL2) can be prevented. Furthermore, when electrically connecting to the capacitor structure (CAS) by the first pad (BP1) and the second pad (BP2), electrical resistance, etc., can be reduced, thereby improving signal quality. For example, the thickness of the first pad (BP1) and the second pad (BP2) may be greater than the thickness of the first via land (VL1), the second via land (VL2), and the dielectric layer (DL) in the capacitor structure (CAS).

[0199] Referring to FIGS. 8 and 9, the thickness (T5) of the first pad (BP1) may be smaller than the thickness (T6) of the second pad (BP2). Accordingly, the second pad (BP2) may overlap the first pad (BP1), the dielectric layer (DL), and the second via land (VL2) in a horizontal direction (Y-axis direction). With this configuration, signal transmission can be facilitated by reducing electrical resistance.

[0200] And the upper surface of the first pad (BP1) can form the same layer as the upper surface of the second pad (BP2). That is, based on the upper surface of the first via land (VL1), the upper surface of the first pad (BP1) and the upper surface of the second pad (BP2) can be positioned at the same location.

[0201] And the length (T8) in the vertical direction or first direction (X-axis direction) of the first sub-electrode (122ba) may be the same as the length (T9) in the vertical direction or first direction (X-axis direction) of the second sub-electrode (122bb).

[0202] And the length (T10) in the vertical direction or first direction (X-axis direction) of the third sub-electrode (122bc) may be greater than the length (T8) in the vertical direction or first direction (X-axis direction) of the first sub-electrode (122ba) (or the length (T9) in the vertical direction or first direction (X-axis direction) of the second sub-electrode (122bb).

[0203] Furthermore, in this embodiment, each insulating layer may be made of the same or different materials. For example, the first insulating layer (111) and the second insulating layer (112) may be made of the same material. And the third insulating layer (113) and the fourth insulating layer (114) may be made of the same material.

[0204] And in this example, the angle of inclination (θ) of the first via electrode (121b) may be the same as the angle of inclination (θ) of the second via electrode (122b). For example, the angle of inclination (θ) of the first via electrode (121b) may be the same as the angle of inclination (θ) of the third sub-electrode (122bc).

[0205] Additionally, the width of the via electrodes formed in each insulating layer may differ at least partially. In this example, the angle of inclination (θ or the angle of inclination of the second via electrode) of the first via electrode (121b) may differ from the angle of inclination (θ) of the third via electrode (123b).

[0206] And the width (W5) of the first via electrode (121b) may increase along the vertical direction or the first direction (X-axis direction). For example, the width of the first via electrode (121b) on the upper surface of the first insulating layer (111) may be greater than the width on the lower surface of the first insulating layer (111). Additionally, the width of the first via electrode (121b) may decrease as it moves from the upper surface of the first insulating layer (111) toward the lower surface of the first insulating layer (111).

[0207] Additionally, the width (W4') of the second via electrode (122b) may increase along the vertical direction or the first direction (X-axis direction). For example, the width of the second via electrode (122b) on the upper surface of the second insulating layer (112) may be greater than the width on the lower surface of the second insulating layer (112) (or the region closest to the lower surface). Additionally, the width of the second via electrode (122b) may decrease as it moves from the upper surface of the second insulating layer (112) toward the lower surface of the second insulating layer (112).

[0208] And the width (W6) of the third via electrode (123b) may decrease along the vertical direction or the first direction (X-axis direction). The width of the third via electrode (123b) on the upper surface of the third insulating layer (113) may be smaller than the width on the lower surface of the third insulating layer (113). Additionally, the width of the third via electrode (123b) may increase as it moves from the upper surface of the first insulating layer (111) (or the third insulating layer) toward the lower surface of the first insulating layer (111) (or the third insulating layer).

[0209] FIGS. 10a to 10l are drawings illustrating a method for manufacturing a circuit board according to a second embodiment.

[0210] Referring to FIG. 10a, in this embodiment, a first insulating layer (111) and a capacitor structure layer on the first insulating layer (111) can be formed on a structure in which a fourth insulating layer (114) and a third insulating layer (113) are stacked as described above. The capacitor structure layer can be formed as the aforementioned capacitor structure layer by etching as described below. Furthermore, the capacitor structure layer can have a first electrode layer, a dielectric layer, and a second electrode layer stacked sequentially. The first electrode layer can correspond to the aforementioned first via land when a portion of its region is removed by etching or the like. The second electrode layer can correspond to the aforementioned second via land when a portion of its region is removed by etching or the like. Additionally, the dielectric layer can correspond to the aforementioned dielectric layer. In addition, the capacitor structure layer is denoted as 'CAS' in the following description corresponding to the capacitor structure, the first electrode layer as 'VL1' in the following description corresponding to the first via land, the dielectric layer as 'DL' in the following description corresponding to the dielectric layer, and the second electrode layer as 'VL2' in the following description corresponding to the second via land. Also, the content described in FIG. 6 may be applied in the same way, except for the content described below.

[0211] Here, the third insulating layer (113) may have a third electrode portion (123) formed thereon. Additionally, the fourth insulating layer (114) may have a fourth electrode portion (124) formed thereon.

[0212] For example, a third insulating layer (113) may be formed on a carrier board, and a third electrode portion (123) may be formed on the third insulating layer (113) in various ways. For example, the third electrode portion (123) may be formed on the third insulating layer (113) using the Embedded Trace Substrate (ETS) method. Furthermore, a fourth insulating layer (114) may be formed on the third insulating layer (113). And a fourth electrode portion (124) may be formed on the fourth insulating layer (114). Subsequently, the carrier board is removed, and a first insulating layer (111) may be formed on the third insulating layer (113). And a capacitor structure layer may be formed on the upper surface of the first insulating layer (111).

[0213] Referring to FIG. 10b and FIG. 10c, in the embodiment, a mask such as a dry film may be formed on a carrier metal layer. At this time, after the dry film covers the entire capacitor structure layer, an opening or pattern that exposes the surface of the capacitor structure layer may be formed by exposure and development. The opening may be formed corresponding to the area where the first via land (VL1), the second via land (VL2), and the dielectric layer (DL) are to be formed on the capacitor structure layer. In this step, the opening of the mask may be formed corresponding to the area where the second via land (VL2) and the dielectric layer (DL2) are to be formed.

[0214] For example, a second via land (VL2) can be formed by etching. That is, an area other than the second via land (VL2) in the capacitor structure layer (CAS) can be removed by etching.

[0215] And a dielectric layer (DL) can be formed by etching (e.g., plasma etching). That is, regions other than the dielectric layer (DL) in the capacitor structure layer (CAS) can be removed by etching.

[0216] Referring to FIG. 10d, vias can be formed in the first insulating layer (111) by various methods. In the first insulating layer (111), vias can be formed corresponding to the first via electrode (121b). For example, vias can be formed in an area corresponding to the first via electrode (121b) by a laser drill, etc.

[0217] Referring to FIG. 10e, a third mask (M3) may be formed on the capacitor structure layer. The third mask (M3) may partially correspond to the first mask described above. The third mask (M3) may form an opening (PT3) patterned by exposure, etc. The opening (PT3) may be formed corresponding to a location where a plurality of sub-electrodes are formed in the capacitor structure layer (CAS). For example, the opening (PT3) of the third mask (M3) may be formed corresponding to the first pad and the second pad. Additionally, the opening (PT3) of the third mask (M3) may be formed corresponding to the first wiring portion.

[0218] Referring to FIG. 10f, a plating layer can be formed. For example, a plating layer for chemical plating can be formed. However, various processes other than this plating process may be applied. Additionally, electrolytic copper can be formed on the plating layer. Through this plating, a first pad, a second pad, and a first wiring portion can be formed.

[0219] Referring to FIG. 10g, an additional mask (M3') may be formed on the first pad and the second pad. The third mask for plating the first pad and the second pad in the previous process may be removed. The additional mask (M3') is formed on the capacitor structure and may be positioned corresponding to the capacitor structure. That is, the additional mask (M3') may be formed corresponding to the first via land of the capacitor structure. Thus, a portion of the first wiring portion and the first electrode layer may be exposed.

[0220] Referring to FIG. 10h, etching can be performed on an area exposed by an additional mask (M3') remaining on the first electrode layer located on the upper surface of the first insulating layer (111). At this time, the area exposed by the additional mask (M3') can be partially removed by etching. For example, an electroplated area, etc., in the first wiring section can be removed by etching. Accordingly, the upper surfaces of the first pad (BP1) and the second pad (BP2) can be offset in the horizontal direction and spaced apart in the vertical direction from the upper surface of the first wiring section. In particular, the upper surfaces of the first pad (BP1) and the second pad (BP2) can be located above the upper surface of the first wiring section. For example, the distance from the upper surface of the first insulating layer to the upper surface of the first insulating layer may be greater than the distance from the upper surface of the first wiring section.

[0221] Referring to FIG. 10i, the additional mask (M3') can be removed. The capacitor structure can be exposed by peeling off the additional mask (M3').

[0222] Referring to FIG. 10j, a second insulating layer (112) can be formed on the first insulating layer (111), the capacitor structure, and the first wiring portion. The second insulating layer (112) can be hardened by a press or the like.

[0223] Referring to FIG. 10k, a through hole for a second via electrode of a second wiring section may be formed on the second insulating layer (112). Various methods may be used to form the through hole. For example, the through hole may be formed by a laser drill, etc. The through hole may be formed corresponding to a plurality of sub-electrodes. The through holes corresponding to the first sub-electrode and the second sub-electrode may have the same length in the direction of mutual agreement. Also, the length of the through hole corresponding to the third sub-electrode on the first wiring section may be greater than the length of the through hole corresponding to the first sub-electrode (or the second sub-electrode).

[0224] Referring to FIG. 10L, a second wiring portion may be formed on the second insulating layer (112). The second wiring portion may be formed by various methods (e.g., plating). A circuit pattern may be formed on the second insulating layer (112). The circuit pattern may be formed by a plating process using a mask having patterned openings as described above. As described above, chemical plating and electroplating may be performed corresponding to the second wiring portion.

[0225] FIG. 11 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, FIG. 12 is an enlarged view of portion K5 in FIG. 11, FIG. 13 is an enlarged view of portion K6 in FIG. 11, FIG. 14 is an enlarged view of portion K7 in FIG. 11, FIG. 15 is one variation of FIG. 13, FIG. 16 is another variation of FIG. 13, and FIG. 17 is yet another variation of FIG. 13.

[0226] Referring to FIG. 11, a circuit board (100B) according to a third embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100B) may further include a core layer which is a protective layer disposed on the electrode portion (120) or an insulating layer disposed within the insulating layer (110). Furthermore, the configuration described in the embodiments of the present invention may be applied identically, except for the details described below. Furthermore, the structure for the various variations described above may also be applied identically, except for the details described below.

[0227] The insulating layer (110) may be composed of a plurality of layers. The insulating layer (110) may include a first insulating layer (113), a second insulating layer (111), and a third insulating layer (112).

[0228] The first insulating layer (113), the second insulating layer (111), and the third insulating layer (112) may be positioned sequentially along the stacking direction or vertical direction (the first direction or the X-axis direction). In other words, the circuit board (100B) may include the first insulating layer (113), the second insulating layer (111) disposed on the first insulating layer (113), and the third insulating layer (112) disposed on the second insulating layer (111). Additionally, the insulating layer (110) may include additional insulating layers in addition to the first insulating layer (113). Conversely, the first insulating layer (113) may be disposed below the second insulating layer (111), and the second insulating layer (111) may be disposed below the third insulating layer (112). For example, at least one additional first insulating layer may be disposed below the first insulating layer (113), or at least one additional fifth insulating layer may be disposed above the third insulating layer (112).

[0229] Each insulating layer may be made of the same or different materials. For example, in the embodiment, the first insulating layer (113) and the insulating layer below the first insulating layer (113) may be made of PPG. Also, the second insulating layer (111) and the third insulating layer (112) may be made of RCC (resin-coated copper foil). Additionally, the second insulating layer (111) and the third insulating layer (112) may be made of ABF, PID, etc.

[0230] As such, in the embodiment, at least some of the insulating layers (110) may be made of different materials. For example, at least some of the second insulating layer (111), the third insulating layer (112), and the first insulating layer (113) may be made of different materials.

[0231] For example, the second insulating layer (111) and the third insulating layer (112) may be made of the same material. And the first insulating layer (113) may be made of a different material from the second insulating layer (111) (or the third insulating layer).

[0232] Additionally, the second insulating layer (111) and the third insulating layer (112) may be made of a resin-based material. Alternatively, the first insulating layer (113) may be made of a material to which glass fibers are added to the resin. For example, the first insulating layer (113) may include glass fibers and resin. And the second insulating layer (111) and the third insulating layer (112) may include resin without glass fibers.

[0233] As such, the insulating layer (third insulating layer) on which the capacitor structure (CAS) described later is disposed, and the insulating layer (first insulating layer) located below the lower insulating layer (second insulating layer), are made of a material different from the insulating layer (first and second insulating layers) above the first insulating layer; in particular, the insulating layer above the first insulating layer may not contain glass fibers. That is, the insulating layer surrounding or covering the capacitor structure (CAS) may not contain glass fibers. With this configuration, a thin capacitor structure (CAS) can be formed to facilitate the miniaturization of the circuit board. Furthermore, by forming the thickness of the insulating layer covering the capacitor structure (CAS) thinly, the miniaturization of the circuit board can be maximized. There are structural differences in specific components resulting from this, and these structural differences will be described later.

[0234] The electrode portion (120) may include a second electrode portion (121), a third electrode portion (122), and a first electrode portion (123). Each electrode portion may include a wiring portion and a via electrode as described above.

[0235] The second electrode portion (121) may be located on the second insulating layer (111). The third electrode portion (122) may be located on the third insulating layer (112). The first electrode portion (123) may be located on the first insulating layer (113). Furthermore, additional electrode portions may be disposed in each insulating layer.

[0236] In an example, the second electrode portion (121) may include a second via electrode (121b) and a second wiring portion (121a). Additionally, the third electrode portion (122) may include a third via electrode (122b) and a third wiring portion (122a). The first electrode portion (123) may include a first via electrode (123b) and a first wiring portion (123a).

[0237] Additionally, the second wiring section (121a) may be placed on the upper surface (US1) of the second insulating layer (111). The second via electrode (121b) may penetrate the second insulating layer (111). The third wiring section (122a) may be placed on the upper surface (US2) of the third insulating layer (112). The third via electrode (122b) may penetrate the third insulating layer (112). The first wiring section (123a) may be located on the lower surface (BS1) of the second insulating layer (111) or on the first insulating layer (113). For example, the first wiring section (123a) may be embedded in the first insulating layer (113). And the first wiring section (123a) may be located adjacent to the upper surface (US3) of the first insulating layer (113). The first via electrode (123b) can penetrate the first insulating layer (113). Additionally, an electrode portion (e.g., a wiring portion) may be further disposed on the lower surface (BS3) of the first insulating layer (113). Furthermore, as described above, an additional electrode portion may be further disposed on the additional insulating layer.

[0238] A capacitor structure (CAS) may be located on the second insulating layer (111). The capacitor structure (CAS) may be located on the upper surface (US1) of the second insulating layer (111) and may be in contact with the upper surface (US1). Alternatively, the capacitor structure (CAS) may be located on the lower surface (BS2) of the third insulating layer (112). The capacitor structure (CAS) may be located between the second insulating layer (111) and the third insulating layer (112). Alternatively, the capacitor structure (CAS) may be located between the upper surface (US1) (or lower surface (BS1)) of the second insulating layer (111) and the upper surface (US2) of the third insulating layer (112). Alternatively, the capacitor structure (CAS) may be placed on the third insulating layer (112). Additionally, the capacitor structure (CAS) may be covered by the third insulating layer (112).

[0239] A capacitor structure (CAS) according to an embodiment may include a first metal layer (VL1), a dielectric layer (DL), and a second metal layer (VL2). In the capacitor structure (CAS), the first metal layer (VL1), the dielectric layer (DL), and the second metal layer (VL2) may be stacked or positioned sequentially along a vertical direction (X-axis direction). For example, the second metal layer (VL2) may be located on top of the first metal layer (VL1) and the dielectric layer (DL). For example, the second metal layer (VL2) may be located between the first metal layer (VL1) (or dielectric layer) and the upper surface (US2) of the third insulating layer (112). The first metal layer (VL1) and the second metal layer (VL2) may be directly connected to via electrodes. Through the first metal layer (VL1) and the second metal layer (VL2), functions such as securing the positional alignment of the via electrode and the functions of the circuit electrically connected to the via electrode can be implemented. Furthermore, here, via lands can refer to electrodes, for example, one electrode (layer) and another electrode (layer) of a capacitor structure that performs the role of a capacitor. Moreover, although the via electrodes connected to the first metal layer and the second metal layer of the capacitor are shown as a single number, they may be connected in a single or multiple numbers depending on the circuit connection. Also, the dielectric layer (DL) may be located on the first metal layer (VL1). Additionally, the dielectric layer (DL) may be located between the first metal layer (VL1) and the second metal layer (VL2). Also, the first metal layer (VL1) may be in contact with the upper surface (US1) of the second insulating layer (111). The lower surface of the dielectric layer (DL) may be in contact with the upper surface of the first metal layer (VL1). The second metal layer (VL2) and the dielectric layer (DL) may be located between the upper surface (US1) of the second insulating layer (111) and the upper surface (US2) of the third insulating layer (112). Also, the areas of the first metal layer (VL1) and the second metal layer (VL2) may be the same or different. For example, the area of ​​the first metal layer (VL1) may be larger than the area of ​​the second metal layer (VL2).With this configuration, the first metal layer (VL1) can be connected to the third via electrode, etc., to easily form an electrical connection to the upper side. Additionally, the first metal layer (VL1) can be connected to the second via electrode (121b) penetrating the second insulating layer (111) to form an electrical connection to the lower side.

[0240] Referring further to FIG. 12, as described above, the second insulating layer (111) and the third insulating layer (112) may have a lower surface of the first metal layer (VL1) of the capacitor structure (CAS) as an interface and may simultaneously contain a resin. However, the first insulating layer (113) disposed below the second insulating layer (111) having such an interface may contain glass fibers and a resin. That is, the second insulating layer (111) and the third insulating layer (112) in contact with the first metal layer (VL1) of the capacitor structure (CAS) may not contain glass fibers.

[0241] In an example, the second insulating layer (111) may include a first filler (FL1) and a first resin (RS1). Additionally, the third insulating layer (112) may include a second filler (FL2) and a second resin (RS2). For example, the second insulating layer (111) and the third insulating layer (112) may be RCC, ABF, PID, etc. And the first insulating layer (113) may include a third filler (FL3), a third resin (RS3), and a fiber (or fiber, FI).

[0242] Accordingly, the thickness (d6) of the first insulating layer (113) may be different from the thickness (d4) of the second insulating layer (111) or the thickness (d5) of the third insulating layer (112). In an example, the thickness (d6) of the first insulating layer (113) may be greater than the thickness (d4) of the second insulating layer (111) or the thickness (d5) of the third insulating layer (112). Also, the thickness (d4) of the second insulating layer (111) may be the same as or different from the thickness (d5) of the third insulating layer (112). For example, by placing a capacitor structure (CAS) or a second wiring part (121a) on the upper surface of the second insulating layer (111), the thickness (d5) of the third insulating layer (112) may be greater than the thickness (d4) of the second insulating layer (111). Accordingly, the thickness (d4) of the second insulating layer (111), the thickness (d5) of the third insulating layer (112), and the thickness (d6) of the first insulating layer (113) can be increased sequentially. With this configuration, even if the capacitor structure (CAS) is mounted on the circuit board, the increase in the thickness of the circuit board can be minimized. Furthermore, the total thickness (d4+d5) of the second insulating layer (111) and the third insulating layer (112) can be smaller than the thickness (d6) of the first insulating layer (113). With this configuration, the miniaturization of the circuit board can be easily realized. Furthermore, by minimizing the distance between the upper or lower surface of the insulating layer adjacent to the capacitor structure (CAS), the processability of the via hole for the via electrode can be improved. Furthermore, the alignment of the via within the insulating layer can be achieved more accurately.

[0243] Additionally, by placing a thin insulating layer (e.g., a second insulating layer and a third insulating layer) between capacitor structures (CAS), the distance between components (e.g., wiring section, via electrode, capacitor structure, etc.) can also be reduced. According to an embodiment, the distance (d1, d2) between the upper surface (US2) of the third insulating layer (112) and a portion of the capacitor structure (CAS) may be smaller than the distance (d3) from the first wiring section (123a) to the lower surface (BS3) of the first insulating layer (113).

[0244] Additionally, the distance (d3) from the first wiring section (123a) to the lower surface (BS3) of the first insulating layer (113) may be greater than the thickness (d5) of the third insulating layer (112). Accordingly, the distance (d3) from the first wiring section (123a) to the lower surface (BS3) of the first insulating layer (113) may be greater than the length (d2) from the upper surface of the first metal layer (VL1) to the upper surface of the third insulating layer (112). Additionally, the distance (d3) from the first wiring section (123a) to the lower surface (BS3) of the first insulating layer (113) may be greater than the length (d1) from the upper surface of the second metal layer (VL2) to the upper surface of the third insulating layer (112). Accordingly, the penetrating thickness formed in at least a portion of the third insulating layer (112) may be smaller than the penetrating thickness formed by the via electrode in the first insulating layer (113). In addition, the spacing distance in the stacking direction (X-axis direction) between the upper surface of the first metal layer (VL1) and the second metal layer (VL2) and the third insulating layer (112) may be smaller than the length in the stacking direction of the first insulating layer (113) or the first via electrode. This makes via formation easier to implement and improves the positional alignment between the via land and the via electrode. This improves the electrical reliability of the circuit board.

[0245] Furthermore, the thickness (d4) of the second insulating layer (111) may be smaller than the thickness (d5) of the third insulating layer (112). This improves via processing capabilities, allowing the first metal layer (VL1) to be connected to the lower first wiring section more accurately.

[0246] Referring further to FIGS. 13 and 14, in the embodiment, the second via electrode (121b) penetrates the second insulating layer (111) and may be in the plurality. For example, the plurality of second via electrodes may include a second-1 via electrode (122ba) and a second-2 via electrode (122bb).

[0247] The second-1 via electrode (122ba) may be in contact with the first metal layer (VL1). For example, the second-1 via electrode (122ba) may be overlapped in a vertical direction with the first metal layer (VL1). And the second-2 via electrode (122bb) may be in contact with the second wiring portion (121a). For example, the second-2 via electrode (122bb) may be overlapped in a vertical direction with the second wiring portion (121a).

[0248] The second-1 via electrode (122ba) and the second-2 via electrode (122bb) may be spaced apart from each other and may be electrically separated. The second-1 via electrode (122ba) and the second-2 via electrode (122bb) may have the same length (d13) in the vertical direction. The length (d13) of the second-1 via electrode (122ba) and the second-2 via electrode (122bb) in the vertical direction may be the same as the thickness (d4) of the second insulating layer (111). Accordingly, the thickness of the second insulating layer (111) can be minimized, thereby reducing the overall thickness of the circuit board.

[0249] Additionally, in the embodiment, the third via electrode (122b) may penetrate the third insulating layer (112). Furthermore, the third via electrode (122b) penetrating the third insulating layer (112) according to the embodiment may be multiple and may have different lengths in the vertical direction. That is, the multiple third via electrodes (122ba, 122bb, 122bc) may have different lengths in the vertical direction (X-axis direction). In some cases, at least some of the multiple sub-electrodes may have the same length in the vertical direction. Furthermore, each sub-electrode may also be at least one.

[0250] Specifically, the third via electrode (122b) may include a third-1 via electrode (122ba), a third-2 via electrode (122bb), and a third-3 via electrode (122bc). Furthermore, the third via electrode (122b) may further include a third-4 via electrode. However, this will be described later.

[0251] First, the 3-1 via electrode (122ba) penetrates the third insulating layer (112) and can be positioned between the second wiring section (121a) and the upper surface (US2) of the third insulating layer (112). The 3-1 via electrode (122ba) can be in contact with the second wiring section (121a). The 3-1 via electrode (122ba) can be in contact with the upper surface of the second wiring section (121a). The 3-1 via electrode (122ba) can be spaced apart from the 3-2 via electrode (122bb), the 3-3 via electrode (122bc), and the 3-4 via electrode. Additionally, the 3-1 via electrode (122ba) can also be spaced apart from the capacitor structure (CAS) in the horizontal direction (Y-axis direction). Additionally, at least a portion of the 3-1 via electrode (122ba) may be positioned offset from the capacitor structure (CAS) in the horizontal direction (Y-axis direction). That is, at least a portion of the 3-1 via electrode (122ba) may not overlap with the capacitor structure (CAS) in the horizontal direction.

[0252] In various examples, the third-1 via electrode (122ba) may overlap horizontally with at least a portion of the capacitor structure (CAS) depending on the degree of etching or plating during the process. For example, depending on the thickness (d14) of the second wiring portion (121a), the third-1 via electrode (122ba) may overlap horizontally with the second metal layer (VL2). Additionally, the third-1 via electrode (122ba) may overlap horizontally (in the Y-axis direction) with the capacitor structure (CAS). For example, the thickness (d10) of the third-1 via electrode (122ba) may be smaller than the thickness (d12) of the third-3 via electrode (122bc). Conversely, the thickness (d12) of the third-3 via electrode (123bc) may be larger than the thickness (d10) of the third-1 via electrode (122ba). Accordingly, the second wiring portion (121a) can be overlapped horizontally with the first metal layer (VL1), the second metal layer (VL2), and the dielectric layer (DL).

[0253] The third-2 via electrode (122bb) can penetrate the second insulating layer (111) and the third insulating layer (112). That is, the third-2 via electrode (122bb) can extend downward through the lower surface (BS2) of the third insulating layer (112). The thickness (d11) of the third-2 via electrode (122bb) may be the largest at the third via electrode.

[0254] The third-3 via electrode (122bc) can be placed between the second metal layer (VL2) and the upper surface (US2) of the third insulating layer (112). The third-3 via electrode (122bc) can be in contact with the second metal layer (VL2). That is, the third-3 via electrode (122bc) can be in contact with the capacitor structure (CAS). And the third-3 via electrode (122bc) can be in contact with the upper surface of the second metal layer (VL2) and can be overlapped with the capacitor structure (CAS) in a vertical direction (X-axis direction). In particular, the third-3 via electrode (122bc) can be overlapped with the first metal layer (VL1), the dielectric layer (DL), and the second metal layer (VL2) in the capacitor structure (CAS) in a first direction (X-axis direction). However, depending on the case, the third-third via electrode (122bc) may overlap at least partially with the second metal layer (VL2) in a vertical direction.

[0255] In a capacitor structure (CAS), the first metal layer (VL1), the dielectric layer (DL), and the second metal layer (VL2) may have the same or different lengths or thicknesses in a direction perpendicular to each other. In an example, the thickness (d8) of the dielectric layer (DL) may be 3 μm to 15 μm. The thickness (d7) of the first metal layer (VL1) and the thickness (d9) of the second metal layer (VL2) may be 1.5 μm to 10 μm. For example, by making the thicknesses of the first metal layer (VL1), the second metal layer (VL2), and the dielectric layer (DL) in the capacitor structure (CAS) the same, the capacitor structure (CAS) can be miniaturized.

[0256] Additionally, the thickness (d7) of the first metal layer (VL1) or the thickness (d9) of the second metal layer (VL2) can be made greater than the thickness (d8) of the dielectric layer (DL) or the thickness of other via lands. For example, the thickness (d7) of the first metal layer (VL1) may be greater than the thickness (d9) of the second metal layer (VL2). Conversely, the thickness (d9) of the second metal layer (VL2) may be greater than the thickness (d7) of the first metal layer (VL1). With this configuration, exposure or removal of via lands can be suppressed when vias are formed in the region overlapping with the first metal layer or the second metal layer. This can improve the electrical reliability of the capacitor structure within the circuit board. A detailed explanation will be provided later.

[0257] And the thickness (d14) of the second wiring section (121a) may be greater than the thickness (dcas) of the capacitor structure (CAS). The upper surface of the second metal layer (VL2) in the capacitor structure (CAS) may be located below the upper surface of the second wiring section (121a). Accordingly, the second wiring section (121a) may overlap with the capacitor structure (CAS) in a horizontal direction or a second direction (Y-axis direction). The horizontal direction or the second direction (Y-axis direction) may be a direction perpendicular to the vertical direction (or the first direction, X-axis direction). Furthermore, at least a portion of the second wiring section (121a) may not overlap with the capacitor structure (CAS) in a horizontal direction (Y-axis direction). For example, the thickness (d14) of the second wiring section (121a) may be 10㎛ to 20㎛. This may be applied equally to other wiring sections (e.g., third wiring section, first wiring section, etc.).

[0258] And the total thickness (d11) of the second insulating layer (111) and the third insulating layer (112) may be different from the thickness (d6) of the first insulating layer (113). For example, the total thickness (d11) of the second insulating layer (111) and the third insulating layer (112) may be smaller than the thickness (d6) of the first insulating layer (113).

[0259] Furthermore, the distance (d3) from the first wiring section (123a) to the lower surface (BS3) of the first insulating layer (113) may be smaller than the thickness (d6) of the first insulating layer (113). Also, the distance (d3, same as d15) from the first wiring section (123a) to the lower surface (BS3) of the first insulating layer (113) may be different from the total thickness (d11) of the second insulating layer (111) and the third insulating layer (112). The distance (d15, same as d3) from the first wiring section (123a) to the lower surface (BS3) of the first insulating layer (113) may be smaller or larger than the total thickness (d11) of the second insulating layer (111) and the third insulating layer (112). For example, the distance (d15, same as d3) from the third wiring section (123a) to the lower surface (BS3) of the first insulating layer (113) may be greater than the total thickness (d11) of the second insulating layer (111) and the third insulating layer (112). This allows for minimizing the increase in the thickness of the insulating layer according to the capacitor structure (CAS).

[0260] And the thickness (d6) of the first insulating layer (113) may be different from the thickness (d11) of the third-2 via electrode (122bb). For example, the thickness (d6) of the first insulating layer (113) may be greater than the thickness (d11) of the third-2 via electrode (122bb). That is, the thickness (d11) of the third-2 via electrode (122bb) may be smaller than the thickness (d6) of the first insulating layer (113). Accordingly, even if the third-2 via electrode (122b) penetrates a plurality of insulating layers, the formation of a via electrode that allows for easy position adjustment of the via can be easily implemented.

[0261] The length (d1) from the upper surface of the second metal layer (VL2) to the upper surface of the third insulating layer (112) may differ from the total thickness (dcas) of the capacitor structure (CAS). The length (d1) from the upper surface of the second metal layer (VL2) to the upper surface of the third insulating layer (112) may be greater than the total thickness (dcas) of the capacitor structure (CAS).

[0262] Additionally, the length (d1) from the upper surface of the second metal layer (VL2) to the upper surface of the third insulating layer (112) may differ from the thickness of one wiring section. For example, the length (d1) from the upper surface of the second metal layer (VL2) to the upper surface of the third insulating layer (112) may be smaller than the thickness of one wiring section. For example, the length (d1) from the upper surface of the second metal layer (VL2) to the upper surface of the third insulating layer (112) may be smaller than the thickness (d14 or d6-d15, etc.) of the second wiring section (121a), the third wiring section (122a), or the first wiring section (123a). The thickness of each wiring section may be 10㎛ to 20㎛.

[0263] Additionally, the length (d2) from the upper surface of the first metal layer (VL1) to the upper surface of the third insulating layer (112) may be greater than the total thickness (dcas) of the capacitor structure (CAS).

[0264] With these configurations, even if a capacitor structure (CAS) is mounted within the insulating layer, a reduction in the overall thickness of the circuit board can be effectively achieved.

[0265] Furthermore, the thickness (d11) of the third-2 via electrode (122bb) may differ from the thickness (d15) of the first via electrode (123b). For example, the thickness (d11) of the third-2 via electrode (122bb) may be greater or smaller than the thickness (d15) of the first via electrode (123b). For example, the thickness (d11) of the second-2 via electrode (122bb) may be smaller than the thickness (d15) of the first via electrode (123b). By doing so, the reduction in thickness of the circuit board can be implemented more effectively.

[0266] And the thickness (d11) of the third-2 via electrode (122bb) may be different from the thickness (d10) of the third-1 via electrode (122ba) or the thickness (d12) of the third-3 via electrode (122bc). For example, the thickness (d11) of the third-2 via electrode (122bb) may be greater than the thickness (d10) of the third-1 via electrode (122ba) or the thickness (d12) of the third-3 via electrode (122bc).

[0267] Additionally, in the embodiment, at least some of the plurality of via electrodes may have different directions of increase in width. For example, the width (W7) of the second via electrode (121b) may increase or decrease along the vertical direction (X-axis direction). For example, the width (W7) of the second via electrode (121b) may increase along the vertical direction or the first direction (X-axis direction). For example, the width of the second via electrode (121b) on the upper surface of the second insulating layer (111) may be greater than the width on the lower surface of the second insulating layer (111). Also, the width (W7) of the second via electrode (121b) may decrease as it moves from the upper surface of the second insulating layer (111) toward the lower surface of the second insulating layer (111).

[0268] And the third via electrode (122b) may increase or decrease along the vertical direction (X-axis direction). For example, the width (W8) of the third via electrode (122b) may increase along the vertical direction or the first direction (X-axis direction). For example, the width of the third via electrode (122b) on the upper surface of the third insulating layer (112) may be greater than the width on the lower surface of the third insulating layer (112). Also, the width (W8) of the third via electrode (122b) may decrease as it moves from the upper surface of the third insulating layer (112) toward the lower surface of the third insulating layer (112).

[0269] And the width (W9) of the first via electrode (123b) may decrease along the vertical direction or the first direction (X-axis direction). The width of the first via electrode (123b) on the upper surface of the first insulating layer (113) may be smaller than the width on the lower surface of the first insulating layer (113). Additionally, the width (W9) of the first via electrode (123b) may increase as it moves from the upper surface of the second insulating layer (111) (or the first insulating layer) toward the lower surface of the second insulating layer (111) (or the first insulating layer).

[0270] In this way, the width (W7) of the second via electrode (121b) and the width (W8) of the third via electrode (122b) may increase along the stacking direction or vertical direction (X-axis direction), and the width (W9) of the first via electrode (123b) may decrease along the stacking direction or vertical direction (X-axis direction).

[0271] Referring to FIG. 15, as a variation example, the width (W1') of the second via electrode (121b) may decrease along the vertical direction, and the width (W8) of the third via electrode (122b) may increase along the vertical direction. That is, in the embodiment, at least some of the multiple via electrodes may have different directions of increase in width.

[0272] That is, the width of the second via electrode (121b) on the upper surface of the second insulating layer (111) may be smaller than the width on the lower surface of the second insulating layer (111). Additionally, the width (W1') of the second via electrode (121b) may increase as it moves from the upper surface of the second insulating layer (111) toward the lower surface of the second insulating layer (111).

[0273] And the third via electrode (122b) may increase or decrease along the vertical direction (X-axis direction). For example, the width (W8) of the third via electrode (122b) may increase along the vertical direction or the first direction (X-axis direction). For example, the width of the third via electrode (122b) on the upper surface of the third insulating layer (112) may be greater than the width on the lower surface of the third insulating layer (112). Also, the width (W8) of the third via electrode (122b) may decrease as it moves from the upper surface of the third insulating layer (112) toward the lower surface of the third insulating layer (112).

[0274] As such, the second insulating layer (111) and the third insulating layer (112), which are in contact with at least a portion of the capacitor structure (CAS), may have the direction of increase in the width of the via electrode opposite to the lower surface of the first metal layer (VL1). The lower surface of the first metal layer (VL1) may be the boundary surface of the insulating layer. Furthermore, the width of the via electrode formed in the upper insulating layer relative to the lower surface of the first metal layer (VL1) may increase along the vertical direction. Additionally, the width of the via electrode formed in the lower insulating layer relative to the lower surface of the first metal layer (VL1) may decrease along the vertical direction. Furthermore, as described above, the thickness of the second insulating layer (111) may be smaller than the thickness of the third insulating layer (112).

[0275] Additionally, the angle formed by the second via electrode (121b) with the upper surface of the second insulating layer (111) may be different from the angle formed by the first via electrode (123b) with the upper surface of the first insulating layer (113). As described above, the second insulating layer (111) and the first insulating layer (113) may be made of different materials. Accordingly, the via for forming the via electrode may also have inclined surfaces at different angles.

[0276] Referring to FIG. 16, as a variation example, the second electrode portion (121) located on the second insulating layer (111) may only have a second via electrode (121b). For example, the second electrode portion (121) may not have a second wiring portion disposed on the upper surface of the second insulating layer (111). Accordingly, the second via electrode (121b) overlaps in a vertical direction with the first metal layer (VL1) and may come into contact with the first metal layer (VL1).

[0277] Accordingly, since the aforementioned second wiring section does not exist in the second insulating layer, the third wiring section (122a) and the first wiring section (123a) can be connected through the third-2 via electrode (122bb). The third-2 via electrode (122bb) can be superimposed in a vertical direction with the third wiring section (122a) and the first wiring section (123a). Also, the third-2 via electrode (122b) can be in contact with the third wiring section (122a) and the first wiring section (123a). And since the second wiring section (121a) does not exist, the aforementioned third-1 via electrode may also not exist. The third-2 via electrode (122bb) may be larger than the sum of the thicknesses of the third-3 via electrode (122bc) and the second via electrode (121b).

[0278] Furthermore, since only a capacitor structure (CAS) exists on the upper surface of the second insulating layer (111) and the second wiring part is not located thereon, the thickness of the third insulating layer (112) can be further reduced. Thus, the miniaturization of the circuit board can be achieved more effectively.

[0279] Referring to FIG. 17, as a variation, the thickness of each layer in the capacitor structure (CAS) can be varied. For example, the thickness (d7') of the first metal layer (VL1) may differ from the thickness (d9) of the second metal layer (VL2) or the thickness (d8) of the dielectric layer (DL). For example, the thickness (d7') of the first metal layer (VL1) may be greater than the thickness (d9) of the second metal layer (VL2). With this configuration, exposure or removal of via lands can be suppressed when vias are formed in the region overlapping with the first metal layer. As a result, the electrical reliability of the capacitor structure within the circuit board can be improved. A detailed explanation will be provided later.

[0280] Furthermore, due to the thickness control of the first metal layer (VL1) or the second metal layer (VL2), the thickness of the capacitor structure (CAS) may be greater than the thickness (d14') of the second wiring section (121a). Also, the thickness (d10') of the third-1 via electrode (122ba) may be greater than the thickness (d12') of the third-3 via electrode (122bc). With this configuration, at least a portion of the capacitor structure (CAS) may not overlap with the second wiring section (121a) in the horizontal direction (Y-axis direction). And at least a portion of the capacitor structure (CAS) may overlap with the third-1 via electrode (122ba) in the horizontal direction (Y-axis direction).

[0281] Conversely, the thickness (d9) of the second metal layer (VL2) may be greater than the thickness (d7) of the first metal layer (VL1). Accordingly, exposure or removal of via lands can be suppressed when vias are formed in the area overlapping with the second metal layer.

[0282] FIG. 18 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, FIG. 19 is an enlarged view of the K8 portion in FIG. 18, and FIG. 20 is a variation of FIG. 19.

[0283] Referring to FIG. 18, a circuit board (100C) according to the fourth embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100B) may further include a core layer which is a protective layer disposed on the electrode portion (120) or an insulating layer disposed within the insulating layer (110). Furthermore, the configurations described in the embodiments of the present invention may be applied identically, except for the details described below. Furthermore, the structures for the various variations described above may also be applied identically, except for the details described below.

[0284] In particular, in this embodiment, the third via electrode (122b) may further include a third-fourth via electrode (124bd). The third-fourth via electrode (122bd) may be disposed between the first metal layer (VL1) and the upper surface (US2) of the third insulating layer (112). The third-fourth via electrode (122bd) may be in contact with the first metal layer (VL1). The third-fourth via electrode (122bd) may be in contact with the upper surface of the first metal layer (VL1). The third-fourth via electrode (122bd) may be spaced apart from the third-third via electrode (122bc) in the horizontal direction (Y-axis direction). The third-fourth via electrode (122bd) may overlap with the capacitor structure (CAS) in the horizontal direction (Y-axis direction). Additionally, the third-fourth via electrode (122bd) may overlap the second wiring portion (121a) in a horizontal direction (Y-axis direction). Also, the thickness (d16) of the third-fourth via electrode (122bd) may be greater than the thickness of the second wiring portion (121a). Furthermore, the thickness (d16) of the third-fourth via electrode (122bd) may be greater than the thickness of the capacitor structure (CAS).

[0285] Additionally, the third-fourth via electrode (122bd) may overlap with a part of the capacitor structure (CAS) in the first direction (X-axis direction). The third-fourth via electrode (122bd) may overlap with the dielectric layer (DL) and the second metal layer (VL2) in the capacitor structure (CAS) in the horizontal direction (Y-axis direction).

[0286] Additionally, the third-fourth via electrode (122bd) may overlap vertically with the first metal layer (VL1) of the capacitor structure (CAS). The third-fourth via electrode (122bd) may be positioned offset from the dielectric layer (DL) and the second metal layer (VL2) of the capacitor structure (CAS) without overlapping vertically. For example, the third-fourth via electrode (122bd) may be spaced apart horizontally (in the Y-axis direction) from the dielectric layer (DL) and the second metal layer (VL2) of the capacitor structure (CAS). Furthermore, the third-third via electrode (122bc) and the third-fourth via electrode (122bd) may be electrically connected to the capacitor structure (CAS).

[0287] Furthermore, the third-4 via electrode (122bd) may overlap at least a portion of the third-1 via electrode (122ba), the third-2 via electrode (122bb), and the third-3 via electrode (122bc) in the horizontal direction. And the third-4 via electrode (122bd) may have the longest length in the vertical direction among the plurality of third via electrodes, excluding the third-2 via electrode.

[0288] Referring to FIG. 20, as described above as a variation example, the thickness of each layer in the capacitor structure (CAS) can be varied. For example, the thickness of the first metal layer (VL1) may differ from the thickness of the second metal layer (VL2) or the thickness of the dielectric layer (DL). For example, the thickness of the first metal layer (VL1) may be greater than the thickness of the second metal layer (VL2). With this configuration, exposure or removal of via lands can be suppressed when vias are formed in the region overlapping with the first metal layer. As a result, electrical reliability of the capacitor structure within the circuit board can be improved.

[0289] In particular, as the thickness of the first metal layer (VL1) increases, the thickness of the third-fourth via electrode (122bd) may decrease. This allows the formation of the third-fourth via electrode (122bd) to be implemented more easily and accurately.

[0290] Furthermore, due to the thickness control of the first metal layer (VL1) or the second metal layer (VL2), the thickness of the capacitor structure (CAS) may be greater than the thickness of the second wiring portion (121a). Furthermore, the thickness of the third-1 via electrode (122ba) may be greater than the thickness of the third-4 via electrode (122bd).

[0291] FIG. 21 is an SEM image of a circuit board according to an embodiment, and FIG. 22 is an enlarged view of the K9 portion in FIG. 21.

[0292] Referring to FIGS. 21 and 22, it is shown that in a circuit board according to an embodiment, a first insulating layer (114) is further disposed below the first insulating layer (113), and a first electrode portion (124) is further formed on the first insulating layer (114).

[0293] In particular, it can be seen that the capacitor structure (CAS) on the circuit board has a thickness smaller than the thickness of the first insulating layer (113). Furthermore, it can be seen that the third and fourth via electrodes have a thickness smaller than the thickness of the first insulating layer (113). Additionally, it can be seen that the thickness of the first insulating layer (113) is smaller than the thickness of the second insulating layer (111) or the thickness of the third insulating layer (112). Moreover, it can be seen that the thickness of the first insulating layer (113) is greater than the total thickness of the second insulating layer (111) and the third insulating layer (112). Thus, it can be seen that the thickness of the first and second insulating layers (111, 112) covering the capacitor structure (CAS) within the circuit board on which the capacitor structure (CAS) is mounted can have a thickness smaller than that of the lower first insulating layer (113). Thus, as described above, the miniaturization of the circuit board can be efficiently implemented.

[0294] FIG. 23 is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 24 is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 25 is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 26 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0295] In the various semiconductor packages described below, the circuit board described above may be located in a part of the area or correspond to a single substrate.

[0296] Referring to FIG. 23, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor device (1300).

[0297] The first substrate (1100) may mean a 'package substrate' or a 'circuit board', or may include such meanings. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). Additionally, the external substrate may mean a main board included in an electronic device coupled to the lower part of the first substrate (1100).

[0298] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space for mounting at least one semiconductor device.

[0299] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0300] A second substrate (1200) can be placed on the first substrate (1100).

[0301] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space for mounting at least one semiconductor device. The second substrate (1200) may be connected to at least one semiconductor device (1300). For example, the second substrate (1200) may provide a space for mounting a first semiconductor device (1310) and a second semiconductor device (1320). The second substrate (1200) may electrically connect the first semiconductor device (1310) and the second semiconductor device (1320), and electrically connect the first and second semiconductor devices (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between multiple semiconductor devices and a vertical connection function between a semiconductor device and a package substrate.

[0302] Additionally, although it has been illustrated that two semiconductor devices (1310, 1320) are disposed on the second substrate (1200) as in the example above, it is not limited thereto. For example, one semiconductor device may be disposed on the second substrate (1200), or three or more semiconductor devices may be disposed therein.

[0303] The second substrate (1200) can be placed between at least one semiconductor device (1300) and the first substrate (1100).

[0304] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a stacked structure in a vertical direction on the first substrate (1100) and may function as a plurality of logic chips. The ability to function as a logic chip may mean that it may have the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may have the function of an active device. Additionally, while the active interposer functions as a corresponding logic chip, it may perform a signal transmission function between the second logic chip placed on top of it and the first substrate (1100).

[0305] According to another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, capacitor, or inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IOT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between multiple terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of an electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for being connected to the semiconductor device (1300) and the main board, respectively, there is a problem in that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complex. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor device (1300). The second substrate (1200) may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device (1300).

[0306] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stacked memory such as HBM.

[0307] Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0308] For example, the semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) can electrically connect the two substrates while coupling the second substrate (1200) to the first substrate (1100).

[0309] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor device (1300). The second connection portion (1420) can electrically connect the semiconductor device (1300) while coupling it to the second substrate (1200).

[0310] The semiconductor package may include a third connection portion (1430) disposed on the lower surface of the first substrate (1100). The third connection portion (1430) can electrically connect the first substrate (1100) to the main board while coupling them together.

[0311] At this time, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can electrically connect multiple components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection part (1410), the second connection part (1420), and the third connection part (1430) have the function of electrically connecting multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as an electrically connected part rather than solder or wire.

[0312] Wire bonding may refer to electrically connecting multiple components using a conductor such as gold (Au). Additionally, solder bonding may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. Furthermore, direct metal-to-metal bonding may refer to directly bonding multiple components by applying heat and pressure between them to cause recrystallization without the use of solder, wire, conductive adhesive, etc. And direct metal-to-metal bonding may refer to a bonding method using the second connection part (1420). In this case, the second connection part (1420) may refer to a metal layer formed between multiple components by recrystallization.

[0313] Specifically, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can join multiple components together by a thermal compression bonding method. A thermal compression bonding method may refer to a method of directly joining multiple components by applying heat and pressure to the first connection part (1410), the second connection part (1420), and the third connection part (1430).

[0314] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrode on which the first connection part (1410), the second connection part (1420), and the third connection part (1430) are disposed may be provided with a protrusion extending outwardly away from the insulating layer of the corresponding substrate. The protrusion may extend outwardly from the first substrate (1100) or the second substrate (1200).

[0315] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor device (1300) is disposed among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor device (1300) becomes finer, a short circuit may occur between a plurality of second connection portions (1420) that are each connected to a plurality of terminals of the semiconductor device (1300) by a conductive adhesive such as solder. Therefore, the embodiment may perform thermal compression bonding to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion on the electrode of the second substrate (1200) on which the second connection portion (1420) is disposed, in order to secure a degree of alignment, diffusion power, and a diffusion prevention power that prevents an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or substrate.

[0316] Additionally, looking further at FIG. 23, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0317] The connecting member (1210) can be a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) can function to electrically connect a plurality of semiconductor devices horizontally to each other. For example, because the area that a semiconductor device generally needs to have is too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or breadth of the circuit pattern, a buffering role for the circuit pattern for electrical connection is required. The buffering role may mean having an intermediate size between the size of the width or breadth of the circuit pattern of the semiconductor package and the size of the width or breadth of the circuit pattern of the semiconductor device, and the redistribution layer may include a function that performs the buffering role.

[0318] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate containing an organic material instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0319] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be disposed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements disposed on the second substrate (1200).

[0320] Referring to FIG. 24, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor device (1300). In this case, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0321] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0322] The first connection part (1410) disposed on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0323] Referring to FIG. 25, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor device (1300).

[0324] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0325] That is, the first substrate (1100) of the third embodiment functions as a package substrate and can also function to connect between a semiconductor device (1300) and a main board. To this end, the first substrate (1100) may include a connecting member (1110) for connecting between a plurality of semiconductor devices. The connecting member (1110) may be an organic bridge connecting between a plurality of semiconductor devices.

[0326] Referring to FIG. 26, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connection portion may be further disposed on one side of the first substrate (1100).

[0327] Thus, the semiconductor package of the fourth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively. At this time, the third semiconductor device (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0328] And a connecting member (1110) may be embedded in the first substrate (1100). The connecting member (1110) may horizontally connect the first and second semiconductor devices (1310, 1320).

[0329] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may protrude further from the first substrate (1100) toward the second semiconductor device (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, a post. The conductive coupling portion (1450) may be disposed having a structure protruding on an electrode disposed on the uppermost side of the first substrate (1100).

[0330] A third semiconductor device (1330) may be disposed on the conductive coupling portion (1450). At this time, the third semiconductor device (1330) may be connected to the first substrate (1100) through the conductive coupling portion (1450). Additionally, a second connection portion (1420) may be disposed between the first and second semiconductor devices (1310, 1320) and the third semiconductor device (1330).

[0331] Accordingly, the third semiconductor device (1330) can be electrically connected to the first and second semiconductor devices (1310, 1320) through the second connection part (1420).

[0332] That is, the third semiconductor device (1330) is connected to the first substrate (1100) through the conductive coupling portion (1450), and can also be connected to the first and second semiconductor devices (1310, 1320) through the second connection portion (1420).

[0333] At this time, the third semiconductor device (1330) can receive a power signal and / or power through the conductive coupling portion (1450). In addition, the third semiconductor device (1330) can exchange communication signals with the first and second semiconductor devices (1310, 1320) through the second connection portion (1420).

[0334] The semiconductor package of the fourth embodiment can supply a power signal and / or power to the third semiconductor device (1330) through the conductive coupling portion (1450), thereby enabling the provision of sufficient power for driving the third semiconductor device (1330) or smooth control of power operation.

[0335] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor device (1330). That is, the embodiment can solve the problem of insufficient power being supplied to the third semiconductor device (1330). Furthermore, the embodiment can allow at least one of the power signal, power, and communication signal of the third semiconductor device (1330) to be provided through different paths via the conductive coupling part (1450) and the second connection part (1420). By doing so, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0336] Meanwhile, the third semiconductor device (1330) in the fourth embodiment may be disposed on the first substrate (1100) having a POP (Package On Package) structure in which a plurality of package substrates are stacked. For example, the third semiconductor device (1330) may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling portion (1450). At this time, the memory package may not be connected to the first and second semiconductor devices (1310, 1320).

[0337] Furthermore, the semiconductor package of the modified example may include a first substrate (1100) and first and second semiconductor devices (1310, 1320) disposed on the first substrate (1100) as in the example above. Furthermore, the semiconductor package may include a first connection portion (1410) disposed between the first substrate (1100) and the first and second semiconductor devices (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the example above.

[0338] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0339] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0340] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0341] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0342] Although the above description has focused on the embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulating layer; A second insulating layer disposed on the first insulating layer; A capacitor structure disposed between the first insulating layer and the second insulating layer; A first via electrode penetrating the first insulating layer; and A second via electrode disposed between the upper surface of the first insulating layer and the upper surface of the second insulating layer; comprising The first via electrode and the second via electrode are circuit boards having different inclination angles.

2. In Paragraph 1, A circuit board comprising: a first wiring portion disposed on the first insulating layer.

3. In Paragraph 2, The first wiring section is a circuit board that overlaps horizontally with the capacitor structure.

4. In Paragraph 2, A circuit board in which the width of the first wiring portion corresponds to the width of the second via electrode.

5. In Paragraph 2, The above-mentioned first wiring portion comprises a first layer and a second layer disposed on the first layer; a circuit board.

6. In Paragraph 5, A circuit board comprising: a first layer having a protrusion protruding toward the second insulating layer and an outer portion disposed on the outside of the protrusion.

7. In Paragraph 1, The above capacitor structure is, A circuit board comprising a first via land, a dielectric layer, and a second via land sequentially stacked on the first insulating layer.

8. In Paragraph 7, The second via electrode above is, A first sub-electrode disposed between the second via land and the upper surface of the second insulating layer; and A circuit board comprising: a second sub-electrode disposed between the first via land and the upper surface of the second insulating layer.

9. In Paragraph 8, The first sub-electrode is superimposed in a vertical direction with the capacitor structure, and The second sub-electrode is offset in a direction perpendicular to the second via-land and overlaps with the first via-land in a direction perpendicular to the circuit board.

10. In Paragraph 8, A circuit board in which the length in the vertical direction of the first sub-electrode is smaller than the length in the vertical direction of the second sub-electrode.

Images