Electronic device for checking quality of plurality of links, and operating method of electronic device

Abstract

In an electronic device and an operating method of an electronic device, according to various embodiments, the electronic device comprises: a communication circuit including a main processor for transmitting and / or receiving a signal through an activated link from among a plurality of links associated with an access point (AP), and an auxiliary processor for receiving the signal through one antenna electrically connected to both the main processor and the auxiliary processor; a memory for storing a computer program including instructions; and at least one application processor, wherein, when individually or collectively executed by the at least one application processor, the instructions can instruct the electronic device to: check that a performance condition of an operation for checking the quality of the respective links is satisfied while performing short-range wireless communication through the activated link; on the basis of checking that the performance condition of the operation for checking the quality of the respective links is satisfied, control the communication circuit such that the main processor checks the quality of the activated link and the auxiliary processor checks the quality of a deactivated link from among the plurality of links; and control at least one link from among the plurality of links on the basis of the quality of the respective links.

Description

Electronic device for verifying the quality of multiple links and method of operation of the electronic device

[0001] One embodiment relates to an electronic device and a method of operating the electronic device, and is an electronic device for verifying the quality of a plurality of links.

[0002] With the proliferation of various electronic devices, speed improvements have been achieved for wireless communication that these devices can use. Among the wireless communications supported by recent electronic devices, IEEE 802.11 WLAN (or Wi-Fi) is a standard for implementing high-speed wireless connections on various electronic devices. While the first implemented Wi-Fi could support transmission speeds of up to 1 to 9 Mbps, Wi-Fi 6 technology (or IEEE 802.11 ax) can support transmission speeds of up to approximately 10 Gbps.

[0003] The electronic device can support various services using relatively large data (e.g., UHD quality video streaming service, AR (augmented reality) service, VR (virtual reality) service, or MR (mixed reality) service) through wireless communication that supports high transmission speeds.

[0004] The IEEE 802.11 WLAN standard plans to introduce technology supporting multi-link operation (MLO) to improve data transmission and reception speeds and reduce latency. Electronic devices supporting multi-link operation can transmit or receive data through multiple links, and are expected to achieve relatively high transmission speeds and low latency.

[0005] An electronic device can check the quality of multiple links to perform short-range wireless communication using multiple links. According to one example, the electronic device can perform short-range wireless communication through an active link among the multiple links. A deactivated link among the multiple links may not be used for short-range wireless communication. However, the electronic device may enable a deactivated link among the multiple links due to various causes. According to one example, if the quality of at least some of the active links is degraded, the electronic device may check the quality of a deactivated link and switch the deactivated link to an active state based on the fact that the quality of the deactivated link is higher than the quality of some of the active links.

[0006] The electronic device may need to continuously check the quality of the disabled link and the quality of the enabled link. However, the electronic device may be unable to use the enabled link in order to check the quality of the disabled link. For example, the electronic device may need to interrupt the transmission of a signal (or data, frame) through the enabled link in order to check the quality of a signal received through the disabled link. Interruption of the transmission and / or reception of signals through the enabled link may cause a degradation in the performance of the short-range wireless communication.

[0007] The technical problems to be solved in this document are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which this invention belongs from the description below.

[0008] An electronic device according to one example may include a communication circuit comprising a main processor that transmits and / or receives a signal through an active link among a plurality of links associated with an access point (AP), and an auxiliary processor that receives a signal through an antenna electrically connected to both the main processor and the auxiliary processor. The electronic device may include a memory that stores a computer program including instructions. The electronic device may include at least one application processor. The instructions may cause the electronic device to confirm, when executed individually or collectively by the at least one application processor, that the conditions for performing an operation to check the quality of each of the plurality of links are satisfied while performing short-range wireless communication through the active link. The instructions may cause the communication circuit to be controlled so that, when executed individually or collectively by the at least one application processor, the main processor checks the quality of the active link and the auxiliary processor checks the quality of the inactive link among the plurality of links, based on the confirmation that the electronic device satisfies the conditions for performing an operation to check the quality of each of the plurality of links. The above instructions may enable the electronic device to control at least one of the plurality of links based on the quality of each of the plurality of links when executed individually or collectively by the at least one application processor.

[0009] A computer-readable recording medium storing instructions that cause an electronic device to perform when executed by at least one processor of an electronic device according to one example, wherein the instructions may cause the electronic device to perform short-range wireless communication through an active link among a plurality of links associated between an access point (AP) and the electronic device when executed individually or collectively by the at least one processor. The instructions may cause the electronic device to control the communication circuit so that, when executed individually or collectively by the at least one processor, a main processor included in the communication circuit of the electronic device checks the quality of the active link and an auxiliary processor included in the communication circuit checks the quality of the inactive link among the plurality of links. The instructions may cause the electronic device to control at least one link among the plurality of links based on the quality of each of the plurality of links when executed individually or collectively by the at least one processor.

[0010] A method of operation of an electronic device according to one example may include an operation of performing short-range wireless communication through an active link among a plurality of links associated between an access point (AP) and the electronic device. The method of operation of the electronic device may include an operation in which a main processor included in the communication circuit of the electronic device checks the quality of the active link, and an auxiliary processor included in the communication circuit checks the quality of an inactive link among the plurality of links. The method of operation of the electronic device may include an operation of controlling at least one link among the plurality of links based on the quality of each of the plurality of links.

[0011] According to one embodiment, an electronic device and a method of operating the electronic device may control the communication circuit so that the main processor of the communication circuit checks the quality of an active link, and the auxiliary processor of the communication circuit checks the quality of a deactivated link. The auxiliary processor of the communication circuit may not affect the performance of the active link and may prevent the main processor performing short-range wireless communication through the active link from switching the active link to a deactivated state in order to check the quality of the deactivated link. Accordingly, the electronic device can check the quality of a deactivated link without affecting the active link and can improve the performance of short-range wireless communication through appropriate control of a plurality of links.

[0012] The effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present disclosure belongs from the description below.

[0013] FIG. 1 is a block diagram of an electronic device according to one embodiment.

[0014] FIG. 2a is a diagram illustrating an embodiment in which an electronic device operates as a multi-link operation (MLO) according to one embodiment.

[0015] FIG. 2b is a diagram illustrating an embodiment in which an electronic device according to one embodiment operates in a non-STR (simultaneous transmission and reception) mode.

[0016] FIG. 3 is a diagram illustrating an example of checking the quality of a third link while an electronic device according to one embodiment performs short-range wireless communication through a first link and a second link.

[0017] FIG. 4 is a block diagram of an electronic device according to one embodiment.

[0018] FIG. 5 is a diagram illustrating an example in which an electronic device according to one embodiment checks the quality of a plurality of links.

[0019] FIG. 6 is a diagram illustrating an example in which an electronic device according to one embodiment checks the quality of a plurality of links.

[0020] FIG. 7 is a diagram illustrating an example of switching an active link when an electronic device according to one embodiment operates as a multi links single radio (MLSR).

[0021] FIG. 8 is a diagram illustrating an example of switching combinations of activated links when an electronic device according to one embodiment operates in MLMR (multi links multi radio) mode.

[0022] FIG. 9 is an operation flowchart illustrating the operation method of an electronic device according to one embodiment.

[0023] FIG. 1 is a block diagram of an exemplary electronic device (100) capable of performing the operations described in this document.

[0024] Referring to FIG. 1, the electronic device (100) may be one of various forms of electronic devices, such as a notebook (190), smartphones (191) having various form factors (e.g., a bar-type smartphone (191-1), a foldable-type smartphone (191-2), or a sliderable (or rollable)-type smartphone (191-3)), a tablet (192), a cellular phone (not shown), and other similar computing devices (not shown). The components, their relationships, and their functions illustrated in FIG. 1 are illustrative only and are not intended to limit the implementations described or claimed herein. The electronic device (100) may be referred to as a mobile device, a user device, a multifunction device, a portable device, or a server.

[0025] The electronic device (100) may include components comprising at least one processor (110) (hereinafter referred to as processor (110)), at least one memory (120) (hereinafter referred to as memory (120))11, at least one display (140) (hereinafter referred to as display (140)), at least one image sensor (150) (hereinafter referred to as image sensor (150)), at least one communication circuit (160) (hereinafter referred to as communication circuit (160)), and / or at least one sensor (170) (hereinafter referred to as sensor (170)). The components are merely exemplary. For example, the electronic device (100) may include other components (e.g., power management integrated circuitry (PMIC), audio processing circuit, antenna, rechargeable battery, or input / output interface). For example, some components may be omitted from the electronic device (100). For example, some components may be integrated into a single component.

[0026] The processor (110) may be implemented as one or more IC (integrated circuit (or circuitry)) chips and may perform various data processing operations. The processor (110) may include at least one electrical circuit and may process instructions (or programs, data, etc.) stored in memory (120) individually or collectively in a distributed manner. The processor (110) may include a processor assembly comprising one or more processing circuits. The processor (110) may include any processing circuit that is operative to control the performance and operations of one or more components of the electronic device (100) (e.g., memory (120), display (140), image sensor (150), communication circuit (160), and / or sensor (170)). For example, the processor (110) (e.g., application processor (AP)) may be implemented as a system on chip (SoC) (e.g., a single chip or chipset). For example, the processor (110) may be implemented with a plurality of cores (or at least one core circuit), a plurality of chips, or a plurality of chipsets. For example, the processor (110) may include one or more processing circuits. For example, the processor (110) may include one or more processing circuits configured to perform the various functions of the present disclosure individually and / or collectively. As an example without limitation, at least a portion of the processor (110) may be included in a first chip of the electronic device (100), and at least another portion of the processor (110) may be included in a second chip of the electronic device (100) different from the first chip of the electronic device (100).

[0027] For example, the processor (110) may include a central processing unit (111), a graphics processing unit (112), a neural processing unit (113), an image signal processor (114), a display controller (115), a memory controller (116), a storage controller (117), a communication processor (118), and / or a sensor interface (119). These components of the processor (110) are merely exemplary. For example, the processor (110) may include other components. For example, some components of the processor (110) may be omitted from the processor (110). For example, some components of the processor (110) may be included as separate components of the electronic device (100) outside of the processor (110). For example, some components of the processor (110) (e.g., memory controller (116)) may be included in other components (e.g., at least part of memory (120), an interface (e.g. available for connection to at least one component of the electronic device (100)), a display (140) and / or an image sensor (150)).

[0028] The processor (110) may cause other components of the electronic device (100) to perform various operations by executing instructions stored in memory (120). The CPU (111) (or central processing circuit) may be configured to control the components of the processor (110) based on the execution of instructions stored in memory (120) (e.g., volatile memory (121) and / or non-volatile memory (122)). The GPU (112) (or graphics processing circuit) may be configured to execute parallel operations (e.g., rendering). The NPU (113) (or neural processing circuit, or AI (artificial intelligence) chip) may be configured to execute operations for an artificial intelligence model (e.g., convolution computation). An ISP (114) (or image signal processing circuit) may be configured to process a raw image acquired through an image sensor (150) into a format suitable for a component within the electronic device (100) or a component of the processor (110). A display controller (115) (or display control circuit, or DPU (display processing unit)) may be configured to process an image acquired from a CPU (111), GPU (112), ISP (114), or memory (120) (e.g., volatile memory (121)) into a format suitable for a display (140). A memory controller (116) (or memory control circuit) may be configured to control reading data from the volatile memory (121) and writing data to the volatile memory (121). A storage controller (117) (or storage control circuit) may be configured to control reading data from the non-volatile memory (122) and writing data to the non-volatile memory (122).The CP (118) (communication processing circuit) may be configured to process data obtained from a component of the processor (110) into a format suitable for transmitting to another electronic device via the communication circuit (160), or to process data obtained from another electronic device via the communication circuit (160) into a format suitable for processing by the component of the processor (110). For example, the communication circuit (160) may include one or more communication circuits. The sensor interface (119) (or sensing data processing circuit, sensor hub) may be configured to process data regarding the state of the electronic device (100) and / or the state around the electronic device (100), obtained through the sensor (170), into a format suitable for the component of the processor (110).

[0029] Memory (120) may include one or more storage media (or one or more storage devices). For example, memory (120) may include a memory assembly comprising one or more storage media. For example, the one or more storage media may include a hard drive, a permanent memory such as flash memory, read-only memory (ROM) (e.g., non-volatile memory (122)), a semi-permanent memory such as random access memory (RAM) (e.g., volatile memory (121)), any other suitable type of storage (or storage assembly), or any combination thereof. Memory (120) may include a cache memory, which is one or more different types of memory used to temporarily store data for a function or feature of the electronic device (100). As an example not limited to, the cache memory may be included within the processor (110). The memory (120) may be fixedly embedded within the electronic device (100) or incorporated into one or more suitable types of components (e.g., a SIM (subscriber identity module) card and / or an SD (secure digital) card) that can be repeatedly inserted into and removed from the electronic device (100).

[0030] For example, memory (120) may store one or more software applications, such as operating system (or system) software applications, firmware software applications, driver software applications, plugin (e.g., add-in, add-on, and / or applet) software applications, and / or any other suitable software applications. For example, the one or more software applications may include instructions executable by the processor (110). For example, memory (120) may store instructions that can be called by an application programming interface (API). For example, memory (120) may store instructions within a library.

[0031] FIG. 2a is a diagram illustrating an embodiment in which an electronic device and an access point (AP) operate as a multi-link operation (MLO) according to one embodiment.

[0032] Referring to FIG. 2a, the wireless LAN system (200) may include an electronic device (210) and / or an external electronic device (220). According to one embodiment, the electronic device (210) may perform short-range wireless communication with the external electronic device (220). Short-range wireless communication may refer to various communication methods that both the electronic device (210) and / or the external electronic device (220) can support. For example, the short-range wireless communication may be Wi-Fi. The external electronic device (220) may serve as a base station providing short-range wireless communication to at least one electronic device (210) located within the communication radius of the wireless LAN system (200). For example, the external electronic device (220) may include an IEEE 802.11 access point (AP). The electronic device (210) may include an IEEE 802.11 station (STA).

[0033] The Wi-Fi of the electronic device (210) may have a separate Wi-Fi network interface on a host processor for controlling operation in a wireless local area network (LAN) chipset. This may include the contents of a separate standard defined in software at an upper layer of the MAC / PHY in the WLAN chipset in accordance with the IEEE 802.11 standard.

[0034] For example, in the case of a Wi-Fi network interface compliant with Wi-Fi Direct, the interface can be created according to the Wi-Fi Direct standard, and in the case of Wi-Fi Aware, the interface can be created according to the Wi-Fi Aware standard. Here, the term "interface" refers to a high-level software protocol stack of a WLAN chipset that can control WLAN chipsets by creating a separate protocol based on the MAC / PHY standard protocol of the WLAN chipset compliant with the IEEE 802.11 standard. When a host processor application uses the WLAN chipset via the corresponding network interface, it can make the WLAN chipset operate according to the corresponding protocol.

[0035] For example, in the case of a mirroring application that creates a network interface using Wi-Fi Direct, it can find and connect to a device called a TV using the Wi-Fi Direct standard protocol based on the IEEE 802.11 standard.

[0036] One or more network interfaces can be created to control the WLAN chipset. For example, an electronic device can create an STA network interface to communicate with a Wi-Fi AP and establish a connection with the Wi-Fi AP in accordance with the IEEE 802.11 standard, and applications requiring communication with an external server used by the user (e.g., an internet browser) can utilize this STA interface. To mirror to a TV using Wi-Fi Direct, the task can be dedicated to a mirroring application that uses signals in accordance with the Wi-Fi Direct standard to find and connect to the device and transmit the Wi-Fi screen.

[0037] According to one embodiment, each network interface can simultaneously control a WLAN chipset. For example, an STA network interface can communicate with a Wi-Fi AP device through communication to a first link of the WLAN chipset. Mirroring data can be transmitted to a TV through a second link using a Wi-Fi Direct network interface. That is, depending on the network interface, different data can be transmitted to different devices via different links simultaneously.

[0038] According to one embodiment, the electronic device (210) and / or the external electronic device (220) may support multi-link operation (MLO). Multi-link operation may be an operation mode that transmits or receives data through multiple links (e.g., a first link (231), a second link (232)). Multi-link operation may be an operation mode that transmits or receives data through multiple links based on multiple bands or channels, as an operation mode scheduled to be introduced in IEEE 802.11be.

[0039] According to one embodiment, the electronic device (210) may include a plurality of processors (e.g., a first processor (211) and / or a second processor (212)) to support multi-link operation. The first processor (211) may transmit data to an external electronic device (220) through a first link (231) or receive data transmitted by the external electronic device (220) through the first link (231). The first processor (211) may output or receive a signal of a frequency band corresponding to the first link (231) through a first antenna (213). The second processor (212) may transmit data to an external electronic device (220) through a second link (232) or receive data transmitted by the external electronic device (220) through the second link (232). The second processor (212) can output or receive a signal of a frequency band corresponding to the second link (232) through the second antenna (214). The first processor (211) and the second processor (212) are entities implemented on a communication circuit for performing short-range wireless communication of the electronic device (210), and may be entities that perform demodulation and decoding of a signal received through short-range wireless communication. The first processor (211) and the second processor (212) may be referred to as a core or a radio.

[0040] According to one embodiment, an external electronic device (220) may include a plurality of communication circuits (e.g., a third processor (221) and / or a fourth processor (222)) to support multi-link operation. The third processor (221) may transmit data to the electronic device (210) through the first link (231) or receive data transmitted by the electronic device (210) through the first link (231). The third processor (221) may output or receive a signal of a frequency band corresponding to the first link (231) through the third antenna (223). The fourth processor (222) may transmit data to the electronic device (210) through the second link (232) or receive data transmitted by the electronic device (210) through the second link (232). The fourth processor (222) can output or receive a signal of a frequency band corresponding to the second link (232) through the fourth antenna (224). The third processor (221) and the fourth processor (222) are entities implemented on a communication circuit for performing short-range wireless communication of an external electronic device (220), and may be entities that perform demodulation and decoding of a signal received through short-range wireless communication. The third processor (221) and the fourth processor (222) may be referred to as a core or a radio.

[0041] According to one embodiment, the frequency band of the first link (231) and the frequency band of the second link (232) may be different from each other. For example, the frequency band of the first link (231) may be 2.4 GHz, and the frequency band of the second link (232) may be 5 GHz or 6 GHz. Alternatively, the frequency band of the first link (231) and the frequency band of the second link (233) may be the same, but the channel number of the first link (231) and the channel number of the second link (333) may be different. For example, the first link (231) may be channel 1 of the 2.4 GHz frequency band, and the second link (233) may be channel 12 of the 2.4 GHz frequency band.

[0042] FIG. 2b is a diagram illustrating an embodiment in which an electronic device according to one embodiment operates in a non-STR (simultaneous transmission and reception) mode.

[0043] Referring to FIG. 2b, the wireless LAN system (200) may include an electronic device (210) and / or an external electronic device (220). According to one embodiment, the electronic device (210) may perform wireless communication with the external electronic device (220) via short-range wireless communication. Wireless communication may refer to various communication methods that both the electronic device (210) and / or the external electronic device (220) can support. For example, wireless communication may be Wi-Fi. The external electronic device (220) may serve as a base station providing wireless communication to at least one electronic device (210) located within the communication radius of the wireless LAN system (200). For example, the external electronic device (220) may include an IEEE 802.11 access point (AP). The electronic device (210) may include an IEEE 802.11 station (STA).

[0044] According to one embodiment, the electronic device (210) and / or the external electronic device (220) may support multi-link operation (MLO). Multi-link operation may be an operation mode that transmits or receives data through multiple links (e.g., a first link (231), a second link (22232)). Multi-link operation may be an operation mode that transmits or receives data through multiple links based on multiple bands or channels, as an operation mode scheduled to be introduced in IEEE 802.11be.

[0045] According to one embodiment, the electronic device (210) may include a plurality of communication circuits (e.g., a first processor (211) and / or a second processor (212)) to support multi-link operation. The first processor (211) may transmit data to an external electronic device (220) through a first link (231) or receive data transmitted by the external electronic device (220) through the first link (231). The first processor (211) may output or receive a signal of a frequency band corresponding to the first link (231) through a first antenna (213). The second processor (212) may transmit data to an external electronic device (220) through a second link (232) or receive data transmitted by the external electronic device (220) through the second link (232). The second processor (212) can output or receive a signal of a frequency band corresponding to the second link (232) through the second antenna (214).

[0046] According to one embodiment, an external electronic device (220) may include a plurality of communication circuits (e.g., a third processor (221) and / or a fourth processor (222)) to support multi-link operation. The third processor (221) may transmit data to the electronic device (210) through the first link (231) or receive data transmitted by the electronic device (210) through the first link (231). The third processor (221) may output or receive a signal of a frequency band corresponding to the first link (231) through the third antenna (223). The fourth processor (222) may transmit data to the electronic device (210) through the second link (232) or receive data transmitted by the electronic device (210) through the second link (232). The fourth processor (222) can output or receive a signal of a frequency band corresponding to the second link (232) through the fourth antenna (224).

[0047] According to one embodiment, the frequency band of the first link (231) and the frequency band of the second link (232) may be different from each other. For example, the frequency band of the first link (231) may be 2.5 GHz, and the frequency band of the second link (232) may be 5 GHz.

[0048] According to one embodiment, the electronic device (210) may not be able to secure a sufficient space (241) between the first antenna (213) and the second antenna (214) for implementation reasons. According to one embodiment, if a sufficient space (241) between the first antenna (213) and the second antenna (214) is not secured, interference may occur between the signal output by the first antenna (213) and the signal received through the second antenna (214). For example, the quality of the signal received through the second link (232) may be degraded as the second antenna (214) receives a signal in which a portion of the signal output by the first antenna (213) is combined with the signal received through the second link (232).

[0049] According to one embodiment, the electronic device (210) may support a non-STR (simultaneous transmission and reception) mode to prevent a situation in which the signal output by the first antenna (213) and the signal output by the second antenna (214) interfere with each other. The non-STR mode may mean a mode in which the electronic device (210) does not receive data through the second link (232) when transmitting data to an external electronic device (220) through the first link (231). The non-STR mode may support an operation of receiving data through the second link (232) while receiving data through the first link (231) and / or an operation of transmitting data through the second link (232) while transmitting data through the first link (231).

[0050] FIG. 3 is a diagram illustrating an example of checking the quality of a third link while an electronic device according to one embodiment performs short-range wireless communication through a first link and a second link.

[0051] Referring to FIG. 3, the wireless LAN system (200) may include an electronic device (210) and / or an external electronic device (220). According to one embodiment, the electronic device (210) may perform short-range wireless communication with the external electronic device (220). Short-range wireless communication may refer to various communication methods that both the electronic device (210) and / or the external electronic device (220) can support. For example, the short-range wireless communication may be Wi-Fi. The external electronic device (220) may serve as a base station providing short-range wireless communication to at least one electronic device (210) located within the communication radius of the wireless LAN system (200). For example, the external electronic device (220) may include an IEEE 802.11 access point (AP). The electronic device (210) may include an IEEE 802.11 station (STA).

[0052] According to one embodiment, the electronic device (210) and / or the external electronic device (220) may support a multi-link operation (MLO). A multi-link operation may be an operation mode that transmits or receives data through a plurality of links (e.g., a first link (231), a second link (232), a third link (233)).

[0053] According to one embodiment, the electronic device (210) may include a plurality of processors (e.g., a first processor (211) and / or a second processor (212)) to support multi-link operation. The first processor (211) may transmit data to an external electronic device (220) via a first link (231) or receive data transmitted by the external electronic device (220) via the first link (231). The first processor (211) may output or receive a signal of a frequency band corresponding to the first link (231) via a first antenna (213). The second processor (212) may transmit data to an external electronic device (220) via a second link (232) or a third link (233) or receive data transmitted by the external electronic device (220) via the second link (232) or the third link (233). The second processor (212) can output or receive a signal in a frequency band corresponding to the second link (232) or a signal in a frequency band corresponding to the third link (233) through the second antenna (214). The first processor (211) and the second processor (212) are entities implemented on a communication circuit for performing short-range wireless communication of the electronic device (210), and may be entities that perform demodulation and decoding of a signal received through short-range wireless communication. The first processor (211) and the second processor (212) may be referred to as a core or a radio.

[0054] According to one example, the electronic device (210) may perform a series of operations to connect with an external electronic device (220) in order to perform short-range wireless communication. For example, the electronic device (210) may perform an operation to discover the external electronic device (220) in order to connect with the external electronic device (220) that supports short-range wireless communication.

[0055] According to one example, the electronic device (210) can discover the external electronic device (220) by receiving a signal (e.g., beacon signal, probe response signal) transmitted (or broadcasted) by the external electronic device (220) through a plurality of frequency bands supported by the electronic device (210) (e.g., a frequency band corresponding to the first link (231), a frequency band corresponding to the second link (232), and / or a frequency band corresponding to the third link (233)).

[0056] After the electronic device (210) discovers the external electronic device (220), it can perform authentication with the external electronic device (220). After the electronic device (210) successfully authenticates with the external electronic device (220), it can perform an association operation.

[0057] The electronic device (210) can transmit an association request frame to an external electronic device (220), and after receiving the association request frame, the external electronic device (220) can transmit an association response frame containing information indicating whether the association was successful.

[0058] According to one embodiment, the association request frame and / or association response frame may include information related to various capabilities. For example, the association request frame may include information related to various capabilities, a beacon listen interval, a service set identifier (SSID), supported rates, supported channels, an RSN, a mobility domain, supported operating classes, a traffic indication map broadcast request, and / or information regarding interworking service capabilities. For example, the association response frame may include information related to various capabilities, such as a status code, an association ID (AID), supported rates, an enhanced distributed channel access (EDCA) parameter set, a received channel power indicator (RCPI), a received signal to noise indicator (RSNI), a mobility domain, a timeout interval (association comeback time), overlapping BSS scan parameters, a TIM broadcast response, and / or a QoS map.

[0059] According to one example, if the electronic device (210) and the external electronic device (220) support MLO, the combined operation can be performed through a first link (231) corresponding to a first frequency band, a second link (232) corresponding to a second frequency band, and / or a third link (233) corresponding to a third frequency band.

[0060] The electronic device (210) can perform a security setup operation after completing the coupling operation. The electronic device (210) and the external electronic device (220) can perform short-range wireless communication after performing the security setup.

[0061] According to one example, the electronic device (210) or the second processor (212) may not be able to simultaneously perform short-range wireless communication using the second link (232) and short-range wireless communication using the third link (233). The first processor (211) and the second processor (212) may not be able to receive and / or transmit a signal through the other link while receiving and / or transmitting a signal through one link. The second processor (212) may not be able to simultaneously process a signal in the frequency band corresponding to the second link (232) and a signal in the frequency band corresponding to the third link (233). For example, the second processor (212) may not be able to perform short-range wireless communication using the third link (233) while performing short-range wireless communication using the second link (232). As another example, the second processor (212) may not be able to perform short-range wireless communication using the second link (232) while performing short-range wireless communication using the third link (233).

[0062] The electronic device (210) can perform short-range wireless communication through the first link (231) and the second link (232). The first link (231) and the second link (232) are links associated with the external electronic device (220) and may be active links. The third link (233) is a link associated with the external electronic device (220) and may be a deactivated link.

[0063] Considering that the electronic device (210) cannot perform short-range wireless communication using the second link (232) and the third link (233), the electronic device (210) may switch (or maintain) one of the second link (232) and the third link (233) to a disabled state. To switch one of the second link (232) and the third link (233) to a disabled state, the electronic device (210) may transmit a disabled request signal to an external electronic device (220) containing information indicating the link to be disabled. According to one example, the electronic device (210) may transmit a signal (e.g., a Qos Null frame with the power management bit set to 1) to the external electronic device (220) indicating to switch to a power saving mode. In FIG. 3, for convenience of explanation, it is assumed that the third link (233) is disabled.

[0064] The electronic device (210) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0065] According to one example, the electronic device (210) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0066] The electronic device (210) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (210) can receive a signal through the first link (231) and measure the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (210) can receive a signal through the second link (232) and measure the quality of the second link (232) based on at least one parameter related to the signal.

[0067] The electronic device (210) can check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). However, the electronic device (210) may switch an activated link (e.g., a second link (232)) to a deactivated state in order to check the quality of the deactivated link. This is because, as previously stated, the second link (232) and the third link (233) cannot be in an activated state at the same time. The electronic device (210) may switch the second link (232) to a deactivated state in order to check the quality of the third link (233). However, if the electronic device (210) is performing short-range wireless communication through the first link (231) and / or the second link (232), the quality of the short-range wireless communication may be degraded by switching the second link (232) to a deactivated state.

[0068] In the following, an example is described in which an electronic device (210) checks the quality of a link in a deactivated state without switching a link in an active state to a deactivated state.

[0069] FIG. 4 is a block diagram of an electronic device according to one embodiment.

[0070] According to one embodiment, an electronic device (e.g., the electronic device (210) of FIG. 3) may include a communication circuit (410) (e.g., the communication circuit (160) of FIG. 1), an application processor (420) (e.g., the processor (110) of FIG. 1) and / or a memory (430) (e.g., the memory (120) of FIG. 1).

[0071] The communication circuit (410) may be a communication circuit that supports short-range wireless communication. For example, the short-range wireless communication may be Wi-Fi, which is a short-range wireless communication defined in IEE 802.11.

[0072] The communication circuit (410) may include various circuit structures used for modulating and / or demodulating a signal within the electronic device (210). For example, the communication circuit (410) may modulate a baseband signal into a radio frequency (RF) band signal to output it through an antenna (not shown), or demodulate an RF band signal received through the antenna into a baseband signal and transmit it to an application processor (420).

[0073] The communication circuit (410) can support multi-link operation (MLO). The communication circuit (410) supporting MLO can perform short-range wireless communication through at least one of a first link (e.g., the first link (231) of FIG. 3), a second link (e.g., the second link (232) of FIG. 3), and / or a third link (e.g., the third link (233) of FIG. 3). The first link (231) may be a link that includes at least a portion of a first frequency band (e.g., 2.4 GHz), the second link (232) may be a link that includes at least a portion of a second frequency band (e.g., 5 GHz), and the third link (233) may be a link that includes at least a portion of a third frequency band (e.g., 6 GHz).

[0074] The communication circuit (410) may include a main processor (411) (e.g., the first processor (211), the second processor (222) of FIG. 3)) that performs short-range wireless communication through a plurality of links (e.g., the first link (231), the second link (232) and / or the third link (233)) combined between an external electronic device (e.g., the external electronic device (220) of FIG. 3) and the electronic device (100). Although the main processor (411) is shown as one in FIG. 4, there is no limit to the number. The main processor (411) is an entity capable of receiving and / or transmitting signals through a plurality of links and may be referred to as a main core or a main radio.

[0075] The communication circuit (410) may include an auxiliary processor (412) that receives a signal through one of the multiple antennas (e.g., the first antenna (213) and the second antenna (214) of FIG. 3) included in the electronic device (100). The auxiliary processor (412) may be electrically (or kinetically) connected to one of the multiple antennas, and the antenna electrically connected to the auxiliary processor (412) may also be connected to the main processor (411). The auxiliary processor (412) may receive a signal through one antenna and, depending on the implementation, may not be able to transmit a signal. The auxiliary processor (412) may be an entity that does not support multiple spatial streams, and the auxiliary processor (412) may have lower performance than the main processor (411). The power consumed by the auxiliary processor (412) may be less than the power consumed by the main processor (411). The auxiliary processor (412) may be referred to as an aux core or an aux radio.

[0076] The communication circuit (410) can perform an operation to receive a signal transmitted by an external electronic device (e.g., the external electronic device (220) of FIG. 3) based on the control of the application processor (420). The communication circuit (410) can control the components of the communication circuit (410) (e.g., a low-noise amplifier, a switch, and / or a filter) so that the signal can be received through a frequency band corresponding to a specific channel.

[0077] The application processor (420) is electrically or operationally connected to the communication circuit (410) and can control the communication circuit (410).

[0078] The memory (430) may store at least one computer program containing instructions that can be executed by the application processor (420). The operation of the application processor (420) described below may be performed according to the execution of instructions included in the computer program stored in the memory (430). If the application processor (420) includes at least one processing circuit (or processor), the at least one processing circuit (or processor) included in the application processor (420) may execute instructions individually or collectively.

[0079] According to one example, the application processor (420) may perform a series of operations to connect with an external electronic device (220) in order to perform short-range wireless communication. For example, the application processor (420) may perform an operation to discover an external electronic device (220) in order to connect with an external electronic device (220) that supports short-range wireless communication.

[0080] According to one example, the application processor (420) can discover the external electronic device (220) by receiving a signal (e.g., beacon signal, probe response signal) transmitted (or broadcasted) by the external electronic device (220) through a plurality of frequency bands supported by the electronic device (210) (e.g., a frequency band corresponding to the first link (231), a frequency band corresponding to the second link (232), and / or a frequency band corresponding to the third link (233)).

[0081] The application processor (420) can perform authentication with the external electronic device (220) after discovering the external electronic device (220). The electronic device (210) can perform an association operation after successfully authenticating with the external electronic device (220).

[0082] The application processor (420) can transmit an association request frame to an external electronic device (220), and the external electronic device (220), after receiving the association request frame, can transmit an association response frame containing information indicating whether the association was successful.

[0083] According to one embodiment, the association request frame and / or association response frame may include information related to various capabilities. For example, the association request frame may include information related to various capabilities, a beacon listen interval, a service set identifier (SSID), supported rates, supported channels, an RSN, a mobility domain, supported operating classes, a traffic indication map broadcast request, and / or information regarding interworking service capabilities. For example, the association response frame may include information related to various capabilities, such as a status code, an association ID (AID), supported rates, an enhanced distributed channel access (EDCA) parameter set, a received channel power indicator (RCPI), a received signal to noise indicator (RSNI), a mobility domain, a timeout interval (association comeback time), overlapping BSS scan parameters, a TIM broadcast response, and / or a QoS map.

[0084] According to one example, if the electronic device (100) and the external electronic device (220) support MLO, the combined operation can be performed through a first link (231) corresponding to a first frequency band, a second link (232) corresponding to a second frequency band, and / or a third link (233) corresponding to a third frequency band.

[0085] The electronic device (210) can perform a security setup operation after completing the coupling operation. The electronic device (210) and the external electronic device (220) can perform short-range wireless communication after performing the security setup.

[0086] The application processor (420) can control the communication circuit (410) to perform short-range wireless communication through an activated link among a plurality of links combined between the electronic device (100) and the external electronic device (220).

[0087] According to one example, the number of active links may be multiple. For example, a first link (231) and a second link (232) may be active links. An active link may be a link connected between an electronic device (100) and an external electronic device (220), and may be a link capable of performing short-range wireless communication. Conversely, a deactivated link may be a link connected between an electronic device (100) and an external electronic device (220), but may be a link that cannot perform short-range wireless communication. According to one example, a deactivated link is a link that has entered a power saving mode, such that the electronic device (100) may not transmit data to the external electronic device (220) through the deactivated link, and the external electronic device (220) may also not transmit data to the electronic device (100) through the deactivated link.

[0088] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using the second link (232) and short-range wireless communication using the third link (233). In the implementation of the communication circuit (410), one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). For example, a front end module (FEM) electrically connected to one main processor (411) may process one of the frequency bands of a signal in a second frequency band corresponding to the second link (232) and a signal in a third frequency band corresponding to the third link (233), and thus, one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). Specific examples are described later in FIGS. 5 and FIGS. 6. For example, the electronic device (100) may not be able to perform short-range wireless communication using the third link (233) while performing short-range wireless communication using the second link (232). As another example, the electronic device (100) may not be able to perform short-range wireless communication using the second link (232) while performing short-range wireless communication using the third link (233).

[0089] The application processor (420) may control the communication circuit (410) to switch (or maintain) one of the second link (232) and the third link (233) to a disabled state, considering that short-range wireless communication using the second link (232) and the third link (233) cannot be performed. The application processor (420) may control the communication circuit (410) to transmit a disabled request signal containing information indicating the link to be disabled to an external electronic device (220) in order to switch one of the second link (232) and the third link (233) to a disabled state. According to one example, the electronic device (210) may transmit a signal (e.g., a Qos Null frame with the power management bit set to 1) to the external electronic device (220) instructing to switch to a power saving mode. In FIG. 4, for convenience of explanation, it is assumed that the third link (233) is disabled.

[0090] The application processor (420) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0091] According to one example, the application processor (420) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0092] The application processor (420) can control the communication circuit (410) so that the main processor (411) checks the quality of an active link among a plurality of links combined between the electronic device (100) and the external electronic device (220), and the auxiliary processor (412) checks the quality of a deactivated link among a plurality of links combined between the electronic device (100) and the external electronic device (220). The main processor (411) may receive a signal from the external electronic device (220) through the active link and can check the quality of the active link based on the received signal. If the main processor (411) checks the quality of a deactivated link that cannot be used simultaneously with the active link, the active link must be switched to a deactivated state. Therefore, the application processor (420) can prevent the active link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0093] The application processor (420) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links coupled with an external electronic device (220). The application processor (420) or the communication circuit (410) can receive a signal through the first link (231) and measure the quality of the first link (231) based on at least one parameter related to the signal. The application processor (420) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the first link (231).

[0094] The application processor (420) can receive a signal through the second link (232) and measure the quality of the second link (232) based on at least one parameter related to the signal. The application processor (420) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the second link (232).

[0095] The application processor (420) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The application processor (420) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0096] The auxiliary processor (412) can receive a signal through the third link (233) using an antenna electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the main processor (411) from switching to a deactivated state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the main processor (411) from performing the operation of checking the quality of the third link (233).

[0097] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) while the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). The operation of the main processor (411) checking the quality of the activated links and the operation of the auxiliary processor (412) checking the quality of the deactivated links may be performed in parallel. For example, the operation of the main processor (411) checking the quality of the activated links may be performed substantially simultaneously with the operation of the auxiliary processor (412) checking the quality of the deactivated links. Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links may also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0098] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) before the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). According to one example, the auxiliary processor (412) may be configured to check the quality of deactivated links at specified intervals, and the auxiliary processor (412) may check the quality of deactivated links at specified intervals. The application processor (420) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the application processor (420) detects that the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210). The communication circuit (410) can enable the main processor (411) to check the quality of the active link upon receiving a control signal from the application processor (420), and can transmit to the application processor (420) information indicating the quality of the inactive link previously checked by the auxiliary processor (412) and information indicating the quality of the active link checked upon receiving the control signal from the application processor (420). Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links can also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0099] According to one example, the quality of multiple links (e.g., a first link (231), a second link (232) and / or a third link (233)) may refer to the expected data rate when transmitting and / or receiving data through each link. The higher the expected data rate, the higher the quality of the link may be. Conversely, the lower the expected data rate, the lower the quality of the link may be.

[0100] Alternatively, the quality of multiple links (e.g., first link (231), second link (232) and / or third link (233)) may refer to a score determined based on the expected data rate when transmitting and / or receiving data through the link. The higher the score, the higher the quality of the link may be. Conversely, the lower the score, the lower the quality of the link may be.

[0101] The application processor (420) can determine the expected data rate of each of the multiple links based on the following mathematical formula 1.

[0102]

[0103] ( : The rate of the idle state where data transmission and / or reception through the link does not occur, : The ratio of the time spent performing other wireless communication sharing the antenna to the time spent performing short-range wireless communication, : Link data rate)

[0104] The application processor (420) is a data rate included in mathematical formula 1 ( ) can be verified based on the following mathematical formula 2.

[0105]

[0106] ( : The signal-to-noise ratio (SNR) of a received signal, defined through a tone that refers to a specific frequency included in a frequency band. : Maximum number of bits that can be included per tone, : Maximum number of space streams that both the external electronic device (220) and the electronic device (100) can support, : Spacing between symbols

[0107] The application processor (420) has an SNR of a signal received through a tone that refers to a specific frequency included in the frequency band included in Equation 2. ) can be verified based on the mathematical formula 3 below.

[0108]

[0109] ( : RSSI (Received signal strength indicator) of the signal received through the link, : Parameter used when converting RSSI to SNR)

[0110] The application processor (420) can determine (or determine, calculate) the expected data rate of each of the multiple links based on mathematical formulas 1 to 3, and can determine the quality of each of the multiple links.

[0111] The application processor (420) can control the communication circuit (410) to control at least one of the multiple links based on the quality of each of the multiple links.

[0112] An electronic device (210) can perform short-range wireless communication using one of at least one main processor (411). The electronic device (210) performing short-range wireless communication using one main processor (411) may be referred to as MLSR (multi-link single radio). When the electronic device (210) performs short-range wireless communication using one main processor (411), it can perform short-range wireless communication through any one of multiple links. The electronic device (100) (or application processor (420)) can determine whether there exists a link with a higher quality than the quality of the currently active link based on the quality of each of the multiple links. If there exists a link with a higher quality than the quality of the currently active link, the application processor (420) can switch the link with the higher quality to an active state and switch the currently active link to an inactive state.

[0113] An electronic device (210) can perform short-range wireless communication using at least two main processors (411) among at least one main processor (411). The electronic device (210) performing short-range wireless communication using two or more processors (411) may be referred to as MLMR (multi-link multi-radio). When the electronic device (210) performs short-range wireless communication using two or more main processors (411), short-range wireless communication can be performed through a combination of some links among multiple links. The electronic device (100) (or application processor (420)) can determine whether there exists a combination of links having a higher quality than the quality of the combination of currently active links, based on the quality of each of the multiple links. The application processor (420) can control the communication circuit (410) to perform short-range wireless communication through the combination of links having a higher quality than the quality of the combination of currently active links, based on the quality of each of the multiple links, if there exists a combination of links having a higher quality than the quality of the combination of currently active links.

[0114] According to one example, the application processor (420) can control the communication circuit (410) so that the link included in the combination of links having a higher quality among the links included in the combination of currently active links remains in an active state.

[0115] According to one example, the application processor (420) can control the communication circuit (410) so that links included in the combination of currently active links that are not included in the combination of links with higher quality are switched from an active state to a disabled state. The communication circuit (410) can cause links included in the combination of currently active links that are not included in the combination of links with higher quality to be switched to a power saving mode by transmitting a signal (e.g., a Qos Null frame with the power management bit set to 1) to an external electronic device (220) that instructs (or requests) the links included in the combination of currently active links that are not included in the combination of links with higher quality to be switched from an active state to a disabled state.

[0116] According to one example, the application processor (420) can control the communication circuit (410) to switch a link included in the combination of links with higher quality among the links not included in the combination of currently active links (or, disabled links) from a disabled state to an enabled state. The communication circuit (410) can switch a link included in the combination of links with higher quality among the links not included in the combination of currently active links (or, disabled links) from a disabled state to an enabled state by transmitting a signal (e.g., a Qos Null frame with the power management bit set to 0) to an external electronic device (220) that instructs (or requests) the link not included in the combination of links with higher quality among the links included in the combination of currently active links to be released from power saving mode.

[0117] FIG. 5a is a diagram illustrating an example in which an electronic device according to one embodiment checks the quality of a plurality of links.

[0118] A communication circuit (410) (e.g., communication circuit (410) of FIG. 4) of an electronic device (e.g., electronic device (100) of FIG. 4) may include a first main processor (411-1) (e.g., main processor (411) of FIG. 4), a second main processor (411-2) (e.g., main processor (411) of FIG. 4) and / or an auxiliary processor (412) (e.g., auxiliary processor (412) of FIG. 4).

[0119] The first main processor (411-1) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the first main processor (411-1) can perform short-range wireless communication through a plurality of links implemented on a first frequency band (e.g., 2.4 GHz).

[0120] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be transmitted to the first main processor (411-1) through a first diplexer (511) and a first front end module (FEM) (521) that separate a signal of a first frequency band, a signal of a second frequency band (e.g., 5 GHz), and / or a signal of a third frequency band (e.g., 6 GHz). According to one example, the first front end module (521) may include at least one of a low-noise amplifier that amplifies a received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0121] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna can be transmitted to the first main processor (411-1) through a second diplexer (512) and a third front end module (FEM) (523) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the third front end module (523) may include at least one of a low-noise amplifier that amplifies the received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0122] The first main processor (411-1) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in a first frequency band. According to one example, the first main processor (411-1) can transmit a signal to an external electronic device (220) through one of a plurality of links in a first frequency band that is operatively connected to a first antenna (213). According to one example, the first main processor (411-1) can receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The first main processor (411-1) can transmit the processed signal to the first FEM (521). The first FEM (521) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the first diplexer (511).

[0123] Alternatively, the first main processor (411-1) may transmit a signal to an external electronic device (220) through another link among a plurality of links in the first frequency band that is operatively connected to the second antenna (214). According to one example, the first main processor (411-1) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The first main processor (411-1) may transmit the processed signal to a third FEM (523). The third FEM (523) may amplify the processed signal and radiate the amplified signal to the second antenna (214) through the second diplexer (512).

[0124] The second main processor (411-2) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the second main processor (411-2) can perform short-range wireless communication through a plurality of links implemented on either a second frequency band or a third frequency band. For example, the second main processor (411-2) can perform short-range wireless communication through a single link implemented on the second frequency band.

[0125] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be transmitted to the second main processor (411-2) through a first diplexer (511) and a second front end module (FEM) (522) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the second front-end module (522) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0126] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna (214) can be transmitted to the second main processor (411-2) through a first diplexer (511) and a fourth front end module (FEM) (524) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the fourth front-end module (524) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0127] The second main processor (411-2) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in a second frequency band or a third frequency band. According to one example, the second main processor (411-2) can transmit a signal to an external electronic device (220) through one of a plurality of links in a second frequency band or a third frequency band that is operatively connected to the first antenna (213). According to one example, the second main processor (411-2) can receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4) and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The second main processor (411-2) can transmit the processed signal to the second FEM (522). The second FEM (522) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the first diplexer (511).

[0128] Alternatively, the second main processor (411-2) may transmit a signal to an external electronic device (220) through another link among a plurality of links in the second frequency band or the third frequency band that is operatively connected to the second antenna (214). According to one example, the second main processor (411-2) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The second main processor (411-2) may transmit the processed signal to a fourth FEM (524). The fourth FEM (524) may amplify the processed signal and radiate the amplified signal to the second antenna (214) through the second diplexer (512).

[0129] The auxiliary processor (412) can receive a signal through the second antenna (214). The auxiliary processor (412) can receive a signal of the first frequency band, a signal of the second frequency band, and / or a signal of the third frequency band through the second antenna (214). The auxiliary processor (412) may be an entity that does not support multiple spatial streams, and the auxiliary processor (412) may have lower performance than the first main processor (411-1) or the second main processor (411-2). The power consumed by the auxiliary processor (412) may be less than the power consumed by the first main processor (411-1) or the second main processor (411-2).

[0130] The auxiliary processor (412) can receive a signal of the first frequency band received through the second antenna (214) via the second diplexer (512) and the third FEM (523), and can receive a signal of the second frequency band received through the second antenna (214) via the second diplexer (512) and the fourth FEM (524). The auxiliary processor (412) can be connected to the third FEM (523) and the fourth FEM (524) via a switch (not shown). The switch can cause the auxiliary processor (412) to be electrically (or operatively) connected to either the third FEM (523) or the fourth FEM (524) and can operate based on a control signal transmitted by the first main processor (411-1) or the second main processor (411-2). According to one example, the switch may operate differently depending on the frequency band received by the auxiliary processor (412). For example, the switch may allow the third FEM (523) and the auxiliary processor (412) to be connected to receive a signal of the first frequency band. The switch may allow the fourth FEM (524) and the auxiliary processor (412) to be connected to receive a signal of the second frequency band.

[0131] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using a link implemented on a second frequency band (e.g., a second link (232)) and a link implemented on a third frequency band (e.g., a third link (233)). Referring to FIG. 5, the signal in the second frequency band and the signal in the third frequency band may be processed by a second main processor (411-2), and the second main processor (411-2) may only process one of the signals in the second frequency band and the signal in the third frequency band.

[0132] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0133] According to one example, the electronic device (100) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0134] The electronic device (100) may allow a first main processor (411-1) to check the quality of an activated first link (231) among a plurality of links combined between the electronic device (100) and an external electronic device (220), and a second main processor (411-2) to check the quality of an activated second link (232) among a plurality of links combined between the electronic device (100) and an external electronic device (220). The electronic device (100) may control a communication circuit (410) so that an auxiliary processor (412) checks the quality of a deactivated third link (233) among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0135] The first main processor (411-1) may receive a signal from an external electronic device (220) through an activated first link (231) and may check the quality of the activated link based on the received signal. The second main processor (411-2) may receive a signal from an external electronic device (220) through an activated second link (232) and may check the quality of the activated link based on the received signal. When the second main processor (411-2) checks the quality of a deactivated link (e.g., a third link (233)) that cannot be used simultaneously with an activated link (e.g., a second link (232)), the activated link must be switched to a deactivated state. Accordingly, the electronic device (100) may prevent the activated link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0136] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (100) can control a first main processor (411-1) to receive a signal through the first link (231) and check the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the first main processor (411-1) of the communication circuit (410) measures the quality of the first link (231).

[0137] The electronic device (100) can control the second main processor (411-2) to receive a signal through the second link (232) and check the quality of the second link (232) based on at least one parameter related to the signal.

[0138] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0139] The auxiliary processor (412) can receive a signal through the third link (233) using a second antenna (214) that is electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the second main processor (411-2) from switching to a deactivated state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the second main processor (411-2) from performing the operation of checking the quality of the third link (233).

[0140] FIG. 5b is a diagram illustrating an example in which an electronic device according to one embodiment checks the quality of a plurality of links.

[0141] A communication circuit (410) (e.g., communication circuit (410) of FIG. 4) of an electronic device (e.g., electronic device (100) of FIG. 4) may include a first main processor (411-1) (e.g., main processor (411) of FIG. 4), a second main processor (411-2) (e.g., main processor (411) of FIG. 4) and / or at least two auxiliary processors (412-1, 412-2) (e.g., auxiliary processor (412) of FIG. 4).

[0142] The first main processor (411-1) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the first main processor (411-1) can perform short-range wireless communication through a plurality of links implemented on a first frequency band (e.g., 2.4 GHz).

[0143] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be transmitted to the first main processor (411-1) through a first diplexer (511) and a first front end module (FEM) (521) that separate a signal of a first frequency band, a signal of a second frequency band (e.g., 5 GHz), and / or a signal of a third frequency band (e.g., 6 GHz). According to one example, the first front end module (521) may include at least one of a low-noise amplifier that amplifies a received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0144] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna can be transmitted to the first main processor (411-1) through a second diplexer (512) and a third front end module (FEM) (523) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the third front end module (523) may include at least one of a low-noise amplifier that amplifies the received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0145] The first main processor (411-1) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in a first frequency band. According to one example, the first main processor (411-1) can transmit a signal to an external electronic device (220) through one of a plurality of links in a first frequency band that is operatively connected to a first antenna (213). According to one example, the first main processor (411-1) can receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The first main processor (411-1) can transmit the processed signal to the first FEM (521). The first FEM (521) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the first diplexer (511).

[0146] Alternatively, the first main processor (411-1) may transmit a signal to an external electronic device (220) through another link among a plurality of links in the first frequency band that is operatively connected to the second antenna (214). According to one example, the first main processor (411-1) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The first main processor (411-1) may transmit the processed signal to a third FEM (523). The third FEM (523) may amplify the processed signal and radiate the amplified signal to the second antenna (214) through the second diplexer (512).

[0147] The second main processor (411-2) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the second main processor (411-2) can perform short-range wireless communication through a plurality of links implemented on either a second frequency band or a third frequency band. For example, the second main processor (411-2) can perform short-range wireless communication through a single link implemented on the second frequency band.

[0148] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be transmitted to the second main processor (411-2) through a first diplexer (511) and a second front end module (FEM) (522) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the second front-end module (522) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0149] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna (214) can be transmitted to the second main processor (411-2) through a first diplexer (511) and a fourth front end module (FEM) (524) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the fourth front-end module (524) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0150] The second main processor (411-2) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in a second frequency band or a third frequency band. According to one example, the second main processor (411-2) can transmit a signal to an external electronic device (220) through one of a plurality of links in a second frequency band or a third frequency band that is operatively connected to the first antenna (213). According to one example, the second main processor (411-2) can receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4) and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The second main processor (411-2) can transmit the processed signal to the second FEM (522). The second FEM (522) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the first diplexer (511).

[0151] Alternatively, the second main processor (411-2) may transmit a signal to an external electronic device (220) through another link among a plurality of links in the second frequency band or the third frequency band that is operatively connected to the second antenna (214). According to one example, the second main processor (411-2) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The second main processor (411-2) may transmit the processed signal to a fourth FEM (524). The fourth FEM (524) may amplify the processed signal and radiate the amplified signal to the second antenna (214) through the second diplexer (512).

[0152] The auxiliary processor (412-1) can receive a signal through the second antenna (214). The auxiliary processor (412-1) can receive a signal of the first frequency band, a signal of the second frequency band, and / or a signal of the third frequency band through the second antenna (214). The auxiliary processor (412-1) may be an entity that does not support multiple spatial streams, and the auxiliary processor (412-1) may have lower performance than the first main processor (411-1) or the second main processor (411-2). The power consumed by the auxiliary processor (412-1) may be less than the power consumed by the first main processor (411-1) or the second main processor (411-2).

[0153] The auxiliary processor (412-1) can receive a signal of the first frequency band received through the second antenna (214) via the second diplexer (512) and the third FEM (523), and can receive a signal of the second frequency band received through the second antenna (214) via the second diplexer (512) and the fourth FEM (524). The auxiliary processor (412-1) can be connected to the third FEM (523) and the fourth FEM (524) via a switch (not shown). The switch may allow the auxiliary processor (412-1) to be electrically (or kinetically) connected to either the third FEM (523) or the fourth FEM (524), and may operate based on a control signal transmitted by the first main processor (411-1) or the second main processor (411-2). According to one example, the switch may operate differently depending on the frequency band received by the auxiliary processor (412-1). For example, the switch may allow the third FEM (523) and the auxiliary processor (412-1) to be connected to receive a signal of the first frequency band. The switch may allow the fourth FEM (524) and the auxiliary processor (412-1) to be connected to receive a signal of the second frequency band.

[0154] The auxiliary processor (412-2) can receive a signal through the first antenna (213). The auxiliary processor (412-2) can receive a signal of the first frequency band, a signal of the second frequency band, and / or a signal of the third frequency band through the first antenna (213). The auxiliary processor (412-2) may be an entity that does not support multiple spatial streams, and the auxiliary processor (412-2) may have lower performance than the first main processor (411-1) or the second main processor (411-2). The power consumed by the auxiliary processor (412-2) may be less than the power consumed by the first main processor (411-1) or the second main processor (411-2).

[0155] The auxiliary processor (412-2) can receive a signal of a first frequency band received through the first antenna (213) via the first diplexer (511) and the first FEM (521), and can receive a signal of a second frequency band received through the first antenna (213) via the first diplexer (511) and the second FEM (522). The auxiliary processor (412-2) can be connected to the first FEM (521) and the second FEM (522) via a switch (not shown). The switch may allow the auxiliary processor (412-2) to be electrically (or kinetically) connected to either the first FEM (521) or the second FEM (522), and may operate based on a control signal transmitted by the first main processor (411-1) or the second main processor (411-2). According to one example, the switch may operate differently depending on the frequency band received by the auxiliary processor (412-2). For example, the switch may allow the first FEM (521) and the auxiliary processor (412-2) to be connected to receive a signal of the first frequency band. The switch may allow the second FEM (522) and the auxiliary processor (412-2) to be connected to receive a signal of the second frequency band.

[0156] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using a link implemented on a second frequency band (e.g., a second link (232)) and a link implemented on a third frequency band (e.g., a third link (233)). Referring to FIG. 5, the signal in the second frequency band and the signal in the third frequency band may be processed by a second main processor (411-2), and the second main processor (411-2) may only process one of the signals in the second frequency band and the signal in the third frequency band.

[0157] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0158] According to one example, the electronic device (100) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0159] The electronic device (100) may allow a first main processor (411-1) to check the quality of an activated first link (231) among a plurality of links combined between the electronic device (100) and an external electronic device (220), and a second main processor (411-2) to check the quality of an activated second link (232) among a plurality of links combined between the electronic device (100) and an external electronic device (220). The electronic device (100) may control a communication circuit (410) so that an auxiliary processor (412-1) checks the quality of a deactivated third link (233) among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0160] The first main processor (411-1) may receive a signal from an external electronic device (220) through an activated first link (231) and may check the quality of the activated link based on the received signal. The second main processor (411-2) may receive a signal from an external electronic device (220) through an activated second link (232) and may check the quality of the activated link based on the received signal. When the second main processor (411-2) checks the quality of a deactivated link (e.g., a third link (233)) that cannot be used simultaneously with an activated link (e.g., a second link (232)), the activated link must be switched to a deactivated state. Accordingly, the electronic device (100) may prevent the activated link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412-1) checks the quality of the deactivated link.

[0161] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (100) can control a first main processor (411-1) to receive a signal through the first link (231) and check the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the first main processor (411-1) of the communication circuit (410) measures the quality of the first link (231).

[0162] The electronic device (100) can control the second main processor (411-2) to receive a signal through the second link (232) and check the quality of the second link (232) based on at least one parameter related to the signal.

[0163] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412-1) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412-1) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412-1) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0164] The auxiliary processor (412-1) can receive a signal through the third link (233) using a second antenna (214) that is electrically (or kinetically) connected to the auxiliary processor (412-1). The auxiliary processor (412-1) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the second main processor (411-2) from switching to a deactivated state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the second main processor (411-2) from performing the operation of checking the quality of the third link (233).

[0165] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412-2) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412-2) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412-2) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0166] The auxiliary processor (412-2) can receive a signal through the third link (233) using a first antenna (213) that is electrically (or kinetically) connected to the auxiliary processor (412-2). The auxiliary processor (412-2) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the second main processor (411-2) from switching to a deactivated state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the second main processor (411-2) from performing the operation of checking the quality of the third link (233).

[0167] FIG. 5c is a diagram illustrating an example in which an electronic device according to one embodiment checks the quality of a plurality of links.

[0168] A communication circuit (410) (e.g., communication circuit (410) of FIG. 4) of an electronic device (e.g., electronic device (100) of FIG. 4) may include a first main processor (411-1) (e.g., main processor (411) of FIG. 4), a second main processor (411-2) (e.g., main processor (411) of FIG. 4) and / or an auxiliary processor (412) (e.g., auxiliary processor (412) of FIG. 4).

[0169] The first main processor (411-1) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the first main processor (411-1) can perform short-range wireless communication through a plurality of links implemented on a first frequency band (e.g., 2.4 GHz).

[0170] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be transmitted to the first main processor (411-1) through a first diplexer (511) and a first front end module (FEM) (521) that separate a signal of a first frequency band, a signal of a second frequency band (e.g., 5 GHz), and / or a signal of a third frequency band (e.g., 6 GHz). According to one example, the first front end module (521) may include at least one of a low-noise amplifier that amplifies a received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0171] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna can be transmitted to the first main processor (411-1) through a second diplexer (512) and a third front end module (FEM) (523) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the third front end module (523) may include at least one of a low-noise amplifier that amplifies the received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0172] The first main processor (411-1) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in a first frequency band. According to one example, the first main processor (411-1) can transmit a signal to an external electronic device (220) through one of a plurality of links in a first frequency band that is operatively connected to a first antenna (213). According to one example, the first main processor (411-1) can receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The first main processor (411-1) can transmit the processed signal to the first FEM (521). The first FEM (521) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the first diplexer (511).

[0173] Alternatively, the first main processor (411-1) may transmit a signal to an external electronic device (220) through another link among a plurality of links in the first frequency band that is operatively connected to the second antenna (214). According to one example, the first main processor (411-1) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The first main processor (411-1) may transmit the processed signal to a third FEM (523). The third FEM (523) may amplify the processed signal and radiate the amplified signal to the second antenna (214) through the second diplexer (512).

[0174] The second main processor (411-2) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the second main processor (411-2) can perform short-range wireless communication through a plurality of links implemented on either a second frequency band or a third frequency band. For example, the second main processor (411-2) can perform short-range wireless communication through a single link implemented on the second frequency band.

[0175] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be transmitted to the second main processor (411-2) through a first diplexer (511) and a second front end module (FEM) (522) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the second front-end module (522) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0176] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna (214) can be transmitted to the second main processor (411-2) through a first diplexer (511) and a fourth front end module (FEM) (524) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the fourth front-end module (524) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal.

[0177] The second main processor (411-2) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in a second frequency band or a third frequency band. According to one example, the second main processor (411-2) can transmit a signal to an external electronic device (220) through one of a plurality of links in a second frequency band or a third frequency band that is operatively connected to the first antenna (213). According to one example, the second main processor (411-2) can receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4) and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The second main processor (411-2) can transmit the processed signal to the second FEM (522). The second FEM (522) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the first diplexer (511).

[0178] Alternatively, the second main processor (411-2) may transmit a signal to an external electronic device (220) through another link among a plurality of links in the second frequency band or the third frequency band that is operatively connected to the second antenna (214). According to one example, the second main processor (411-2) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210). The second main processor (411-2) may transmit the processed signal to a fourth FEM (524). The fourth FEM (524) may amplify the processed signal and radiate the amplified signal to the second antenna (214) through the second diplexer (512).

[0179] The auxiliary processor (412) can receive a signal through the second antenna (214). The auxiliary processor (412) can receive a signal of the first frequency band, a signal of the second frequency band, and / or a signal of the third frequency band through the second antenna (214). The auxiliary processor (412) may be an entity that does not support multiple spatial streams, and the auxiliary processor (412) may have lower performance than the first main processor (411-1) or the second main processor (411-2). The power consumed by the auxiliary processor (412) may be less than the power consumed by the first main processor (411-1) or the second main processor (411-2).

[0180] The auxiliary processor (412) can receive a signal of the first frequency band received through the second antenna (214) via the second diplexer (512) and the third FEM (523), and can receive a signal of the second frequency band received through the second antenna (214) via the second diplexer (512) and the fourth FEM (524).

[0181] The auxiliary processor (412) can receive a signal through the first antenna (213). The auxiliary processor (412) can receive a signal of the first frequency band, a signal of the second frequency band, and / or a signal of the third frequency band through the first antenna (213).

[0182] The auxiliary processor (412) can receive a signal of a first frequency band received through the first antenna (213) via the first diplexer (511) and the first FEM (521), and can receive a signal of a second frequency band received through the first antenna (213) via the first diplexer (511) and the second FEM (522).

[0183] The auxiliary processor (412) may be connected to the first FEM (521), the second FEM (522), the third FEM (523), and the fourth FEM (524) via a switch (not shown). The switch may cause the auxiliary processor (412) to be electrically (or kinetically) connected to any one of the first FEM (521), the second FEM (522), the third FEM (523), and the fourth FEM (524), and may operate based on a control signal transmitted by the first main processor (411-1) or the second main processor (411-2). According to one example, the switch may operate differently depending on the frequency band received by the auxiliary processor (412). For example, the switch may allow the first FEM (521) and the auxiliary processor (412-2) to be connected to receive a signal in the first frequency band. Alternatively, the switch may allow the third FEM (523) and the auxiliary processor (412) to be connected to receive a signal in the first frequency band. The switch may allow the second FEM (522) and the auxiliary processor (412-2) to be connected to receive a signal in the second frequency band. Alternatively, the switch may allow the fourth FEM (524) and the auxiliary processor (412-2) to be connected to receive a signal in the second frequency band.

[0184] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using a link implemented on a second frequency band (e.g., a second link (232)) and a link implemented on a third frequency band (e.g., a third link (233)). Referring to FIG. 5, the signal in the second frequency band and the signal in the third frequency band may be processed by a second main processor (411-2), and the second main processor (411-2) may only process one of the signals in the second frequency band and the signal in the third frequency band.

[0185] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0186] According to one example, the electronic device (100) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0187] The electronic device (100) may allow a first main processor (411-1) to check the quality of an activated first link (231) among a plurality of links combined between the electronic device (100) and an external electronic device (220), and a second main processor (411-2) to check the quality of an activated second link (232) among a plurality of links combined between the electronic device (100) and an external electronic device (220). The electronic device (100) may control a communication circuit (410) so that an auxiliary processor (412) checks the quality of a deactivated third link (233) among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0188] The first main processor (411-1) may receive a signal from an external electronic device (220) through an activated first link (231) and may check the quality of the activated link based on the received signal. The second main processor (411-2) may receive a signal from an external electronic device (220) through an activated second link (232) and may check the quality of the activated link based on the received signal. When the second main processor (411-2) checks the quality of a deactivated link (e.g., a third link (233)) that cannot be used simultaneously with an activated link (e.g., a second link (232)), the activated link must be switched to a deactivated state. Accordingly, the electronic device (100) may prevent the activated link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0189] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (100) can control a first main processor (411-1) to receive a signal through the first link (231) and check the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the first main processor (411-1) of the communication circuit (410) measures the quality of the first link (231).

[0190] The electronic device (100) can control the second main processor (411-2) to receive a signal through the second link (232) and check the quality of the second link (232) based on at least one parameter related to the signal.

[0191] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0192] The auxiliary processor (412) may receive a signal through the third link (233) using a second antenna (214) that is electrically (or kinetically) connected to the auxiliary processor (412). Alternatively, the auxiliary processor (412) may receive a signal through the third link (233) using a first antenna (213) that is electrically (or kinetically) connected to the auxiliary processor (412). According to one example, when using either the first antenna (213) or the second antenna (214), the auxiliary processor (412) may use the antenna connected to the active main processor among the first main processor (411-1) and the second main processor (411-2). For example, the auxiliary processor (412) may use an antenna connected to one of the FEMs, either the second FEM (522) or the fourth FEM (524), connected to the second main processor (411-2) when the first main processor (411-1) is disabled and the second main processor (411-2) is disabled. Alternatively, the auxiliary processor (412) may use an antenna connected to one of the FEMs, either the first FEM (521) or the third FEM (523), connected to the first main processor (411-1) when the first main processor (411-1) is disabled.

[0193] The auxiliary processor (412) processes the received signal and can check parameters related to the signal based on the processed signal and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the second main processor (411-2) from switching to an inactive state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the second main processor (411-2) from performing the operation of checking the quality of the third link (233).

[0194] FIG. 6 is a diagram illustrating an example in which an electronic device according to one embodiment checks the quality of a plurality of links.

[0195] A communication circuit (410) (e.g., communication circuit (410) of FIG. 4) of an electronic device (e.g., electronic device (100) of FIG. 4) may include a first main processor (411-1) (e.g., main processor (411) of FIG. 4), a second main processor (411-2) (e.g., main processor (411) of FIG. 4) and / or an auxiliary processor (412) (e.g., auxiliary processor (412) of FIG. 4).

[0196] The first main processor (411-1) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the first main processor (411-1) can perform short-range wireless communication through a plurality of links implemented on a first frequency band (e.g., 2.4 GHz) and / or a second frequency band (e.g., 5 GHz).

[0197] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be separated through a third diplexer (611) that separates a signal of a first frequency band, a signal of a second frequency band (e.g., 5 GHz), and / or a signal of a third frequency band (e.g., 6 GHz).

[0198] According to one example, a signal of a first frequency band received through a first antenna (213) may be transmitted to a fifth front end module (FEM) (621) through a third diplexer (611). According to one example, the fifth front end module (621) may include at least one of a low-noise amplifier for amplifying the received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) for separating the signal into a transmitted signal or a received signal. The fifth front end module (622) may process the signal of the first frequency band and transmit the processed signal to a first main processor (411-1).

[0199] According to one example, a signal of the second frequency band received through the first antenna (213) may be transmitted to a sixth front end module (FEM) (622) through a third diplexer (611). According to one example, the sixth front end module (622) may include at least one of a low-noise amplifier for amplifying the received signal of the second frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the second frequency band, and a multiplexer (or duplexer) for separating the signal into a transmitted signal or a received signal. The sixth front end module (622) may process the signal of the second frequency band or the signal of the third frequency band and transmit the processed signal to the first main processor (411-1).

[0200] The first main processor (411-1) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna (214) can be separated through a fourth diplexer (612) that separates the signal of the first frequency band, the signal of the second frequency band (e.g., 5 GHz), and / or the signal of the third frequency band (e.g., 6 GHz).

[0201] According to one example, a signal of the first frequency band received through the second antenna (214) may be transmitted to the eighth front end module (FEM) (624) through the fourth diplexer (612). According to one example, the eighth front end module (624) may include at least one of a low-noise amplifier for amplifying the received signal of the first frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the first frequency band, and a multiplexer (or duplexer) for separating the signal into a transmitted signal or a received signal. The eighth front end module (624) may process the signal of the first frequency band and transmit the processed signal to the first main processor (411-1).

[0202] According to one example, a signal of the second frequency band received through the first antenna (213) may be transmitted to the ninth front end module (FEM) (625) through the fourth diplexer (612). According to one example, the ninth front end module (625) may include at least one of a low-noise amplifier that amplifies the received signal of the second frequency band or the third frequency band, a filter for passing or removing some bands of the frequency band of the received signal of the second frequency band or the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal. The ninth front end module (625) may process the signal of the second frequency band and transmit the processed signal to the first main processor (411-1).

[0203] The first main processor (411-1) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in a first frequency band and a second frequency band. According to one example, the first main processor (411-1) can transmit a signal to an external electronic device (220) through one of a plurality of links in a first frequency band or a second frequency band that is operatively connected to the first antenna (213). According to one example, the first main processor (411-1) can receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210).

[0204] The first main processor (411-1) can modulate the baseband signal to the first frequency band and transmit the modulated signal to the fifth FEM (621). The fifth FEM (621) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the third diplexer (611).

[0205] The first main processor (411-1) can modulate the baseband signal to the second frequency band and transmit the modulated signal to the sixth FEM (622). The sixth FEM (622) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the third diplexer (611).

[0206] Alternatively, the first main processor (411-1) may transmit a signal to an external electronic device (220) through another link among a plurality of links in a first frequency band or a second frequency band that is operatively connected to the second antenna (214). According to one example, the first main processor (411-1) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210).

[0207] The first main processor (411-1) can modulate the baseband signal to the first frequency band and transmit the modulated signal to the eighth FEM (624). The eighth FEM (624) can amplify the processed signal and radiate the amplified signal to the second antenna (214) through the fourth diplexer (612).

[0208] The first main processor (411-1) can modulate the baseband signal to the second frequency band and transmit the modulated signal to the ninth FEM (625). The ninth FEM (625) can amplify the processed signal and radiate the amplified signal to the second antenna (214) through the fourth diplexer (612).

[0209] The second main processor (411-2) can perform short-range wireless communication using a plurality of links coupled between the electronic device (100) and an external electronic device (e.g., the external electronic device (220) of FIG. 3). According to one example, the second main processor (411-2) can perform short-range wireless communication through a plurality of links implemented on either a second frequency band or a third frequency band. For example, the second main processor (411-2) can perform short-range wireless communication through a single link implemented on the second frequency band.

[0210] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a first antenna (e.g., the first antenna (213) of FIG. 3). The signal received through the first antenna can be transmitted to the second main processor (411-2) through a third diplexer (611) and a seventh front end module (FEM) (623) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the seventh front-end module (623) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal. The seventh front-end module (623) may process the signal of the second frequency band or the third frequency band and transmit the processed signal to the second main processor (411-2).

[0211] The second main processor (411-2) can receive a signal transmitted by an external electronic device (220) through a second antenna (e.g., the second antenna (214) of FIG. 3). The signal received through the second antenna (214) can be transmitted to the second main processor (411-2) through a fourth diplexer (612) and a tenth front end module (FEM) (626) that separate a signal of the first frequency band, a signal of the second frequency band (e.g., 5 GHz), and / or a signal of the third frequency band (e.g., 6 GHz). According to one example, the 10th front-end module (626) may include at least one of a low-noise amplifier that amplifies a received signal of a second frequency band or a received signal of a third frequency band, a filter for passing or removing some bands of the frequency bands of the received signal of the second frequency band or the received signal of the third frequency band, and a multiplexer (or duplexer) that separates the signal into a transmitted signal or a received signal. The 10th front-end module (626) may process the signal of the second frequency band or the third frequency band and transmit the processed signal to the second main processor (411-2).

[0212] The second main processor (411-2) can transmit a signal to an external electronic device (220) through at least one of a plurality of links in the second frequency band and the third frequency band. According to one example, the second main processor (411-2) can transmit a signal to an external electronic device (220) through one of a plurality of links in the second frequency band or the third frequency band that is operatively connected to the first antenna (213). According to one example, the second main processor (411-2) receives data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and can process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210).

[0213] The second main processor (411-2) can modulate the baseband signal to the second frequency band and transmit the modulated signal to the seventh FEM (623). The seventh FEM (623) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the third diplexer (611).

[0214] The second main processor (411-2) can modulate the baseband signal to the third frequency band and transmit the modulated signal to the seventh FEM (623). The seventh FEM (623) can amplify the processed signal and radiate the amplified signal to the first antenna (213) through the third diplexer (611).

[0215] Alternatively, the second main processor (411-2) may transmit a signal to an external electronic device (220) through another link among a plurality of links in the second frequency band or the third frequency band that is operatively connected to the second antenna (214). According to one example, the second main processor (411-2) may receive data (or a baseband signal) to be transmitted to the external electronic device (220) from an application processor (e.g., the application processor (420) of FIG. 4), and process the received data according to a modulation and coding scheme (MCS) established between the external electronic device (220) and the electronic device (210).

[0216] The second main processor (411-2) can modulate the baseband signal to the second frequency band and transmit the modulated signal to the 10th FEM (626). The 10th FEM (626) can amplify the processed signal and radiate the amplified signal to the second antenna (214) through the fourth diplexer (612).

[0217] The second main processor (411-2) can modulate the baseband signal to the third frequency band and transmit the modulated signal to the 10th FEM (626). The 10th FEM (626) can amplify the processed signal and radiate the amplified signal to the second antenna (214) through the fourth diplexer (612).

[0218] Referring to FIG. 6, the 6th FEM (622) operatively connected to the 1st main processor (411-1) and the 7th FEM (623) operatively connected to the 2nd main processor (411-2) may have at least a portion of the processing frequency bands (e.g., the 2nd frequency band, the 3rd frequency band) overlap. Accordingly, the communication circuit (410) may include a 1st switch (631) that allows a signal received through the 1st antenna (213) to be transmitted to either the 6th FEM (622) or the 7th FEM (623). The communication circuit (410) may control the 1st switch (631) so that a processor receiving or transmitting a signal through the 1st antenna (213) can be connected to the 1st antenna (213).

[0219] Referring to FIG. 6, the ninth FEM (625) operatively connected to the first main processor (411-1) and the tenth FEM (626) operatively connected to the second main processor (411-2) may have at least some of the processing frequency bands (e.g., the second frequency band, the third frequency band) overlap. Accordingly, the communication circuit (410) may include a second switch (632) that allows a signal received through the second antenna (214) to be transmitted to either the ninth FEM (625) or the tenth FEM (626). The communication circuit (410) may control the second switch (632) so that a processor receiving or transmitting a signal through the second antenna (214) can be connected to the second antenna (214).

[0220] The auxiliary processor (412) can receive a signal through the second antenna (214). The auxiliary processor (412) can receive a signal of the first frequency band, a signal of the second frequency band, and / or a signal of the third frequency band through the second antenna (214). The auxiliary processor (412) may be an entity that does not support multiple spatial streams, and the auxiliary processor (412) may have lower performance than the first main processor (411-1) or the second main processor (411-2). The power consumed by the auxiliary processor (412) may be less than the power consumed by the first main processor (411-1) or the second main processor (411-2).

[0221] The auxiliary processor (412) can receive a signal of the first frequency band received through the second antenna (214) via the fourth diplexer (612) and the eighth FEM (624), receive a signal of the second frequency band or a signal of the third frequency band received through the second antenna (214) via the fourth diplexer (612) and the ninth FEM (625), and receive a signal of the second frequency band or a signal of the third frequency band received through the second antenna (214) via the fourth diplexer (612) and the tenth FEM (626). The auxiliary processor (412) can be connected to the eighth FEM (624), the ninth FEM (625), and the tenth FEM (626) via a switch (not shown). The switch may allow the auxiliary processor (412) to be electrically (or kinetically) connected to any one of the 8th FEM (624), the 9th FEM (625), and the 10th FEM (626), and may operate based on a control signal transmitted by the 1st main processor (411-1) or the 2nd main processor (411-2). According to one example, the switch may operate differently depending on the frequency band received by the auxiliary processor (412). For example, the switch may allow the 8th FEM (624) and the auxiliary processor (412) to be connected to receive a signal of the 1st frequency band. The switch may allow the 9th FEM (625) and the auxiliary processor (412) to be connected to receive a signal of the 2nd frequency band. The switch can be configured to allow the 10th FEM (626) and the auxiliary processor (412) to be connected in order to receive a signal of the third frequency band.

[0222] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using a link implemented on a first frequency band (e.g., a first link (231)), a link implemented on a second frequency band (e.g., a second link (232)), and a link implemented on a third frequency band (e.g., a third link (233)). Referring to FIG. 6, a signal in the first frequency band or a signal in the second frequency band may be processed by a first main processor (411-1), and a signal in the second frequency band or a signal in the third frequency band may be processed by a second main processor (411-2). That is, the electronic device (100) may not be able to activate all of the first link (231), the second link (232), and / or the third link (233).

[0223] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0224] According to one example, the electronic device (100) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0225] The electronic device (100) may allow a first main processor (411-1) to check the quality of an activated first link (231) among a plurality of links combined between the electronic device (100) and an external electronic device (220), and a second main processor (411-2) to check the quality of an activated second link (232) among a plurality of links combined between the electronic device (100) and an external electronic device (220). The electronic device (100) may control a communication circuit (410) so that an auxiliary processor (412) checks the quality of a deactivated third link (233) among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0226] The first main processor (411-1) may receive a signal from an external electronic device (220) through an activated first link (231) and may check the quality of the activated link based on the received signal. The second main processor (411-2) may receive a signal from an external electronic device (220) through an activated second link (232) and may check the quality of the activated link based on the received signal. When the second main processor (411-2) checks the quality of a deactivated link (e.g., a third link (233)) that cannot be used simultaneously with an activated link (e.g., a second link (232)), the activated link must be switched to a deactivated state. Accordingly, the electronic device (100) may prevent the activated link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0227] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (100) can control a first main processor (411-1) to receive a signal through the first link (231) and check the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the first main processor (411-1) of the communication circuit (410) measures the quality of the first link (231).

[0228] The electronic device (100) can control the second main processor (411-2) to receive a signal through the second link (232) and check the quality of the second link (232) based on at least one parameter related to the signal.

[0229] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0230] The auxiliary processor (412) can receive a signal through the third link (233) using a second antenna (214) that is electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can receive a signal of the third frequency band received through the second antenna (214) through the ninth FEM (625) or the tenth FEM (626). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the phenomenon in which the second main processor (411-2) switches to an inactive state by checking the quality of the third link (232) by prohibiting (or refraining from) the second main processor (411-2) from performing the operation of checking the quality of the third link (233).

[0231] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the third link (233).

[0232] The electronic device (100) may allow a first main processor (411-1) to check the quality of an activated first link (231) among a plurality of links combined between the electronic device (100) and an external electronic device (220), and a second main processor (411-2) to check the quality of an activated third link (233) among a plurality of links combined between the electronic device (100) and an external electronic device (220). The electronic device (100) may control a communication circuit (410) so that an auxiliary processor (412) checks the quality of a deactivated second link (232) among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0233] The first main processor (411-1) may receive a signal from an external electronic device (220) through an activated first link (231) and may check the quality of the activated link based on the received signal. The second main processor (411-2) may receive a signal from an external electronic device (220) through an activated third link (233) and may check the quality of the activated link based on the received signal. When the second main processor (411-2) checks the quality of a deactivated link (e.g., second link (232)) that cannot be used simultaneously with an activated link (e.g., third link (233)), the activated link must be switched to a deactivated state. Accordingly, the electronic device (100) may prevent the activated link from being switched to a deactivated state in order to perform the quality check of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0234] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a third link (233)) among a plurality of links combined with an external electronic device (220). The electronic device (100) can control a first main processor (411-1) to receive a signal through the first link (231) and check the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the first main processor (411-1) of the communication circuit (410) measures the quality of the first link (231).

[0235] The electronic device (100) can control the second main processor (411-2) to receive a signal through the third link (233) and check the quality of the third link (233) based on at least one parameter related to the signal.

[0236] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a second link (232)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the 23rd link (232) while the third link (233) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of a deactivated link among the plurality of links.

[0237] The auxiliary processor (412) can receive a signal through the second link (232) using a second antenna (214) that is electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can receive a signal of the second frequency band received through the second antenna (214) through the ninth FEM (625) or the tenth FEM (626). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the phenomenon in which the second main processor (411-2) switches to an inactive state of the third link (233) by checking the quality of the second link (232) by prohibiting (or refraining from) the second main processor (411-2) from performing the operation of checking the quality of the second link (232).

[0238] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the second link (232) and the third link (233).

[0239] The electronic device (100) may allow a first main processor (411-1) to check the quality of an activated second link (232) among a plurality of links combined between the electronic device (100) and an external electronic device (220), and a second main processor (411-2) to check the quality of an activated third link (233) among a plurality of links combined between the electronic device (100) and an external electronic device (220). The electronic device (100) may control a communication circuit (410) so that an auxiliary processor (412) checks the quality of an inactive first link (231) among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0240] The first main processor (411-1) may receive a signal from an external electronic device (220) through an activated second link (232) and may check the quality of the activated link based on the received signal. The second main processor (411-2) may receive a signal from an external electronic device (220) through an activated third link (233) and may check the quality of the activated link based on the received signal. When the first main processor (411-1) checks the quality of a deactivated link (e.g., first link (231)) that cannot be used simultaneously with an activated link (e.g., second link (23@)), the activated link must be switched to a deactivated state. Accordingly, the electronic device (100) may prevent the activated link from being switched to a deactivated state in order to perform the quality check of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0241] The electronic device (100) can check the quality of an active link (e.g., a second link (232) and a third link (233)) among a plurality of links combined with an external electronic device (220). The electronic device (100) can control the first main processor (411-1) to receive a signal through the second link (232) and check the quality of the second link (23@) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the first main processor (411-1) of the communication circuit (410) measures the quality of the second link (232).

[0242] The electronic device (100) can control the second main processor (411-2) to receive a signal through the third link (233) and check the quality of the third link (233) based on at least one parameter related to the signal.

[0243] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a first link (231)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the first link (231) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of a deactivated link among the plurality of links.

[0244] The auxiliary processor (412) can receive a signal through the first link (231) using a second antenna (214) that is electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can receive a signal of the first frequency band received through the second antenna (214) via the eighth FEM (624). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the first link (231) based on the parameters. The communication circuit (410) can prevent the first main processor (411-1) from switching to a deactivated state of the second link (232) by checking the quality of the first link (231) by prohibiting (or restraining) the first main processor (411-1) from performing the operation of checking the quality of the first link (231).

[0245] FIG. 7 is a diagram illustrating an example (700) of switching an active link when an electronic device according to one embodiment operates as a multi links single radio (MLSR).

[0246] An electronic device (e.g., the electronic device (100) of FIG. 4) can, in operation 710, allow a main processor (e.g., the main processor (411) of FIG. 4) to check the quality of an active link and an auxiliary processor (e.g., the auxiliary processor (412) of FIG. 4) to check the quality of an inactive link.

[0247] The electronic device (100) can control the communication circuit (410) to perform short-range wireless communication through an activated link among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0248] According to one example, the number of active links may be multiple. For example, a first link (231) and a second link (232) may be active links. An active link may be a link connected between an electronic device (100) and an external electronic device (220), and may be a link capable of performing short-range wireless communication. Conversely, a deactivated link may be a link connected between an electronic device (100) and an external electronic device (220), but may be a link that cannot perform short-range wireless communication. According to one example, a deactivated link is a link that has entered a power saving mode, such that the electronic device (100) may not transmit data to the external electronic device (220) through the deactivated link, and the external electronic device (220) may also not transmit data to the electronic device (100) through the deactivated link.

[0249] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using the second link (232) and short-range wireless communication using the third link (233). In the implementation of the communication circuit (410), one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). For example, a front end module (FEM) electrically connected to one main processor (411) may process one of the frequency bands of a signal in a second frequency band corresponding to the second link (232) and a signal in a third frequency band corresponding to the third link (233), and thus, one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). Specific examples are described later in FIGS. 5 and FIGS. 6. For example, the electronic device (100) may not be able to perform short-range wireless communication using the third link (233) while performing short-range wireless communication using the second link (232). As another example, the electronic device (100) may not be able to perform short-range wireless communication using the second link (232) while performing short-range wireless communication using the third link (233).

[0250] Considering that short-range wireless communication using the second link (232) and the third link (233) cannot be performed, the electronic device (100) may control the communication circuit (410) to switch (or maintain) one of the second link (232) and the third link (233) to a disabled state. The electronic device (100) may control the communication circuit (410) to transmit a disabled request signal containing information indicating the link to be disabled to an external electronic device (220) in order to switch one of the second link (232) and the third link (233) to a disabled state. According to one example, the electronic device (210) may transmit a signal (e.g., a Qos Null frame with the power management bit set to 1) to the external electronic device (220) instructing to switch to a power saving mode. In FIG. 4, for convenience of explanation, the third link (233) is assumed to be disabled.

[0251] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0252] According to one example, the electronic device (100) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0253] The electronic device (100) can control the communication circuit (410) so that the main processor (411) checks the quality of an active link among a plurality of links combined between the electronic device (100) and an external electronic device (220), and the auxiliary processor (412) checks the quality of a deactivated link among a plurality of links combined between the electronic device (100) and an external electronic device (220). The main processor (411) may receive a signal from the external electronic device (220) through the active link and can check the quality of the active link based on the received signal. If the main processor (411) checks the quality of a deactivated link that cannot be used simultaneously with the active link, the active link must be switched to a deactivated state. Therefore, the electronic device (100) can prevent the active link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0254] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (100) or the communication circuit (410) can receive a signal through the first link (231) and measure the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the first link (231).

[0255] The electronic device (100) can receive a signal through the second link (232) and measure the quality of the second link (232) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the second link (232).

[0256] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0257] The auxiliary processor (412) can receive a signal through the third link (233) using an antenna electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the main processor (411) from switching to a deactivated state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the main processor (411) from performing the operation of checking the quality of the third link (233).

[0258] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) while the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). The operation of the main processor (411) checking the quality of the activated links and the operation of the auxiliary processor (412) checking the quality of the deactivated links may be performed in parallel. For example, the operation of the main processor (411) checking the quality of the activated links may be performed substantially simultaneously with the operation of the auxiliary processor (412) checking the quality of the deactivated links. Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links may also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0259] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) before the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). According to one example, the auxiliary processor (412) may be configured to check the quality of deactivated links at specified intervals, and the auxiliary processor (412) may check the quality of deactivated links at specified intervals. When the electronic device (100) detects that the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded, when a specified time has expired after the first link (231) and the second link (232) are activated, when the size of the data to be transmitted and / or received via short-range wireless communication increases, or when the number of activated links needs to be changed according to the mode switching of the electronic device (210), the communication circuit (410) can be controlled to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the electronic device (100) detects that the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded, when the first link (231) and the second link (232) are activated, when a specified time has expired, when the size of the data to be transmitted and / or received via short-range wireless communication increases, or when the number of activated links needs to be changed according to the mode switching of the electronic device (210). The communication circuit (410) can enable the main processor (411) to check the quality of the activated link upon receiving a control signal from the electronic device (100), and can transmit to the electronic device (100) information indicating the quality of the deactivated link previously checked by the auxiliary processor (412) and information indicating the quality of the activated link checked upon receiving the control signal from the electronic device (100). Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links can also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0260] According to one example, the quality of multiple links (e.g., a first link (231), a second link (232) and / or a third link (233)) may refer to the expected data rate when transmitting and / or receiving data through each link. The higher the expected data rate, the higher the quality of the link may be. Conversely, the lower the expected data rate, the lower the quality of the link may be.

[0261] Alternatively, the quality of multiple links (e.g., first link (231), second link (232) and / or third link (233)) may refer to a score determined based on the expected data rate when transmitting and / or receiving data through the link. The higher the score, the higher the quality of the link may be. Conversely, the lower the score, the lower the quality of the link may be.

[0262] The electronic device (100) can check whether, in operation 720, there exists a link among a plurality of links that has a quality higher than that of the activated link.

[0263] An electronic device (210) can perform short-range wireless communication using one of at least one main processor (411). The electronic device (210) performing short-range wireless communication using one main processor (411) may be referred to as MLSR (multi-link single radio). When the electronic device (210) performs short-range wireless communication using one main processor (411), it can perform short-range wireless communication through any one of a plurality of links. The electronic device (100) (or, electronic device (100)) can determine whether there exists a link having a higher quality than the quality of the currently active link based on the quality of each of the plurality of links.

[0264] The electronic device (100) can control the communication circuit (410) to activate the link with a higher quality and deactivate the activated link based on the fact that, in operation 730, there exists a link with a higher quality than the quality of the activated link among the multiple links (operation 720-Y).

[0265] The electronic device (100) can switch the link with higher quality to an active state and switch the currently active link to an inactive state if there is a link with a higher quality than the quality of the currently active link.

[0266] The electronic device (100) can maintain the activated link in an activated state when there is no link among the multiple links that has a quality higher than that of the activated link (operation 720-N).

[0267] FIG. 8 is a diagram illustrating an example (800) of switching combinations of activated links when an electronic device according to one embodiment operates in MLMR (multi links multi radio) mode.

[0268] An electronic device (e.g., the electronic device (100) of FIG. 4) can, in operation 810, allow a main processor (e.g., the main processor (411) of FIG. 4) to check the quality of an active link and an auxiliary processor (e.g., the auxiliary processor (412) of FIG. 4) to check the quality of an inactive link.

[0269] The electronic device (100) can control the communication circuit (410) to perform short-range wireless communication through an activated link among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0270] According to one example, the number of active links may be multiple. For example, a first link (231) and a second link (232) may be active links. An active link may be a link connected between an electronic device (100) and an external electronic device (220), and may be a link capable of performing short-range wireless communication. Conversely, a deactivated link may be a link connected between an electronic device (100) and an external electronic device (220), but may be a link that cannot perform short-range wireless communication. According to one example, a deactivated link is a link that has entered a power saving mode, such that the electronic device (100) may not transmit data to the external electronic device (220) through the deactivated link, and the external electronic device (220) may also not transmit data to the electronic device (100) through the deactivated link.

[0271] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using the second link (232) and short-range wireless communication using the third link (233). In the implementation of the communication circuit (410), one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). For example, a front end module (FEM) electrically connected to one main processor (411) may process one of the frequency bands of a signal in a second frequency band corresponding to the second link (232) and a signal in a third frequency band corresponding to the third link (233), and thus, one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). Specific examples are described later in FIGS. 5 and FIGS. 6. For example, the electronic device (100) may not be able to perform short-range wireless communication using the third link (233) while performing short-range wireless communication using the second link (232). As another example, the electronic device (100) may not be able to perform short-range wireless communication using the second link (232) while performing short-range wireless communication using the third link (233).

[0272] Considering that short-range wireless communication using the second link (232) and the third link (233) cannot be performed, the electronic device (100) may control the communication circuit (410) to switch (or maintain) one of the second link (232) and the third link (233) to a disabled state. The electronic device (100) may control the communication circuit (410) to transmit a disabled request signal containing information indicating the link to be disabled to an external electronic device (220) in order to switch one of the second link (232) and the third link (233) to a disabled state. According to one example, the electronic device (210) may transmit a signal (e.g., a Qos Null frame with the power management bit set to 1) to the external electronic device (220) instructing to switch to a power saving mode. In FIG. 4, for convenience of explanation, the third link (233) is assumed to be disabled.

[0273] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0274] According to one example, the electronic device (100) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0275] The electronic device (100) can control the communication circuit (410) so that the main processor (411) checks the quality of an active link among a plurality of links combined between the electronic device (100) and an external electronic device (220), and the auxiliary processor (412) checks the quality of a deactivated link among a plurality of links combined between the electronic device (100) and an external electronic device (220). The main processor (411) may receive a signal from the external electronic device (220) through the active link and can check the quality of the active link based on the received signal. If the main processor (411) checks the quality of a deactivated link that cannot be used simultaneously with the active link, the active link must be switched to a deactivated state. Therefore, the electronic device (100) can prevent the active link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0276] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (100) or the communication circuit (410) can receive a signal through the first link (231) and measure the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the first link (231).

[0277] The electronic device (100) can receive a signal through the second link (232) and measure the quality of the second link (232) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the second link (232).

[0278] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0279] The auxiliary processor (412) can receive a signal through the third link (233) using an antenna electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the main processor (411) from switching to a deactivated state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the main processor (411) from performing the operation of checking the quality of the third link (233).

[0280] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) while the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). The operation of the main processor (411) checking the quality of the activated links and the operation of the auxiliary processor (412) checking the quality of the deactivated links may be performed in parallel. For example, the operation of the main processor (411) checking the quality of the activated links may be performed substantially simultaneously with the operation of the auxiliary processor (412) checking the quality of the deactivated links. Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links may also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0281] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) before the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). According to one example, the auxiliary processor (412) may be configured to check the quality of deactivated links at specified intervals, and the auxiliary processor (412) may check the quality of deactivated links at specified intervals. When the electronic device (100) detects that the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded, when a specified time has expired after the first link (231) and the second link (232) are activated, when the size of the data to be transmitted and / or received via short-range wireless communication increases, or when the number of activated links needs to be changed according to the mode switching of the electronic device (210), the communication circuit (410) can be controlled to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the electronic device (100) detects that the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded, when the first link (231) and the second link (232) are activated, when a specified time has expired, when the size of the data to be transmitted and / or received via short-range wireless communication increases, or when the number of activated links needs to be changed according to the mode switching of the electronic device (210). The communication circuit (410) can enable the main processor (411) to check the quality of the activated link upon receiving a control signal from the electronic device (100), and can transmit to the electronic device (100) information indicating the quality of the deactivated link previously checked by the auxiliary processor (412) and information indicating the quality of the activated link checked upon receiving the control signal from the electronic device (100). Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links can also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0282] According to one example, the quality of multiple links (e.g., a first link (231), a second link (232) and / or a third link (233)) may refer to the expected data rate when transmitting and / or receiving data through each link. The higher the expected data rate, the higher the quality of the link may be. Conversely, the lower the expected data rate, the lower the quality of the link may be.

[0283] Alternatively, the quality of multiple links (e.g., first link (231), second link (232) and / or third link (233)) may refer to a score determined based on the expected data rate when transmitting and / or receiving data through the link. The higher the score, the higher the quality of the link may be. Conversely, the lower the score, the lower the quality of the link may be.

[0284] The electronic device (100) can determine, in operation 820, whether there exists a combination of multiple links that has a higher quality than the combination of the activated links.

[0285] The electronic device (100) can activate a deactivated link among the links included in the higher quality combination and deactivate a link among the activated links that is not included in the higher quality combination, based on the fact that, in operation 830, there exists a combination of multiple links that has a higher quality than the combination of activated links (operation 820-Y).

[0286] An electronic device (210) can perform short-range wireless communication using at least two main processors (411) among at least one main processor (411). The electronic device (210) performing short-range wireless communication using two or more processors (411) may be referred to as MLMR (multi-link multi-radio). When the electronic device (210) performs short-range wireless communication using two or more main processors (411), short-range wireless communication can be performed through a combination of some links among multiple links. The electronic device (100) (or, electronic device (100)) can determine whether there exists a combination of links having a higher quality than the quality of the combination of currently active links, based on the quality of each of the multiple links. The electronic device (100) can control the communication circuit (410) to perform short-range wireless communication through the combination of links having a higher quality than the quality of the combination of currently active links, based on the quality of each of the multiple links, if there exists a combination of links having a higher quality than the quality of the combination of currently active links.

[0287] According to one example, the electronic device (100) can control the communication circuit (410) so that the link included in the combination of links having a higher quality among the links included in the combination of currently active links remains in an active state.

[0288] According to one example, the electronic device (100) can control the communication circuit (410) so that links included in the combination of currently active links that are not included in the combination of links with higher quality are switched from an active state to a deactivated state. The communication circuit (410) can cause links included in the combination of currently active links that are not included in the combination of links with higher quality to be switched to a power saving mode by transmitting a signal (e.g., a Qos Null frame with the power management bit set to 1) to an external electronic device (220) that instructs (or requests) the links included in the combination of currently active links that are not included in the combination of links with higher quality to be switched from an active state to a deactivated state.

[0289] According to one example, the electronic device (100) can control the communication circuit (410) to switch a link included in the combination of links with higher quality among the links not included in the combination of currently active links (or, disabled links) from a disabled state to an enabled state. The communication circuit (410) can switch a link included in the combination of links with higher quality among the links not included in the combination of currently active links (or, disabled links) from a disabled state to an enabled state by transmitting a signal (e.g., a Qos Null frame with the power management bit set to 0) to an external electronic device (220) that instructs (or requests) the link not included in the combination of links with higher quality among the links included in the combination of currently active links to disable the power saving mode.

[0290] The electronic device (100) can perform short-range wireless communication using a combination of existing active links based on the fact that there is no combination of multiple links that has a higher quality than the combination of active links (operation 820-N).

[0291] FIG. 9 is an operation flowchart (900) illustrating the operation method of an electronic device according to one embodiment.

[0292] An electronic device (e.g., the electronic device (100) of FIG. 4) can be confirmed to satisfy the conditions for performing an operation to check the quality of multiple links while performing short-range wireless communication through an active link among multiple links in operation 910.

[0293] According to one example, an electronic device (100) may perform a series of operations to connect with an external electronic device (220) in order to perform short-range wireless communication. For example, the electronic device (100) may perform an operation to discover an external electronic device (220) in order to connect with an external electronic device (220) that supports short-range wireless communication.

[0294] According to one example, the electronic device (100) can discover the external electronic device (220) by receiving a signal (e.g., beacon signal, probe response signal) transmitted (or broadcasted) by the external electronic device (220) through a plurality of frequency bands supported by the electronic device (210) (e.g., a frequency band corresponding to the first link (231), a frequency band corresponding to the second link (232), and / or a frequency band corresponding to the third link (233)).

[0295] The electronic device (100) can perform authentication with the external electronic device (220) after discovering the external electronic device (220). The electronic device (210) can perform an association operation after successfully authenticating with the external electronic device (220).

[0296] The electronic device (100) can transmit an association request frame to an external electronic device (220), and the external electronic device (220) can transmit an association response frame containing information indicating whether the association was successful after receiving the association request frame.

[0297] According to one embodiment, the association request frame and / or association response frame may include information related to various capabilities. For example, the association request frame may include information related to various capabilities, a beacon listen interval, a service set identifier (SSID), supported rates, supported channels, an RSN, a mobility domain, supported operating classes, a traffic indication map broadcast request, and / or information regarding interworking service capabilities. For example, the association response frame may include information related to various capabilities, such as a status code, an association ID (AID), supported rates, an enhanced distributed channel access (EDCA) parameter set, a received channel power indicator (RCPI), a received signal to noise indicator (RSNI), a mobility domain, a timeout interval (association comeback time), overlapping BSS scan parameters, a TIM broadcast response, and / or a QoS map.

[0298] According to one example, if the electronic device (100) and the external electronic device (220) support MLO, the combined operation can be performed through a first link (231) corresponding to a first frequency band, a second link (232) corresponding to a second frequency band, and / or a third link (233) corresponding to a third frequency band.

[0299] The electronic device (210) can perform a security setup operation after completing the coupling operation. The electronic device (210) and the external electronic device (220) can perform short-range wireless communication after performing the security setup.

[0300] The electronic device (100) can control the communication circuit (410) to perform short-range wireless communication through an activated link among a plurality of links combined between the electronic device (100) and an external electronic device (220).

[0301] According to one example, the number of active links may be multiple. For example, a first link (231) and a second link (232) may be active links. An active link may be a link connected between an electronic device (100) and an external electronic device (220), and may be a link capable of performing short-range wireless communication. Conversely, a deactivated link may be a link connected between an electronic device (100) and an external electronic device (220), but may be a link that cannot perform short-range wireless communication. According to one example, a deactivated link is a link that has entered a power saving mode, such that the electronic device (100) may not transmit data to the external electronic device (220) through the deactivated link, and the external electronic device (220) may also not transmit data to the electronic device (100) through the deactivated link.

[0302] According to one example, the electronic device (100) may not be able to simultaneously perform short-range wireless communication using the second link (232) and short-range wireless communication using the third link (233). In the implementation of the communication circuit (410), one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). For example, a front end module (FEM) electrically connected to one main processor (411) may process one of the frequency bands of a signal in a second frequency band corresponding to the second link (232) and a signal in a third frequency band corresponding to the third link (233), and thus, one main processor (411) may not be able to simultaneously perform the transmission of a signal through the second link (232) and the transmission of a signal through the third link (233). Specific examples are described later in FIGS. 5 and FIGS. 6. For example, the electronic device (100) may not be able to perform short-range wireless communication using the third link (233) while performing short-range wireless communication using the second link (232). As another example, the electronic device (100) may not be able to perform short-range wireless communication using the second link (232) while performing short-range wireless communication using the third link (233).

[0303] Considering that short-range wireless communication using the second link (232) and the third link (233) cannot be performed, the electronic device (100) may control the communication circuit (410) to switch (or maintain) one of the second link (232) and the third link (233) to a disabled state. The electronic device (100) may control the communication circuit (410) to transmit a disabled request signal containing information indicating the link to be disabled to an external electronic device (220) in order to switch one of the second link (232) and the third link (233) to a disabled state. According to one example, the electronic device (210) may transmit a signal (e.g., a Qos Null frame with the power management bit set to 1) to the external electronic device (220) instructing to switch to a power saving mode. In FIG. 4, for convenience of explanation, the third link (233) is assumed to be disabled.

[0304] The electronic device (100) can check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) while performing short-range wireless communication using the first link (231) and the second link (232).

[0305] According to one example, the electronic device (100) can control the communication circuit (410) to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded; when a specified time has expired after the first link (231) and the second link (232) are activated; when the size of the data to be transmitted and / or received via short-range wireless communication increases; or when the number of activated links needs to be changed according to the mode switching of the electronic device (210).

[0306] The electronic device (100) can, in operation 820, allow the main processor ($11) to check the quality of the active link and the auxiliary processor (412) to check the quality of the deactivated link.

[0307] The electronic device (100) can control the communication circuit (410) so that the main processor (411) checks the quality of an active link among a plurality of links combined between the electronic device (100) and an external electronic device (220), and the auxiliary processor (412) checks the quality of a deactivated link among a plurality of links combined between the electronic device (100) and an external electronic device (220). The main processor (411) may receive a signal from the external electronic device (220) through the active link and can check the quality of the active link based on the received signal. If the main processor (411) checks the quality of a deactivated link that cannot be used simultaneously with the active link, the active link must be switched to a deactivated state. Therefore, the electronic device (100) can prevent the active link from being switched to a deactivated state in order to perform the check of the quality of the deactivated link by controlling the communication circuit (410) so that the auxiliary processor (412) checks the quality of the deactivated link.

[0308] The electronic device (100) can check the quality of an active link (e.g., a first link (231) and a second link (232)) among a plurality of links combined with an external electronic device (220). The electronic device (100) or the communication circuit (410) can receive a signal through the first link (231) and measure the quality of the first link (231) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the first link (231).

[0309] The electronic device (100) can receive a signal through the second link (232) and measure the quality of the second link (232) based on at least one parameter related to the signal. The electronic device (100) can control the communication circuit (410) so that the main processor (411) of the communication circuit (410) measures the quality of the second link (232).

[0310] The electronic device (100) can control the communication circuit (410) to check the quality of a deactivated link (e.g., a third link (233)) among a plurality of links combined with an external electronic device (220). The communication circuit (410) can allow the auxiliary processor (412) to check the quality of the third link (233) while the second link (232) is kept in an active state. The auxiliary processor (412) may be in a deactivated state prior to performing the operation of checking the quality of the plurality of links. The electronic device (100) can control the communication circuit (410) to switch the auxiliary processor (412) from a deactivated state to an active state in order to check the quality of the deactivated link among the plurality of links.

[0311] The auxiliary processor (412) can receive a signal through the third link (233) using an antenna electrically (or kinetically) connected to the auxiliary processor (412). The auxiliary processor (412) can process the received signal, check parameters related to the signal based on the processed signal, and check the quality of the third link (233) based on the parameters. The communication circuit (410) can prevent the main processor (411) from switching to a deactivated state of the second link (232) by checking the quality of the third link (233) by prohibiting (or restraining) the main processor (411) from performing the operation of checking the quality of the third link (233).

[0312] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) while the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). The operation of the main processor (411) checking the quality of the activated links and the operation of the auxiliary processor (412) checking the quality of the deactivated links may be performed in parallel. For example, the operation of the main processor (411) checking the quality of the activated links may be performed substantially simultaneously with the operation of the auxiliary processor (412) checking the quality of the deactivated links. Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links may also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0313] The auxiliary processor (412) may be configured to check the quality of deactivated links (e.g., third link (233)) before the main processor (411) checks the quality of activated links (e.g., first link (231) and / or second link (232)). According to one example, the auxiliary processor (412) may be configured to check the quality of deactivated links at specified intervals, and the auxiliary processor (412) may check the quality of deactivated links at specified intervals. When the electronic device (100) detects that the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded, when a specified time has expired after the first link (231) and the second link (232) are activated, when the size of the data to be transmitted and / or received via short-range wireless communication increases, or when the number of activated links needs to be changed according to the mode switching of the electronic device (210), the communication circuit (410) can be controlled to check (or monitor, measure) the quality of a plurality of links combined with an external electronic device (220) by confirming that any one of the following is satisfied: when the electronic device (100) detects that the performance of short-range wireless communication using the first link (231) and the second link (232) is degraded, when the first link (231) and the second link (232) are activated, when a specified time has expired, when the size of the data to be transmitted and / or received via short-range wireless communication increases, or when the number of activated links needs to be changed according to the mode switching of the electronic device (210). The communication circuit (410) can enable the main processor (411) to check the quality of the activated link upon receiving a control signal from the electronic device (100), and can transmit to the electronic device (100) information indicating the quality of the deactivated link previously checked by the auxiliary processor (412) and information indicating the quality of the activated link checked upon receiving the control signal from the electronic device (100). Accordingly, the electronic device (210) can reduce the time required to check the quality of each of the multiple links, and the time required to control the links can also be reduced as the time required to check the quality of each of the multiple links is reduced.

[0314] According to one example, the quality of multiple links (e.g., a first link (231), a second link (232) and / or a third link (233)) may refer to the expected data rate when transmitting and / or receiving data through each link. The higher the expected data rate, the higher the quality of the link may be. Conversely, the lower the expected data rate, the lower the quality of the link may be.

[0315] Alternatively, the quality of multiple links (e.g., first link (231), second link (232) and / or third link (233)) may refer to a score determined based on the expected data rate when transmitting and / or receiving data through the link. The higher the score, the higher the quality of the link may be. Conversely, the lower the score, the lower the quality of the link may be.

[0316] The electronic device (100) can control at least one link based on the quality of each of the multiple links in operation 830.

[0317] The electronic device (100) can control the communication circuit (410) to control at least one of the multiple links based on the quality of each of the multiple links.

[0318] An electronic device (210) can perform short-range wireless communication using one of at least one main processor (411). The electronic device (210) performing short-range wireless communication using one main processor (411) may be referred to as MLSR (multi-link single radio). When the electronic device (210) performs short-range wireless communication using one main processor (411), it can perform short-range wireless communication through any one of a plurality of links. The electronic device (100) (or, electronic device (100)) can determine whether there exists a link with a higher quality than the quality of the currently active link based on the quality of each of the plurality of links. If there exists a link with a higher quality than the quality of the currently active link, the electronic device (100) can switch the link with the higher quality to an active state and switch the currently active link to an inactive state.

[0319] An electronic device (210) can perform short-range wireless communication using at least two main processors (411) among at least one main processor (411). The electronic device (210) performing short-range wireless communication using two or more processors (411) may be referred to as MLMR (multi-link multi-radio). When the electronic device (210) performs short-range wireless communication using two or more main processors (411), short-range wireless communication can be performed through a combination of some links among multiple links. The electronic device (100) (or, electronic device (100)) can determine whether there exists a combination of links having a higher quality than the quality of the combination of currently active links, based on the quality of each of the multiple links. The electronic device (100) can control the communication circuit (410) to perform short-range wireless communication through the combination of links having a higher quality than the quality of the combination of currently active links, based on the quality of each of the multiple links, if there exists a combination of links having a higher quality than the quality of the combination of currently active links.

[0320] According to one example, the electronic device (100) can control the communication circuit (410) so that the link included in the combination of links having a higher quality among the links included in the combination of currently active links remains in an active state.

[0321] According to one example, the electronic device (100) can control the communication circuit (410) so that links included in the combination of currently active links that are not included in the combination of links with higher quality are switched from an active state to a deactivated state. The communication circuit (410) can cause links included in the combination of currently active links that are not included in the combination of links with higher quality to be switched to a power saving mode by transmitting a signal (e.g., a Qos Null frame with the power management bit set to 1) to an external electronic device (220) that instructs (or requests) the links included in the combination of currently active links that are not included in the combination of links with higher quality to be switched from an active state to a deactivated state.

[0322] According to one example, the electronic device (100) can control the communication circuit (410) to switch a link included in the combination of links with higher quality among the links not included in the combination of currently active links (or, disabled links) from a disabled state to an enabled state. The communication circuit (410) can switch a link included in the combination of links with higher quality among the links not included in the combination of currently active links (or, disabled links) from a disabled state to an enabled state by transmitting a signal (e.g., a Qos Null frame with the power management bit set to 0) to an external electronic device (220) that instructs (or requests) the link not included in the combination of links with higher quality among the links included in the combination of currently active links to disable the power saving mode.

[0323] An electronic device according to one example may include a communication circuit comprising a main processor that transmits and / or receives a signal through an active link among a plurality of links associated with an access point (AP), and an auxiliary processor that receives a signal through an antenna electrically connected to both the main processor and the auxiliary processor. The electronic device may include a memory that stores a computer program including instructions. The electronic device may include at least one application processor. The instructions may cause the electronic device to confirm, when executed individually or collectively by the at least one application processor, that the conditions for performing an operation to check the quality of each of the plurality of links are satisfied while performing short-range wireless communication through the active link. The instructions may cause the communication circuit to be controlled so that, when executed individually or collectively by the at least one application processor, the main processor checks the quality of the active link and the auxiliary processor checks the quality of the inactive link among the plurality of links, based on the confirmation that the electronic device satisfies the conditions for performing an operation to check the quality of each of the plurality of links. The above instructions may enable the electronic device to control at least one of the plurality of links based on the quality of each of the plurality of links when executed individually or collectively by the at least one application processor.

[0324] In an electronic device according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may be configured to prohibit the main processor from checking the quality of the disabled link.

[0325] In an electronic device according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may allow the auxiliary processor to check the quality of the deactivated link while maintaining the connection of the activated link.

[0326] In an electronic device according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may be configured to prohibit the operation of switching the disabled link to an enabled state while the main processor checks the quality of the disabled link with the auxiliary processor.

[0327] In an electronic device according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may enable the link with the best quality among the plurality of links and disable the enabled link when the communication circuit performs short-range wireless communication through one of the plurality of links.

[0328] In an electronic device according to one example, the instructions, when executed individually or collectively by the at least one application processor, may cause the electronic device to select a combination of links having a higher quality than the quality of the at least two links when the communication circuit performs short-range wireless communication through at least two of the plurality of links. The instructions, when executed individually or collectively by the at least one application processor, may cause the electronic device to activate the links included in the combination.

[0329] In an electronic device according to one example, the auxiliary processor may be configured not to transmit a signal through the main processor and one antenna electrically connected to the auxiliary processor.

[0330] In an electronic device according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may switch the auxiliary processor from a disabled state to an enabled state to check the quality of the disabled link.

[0331] In an electronic device according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may control the communication circuit so that the auxiliary processor checks the quality of the inactive link while the main processor checks the quality of the active link.

[0332] In an electronic device according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may control the communication circuit so that the auxiliary processor checks the quality of the deactivated link at specified intervals while performing short-range wireless communication through the activated link. The operation of checking the quality of the deactivated link among the plurality of links may be performed prior to checking whether the conditions for performing a quality measurement of the plurality of links are satisfied.

[0333] A computer-readable recording medium storing instructions that cause an electronic device to perform when executed by at least one processor of an electronic device according to one example, wherein the instructions may cause the electronic device to perform short-range wireless communication through an active link among a plurality of links associated between an access point (AP) and the electronic device when executed individually or collectively by the at least one processor. The instructions may cause the electronic device to control the communication circuit so that, when executed individually or collectively by the at least one processor, a main processor included in the communication circuit of the electronic device checks the quality of the active link and an auxiliary processor included in the communication circuit checks the quality of the inactive link among the plurality of links. The instructions may cause the electronic device to control at least one link among the plurality of links based on the quality of each of the plurality of links when executed individually or collectively by the at least one processor.

[0334] In a recording medium according to one example, when the instructions are executed individually or collectively by the at least one application processor, the electronic device may be configured to prohibit the main processor from performing an operation to check the quality of the disabled link.

[0335] In a recording medium according to one example, the instructions may enable the auxiliary processor to check the quality of the deactivated link while the electronic device maintains the connection of the activated link, when executed individually or collectively by the at least one application processor.

[0336] In a recording medium according to one example, the instructions may be configured such that, when executed individually or collectively by the at least one application processor, the electronic device is configured to prohibit the operation of switching the disabled link to an enabled state while the main processor checks the quality of the disabled link.

[0337] In a recording medium according to one example, the instructions may be executed individually or collectively by the at least one application processor, and the electronic device may be configured to control the communication circuit so that, while performing short-range wireless communication through an active link among the plurality of links, the auxiliary processor checks the quality of an inactive link among the plurality of links at specified intervals. The operation of checking the quality of an inactive link among the plurality of links may be performed prior to checking whether the conditions for measuring the quality of the plurality of links are satisfied.

[0338] A method of operation of an electronic device according to one example may include an operation of performing short-range wireless communication through an active link among a plurality of links associated between an access point (AP) and the electronic device. The method of operation of the electronic device may include an operation in which a main processor included in the communication circuit of the electronic device checks the quality of the active link, and an auxiliary processor included in the communication circuit checks the quality of an inactive link among the plurality of links. The method of operation of the electronic device may include an operation of controlling at least one link among the plurality of links based on the quality of each of the plurality of links.

[0339] A method of operation of an electronic device according to one example may further include an operation to set the main processor to prohibit an operation to check the quality of the disabled link.

[0340] In a method of operation of an electronic device according to one example, the operation of a main processor included in the communication circuit of the electronic device checking the quality of the activated link and an auxiliary processor included in the communication circuit checking the quality of the deactivated link among the plurality of links may include the auxiliary processor checking the quality of the deactivated link while maintaining the connection of the activated link.

[0341] A method of operation of an electronic device according to one example may further include the operation of switching the disabled link to an enabled state while the main processor checks the quality of the disabled link.

[0342] A method of operation of an electronic device according to one example may further include an operation in which, while performing short-range wireless communication through a link that is active among the plurality of links, the auxiliary processor controls the communication circuit to check the quality of a link that is inactive among the plurality of links at specified intervals. A method of operation of the electronic device may further include an operation in which the main processor controls the communication circuit to check the quality of the active link based on confirming that the conditions for performing the operation of checking the quality of the plurality of links are satisfied. The operation of checking the quality of a link that is inactive among the plurality of links may be performed before confirming whether the conditions for performing a measurement of the quality of the plurality of links are satisfied.

Claims

1. In an electronic device that supports short-range wireless communication, A communication circuit comprising a main processor that transmits and / or receives a signal through an active link among a plurality of links associated with an access point (AP), and an auxiliary processor that receives a signal through a single antenna electrically connected to both the main processor and the auxiliary processor; Memory for storing computer programs including instructions; and It includes at least one application processor, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, While performing short-range wireless communication through the above-mentioned activated link, confirm that the conditions for performing an operation to check the quality of each of the plurality of links are satisfied, and Based on confirming that the conditions for performing an operation to check the quality of each of the plurality of links are satisfied, the communication circuit is controlled such that the main processor checks the quality of the activated link and the auxiliary processor checks the quality of the deactivated link among the plurality of links. An electronic device for controlling at least one of the plurality of links based on the quality of each of the plurality of links.

2. In Paragraph 1, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, An electronic device configured to prevent the main processor from performing an operation to check the quality of the disabled link.

3. In paragraphs 1 and 2, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, An electronic device that allows the auxiliary processor to check the quality of the deactivated link while maintaining the connection of the above-mentioned activated link.

4. In paragraphs 1 through 3, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, An electronic device configured such that the main processor prohibits the operation of switching the disabled link to an enabled state while the auxiliary processor checks the quality of the disabled link.

5. In paragraphs 1 through 4, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, An electronic device that, when the communication circuit performs short-range wireless communication through one of the plurality of links, activates the link with the best quality among the plurality of links and deactivates the activated link.

6. In paragraphs 1 through 5, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, When the communication circuit performs short-range wireless communication through at least two of the plurality of links, it selects a combination of links having a higher quality than the quality of the at least two links, An electronic device that enables the activation of links included in the above combination.

7. In Paragraph 1, The above auxiliary processor An electronic device configured not to transmit a signal through a single antenna electrically connected to the main processor and the auxiliary processor.

8. In Paragraph 1, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, An electronic device that switches the auxiliary processor from an inactive state to an active state to check the quality of the link in the inactive state.

9. In Paragraph 1, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, An electronic device that controls the communication circuit so that while the main processor checks the quality of the link in the active state, the auxiliary processor checks the quality of the link in the inactive state.

10. In Paragraph 1, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, While performing short-range wireless communication through the above-mentioned activated link, the auxiliary processor controls the communication circuit to check the quality of the above-mentioned deactivated link at specified intervals, and An electronic device that performs an operation to check the quality of a link in an inactive state among the plurality of links above before checking whether the conditions for measuring the quality of the plurality of links are satisfied.

11. A computer-readable recording medium storing instructions that cause the electronic device to perform when executed by at least one processor of the electronic device, When the above instructions are executed individually or collectively by the at least one processor, the electronic device, Short-range wireless communication is performed through an active link among a plurality of links associated between the AP (access point) and the electronic device, and The communication circuit is controlled so that the main processor included in the communication circuit of the electronic device checks the quality of the activated link, and the auxiliary processor included in the communication circuit checks the quality of the deactivated link among the plurality of links. A recording medium for controlling at least one of the plurality of links based on the quality of each of the plurality of links.

12. In Paragraph 11, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, A recording medium configured to prevent the above main processor from performing an operation to check the quality of the above disabled link.

13. In paragraphs 11 and 12, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, A recording medium that allows the auxiliary processor to check the quality of the deactivated link while maintaining the connection of the activated link.

14. In paragraphs 11 through 13, When the above instructions are executed individually or collectively by the at least one application processor, the electronic device, A recording medium configured such that the main processor prohibits the operation of switching the disabled link to an active state while checking the quality of the disabled link.

15. In a method of operating an electronic device, An operation of performing short-range wireless communication through an activated link among a plurality of links associated between an AP (access point) and the electronic device; An operation in which a main processor included in the communication circuit of the electronic device checks the quality of the activated link, and an auxiliary processor included in the communication circuit checks the quality of the deactivated link among the plurality of links; A method of operation of an electronic device comprising controlling at least one link among the plurality of links based on the quality of each of the plurality of links.

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