Dynamic random access memory (DRAM) device with simultaneous activate and refresh

Abstract

A dynamic random access memory (DRAM) device includes an array of DRAM storage cells. Refresh control circuitry refreshes the DRAM storage cells within a refresh period. The refresh control circuitry includes circuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks. At the end of the first sub-period of the refresh period, a value is generated indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh period. Transmit circuitry transmits the value to the memory controller.

Description

UNITED STATES PATENT APPLICATIONFOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE WITH SIMULTANEOUS ACTIVATE AND REFRESHInventor(s): Thomas VogelsangTorsten PartschPrepared By: Peninsula Patent Group2644 Placer St.Santa Cruz, California 95062 Tel.: 650-468-9654Attorney Docket No. : RBS2 P207WQDYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE WITH SIMULTANEOUS ACTIVATE AND REFRESH TECHNICAL FIELD

[0001] The disclosure herein relates to memory systems, memory controllers, memory devices, and associated methods.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0003] FIG. 1 illustrates one embodiment of a memory system that employs a memory controller, and at least one memory device.

[0004] FIG. 2 illustrates one embodiment of the memory device of FIG. 1 with multiple banks, and an expanded view of multiple regions associated with a given one of the multiple banks.

[0005] FIG. 3 illustrates one embodiment of the refresh control circuitry of FIG. 1.

[0006] FIG. 4 illustrates a timing chart that shows a set of regions associated with a given bank that are selectively and progressively accessed by parallel activate and refresh operations during a first phase of a refresh cycle time, and accessed by normal activate and refresh operations during a second phase of the refresh cycle time.

[0007] FIG. 5 illustrates a table showing one embodiment of eligible regions of a given bank that may be refreshed while another specific region is accessed via an activate command during the first phase of the refresh cycle time shown in FIG. 4.

[0008] FIG. 6 illustrates high-level steps employed in operating the circuitry of FIGs. 1- 3 in accordance with the timings and constraints for the first phase of refresh shown in FIGs.4 and 5.

[0009] FIG. 7 illustrates high-level steps employed in operating the circuitry of FIGs. 1-3 in accordance with the timings and constraints for the second phase of refresh shown in FIG. 4.DETAILED DESCRIPTION

[0010] Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes an array of DRAM storage cells. Refresh control circuitry refreshes the DRAM storage cells within a refresh cycle time. The refresh control circuitry includes circuitry to refresh, during a first sub-period of the refresh cycle time, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks. At the end of the first sub-period of the refresh cycle time, a value is generated indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh cycle time. Transmit circuitry transmits the value to the memory controller. By refreshing at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks, an idle latency interval associated with refresh operations may be reduced.

[0011] Referring now to FIG. 1, a memory system, generally designated 100, is shown that includes a memory controller 102 coupled to one or more memory devices 104 viasignaling media 106. For one embodiment, the memory controller 102 is a dynamic random access memory (DRAM) controller, with the memory device 104 realized as a DRAM memory device. In some embodiments, the memory controller 102 and the memory device 104 may be embodied as integrated circuits, or chips. Other embodiments may employ the memory controller 102 as a circuit in a host central processing unit (CPU) (not shown). Specific embodiments for the DRAM memory controller 102 and the memory device 104 may be compliant with various DRAM standards, including double data rate (DDR) variants, low power (LPDDR) versions, high bandwidth (HBM), and graphics (GDDR) types. Other embodiments may include multi-chip modules that, for example, employ stacked memory die, or stacked packages. Additional embodiments may stack memory die and logic die together in a common package, or in separate packages stacked upon each other. Yet other embodiments may employ multiple memory devices on a substrate (not shown) in a memory module configuration for high-capacity applications.

[0012] Further referring to FIG. 1, for one embodiment, each memory device 104 includes memory interface circuitry 108 for handling communications between the memory controller 102 and memory core circuitry 110 of the memory device 104. The memory core circuitry 110 generally includes row decoder circuitry 112 and column decoder circuitry 114 that activate a given wordline and bitline, shown respectively at 116 and 118 for a given one of multiple banks 120 in response to receiving address information from the memory interface circuitry 108. The activated wordline 116 and bitline 118 cooperate to access a given storage cell 122.

[0013] With continued reference to FIG. 1, data stored in the given storage cell 122 is refreshed at a refresh rate determined by refresh control circuitry 124, and sequenced by a refresh counter circuit 126. For one embodiment, register storage 128 is provided to temporarily store a status of the refresh counter circuit 126 that may be accessed by thememory controller 102 to schedule refresh commands for carrying out remaining refresh operations to refresh unrefreshed rows, described more fully below. The register storage 128 may also store configuration settings set by the memory controller 102 to specify certain parameter settings, such as a default retention time, and / or mode settings to, for example, carry out refresh operations in a default legacy mode, referred to herein as a “normal” refresh mode, or in a multi-phase refresh mode more fully described below.

[0014] In some embodiments, during a sub-period of the multi-phase refresh mode of operation, the given storage cell 122, which resides in a given region of the given bank 120, may be accessed by an activate command (which generally accesses an entire row of storage cells in the bank) in parallel with refresh operations occurring in storage cells of different regions of the same bank. By providing the ability to perform activates and refreshes in parallel within a same bank, improvements to idle latency times may be realized during the multi-phase refresh mode of operation.

[0015] FIG. 2 illustrates one embodiment of an integrated circuit (IC) DRAM device 200 that may be employed in the memory system of FIG. 1. The IC DRAM device 200 is generally configured to support multi-phase refresh operations, where a given refresh period may be divided into sub-periods and where refresh operations may be carried out in parallel with activate commands in a first one of the sub-periods to reduce idle latency effects. The IC DRAM device 200 may also be configurable to support “normal” or legacy refresh modes of operation. For one specific embodiment of the multi-phase refresh mode of operation, each refresh period includes a first sub-period or phase that allows for refreshes to occur in a bank in response to that bank receiving an activate command. The activate command in a DRAM protocol is generally a command that opens or accesses a row in a DRAM bank for a read / write command sequence. During “normal” refresh operations, or those based on legacy refresh techniques, DRAM banks having received an activate command during a givenrefresh period are typically precluded from carrying out refresh operations due to bank conflict risks. The disclosure presented herein identifies ways to mitigate the conflict risks so that refresh operations may be successfully carried out in parallel, or concurrently, with activate commands during the first sub-period of the refresh period. A second sub-period of the refresh period performs normal refresh operations on storage cells that weren’t refreshed during the first phase, allowing refreshes for banks not currently accessed by an activate command.

[0016] To accomplish the multi-phase refresh operations noted above, and with continued reference to FIG. 2, the DRAM device, or chip 200 includes multiple banks 202 that may be arranged on opposing sides of a main circuit stripe including peripheral circuitry 204. For one embodiment, each of the multiple banks 202 is organized into multiple sub-arrays or regions 206. For one specific embodiment, examples described herein organize each bank 202 into eight regions 206, with each region 206 being organized into a predefined number of rows (not shown) in the bank 202.

[0017] Further referring to FIG. 2, each region 206 includes region row control circuitry 208 that is responsive to address, command and various control signals generated by bank row control circuitry 210. Per-region refresh counter circuits 212 track the number of rows that are refreshed during a refresh cycle time, which is a time interval generally implemented by the DRAM device 200 to refresh a given row of DRAM storage cells. For one embodiment, the range of the per-region refresh counter circuits 212 is selected to correspond to the length of a region 206 to avoid missing refreshes or introducing unnecessary refreshes. The per-region refresh counter circuits 212 provide an output count value to a comparator circuit 214. For one embodiment, during the first phase of the refresh cycle time, the comparator circuit 214 determines a lowest counter value from the set of per-region refresh counter circuits 212, and provides the lowest counter value to the peripheral circuitry 204.

[0018] With continued reference to FIG. 2, the bank row control circuitry 210 for a given bank receives row address information “row address”, row command information “row command”, and refresh phase information “phase” from the peripheral circuitry 204, and passes the row address information “row address” and the row command information “row command” to the multiple region row control circuits 208. The refresh phase information “phase” informs the bank row control circuitry 210 which sub-period or phase of the refresh cycle time a given bank is currently operating in. Dedicated per-region enable signals, such as at 216, are selectively generated and sent to one or more of the multiple region row control circuits 208 during the first phase of refresh operation based on certain constraints which are more fully discussed below. The enable signals generated by the bank row control circuitry 210 allow for one or more regions of a given bank to be refreshed during the first phase of operation in response to the bank receiving an activate command. For one embodiment, topological constraints for the conditional enable signals are described below, and shown in FIG. 5. During the second phase of refresh operation, the enable signals are all disabled to allow the regions to be refreshed via the “normal” or legacy refresh technique where refresh commands are dispatched by the memory controller 102, and refreshes are carried out in response to the externally-generated refresh commands.

[0019] Referring now to FIG. 3, for one embodiment, the peripheral circuitry 204 includes main refresh control circuitry 302 that feeds refresh commands, address information, and refresh phase information to per-bank refresh control circuits 304. During the first phase of a refresh operation, the main refresh control circuitry 302 generates on-chip refresh commands for selected ones of the per-bank refresh control circuits 304 in response to detecting activate commands directed to the banks. During the second phase of the refresh operation, the main refresh control circuitry 302 distributes off-chip refresh commands (generated by the memory controller 102) to the per-bank refresh control circuits 304.

[0020] Further referring to FIG. 3, the main refresh control circuitry 302 couples to refresh count control circuitry 306. For one embodiment, the refresh count control circuitry 306 receives the various lowest counter values from the comparator circuit 214 (FIG. 2) of each bank 202 and determines a lowest refresh start value for the entire chip for the second phase of refresh operation. The lowest refresh start value may then be stored in register circuitry 308 (which corresponds to the register circuitry 128 in FIG. 1), and accessed by the memory controller 102 for an indication of the remaining number of refreshes that need to be carried out in order to fully refresh the entire DRAM device 104. For one embodiment, the register circuitry 308 may include other refresh-related fields, such as a mode field indicating whether the DRAM is configured to operate in the multi-phase refresh mode of operation, or whether the DRAM is configured to operate solely in a “normal” (legacy) refresh mode of operation during the entire refresh period that generally prohibits refresh and activate operations from occurring in a same bank at the same time.

[0021] FIG. 4 illustrates a timing chart that shows a set 402 of storage regions 404 associated with a given bank that is selectively and progressively accessed by parallel activate “A” and refresh “R” operations within a sequence of refresh cycle-time (TRFC) timeslots 406 during a first phase 408 of a refresh period 410, and accessed by normal activate A and refresh R operations during a second phase 412 of the refresh period 410. While not shown in FIG. 4, for some embodiments, the first phase 408 and the second phase 412 combine to form a first sub-period of the refresh period 410, with at least a second sequence of the first phase 408 and the second phase 412 defining a second sub-period of the refresh period 410.

[0022] For some embodiments, certain constraints may be observed while performing the multi-phased refresh technique to maintain a stable and robust memory system. For example, during the first phase 408 of refresh operation, a predefined number of “n” rows may berefreshed in a given bank that has received an activate command for another row in the bank. For timing purposes, the DRAM power system may be configured and the predetermined number “n” of rows chosen so that the row cycle time tRC for activated and refreshed rows are the same. Since normal refresh operations in standards-based DRAM devices generally prohibit parallel activate and refresh operations to a same bank, a count of rows refreshed during the first phase 408 of refresh operation may be tracked so that at the end of the first phase 408 of refresh, it is known how many refresh commands are required in the second phase 412 to fully refresh the DRAM device 104. Another constraint that may be employed during the first phase 408 of refresh involves prohibiting adjacent regions of a same bank from performing activate and refresh operations in parallel. Enforcing such a constraint may reduce the risk of bank conflicts.

[0023] FIG. 5 illustrates one specific embodiment of a table that identifies eligible regions within a bank that may be refreshed in response to the bank receiving an activate command to a selected region. The table assumes a hypothetical number of eight regions, numbered 1 through 8, assumes that consecutive-numbered regions correspond to topologically-adjacent regions within the bank, and also assumes a maximum constraint of refreshing only up to four regions in parallel with the activated region (a power-related constraint). As an example, should region 3 receive an activate command, such as at 502, the refresh control circuitry may direct refreshes to regions 5 through 8, as shown at 504.Regions 2 and 4 would not be eligible for refreshes due to their proximity to region 3.

[0024] Referring back to FIG. 4, for one embodiment, with the system configured in the multi-phase refresh mode of operation, and starting at the beginning of the first phase 408 of refresh, a given region, at 414, receives an activate command A, at 416, during a first row cycle time TRC timeslot 418. Regions of the same bank that are not adjacent to the activated region 414, such as at 420 and 422, are free to receive refresh commands R (generated on-chip by the corresponding per-region row control circuits 208) to refresh corresponding rows for the regions, such as at 424 and 426. As the rows are refreshed, the local per-region counters 212 track the refresh count for each of the regions, at 428 and 430.

[0025] With continued reference to FIG. 4, at the next row cycle time TRC timeslot, at 432, an activate command A, at 434, is issued to a different region, at 436, which may be different than the previous timeslot, with triggered refreshes R occurring in separate regions non-adjacent to the activated region, at 438 and 440. Note that for the lower region, at 442, the per-region refresh counter has incremented further to show the level of refreshes as compared to the other regions of the bank. This basic methodology, where an activate command A directed to a given region of a bank during the first phase of refresh triggers refresh operations to other regions of the bank in parallel with the activate, continues until the first phase of refresh ends, at 444.

[0026] With continuing reference to FIG. 4, following the end of the first phase 408 of refresh, the multi-phase refresh begins the second phase 412 of refresh, at 444. Since the DRAM on-chip main refresh control circuitry 302 (FIG. 3) generates the refresh commands for refreshes during the first phase 408 of refresh operation, an important part of the transition from the first phase 408 of refresh to the second phase 412 of refresh involves communicating an indication of the lowest per-region count value to the memory controller 102. Thus, as the per-region count values are determined and fed to the comparator circuitry 214 (FIG. 2), the lowest value, such as at 446, (in terms of the fewest number of rows refreshed during the first phase of refresh) is stored in the register circuitry 308 (FIG. 3). The memory controller 102 then accesses the stored value via, for example, a mode register read (MRR) command, and schedules sufficient refresh commands for dispatch to the DRAM device 104 to refresh, during the second phase 412 of refresh, the remaining rows that remain unrefreshed.

[0027] As noted above, the second phase of refresh 412 involves refreshing regions in response to refresh commands generated by the memory controller 102, and in a manner consistent with normal refresh schemes that generally preclude refreshes in parallel with activates being directed to a same bank. Thus, as can be seen at 448, should an activate command A be directed to a given region 450 of a bank, no other regions within that bank will receive refresh commands from the memory controller 102. Further, for some embodiments, where one or more rows, such as at 452 and 454, within respective regions, receive refresh commands during the second phase, but were previously refreshed during the first phase 408 (indicated by a dashed line), the per-region row control circuitry 208 will prevent the refresh operations from happening to save power. For some embodiments, the end of a first iteration of the second phase 412 of refresh results in all rows of the DRAM device 104 being refreshed within the refresh period.

[0028] For some embodiments, the duration of the second phase 412 of refresh is selected to be long enough to refresh all rows in a normal standards-based manner (such as by one of an all-bank refresh method, a fine-grained refresh method or a same-bank refresh method) to cover the possible situation where at least one bank is not refreshed at all in the first phase of refresh operation. For one specific embodiment, the duration of the second phase 412 is longer than the duration of the first phase 408. As an example, the first phase 408 may span an period of 25% of the refresh period, while the second phase 412 may span the remaining 75% of the refresh period. For some embodiments, it may be beneficial to apply multiple first phase 408 and second phase 412 periods as multiple refresh sequences, and iterate the sequences within a single refresh period. This is especially useful for situations where patterns are used to spread refreshes of a wordline between the beginning of the first phase 408 in one sequence, and the end of the second phase 412 in the next sequence.

[0029] FIGs. 6 and 7 illustrate respective flowcharts for one specific implementation of a multi-phase refresh technique that is consistent with the generic methodology outlined with respect to the timing chart of FIG. 4. Steps carried out by both the memory controller 102 and the DRAM device 104 for one embodiment of the first phase of refresh operation are shown in FIG. 6, while steps carried out by both the memory controller 102 and the DRAM device 104 for one embodiment of the second phase of refresh operation are shown in FIG. 7.

[0030] Referring now to FIG. 6, prior to operation, the DRAM device 104 is configured to fully refresh each active storage cell of the DRAM device 104 within a refresh period, such as an period of 64 ms, 32 ms, or 16 ms, depending on the DRAM device type. Additional configuration information that may be stored in the register circuitry 308 may involve whether the system will operate in the multi-phase refresh mode of operation, which is usually advantageous during heavily-loaded periods of operation, or in a “normal” or legacy refresh mode of operation. Such “normal” or legacy modes of refresh operation may involve standards-based refresh techniques such as all-bank refresh, fine-grained refresh, or samebank refresh, to name but a few. Additional information for the register circuitry 308 to store may involve the respective sub-period durations for the first phase and second phase of refresh operation, and whether multiple sequences of the first and second refresh phases are to be employed within a single refresh period.

[0031] Further referring to FIG. 6, as operation of the memory system 100 commences, once each new refresh period is initiated, at 602, a first phase of refresh operation begins with the memory controller 102 issuing a refresh start command, at 604, which is received by the DRAM device 104, at 606. In response to receiving the refresh start command, the per-region refresh counters 212 are reset to zero, at 608, while the memory controller 102 schedules a next access (to, for example, perform a write operation or a read operation) at 610. In association with the next access, the memory controller 102 then dispatches an activatecommand to a region within an addressed bank, at 612, which is received by the DRAM device 104, at 614.

[0032] Further referring to FIG. 6, while still in the first phase of refresh operation, after the DRAM device 104 receives the activate command, at 614, the main refresh control circuitry 302 determines the region of a given bank where the activate is directed, and the possible other non-adjacent regions of the bank where refresh operations may be directed, at 616. At 618, the main refresh control circuitry 302 executes the activate command, which triggers internal generation of refresh commands (by the local per-region row control circuits 208) corresponding to the refresh commands determined in step 616. As the refresh operations in the various regions are completed, the per-region refresh counters 212 increment, at 620. As the first refresh phase progresses in time, the DRAM device 104 may periodically update the lowest counter value for a given bank, at 622, and the lowest counter value on the die, at 624. These values may be used to set a starting value of a per-die refresh counter, at 626. As rows become refreshed during the first phase sub-period, refreshes in regions that have reached a maximum counter value are disabled, at 628.

[0033] With continued reference to FIG. 6, while the DRAM device 104 is performing refreshes to the various banks that have received activate commands, the memory controller 102 is free to dispatch non-activate commands to other banks of the DRAM, at 630, which are received and executed by the DRAM device 104, at 632. Once the duration of the first phase of refresh is reached, at 634, operation transitions to steps associated with the second phase of refresh operation, which are shown in FIG. 7 (which is coupled to FIG. 6 via bubble “A”).

[0034] As the system transitions to the second phase of refresh operation, and referring to FIG. 7, the memory controller 102 sends a mode register read MRR command, at 702, to readthe refresh counter information stored in the DRAM register circuitry 308. In response to receiving the MRR command, at 704, the DRAM device 104 transfers the lowest counter value information to the memory controller 102, at 706. Once the memory controller 102 receives the counter information from the DRAM device 104, at 708, it uses the information to determine how many refreshes were performed out of the total number of refreshes needed for the entire DRAM device 104. The memory controller 102 then sets the number of remaining refreshes to perform during the second phase of refresh, at 710. The memory controller 102 then schedules the refreshes, at 712, and dispatches associated refresh commands, at 714, to the DRAM device 104. Once the refresh commands are received by the DRAM device 104, they are executed using the per-die refresh counter, at 716. Additional accesses and commands may then be scheduled and sent to the DRAM device 104, at 712 and 714, until the duration of the refresh period is reached, at 718.

[0035] In some situations, as noted above, it may be desirable to divide the multi-phase refresh sequence into at least two sub-sequences, each sub-sequence including a first phase of refresh followed by a second phase of refresh, and then repeating the sequence within the refresh period. This may be beneficial for refresh patterns that are designed to spread refreshes of a wordline between the beginning of a first phase of refresh in a first refresh sequence, and at the end of a second phase of refresh in a subsequent sequence.

[0036] Those skilled in the art will appreciate the relatively straightforward circuitry for enabling parallel activate and refresh operations as described above. By employing a multiphased refresh mode that takes advantage of parallel or concurrent refresh and activate operations within a same bank, significant reductions in DRAM idle latency may be realized, leading to better DRAM performance.

[0037] When received within a computer system via one or more computer-readable media, such data and / or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

[0038] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present disclosure. In some instances, the terminology and symbols may imply specific details that are not required to practice aspects of the disclosure. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state ordischarged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “ / ” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘ < signal name >’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement.

[0039] Memory controller functionality may be disposed on a separate Input / Output (I / O) die along with the transmitter / receiver circuits that interface to the DRAM device. Such an I / O die may include other types of I / O interfaces, as well as one or more chiplet interfacesthat communicate with one or more respective CPU chiplet dies. The I / O die and CPU chiplet dies may be co-packaged together and coupled to one-another via a silicon interposer.

[0040] While aspects of the disclosure have been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS1. A dynamic random access memory (DRAM) device, comprising:an array of DRAM storage cells organized into multiple banks;refresh control circuitry to refresh the DRAM storage cells within a refresh period, the refresh control circuitry comprisingcircuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks;circuitry to generate, following the end of the first sub-period of the refresh period, a value indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh cycle time; andcircuitry to transmit the value off-chip to the memory controller.

2. The DRAM device of claim 1, further comprising:circuitry to receive, from the memory controller, during a second sub-period of the refresh period, a number of refresh commands that is based on the value.

3. The DRAM device of claim 2, wherein:the refresh control circuitry conditionally refreshes DRAM storage cells of the selected one of the multiple banks that were not refreshed during the first sub-period in response to the refresh commands.

4. The DRAM device of claim 3, wherein:the refresh control circuitry conditionally refreshes the DRAM storage cells of the selected one of the multiple banks based on whether the selected one of the multiple banks is activated by an activate command.

5. The DRAM device of claim 2, wherein:the first sub-period and the second sub-period collectively span at least a first half of the refresh cycle time.

6. The DRAM device of claim 1, wherein:the circuitry to refresh begins operation during the first sub-period of the refresh period in response to receipt of a phase start command from the memory controller.

7. The DRAM device of claim 1, wherein:during the first sub-period, the refresh controller operates in a self-refresh state; andwherein the circuitry to transmit the value off-chip to the memory controller carries out the transmission of the value in response to the refresh controller exiting the self-refresh state.

8. The DRAM device of claim 1, further comprising:register storage to store the value; andwherein the circuitry to transmit the value off-chip to the memory controller is responsive to a register command from the memory controller to access the value from the register storage and to transmit the value to the memory controller.

9. A method of operating a dynamic random access memory (DRAM) device, the memory device comprising an array of DRAM storage cells organized into multiple banks, the method comprising:refreshing, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks;generating, following the end of the first sub-period of the refresh period, a value indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of storage cells within a remaining period of the refresh period; andtransmitting the value off-chip to the memory controller.

10. The method of claim 9, further comprising:receiving, from the memory controller, during a second sub-period of the refresh period, a number of refresh commands that is based on the value.

11. The method of claim 10, wherein:conditionally refreshing DRAM storage cells of the selected one of the multiple banks that were not refreshed during the first sub-period in response to the refresh commands.

12. The method of claim 11, wherein:the conditionally refreshing the DRAM storage cells is based on whether the selected one of the multiple banks is activated by an activate command.

13. The method of claim 10, wherein:the first sub-period and the second sub-period collectively span at least a first half of the refresh period.

14. The method of claim 9, wherein:the refreshing begins during the first sub-period of the refresh period in response to receipt of a phase start command from the memory controller.

15. The method of claim 9, further comprising:during the first sub-period, the refreshing comprises self-refreshing by a refresh controller in a self-refresh state; andwherein the transmitting of the value is carried out in response to the refresh controller exiting the self-refresh state.

16. An integrated circuit (IC) dynamic random access memory (DRAM) chip, comprising:an array of DRAM storage cells organized into multiple banks, each of the multiple banks organized into multiple regions;refresh control circuitry to refresh the DRAM storage cells within a refresh period, the refresh control circuitry comprisingcircuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to a selected region of the selected one of the multiple banks, the at least one row being refreshed residing in at least one region that is not the selected region associated with the activate command;circuitry to generate, following the end of the first sub-period of the refresh period, a value indicating a remaining number of refresh operations to refresh aremaining number of unrefreshed storage cells of the array of storage cells within a remaining period of the refresh period;circuitry to transmit the value off-chip to the memory controller; and circuitry to receive, from the memory controller, during a second sub-period of the refresh period, a number of refresh commands that is based on the value.

17. The IC DRAM chip of claim 16, further comprising:register storage to store the value; andwherein the circuitry to transmit the value off-chip to the memory controller is responsive to a register command from the memory controller to access the value from the register storage and to transmit the value to the memory controller.

18. The IC DRAM chip of claim 16, wherein:the at least one row being refreshed resides in at least one region that is not the selected region associated with the activate command.

19. The IC DRAM chip of claim 16, wherein:the first sub-period and the second sub-period collectively span at least a first half of the refresh period.

20. The IC DRAM chip of claim 16, wherein:the circuitry to refresh begins operation during the first sub-period of the refresh period in response to receipt of a phase start command from the memory controller.

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