Semiconductor package and redistribution processing method for semiconductor package

Abstract

A semiconductor package and a redistribution processing method including same are disclosed. The redistribution processing method according to one embodiment of the present disclosure may comprise the steps of: using a UV laser to drill a first metal layer provided on an insulating layer; using the UV laser to etch a portion of the insulating layer provided below the first metal layer; and using plasma to etch the remaining portion of the insulating layer.

Description

Semiconductor package and method for performing a rewiring process of a semiconductor package

[0001] The present disclosure relates to a semiconductor package and a method for performing a rewiring process of a semiconductor package. More specifically, the invention relates to a semiconductor package and a method for performing a rewiring process of a semiconductor package, wherein a first metal layer provided on top of an insulating layer is drilled and a portion of the insulating layer is etched using a UV laser, and a remaining portion of the insulating layer is etched using plasma.

[0002] With the advancement of semiconductor integration technology and the development of new electronic devices, the demand for new high-performance semiconductor systems is increasing. In the case of system semiconductors, multiple semiconductor devices and other electronic components are integrated within a single package. To efficiently produce such system semiconductors, various technical elements are required, including integration technology that optimizes multiple chips into a single space, wiring design technology that minimizes electrical wiring between components, and stacking technology between the substrate and electronic components.

[0003] As semiconductor chips become miniaturized, there are limitations to direct electrical connections with other components or substrates; therefore, package substrates are used to establish electrical connections with external circuit boards. Recently, there has been an increasing trend of using silicon of the same material as the package substrate for semiconductor chips. In this case, via technology, which utilizes electrical pathways penetrating the silicon substrate, is primarily used. Through-vias are advantageous in that they minimize the signal length of the semiconductor package while leveraging the benefits of the silicon substrate, making them suitable for realizing high-performance, multi-functional semiconductor systems.

[0004] Recently, semiconductor packages are being implemented to apply integrated circuit-related chips with various functions in a form suitable for electronic products. Generally, semiconductor packages typically involve mounting semiconductor chips on a printed circuit board and electrically connecting them using bonding wires and bumps.

[0005] Meanwhile, the formation of a Redistributed Layer (RDL) may be required to connect the semiconductor package to external terminals. The redistributed layer may include conductive metal lines having a specific pattern. Although laser drilling is generally performed to carry out the redistribution (RDL) process, CO2 drilling damages the underlying metal layer, and there are difficulties in processing by miniaturizing the drilling or etching size.

[0006] The present disclosure aims to minimize physical damage to a metal layer or a lower metal layer provided on an insulating layer during a rewiring process, and to minimize physical damage to a metal pad connected to the metal layer.

[0007] The present disclosure aims to provide a semiconductor package structure comprising an insulating layer provided on a substrate, a first metal layer provided on the insulating layer, a second metal layer provided below the insulating layer, and a via structure penetrating the first metal layer and the insulating layer in a vertical direction of the substrate.

[0008] The problems that this disclosure aims to solve are not limited to those described above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below.

[0009] A method for performing a rewiring process according to one embodiment of the present disclosure may include: a step of drilling a first metal layer provided on top of an insulating layer using a UV laser; a step of etching a portion of an insulating layer provided on bottom of the first metal layer using the UV laser; and a step of etching a remaining portion of the insulating layer using plasma.

[0010] In some embodiments, the remaining portion may correspond to the remaining area that is not etched during the step of etching a portion of the insulating layer.

[0011] In some embodiments, the drilling step may involve irradiating a UV laser multiple times, and the number of times may be 5 or more and 20 or less.

[0012] In some embodiments, some of the insulating layer may be 10% to 90% of the entire insulating layer.

[0013] In some embodiments, the insulating layer may have a second metal layer provided at the bottom.

[0014] In some embodiments, the second metal layer may be a wiring layer or a metal layer for wiring.

[0015] In some embodiments, the second metal layer may be electrically connected to a metal pad.

[0016] In some embodiments, the UV laser may include at least one of an excimer laser, a solid-state UV laser, a fiber UV laser, and a femtosecond UV laser.

[0017] In some embodiments, the wavelength of the UV laser may be 200 nm to 400 nm.

[0018] In some embodiments, the plasma may include at least one of an oxidizing plasma, a fluoride plasma, and a chlorine plasma.

[0019] In some embodiments, the first metal layer may include a conductive material, and the conductive material may include copper, aluminum, or an alloy thereof.

[0020] In some embodiments, the insulating layer may include at least one of an organic insulating material and an inorganic insulating material.

[0021] A semiconductor package according to one embodiment of the present disclosure may include an insulating layer provided on a substrate; a first metal layer provided on the insulating layer; a second metal layer provided below the insulating layer; and a via structure penetrating the first metal layer and the insulating layer in a vertical direction of the substrate.

[0022] In some embodiments, the second metal layer may be a wiring layer or a metal layer for wiring.

[0023] In some embodiments, the second metal layer may be electrically connected to a metal pad.

[0024] In some embodiments, the first metal layer may include a conductive material, and the conductive material may include copper, aluminum, or an alloy thereof.

[0025] In some embodiments, the insulating layer may include at least one of an organic insulating material and an inorganic insulating material.

[0026] In some embodiments, the substrate may include an insulating material, and the insulating material may include at least one of FR4 (fiberglass-reinforced epoxy laminate), BT (Bismaleimide-Triazine), ceramic, and polyimide.

[0027] A method for performing a rewiring process according to an exemplary embodiment of the present disclosure can minimize physical damage to a second metal layer or a lower metal layer provided on a substrate and minimize physical damage to a metal pad connected to the second metal layer by drilling a first metal layer provided on top of an insulating layer using a UV laser, etching a portion of an insulating layer provided on a substrate using a UV laser, and etching a remaining portion of an insulating layer using plasma.

[0028] In addition, a method for performing a rewiring process according to an exemplary embodiment of the present disclosure may provide a semiconductor package structure comprising an insulating layer provided on a substrate, a first metal layer provided on the insulating layer, a second metal layer provided below the insulating layer, and a via structure penetrating the first metal layer and the insulating layer in the vertical direction of the substrate.

[0029] The effects according to the present disclosure are not limited to those described above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below.

[0030] FIG. 1 is a cross-sectional view of a semiconductor package including a redistribution layer manufactured according to one embodiment of the present invention.

[0031] FIGS. 2a and 2b are processes for explaining a method for manufacturing a semiconductor package including a redistribution layer according to an embodiment of the present invention.

[0032] FIG. 3 is a schematic flowchart illustrating a method for manufacturing a redistribution layer according to exemplary embodiments.

[0033] FIGS. 4a to 4c are cross-sectional views illustrating the step-by-step shapes of a method for manufacturing a redistribution layer according to an exemplary embodiment.

[0034] Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the contents described in the attached drawings. However, the present invention is not limited or restricted by exemplary embodiments. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall be used in a meaning that is commonly understood by those skilled in the art to which this disclosure belongs, but this may vary depending on the intent of those skilled in the art, case law, the emergence of new technology, etc.

[0035] Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. In certain cases, terms have been selected at the applicant's discretion, and in such cases, their meanings will be described in detail in the relevant explanatory sections. Accordingly, terms used in this disclosure should be defined not merely by their names, but based on their meanings and the content throughout this disclosure.

[0036] Throughout this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, the singular form used in this specification includes the plural form unless specifically stated otherwise. Additionally, the expression "at least one of a, b, and / or c" as used throughout this specification may encompass 'a alone', 'b alone', 'c alone', 'a and b', 'a and c', 'b and c', or 'a, b, and c all'.

[0037] Meanwhile, terms such as "first and / or second" used in this specification may be used to describe various components, but they are used solely for the purpose of distinguishing one component from another and are not intended to limit the scope to the components referred to by such terms. For example, without departing from the scope of the present invention, the first component may be named the second component, and the second component may also be named the first component.

[0038] Additionally, terms such as “…part,” “…module,” etc., as described in this specification refer to a unit that processes at least one function or operation, which may be implemented in hardware or software, or a combination of hardware and software. Furthermore, embodiments of this disclosure may be represented in this specification by functional block configurations and various processing steps. These functional blocks may be implemented by various numbers of hardware and / or software configurations that execute specific functions. For example, embodiments of this disclosure may employ integrated circuit configurations such as memory, processing, logic, look-up tables, etc., which can execute various functions under the control of one or more microprocessors or other control devices.

[0039] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In describing the embodiments, technical details that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to ensure that the essence of the present invention is conveyed more clearly without obscuring it by omitting unnecessary explanations. For the same reason, some components in the accompanying drawings may be exaggerated, omitted, or schematically depicted. Furthermore, the size of each component does not entirely reflect its actual size. Throughout this specification, the same reference numerals may refer to the same or corresponding components.

[0040]

[0041] FIG. 1 is a cross-sectional view of a semiconductor package including a redistribution layer manufactured according to one embodiment of the present invention.

[0042] Referring to FIG. 1, a semiconductor package (100) according to one embodiment of the present invention may include a wiring board (110) having a second metal layer (101, 102) formed on its upper and lower surfaces, an insulating layer (120) encapsulating the wiring board (110), a through encapsulation via (TEV) (130) penetrating the interior of the insulating layer (120), a redistribution seed layer (140) formed on a first surface (120a) of the insulating layer (120), a redistribution layer (150) formed on the redistribution seed layer (140), a first semiconductor chip (160) electrically connected to the redistribution layer (150), and a second semiconductor chip (170) stacked on the first semiconductor chip (160) and electrically connected to the redistribution layer (150). In some embodiments, the second metal layer (101, 102) may be a metal pad.

[0043] The insulating layer (120) can encapsulate the wiring board (110) and through vias (130) can be formed inside. In some embodiments, the insulating layer (120) may be polyimide (PI), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (Bismaleimide Triazine), phenolic resin, epoxy, silicone, oxide film (SiO2), nitride film (Si3N4), and combinations thereof.

[0044] The through-via (130) may be a metal or a metal post. The through-via (130) may be formed on a second metal layer (101) formed on the upper surface of the wiring board (110) and may be electrically connected to the wiring board (110). One end of the through-via (130) may be formed to be exposed to the upper surface (120a) of the insulating layer (120), and the other end of the through-via (130) may be formed to be electrically connected to the second metal layer (101) exposed to the upper surface (120b) of the insulating layer (120). In some embodiments, the through via (130) may be Ti / Cu, TiW / Ni, Ti / Ni, TiW / NiV, Cr / Cu, Cr / Ni, Cr / NiV, Ti / Cu / Ni, TiW / Cu / Ni, TiW / Cu / NiV, Cr / Cu / NiV and combinations thereof.

[0045] The redistribution seed layer (140) is a seed layer for forming a redistribution layer (150) and is formed on a first surface (120a) of an insulating layer (120) and can be electrically connected to one end of a through-via (130) exposed above the first surface (120a). The redistribution seed layer (140) can be electrically connected to one end of a through-via (130) exposed above the first surface (120a).

[0046] The redistribution layer (150) can be formed on the redistribution seed layer (140) and can be electrically connected to the redistribution seed layer (140). The redistribution layer (150) can serve to redistribute the electrical connection path between the input / output pads of the semiconductor chips (160, 170) and the bumps (not shown), regardless of the position of the input / output pads of the semiconductor chips (160, 170). Additionally, the redistribution layer (150) can be formed by drilling the first metal layer (10 in FIG. 4a) provided on the upper part of the insulating layer (120).

[0047]

[0048] Hereinafter, a process for describing a method for manufacturing a semiconductor package including a redistribution layer according to an embodiment of the present invention is described with reference to FIGS. 2a and 2b. FIGS. 2a and 2b may be described with reference to FIG. 1 described above.

[0049] FIGS. 2a and 2b are process cross-sectional views for explaining a method for manufacturing a semiconductor package including a redistribution layer according to an embodiment of the present invention.

[0050] Referring to FIG. 2a, a second metal layer (101, 102) may be formed on the upper and lower surfaces of the wiring board (110). A wiring pattern (not shown) and a second metal layer (101, 102) may be formed on the wiring board (110), and although not shown in FIG. 2a, via contacts that electrically connect the wiring patterns on the upper and lower surfaces may be formed on the wiring board (110). The second metal layer (101, 102) may include a metal pad.

[0051] Next, with reference to FIG. 2b, a process for forming a redistribution layer (150) is described. The redistribution layer (150) is electrically connected to a second metal layer (101) formed on the upper surface of a wiring board (110), and can provide metal wiring for semiconductor chips that are electrically connected to the redistribution layer (150) by mounting or wire bonding in a subsequent process.

[0052] The redistribution layer (150) may refer to a metal wiring line extending outward from the bonding pads to allow input / output terminals to be attached at wider intervals, thereby resolving the issue where input / output terminals, such as solder balls, come into contact with each other and cause an electrical short circuit when they are attached to the bonding pads of each chip that have a fine pitch. At this time, the redistribution layer (150) can be formed by performing a plating process on the insulating layer (120) formed on the wiring board (110).

[0053]

[0054] FIG. 3 is a schematic flowchart for explaining a method for performing a rewiring process according to an exemplary embodiment of the present disclosure.

[0055] FIG. 3 can be described with reference to FIG. 1 and FIG. 2 described above. Referring to FIG. 3, a method for performing a redistribution process (S100) according to an exemplary embodiment of the present disclosure may include the step of forming a first metal layer on top of an insulating layer (S110), the step of drilling the first metal layer using a UV laser (S120), the step of etching a portion of the insulating layer using a UV laser (S130), and the step of etching a remaining portion of the insulating layer using plasma (S140).

[0056] FIG. 3 illustrates steps S110 to S140 being performed sequentially, but is not limited thereto; some steps may be merged and performed simultaneously, some steps may be omitted, or new steps may be added.

[0057] In step S110, a second metal layer (101) may be formed on a substrate or wiring board (110), and an insulating layer (120) and a first metal layer may be formed on the second metal layer (101).

[0058] The insulating layer (120) can encapsulate the wiring board (110) and may be polyimide (PI), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (Bismaleimide Triazine), phenolic resin, epoxy, silicone, oxide film (SiO2), nitride film (Si3N4), and combinations thereof.

[0059] In step S120, a UV laser may be irradiated onto the first metal layer to drill or etch a portion of the first metal layer and the insulating layer (120). Unlike commonly used CO2 lasers, the UV laser may be suitable for micro-processing and may be suitable for processing metals or metal layers such as Cu plates. Additionally, the UV laser may be suitable for fine processing or hole formation, such as forming pores or holes with a size of less than 50 µm through laser irradiation. The UV laser may, for example, include at least one of an excimer laser, a solid-state UV laser, a fiber UV laser, and a femtosecond UV laser, but is not necessarily limited thereto and may further include various types of UV lasers used in semiconductor packaging processes. When drilling by irradiating with a UV laser, processing can be performed by adjusting the hole size without a separate mask. Additionally, the wavelength of the UV laser may be 200 nm or longer and 400 nm or shorter.

[0060] In step S130, a UV laser can be irradiated onto the insulating layer (120) for the reasons and effects described above to etch a portion of the insulating layer.

[0061] A portion of the insulating layer may be 10% to 90% of the total insulating layer. A residue or impurity layer remaining after etching a portion of the insulating layer may be referred to as a smear in this disclosure, which will be described later with reference to FIG. 4b.

[0062] When step S130 is completed, a portion of the redistribution layer (150), the second metal layer (101), or the metal pad and insulating layer may remain. At this time, if the entire insulating layer is etched by irradiating with a UV laser and a portion of the second metal layer (101) is irradiated with a UV laser, physical and chemical damage to the second metal layer or the metal pad may occur, which may reduce the yield of the semiconductor package process. Therefore, in step S130, a portion of the insulating layer may be etched using a UV laser.

[0063] In step S140, the remaining portion of the insulating layer can be etched using plasma. When the smear, which is the remaining portion of the insulating layer, is etched using plasma, physical damage to the second metal layer or metal pad can be prevented. Additionally, when plasma is used, the etch profile, which is the cross-sectional shape of the etched pattern, can be finely controlled. The plasma used in step S140 may include at least one of oxidizing plasma, fluoride plasma, and chlorine plasma, but is not necessarily limited thereto.

[0064] As described above with reference to FIG. 3, a method for performing a rewiring process (S100) according to an exemplary embodiment of the present disclosure can perform a UV laser-plasma hybrid rewiring process to form a rewiring layer of a semiconductor package structure by utilizing both a UV laser and plasma.

[0065]

[0066] FIGS. 4a to 4c are cross-sectional views illustrating the step-by-step appearance of a method for manufacturing a redistribution layer according to an exemplary embodiment.

[0067] FIGS. 4a to 4c can be explained with reference to FIGS. 1 to 3 described above.

[0068] Referring to FIG. 4a, a wiring board (110), a second metal layer (101), an insulating layer (120), and a first metal layer (10) are shown.

[0069] The wiring board (110) may include an insulating material, and the insulating material may include at least one of FR4 (fiberglass-reinforced epoxy laminate), BT (Bismaleimide-Triazine), ceramic, and polyimide. The first metal layer (10) may include a metal material and may include Cu and Al, but is not necessarily limited thereto. The second metal layer (101) may be a metal pad as described above and may be a Cu plate.

[0070]

[0071] Referring to FIG. 4b, a wiring board (110), a second metal layer (101), an insulating layer (120), a first metal layer (10), and a smear are shown.

[0072] Smear generally refers to uneven residue or stains occurring on the surface of wiring or layer structures, and may be residues generated during drilling or etching processes. Specifically, when drilling or etching is performed to form fine wiring during a rewiring process, if the generated residue is not removed, stains or uneven layers may remain on the surface, causing smear.

[0073] As described above with reference to FIGS. 2a and 2b, the residue remaining after etching a portion of the insulating layer (120) using a UV laser can correspond to the smear of FIG. 4b.

[0074]

[0075] Referring to FIG. 4c, smear can be removed through a plasma etching process according to an embodiment of the present invention. Referring to step S140 of FIG. 3, a redistribution layer of a semiconductor package structure can be formed by utilizing both a UV laser and plasma; in other words, a redistribution layer can be formed through a UV laser-plasma hybrid redistribution process that utilizes both a UV laser and plasma.

[0076]

[0077] Meanwhile, the embodiments disclosed in this specification may be implemented in the form of a recording medium that stores instructions executable by a computer. The instructions may be stored in the form of program code and, when executed by a processor, may generate a program module to perform the operations of the disclosed embodiments. The recording medium may be implemented as a computer-readable recording medium. A computer-readable recording medium may include all types of recording media that store instructions decipherable by a computer. Examples include ROM, RAM, magnetic tape, magnetic disk, flash memory, optical data storage devices, etc. A computer-readable recording medium may be distributed and executed by networked computer systems.

[0078] The above descriptions are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present disclosure will include technologies that can be easily modified and implemented using the embodiments described above. Accordingly, the scope of the present disclosure should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of the present disclosure.

Claims

1. A step of drilling a first metal layer provided on top of an insulating layer using a UV laser; A step of etching a portion of the insulating layer provided below the first metal layer using the above UV laser; and A method for performing a redistribution layer process comprising the step of etching the remaining portion of the insulating layer using plasma.

2. In Paragraph 1, The above remaining portion is, Corresponding to the remaining area that is not etched in the step of etching a portion of the above insulating layer, Method for performing the rewiring process.

3. In Paragraph 1, The drilling step is, A UV laser is irradiated multiple times, wherein the multiple times are 5 to 20. Method for performing the rewiring process.

4. In Paragraph 1, A method for performing a redistribution process in which a portion of the insulating layer is 10% to 90% of the entire insulating layer.

5. In Paragraph 1, The above insulating layer has a second metal layer provided at the bottom, Method for performing the rewiring process.

6. In Paragraph 5, The above second metal layer is a wiring layer or a metal layer for wiring, Method for performing the rewiring process.

7. In Paragraph 5, The second metal layer above is electrically connected to a metal pad, Method for performing the rewiring process.

8. In Paragraph 1, A method for performing a rewiring process in which the above UV laser comprises at least one of an excimer laser, a solid-state UV laser, a fiber UV laser, and a femtosecond UV laser.

9. In Paragraph 1, The wavelength of the above UV laser is 200 nm to 400 nm, Method for performing the rewiring process.

10. In Paragraph 1, The above plasma includes at least one of an oxidizing plasma, a fluoride plasma, and a chlorine plasma. Method for performing the rewiring process.

11. In Paragraph 1, The first metal layer above includes a conductive material, and A method for performing a redistribution process comprising the above conductive material, copper, aluminum, or an alloy thereof.

12. In Paragraph 1, A method for performing a redistribution process in which the insulating layer comprises polyimide (PI), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (Bismaleimide Triazine), phenolic resin, epoxy, silicone, oxide film (SiO2), nitride film (Si3N4), and combinations thereof.

13. An insulating layer provided on a substrate; A first metal layer provided on the insulating layer above; A second metal layer provided below the insulating layer; and A semiconductor package comprising a via structure penetrating the first metal layer and the insulating layer in the vertical direction of the substrate.

14. In Paragraph 13, The above second metal layer is a wiring layer or a metal layer for wiring, Semiconductor package.

15. In Paragraph 13, The second metal layer above is electrically connected to a metal pad, Semiconductor package.

16. In Paragraph 13, The first metal layer above includes a conductive material, and The above conductive material comprises copper, aluminum, or an alloy thereof. Semiconductor package.

17. In Paragraph 13, The insulating layer comprises polyimide (PI), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (Bismaleimide Triazine), phenolic resin, epoxy, silicone, oxide film (SiO2), nitride film (Si3N4), and combinations thereof. Semiconductor package.

18. In Paragraph 13, The above substrate includes an insulating material, and The above insulating material comprises at least one of FR4 (fiberglass-reinforced epoxy laminate), BT (Bismaleimide-Triazine), ceramic, and polyimide, Semiconductor package.

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