Wafer edge management in wafer stack

Abstract

Systems and methods for wafer edge management in a wafer stack are disclosed. In one aspect, when two wafers are stacked as part of the creation of a three-dimensional wafer stack, there may be a void formed as a function of wafer edge bevels and / or thin films thickness variation across the wafers and / or variation in wafer thickness proximate the edge of the wafer. This void is filled with a thin-film layer. The thin-film material provides additional structural support for the edge area and may be useful as an etch-stop material or the like. The additional structural support is useful during polishing or grinding steps, which subject the wafer stack to mechanical strain. Still further applications of the present disclosure may be found in situations where wafers are stacked (e.g., in packaging and dummy earner wafers).

Description

Ref. No. P241606-WO-UTL 1WAFER EDGE MANAGEMENT IN WAFER STACKPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 722,646, filed on November 20, 2024, and entitled “WAFER EDGE MANAGEMENT IN WAFER STACK,” the contents of which are incorporated herein by reference in their entirety.BACKGROUNDI. Field of the Disclosure

[0002] The technology of the disclosure generally relates to manufacturing wafer stacks for three-dimensional integrated circuits (3DIC) and three-dimensional (3D) packaging, and particularly to compensating for edge variations as wafers are stacked.IL Background

[0003] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices mean that mobile communication devices have evolved from mere communication tools into sophisticated mobile entertainment centers, enabling enhanced user experiences. With the advent of the myriad functions available on such devices, there has been increased pressure to improve processing capabilities while still conforming to ever-shrinking form factors. This pressure extends to the circuitry used to transmit and receive signals wirelessly. One way to preserve real estate within the form factor is to stack circuits vertically in a three-dimensional integrated circuit (3DIC) assembled from multiple wafers. The use of 3DICs in mobile communication devices provides room for innovation.SUMMARY

[0004] Aspects disclosed in the detailed description include systems and methods for wafer edge management in a wafer stack. In particular, when two wafers are stacked as part of the creation of a three-dimensional integrated circuit (3DIC) and / or a three- dimensional (3D) package, generically referred to herein as a 3D wafer stack (orWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 2 sometimes just wafer stack), there may be a void formed as a function of wafer edge bevels and / or thin films thickness variation across the wafers and / or variation in wafer thickness proximate the edge of the wafer. This void is filled with a thin-film layer. The thin-film material provides additional structural support for the edge area and may be useful as an etch-stop material or the like. The additional structural support is useful during polishing or grinding, which places mechanical strains on the wafer stack. Unchecked, these strains may result in the fracturing or delamination of the wafer stack, potentially ruining the wafer stack. The thin-fdm layer and its structural support help avoid such unwelcome results. Still further applications of the present disclosure may be found in situations where wafers are stacked (e.g., in packaging and dummy carrier wafers).

[0005] In this regard, in one aspect, a 3D wafer stack is disclosed. The 3D wafer stack includes a first wafer comprising a first circuit and a first bonding surface having a first beveled edge, a second wafer comprising a beveled lateral edge, a second bonding surface, the second bonding surface bonded to the first bonding surface extending onto the beveled lateral edge to form a second beveled edge, thereby forming a gap between the first beveled edge and the second beveled edge, and a second circuit electrically coupled to the first circuit through the first bonding surface. The 3D wafer stack also includes a thin-film material positioned in the gap between the first beveled edge and the second beveled edge, such that there is structural support between the first beveled edge and the second beveled edge.

[0006] In another aspect, a method of shaping a 3D wafer stack is disclosed. The method includes filling a void between wafers in the 3D wafer stack to provide mechanical support for a top wafer and removing, by grinding or polishing, a top substrate from the top wafer without edge trimming the top wafer.

[0007] In another aspect, a method of forming a 3D wafer stack is disclosed. The method includes bonding a first wafer to a second wafer, thereby forming a void between the first and second wafers at a lateral edge and filling the void with a thin-film material.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a side elevational cross-sectional view of a conventional wafer with multiple dice therein;

[0009] Figure 2 is a side elevational cross-sectional view of a conventional wafer stack with edges of the wafers having variations in thickness;WT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 3

[0010] Figures 3A-3C are side elevational cross-sectional views of the wafer stack of Figure 2 subjected to an edge trimming process;

[0011] Figure 4 is a flowchart illustrating an exemplary process for wafer edge management according to aspects of the present disclosure;

[0012] Figures 5A-5E are side elevational cross-sectional views of a wafer stack going through the process of Figure 4;

[0013] Figures 6A-6D are side elevational cross-sectional views of a wafer edge of the wafer stack going through the process of Figure 4;

[0014] Figure 7 provides a side elevational cross-sectional view of a package formed from the process of Figure 4, ready for singulation; and

[0015] Figure 8 is a block diagram of a mobile communication device, which may include a circuit instantiated in a wafer stack made according to the process of Figure 4, according to the present disclosure.DETAILED DESCRIPTION

[0016] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0017] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms arc only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed as a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0018] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will beWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 4 understood that when an element, such as a layer, region, or substrate, is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0019] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] In keeping with the above admonition regarding definitions, the present disclosure uses the term transceiver in a broad sense. Current industry literature uses “transceiver” in two ways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industryWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 5 literature, treats the circuit positioned between a baseband processor and a power amplifier as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like, but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevant to distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used respectively.

[0023] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within ten percent (10%).

[0024] Aspects disclosed in the detailed description include systems and methods for wafer edge management in a wafer stack. In particular, when two wafers are stacked as part of the creation of a three-dimensional integrated circuit (3DIC) and / or a three- dimensional (3D) package, generically referred to as a 3D wafer stack (or sometimes just a wafer stack), there may be a void formed as a function of wafer edge bevels and / or thin films thickness variation across the wafers and / or variation in wafer thickness proximate the edge of the wafer. This void is filled with a thin-film layer. The thin-film material provides additional structural support for the edge area and may be useful as an etch-stop material or the like. The additional structural support is useful during polishing or grinding steps, which subject the wafer stack to mechanical strain. Unchecked, these strains may result in fracturing or delamination of the wafer stack, potentially ruining it. The thin-film layer and its structural support help avoid such unwelcome results. Still further applications of the present disclosure may be found in situations where wafers are stacked (e.g., in packaging and dummy carrier wafers).

[0025] Before addressing aspects of the present disclosure, a brief overview of wafer formation and conventional wafer stack formation is provided with reference to Figures 1-3C. A discussion of aspects of the present disclosure begins below with reference to Figure 4.

[0026] In this regard, Figure 1 illustrates a conventional wafer 100 with circuits 102(l)-102(N) therein. The circuits 102(l)-102(N) are identical and intended to be cut into separate dice, as is well understood. The circuits 102(l)-102(N) are formed on a substrate 104 through any conventional means. In an exemplary aspect, the substrate 104 includes metallization layers 106. Alternatively, the metallization layers 106 are positioned on top of the substrate 104, with the circuits 102(1 )- 102(N). A top surface 108 (sometimes called a face) (in the z-axis) may be formed by a bond interface layer 110. In an exemplary aspect, the bond interface layer may be an oxide such as silicon dioxide orWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 6 the like. In an exemplary aspect, the circuits 102(1)- 102(N) are formed in this bond interface layer 110. Alternatively, and more likely, the circuits 102(1)- 102(N) are in a separate layer (not shown explicitly) beneath (in the z-axis) the bond interface layer 110 (either in the substrate 104 or on a top surface of the substrate 104).

[0027] In making a 3D wafer stack and, more particularly, a 3DIC, two wafers 100 are stacked in a face-to-face arrangement (although the circuits 102(l)-102(N) may differ from a bottom wafer 100 and a top wafer 100) and bonded to one another, such as by bonding respective bond interface layers 110. Additional process steps are performed before singulating to produce the actual 3DIC, which has two layers of circuits.

[0028] As shown in Figure 2, in the center region 202 of a package 200, which is an example of a 3D wafer stack (and also happens to be a 3DIC), formed by two wafers 100A, 100B, the package 200 has a uniform thickness (in the z-axis), and the top wafer 100A bonds to the wafer 100B through bond interface layers 110A, HOB. However, edge regions 204A, 204B may have a non-uniform thickness compared to the rest of their respective wafers 100A, 100B. That is, there may be a thinning, roll-off, or bevel 206A, 206B in the edge regions 204A, 204B. Thus, when two such non-uniform wafers 100 A, 100B are stacked, this can create a void 208 where the top wafer 100A does not touch the bottom wafer 100B for some lateral distance. As wafer 100 is circular, the void 208 forms an annulus in the x-y plane.

[0029] In the abstract, such a void 208 is not generally problematic. However, in practice, the void 208 is problematic. That is, the package 200 is typically subjected to a chemical-mechanical polish (CMP) or grinding process, which applies high levels of force in the z-axis direction. When such force is applied in the edge regions 204A, 204B, the absence of structural support in the void 208 causes flexing of the wafers 100 A, 100B. This flexing may cause delamination or fracturing of the wafers 100A, 100B, thereby ruining the package 200 before it can be singulated.

[0030] While the above discussion explicitly refers to wafers 100A, 100B, which have circuits 102(1 )- 102(N) in each wafer 100A, 100B, there are other 3D packages that do not have circuits in each wafer. For example, there may be instances where a wafer is bonded to a dummy carrier wafer, and the void between the wafers remains present. In addition to dummy wafers, there may also be other situations where there are two wafers that are bonded and do not have electrical connections therebetween. Further, while two wafers 100A, 100B have been discussed, it should be appreciated that there are packages that have more than two wafers and have voids at each wafer junction. Thus, there areWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 7 myriad situations where a void is present at an edge of bonded wafers. Still further, 3D wafer stacks also include packages or structures such as microfluidic devices, microelectromechanical systems (MEMS), glass devices, 3D interconnect layers, or the like.

[0031] The traditional approach to avoiding this delamination or fracturing is “edge trimming,” where the void is essentially cut out of the package, as illustrated in Figures 3A-3C. Specifically, as shown in Figure 3A, package 300, comparable to package 200, has an additional thin-film layer 302 positioned on an exterior surface of the substrate 104B. Note that while the thin-film layer 302 does extend partially into the void 208, there remains a gap 304 between the bond interface layers 110A, HOB, and generally between the wafers 100A, 100B. The package 300 is then flipped on the x-y plane, and the edge portion 306 is trimmed through the substrate 104A, through the bond interface layers 110A, 110B, and into the substrate 104B, as shown in Figure 3B. When grinding and / or CMP is performed to remove the substrate 104A, the entire x-y plane of the surface being polished is supported, and no flex-induced strain is created. This leaves the package 300 with a small shoulder region 308, as shown in Figure 3C.

[0032] While edge trimming does avoid delamination or fracturing of the package 300, there are downsides. Initially, assuming a wafer diameter (in the x-y plane) of 200 millimeters, the small shoulder region has a lateral dimension (e.g., in the x-y plane) of approximately 4-5 millimeters. This results in the loss of some portion of the circuits 102(l)-102(N) in each wafer 100A, 100B. For example, if the circuit size is approximately 400 microns by 400 microns, approximately 8000 circuits are lost in the trim. This number (i.e., 8000) goes up or down depending on circuit size, and circuit sizes range from approximately 5 mm by 5 mm down to 200 microns by 200 microns. Still further, by creating the shoulder region 308, the package 300 no longer has a uniform top surface 310, which complicates later processing steps that occur before singulation. Process complications include but are not limited to difficulties with wafer handling, lithography resist coating on wafer surface, thin film delamination from edges of the wafer, where such delamination creates defects on wafers and reduces the final yield.

[0033] Exemplary aspects of the present disclosure contemplate extending the application of the thin-film layer to fill the void 208 such that the thin-film layer provides sufficient structural support that risk of delamination or fracturing during grinding and / or CMP is reduced to acceptable levels. This avoids having to use edge trimming and theWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 8 appurtenant loss of circuitry and complicated topologies. Moreover, it reduces one process step and eliminates the costs associated with it.

[0034] In this regard, Figure 4 provides a flowchart of a process 400 for forming a package according to aspects of the present disclosure, with additional reference to Figures 5A-6D showing intermediate steps and Figure 7 showing a completed package 700 ready for singulation. While the discussion below again contemplates wafers having circuitry in both wafers, the present disclosure is not so limited. That is, the present disclosure can be applied to 3D packages that are more than two wafers thick and / or 3D packages that include wafers without circuits therein (or wafers to which no wafer-to- wafer electrical connections are present).

[0035] With reference to Figure 4, the process 400 begins with the creation of the wafers 100A, 100B (block 402) (or other type of wafer as explained above). This creation includes the creation of circuits 102(l)-102(N) (if present) within the wafers 100A, 100B. The wafers 100 A, 100B are then bonded face-to-face at bond interface layers 110 A, 110B (block 404, see also Figures 5A & 6A) to form intermediate product 500A. If circuits 102(l)-102(N) need to be interconnected between wafers 100A, 100B, this interconnection is made. It should be appreciated that Figure 5A shows a center section 502 of the intermediate product 500A, and Figure 6A shows an edge section 600 of the intermediate product 500A where the void 208 can be seen.

[0036] The process 400 continues by applying a thin-film material 504 to fill the void 208 (block 406, see Figures 5B & 6B) to form intermediate product 500B. Note that “fill” in this context means sufficient material to provide structural support at least to the lateral edge of the bond interface layers 110A, HOB, but does not require full support for the roll-off of the substrates 104A, 104B. Note also that, unlike the use of the thin film in Figures 3A-3C, the thin-film material 504 extends all the way around the intermediate product 500B. In an exemplary aspect, the thin-film material 504 is tetraethyl orthosilicate (TEOS) and may be applied through a chemical vapor deposition (CVD) process (or a plasma-enhanced CVD (PECVD)). This example is not intended to be limiting, and other materials or application processes may be used. By way of further example, the thin-film material 504 is approximately four (4) micrometers thick.

[0037] The top wafer 100A is then backside ground (block 408, see Figures 5C & 6C) to form intermediate product 500C. This may leave approximately 20 micrometers of substrate material (e.g., silicon) in the z-axis, although other thicknesses may be used. As noted above, this grinding and / or CMP may put substantial vertical (z-axis) force andWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 9 strain on the intermediate product 500C. However, the presence of the thin-film material 504 in the void 208 prevents this strain from causing delamination or fracturing.

[0038] The process 400 continues with a backside etch of the top wafer 100 A (block 410, see Figures 5D & 6D) to form intermediate product 500D. This etch may be a wet etch or a dry etch. In some aspects, the thin-film material 504 may act as an etch stop. Suitable wet etch materials include, but are not limited to, potassium hydroxide, ethylenediamine pyrocatechol, tetramethylammonium hydroxide, hydrofluoric acid, nitric acid, acetic acid mixes, and the like. Likewise, dry etching examples include but are not limited to reactive ion etching and deep reactive ion etching.

[0039] The process 400 continues by bump 510 formation on a top surface 508 of the top wafer 100A (block 412, see Figure 5E) to form intermediate product 500E. The bumps 510 may be solder bumps, bimetal bumps (copper and solder), or any metal stack that acts as interconnection electrical pads or the like, as is well understood. Generally, the present disclosure refers to such elements as an input / output (I / O) node.

[0040] The process 400 concludes by singulating the intermediate product 500E to form individual wafer stacks and particularly individual 3DIC packages 700 shown in Figure 7. Again, it should be appreciated that other 3D packages or 3D stacks may be an end product of the process 400.

[0041] The 3D packages formed by the processes according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (c.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0042] Figure 8 is a schematic diagram of an exemplary communication device 800 wherein the 3DIC package 700 can be provided. Herein, the communication device 800 can be any type of communication device, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communicationWT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 10 devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications.

[0043] More particularly, the communication device 800 will generally include a control system 802, a baseband processor 804, transmit circuitry 806, receive circuitry 808, antenna switching circuitry 810, multiple antennas 812, and user interface circuitry 814. Any or all of these circuits (not antennas 812) may be instantiated in a 3DIC package 700. As a non-limiting example, the control system 802 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 802 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 808 receives radio frequency signals via the antennas 812 and through the antenna switching circuitry 810 from one or more base stations. A low-noise amplifier and a filter in the receive circuitry 808 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0044] The baseband processor 804 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 804 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0045] For transmission, the baseband processor 804 receives digitized data, which may represent voice, data, or control information, from the control system 802 and encodes it for transmission. The encoded data is output to the transmit circuitry 806, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 812 through the antenna switching circuitry 810 to the antennas 812. The multiple antennas 812 and the replicated transmit and receive circuitries 806, 808 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.WT Ref. No. 2867-3516-WORef. No. P241606-WO-UTL 11

[0046] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0047] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.WT Ref. No. 2867-3516-WO

Claims

AMENDED CLAIMSreceived by the International Bureau on 28 May 2026 (28.05.2026)1. (Previously Presented) A three-dimensional (3D) wafer stack comprising:a first wafer comprising a first bonding surface having a first beveled edge;a second wafer comprising:a beveled lateral edge; anda second bonding surface, the second bonding surface bonded to the first bonding surface extending onto the beveled lateral edge to form a second beveled edge, thereby forming a gap between the first beveled edge and the second beveled edge; anda thin-film material positioned in the gap between the first beveled edge and the second beveled edge such that there is structural support between the first beveled edge and the second beveled edge, wherein the thin-film material is approximately four micrometers thick.

2. (Original) The 3D wafer stack of claim 1, wherein the first bonding surface comprises an oxide.

3. (Original) The 3D wafer stack of claim 1, wherein the thin-film material comprises tetraethyl orthosilicate (TEOS), silicon dioxide, silicon nitride, or some combination of the TEOS, silicon dioxide, and / or silicon nitride.

4. (Original) The 3D wafer stack of claim 1, further comprising a circuit positioned in either the first wafer or the second wafer and an external input / output (I / O) node positioned on the first wafer and electrically coupled to the circuit.

5. (Original) The 3D wafer stack of claim 4, wherein the external I / O node comprises a solder bump.

6. (Original) The 3D wafer stack of claim 4, wherein the circuit comprises a filter or a power amplifier.

7. (Original) The 3D wafer stack of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

8. (Previously Presented) A method of shaping a three-dimensional (3D) wafer stack, comprising:filling a void between wafers with a thin-film material having a thickness of approximately four micrometers in the 3D wafer stack to provide mechanical support for a top wafer; and removing, by grinding or polishing, a top substrate from the top wafer without edge trimming the top wafer.

9. (Previously Presented) A method of forming a three-dimensional (3D) wafer stack, comprising:bonding a first wafer to a second wafer, thereby forming a void between the first and second wafers at a lateral edge; andfilling the void with a thin-film material having a thickness of approximately four micrometers.

10. (Original) The method of claim 9, further comprising grinding a back side of the first wafer, including applying force to the lateral edge.

11. (Original) The method of claim 10, further comprising applying a wet etch to the back side of the first wafer after grinding.

12. (Original) The method of claim 9, wherein filling the void comprises filling the void with tetraethyl orthosilicate (TEOS).

13. (Original) The method of claim 9, wherein filling the void comprises filling the void using chemical vapor deposition.

14. (Original) The method of claim 9, wherein filling the void comprises filling the void using silicon dioxide, silicon nitride, or a combination of silicon dioxide and silicon nitride.

15. (Original) The method of claim 9, further comprising forming the first wafer.

16. (Original) The method of claim 15, wherein forming the first wafer comprising forming a first circuit and a first bonding surface.

17. (Original) The method of claim 16, wherein forming the first bonding surface comprises forming an oxide layer.

18. (Original) The method of claim 9, further comprising forming an input / output (I / O) node on the first wafer.

19. (Original) The method of claim 9, further comprising singulating the first and second wafers after filling the void.

20. (Original) The method of claim 9, further comprising electrically coupling a circuit in the first wafer to a second circuit in the second wafer.

21. (Original) The method of claim 10, wherein the grinding occurs without edge trimming of either wafer.

22. (Original) The method of claim 9, wherein filling the void comprises using a chemical vapor deposition to provide mechanical support for unbonded regions around a stack edge between the first and second wafers.STATEMENT UNDER ARTICLE 19 (1)Claims 1, 8, and 9 are amended.Support for this amendment can be found in paragraph 0036, and a definition of “approximately” is provided in paragraph 0023.The remaining claims are unchanged.If you have any questions, please do not hesitate to contact me.

Images