A 3D package, working assembly and computing device based on backside power supply technology

Abstract

The application discloses a 3D package based on backside power supply technology, a working assembly and a computing device, the package comprising a printed circuit board, a substrate, and a memory module arranged on one side of the printed circuit board; the memory module comprising memory wafers and logic processing wafers stacked in a direction perpendicular to the printed circuit board or the substrate, wherein the logic wafers are prepared by using the backside power supply technology. The application realizes decoupling of a power supply network and a signal network, shortens a heat dissipation path, and can realize super-large computing power and super-high storage bandwidth, while improving pressure drop and heat dissipation performance and balancing the constraint relationship among chip computing power, bandwidth and power consumption by combining wafer-level 3D packaging with logic wafers prepared by using the backside power supply process and arranging the logic wafers on a top layer of the stack.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and more particularly to a 3D package, working component, and computing device based on back-side power supply technology. Background Technology

[0002] As semiconductor manufacturing technology advances, transistor density approaches its limits, leading to significant issues such as heat generation and power consumption. Currently, the power delivery network (PDN) of high-performance computing chips plays a crucial role in projects. The PDN aims to provide power and reference voltage to the active devices on the chip most efficiently. On the other hand, the memory wall problem has become a core bottleneck restricting the performance improvement of traditional computing architectures. Near-memory computing is a solution proposed to address the memory wall problem by reducing the path length between the processor and memory and increasing the path bandwidth, thereby improving computing performance. Higher computing power requires wider and faster data channels, which incurs significant power consumption. Typically, this increased power consumption translates into heat. If heat dissipation is inadequate, the chip may overheat, throttle down, or fail, forming a "power wall."

[0003] There is a close interdependence between a chip's computing power, bandwidth, and power consumption. If any one of them becomes a bottleneck, the efficiency of the entire system will be greatly reduced.

[0004] Traditionally, the power delivery network of a chip is implemented through a network of low-resistance metal lines fabricated on the front side of the silicon wafer. The power network shares this space with the signal network, with electrons traveling through the metal lines and vias across the entire stack of metal layers on the front side of the silicon wafer (approximately 15 to 20 layers) to reach the standard cell. Due to the presence of interconnect signals, these metal lines and vias become increasingly narrow (and therefore more resistant) as they approach the transistor. During transmission, they lose energy, resulting in a drop in power or voltage. As they approach the transistor, at the standard cell level, electrons eventually enter the power and reference voltages, as well as the ground rails of the metal layers. These rails occupy the space between the boundaries and each standard cell. Further close to the transistor, at the standard cell level, electrons eventually enter the power and ground rails located at the BEOL (Block Entrance Orbit). These power and ground rails occupy the space between each standard cell and its boundaries. From here, they connect to the source and drain of each transistor via an intermediate interconnect network. With each new generation of nodes, the traditional chip-side metal layer architecture struggles to keep pace with the scaling paths of transistors. Today, “signal interconnects” increasingly compete for space within the complex metal layer network, consuming at least 20% of the routing resources. Furthermore, the power and ground rails occupy a considerable area at the standard cell level, limiting further scaling of the standard cell height. At the system level, power density and voltage drop increase dramatically, posing a challenge for designers to maintain a design margin of no more than 10% for power losses between the regulator and the transistor.

[0005] Meanwhile, most existing 3D packaging is based on DRAM die on top and Logic die on the bottom. Since Logic die is a high-power chip in 3D packaging, its power consumption is much higher than that of DRAM die. The fact that Logic die is on the bottom layer makes the overall heat dissipation of 3D packaging more difficult. With the improvement of chip computing power and bandwidth, the power consumption of Logic die is increasing day by day, and heat dissipation is gradually becoming a bottleneck of 3D packaging, which has aroused greater attention from the industry to the heat dissipation problem. Summary of the Invention

[0006] To address the shortcomings of the aforementioned technologies, this invention proposes a 3D packaging method based on back-side power supply technology. By moving the entire power distribution network to the back of the silicon wafer, the power supply network is decoupled from the interconnect signal network, with the silicon wafer currently serving only as a carrier. All interconnect signals are interconnected on the front of the silicon wafer via traditional metal layer stacking. Therefore, the power supply network can directly supply power to the standard power supply via wider, lower-resistance metal lines on the back of the silicon wafer. Furthermore, the number of stacked layers for the power supply network is significantly less than the traditional metal layer stacking where both the signal and power supply networks are entirely on the front of the wafer. This method reduces wiring congestion, resulting in a voltage drop improvement of over 30%, enhancing power supply performance and thus increasing chip computing power. Additionally, by directly connecting the source and drain of transistors on the back of the wafer via nTSVs, the area occupied by power and ground rails at the standard cell level is reduced, allowing for further scaling of the standard cell height. 3D packaging of the back-side powered chip breaks the "memory wall" limitation by reducing the path length between the processor and memory and increasing the path bandwidth, further improving computing performance.

[0007] Meanwhile, in 3D packaging, the logic die, being a high-power device, is placed at the top. It can directly contact external heat dissipation devices, such as vapor chambers, heat sinks, or water-cooled plates, through a thermal interface material. This significantly shortens the heat dissipation path of the logic die and reduces heat dissipation resistance. For high-power chips like the logic die, the junction temperature can be improved by 10% to 30%, which is a very significant improvement in heat dissipation efficiency in 3D packaging. Furthermore, placing the logic die at the top prevents its heat from "baking" the DRAM die below, thus controlling the overall temperature inside the stack.

[0008] To address the shortcomings of the existing technologies, the present invention aims to provide a 3D packaging solution based on back-side power supply technology. This solution decouples the power supply network from the signal network and, combined with the design of the top-level logic chip arrangement in the 3D stacked structure, simultaneously solves problems such as excessive voltage drop, wiring congestion, heat dissipation bottlenecks, and memory wall in the existing technologies, thereby balancing the constraints of chip computing power, bandwidth, and power consumption.

[0009] Definitions of terms in this invention:

[0010] WoW: wafer on wafer (wafer and wafer stacking)

[0011] CoW: chip on wafer (chip and wafer stacking)

[0012] Logic die FS metal: Logic die front side metal (the metal layer on the front of the logic chip)

[0013] Logic die BS metal: Logic die backside metal (the metal layer on the back of the logic chip)

[0014] Logic die silicon: the silicon substrate of a logic chip

[0015] Logic wafer FS metal: Logic wafer front side metal.

[0016] Logic wafer BS metal: Logic wafer backside metal.

[0017] Logic wafer silicon: The silicon-based substrate of a logic wafer

[0018] TSV: Through silicon via

[0019] nTSV: nano Through silicon via

[0020] HB: hybrid bonding

[0021] BEOL: back end of line (back-end process)

[0022] Bump: bump

[0023] ubump: micro-bumps

[0024] PDN: Power Delivery Network

[0025] BSPDN: Back side Power Delivery Network

[0026] FinFET: Fin Field-Effect Transistor

[0027] Substrate: substrate

[0028] PCB: Printed Circuit Board

[0029] RDL: Rewire Layer

[0030] For signals inside a logic chip, some signals are interconnected on the chip's metal layer stack; the remaining signals and power / ground signals are connected to pins such as the bump pin. The presence of these interconnect signals significantly occupies the wiring space on the metal layers, causing the power / ground wiring width to narrow and thus increasing impedance. Simultaneously, the presence of these interconnect signals increases the number of metal layers, resulting in longer signal transmission links and increased voltage drop.

[0031] This invention involves performing special treatments on the back side of the Logic chip to form a back metal layer.

[0032] First, a thin dielectric layer is formed on the upper surface of the wafer. Then, a thin silicon substrate is grown on this dielectric layer. The FinFET device is formed in this thin silicon substrate. A metal layer is then formed on the front side of the wafer above the FinFET layer until all the interconnect signals inside the Logic die are interconnected. As for the power ground of the Logic die and other signals that need to be interconnected with the DRAM die, they are reserved for now and no connection is made on the metal layer on the front side of the wafer.

[0033] The wafer is then flipped over and etched away until the dielectric layer is completely etched. Next, it is directly connected to the FinFET layer through the silicon substrate via nTSV (nanovia). A back metal layer is then created on the nTSV. Power, ground, and signals interconnected with the DRAM are connected to the hybrid bonding through the metal layer. The logic die is interconnected with the DRAM die's signals through the hybrid bonding. The logic die's power and ground are transmitted to the bump via the hybrid bonding and the DRAM die's TSV.

[0034] Since the interconnect signals inside the logic die are already connected on the metal layer on the front side of the wafer, routing on the metal back side has two advantages:

[0035] (1) Moving the power / ground network from the front to the back of the chip decouples it from the interconnect signals, completely eliminating the resource competition between power lines and signal lines in the limited wiring layer. The power network can use a thicker, lower-resistance dedicated metal layer, while the number of metal layers on the back is greatly reduced (about seven or eight layers). The direct result is a significant reduction in voltage drop.

[0036] (2) Since power routing no longer occupies the front metal layer, all front metal layers can be used entirely for signal interconnects. This greatly alleviates routing congestion, allowing designers to achieve shorter, better signal paths and place more standard cells in the same area, thereby improving chip integration and design flexibility.

[0037] Meanwhile, in 3D packaging, the logic die, which is a high-power chip, is placed on the top layer. It can directly contact external heat dissipation devices, such as vapor chambers, heat sinks, or water-cooled plates, through thermal interface materials. Compared to placing the logic die on the bottom layer of the 3D package, this greatly shortens the heat dissipation path of the logic die, reduces heat dissipation resistance, and effectively improves heat dissipation efficiency. Placing the logic die on top prevents its heat from "baking" the chips below, thereby controlling the overall temperature inside the stack.

[0038] This invention proposes the following solutions based on 3D packaging technology with back-side power supply.

[0039] When the area of ​​a single logic die is less than half the area of ​​a single DRAM die, 3D packaging based on back-side power supply technology has the following CoW implementation methods:

[0040] (1) First, the logic wafer is cut into individual logic dies. Then, multiple cut logic dies are considered as a unit. The number of logic dies inside each unit is equal and unlimited. The area of ​​the unit will not exceed the area of ​​a single DRAM die. Each unit is evenly placed on top of the DRAM wafer, so that each DRAM die will have the same number of logic dies on top of it. The back metal layer of each logic die is connected to the DRAM wafer by hybrid bonding, and then it is cut.

[0041] a. After cutting, the DRAM die is connected to the substrate via a bump, and then connected to the PCB via a solder ball, as shown below. Figure 1a As shown.

[0042] In this way, the interconnect signals between the Logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the bump, and then from the bump to the substrate.

[0043] b. After cutting, the DRAM die is connected to the PCB via a solder ball, as shown below. Figure 1e As shown.

[0044] In this way, the interconnect signals between the logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the solder ball, and then from the solder ball to the PCB.

[0045] (2) It can also be done in Figure 1a Based on this, a redistribution layer is added beneath the DRAM wafer. The back metal layer of the logic die is connected to the DRAM wafer via hybrid bonding before dicing. Figure 1a The power ground and signals passing through the DRAM wafer are connected to the rewiring layer via ubump.

[0046] a. The redistribution layer is connected to the substrate via a bump, and then connected to the PCB via a solder ball from the substrate, as shown below. Figure 1b As shown.

[0047] In this way, the interconnect signals between the Logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the ubump, then through the ubump to the redistribution layer, and then through the redistribution layer to the Substrate via the bump.

[0048] b. The redistribution layer is connected to the PCB via a solder ball, such as... Figure 1f As shown.

[0049] In this way, the interconnect signals between the Logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the ubump, then through the ubump to the redistribution layer, and then through the redistribution layer to the PCB via the solder ball.

[0050] (3) Treat multiple Logic dies as a whole unit. The area of ​​each unit (the area occupied by the overall arrangement of the unit) will not exceed the area of ​​a single DRAM die. Each Logic die inside the unit is connected by a scribeline. First, the whole unit is cut on the Logic wafer, and then the cut units are evenly placed on the DRAM wafer. Each unit corresponds to one DRAM die. The number of Logic dies inside each unit is equal and the number of Logic dies is unlimited. The metal layer on the back of the Logic die is connected to the DRAM die through hybrid bonding before cutting.

[0051] a. After cutting, the DRAM die is connected to the substrate via a bump, and then connected to the PCB via a solder ball, as shown below. Figure 1c As shown.

[0052] In this way, the interconnect signals between the logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the bump, and then from the bump to the substrate.

[0053] b. After cutting, the DRAM die is connected to the PCB via a solder ball, as shown below. Figure 1g As shown.

[0054] In this way, the interconnect signals between the logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the solder ball, and then from the solder ball to the PCB.

[0055] (4) It can also be done in Figure 1c Based on this, a redistribution layer is added below the DRAM wafer. The back metal layer of the logic die is connected to the DRAM wafer via hybrid bonding before being cut. In this way, the power ground and signals passing through the DRAM die can be connected to the redistribution layer via ubump.

[0056] a. The redistribution layer is connected to the substrate via a bump, and then connected to the PCB via a solder ball from the substrate, as shown below. Figure 1d As shown.

[0057] In this way, the interconnect signals between the Logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the ubump, then through the ubump to the redistribution layer, and then through the redistribution layer to the Substrate via the bump.

[0058] b. The redistribution layer is connected to the PCB via a solder ball, such as... Figure 1h As shown.

[0059] In this way, the interconnect signals between the Logic die and the DRAM die are connected through hybrid bonding; the power ground and other signals pass through the DRAM die to the ubump, then through the ubump to the redistribution layer, and then through the redistribution layer to the PCB via the solder ball.

[0060] In the above structures, each DRAM chip and the multiple logic dies stacked above it are considered a unit. The number of these units on the redistribution layer, substrate, or PCB is unlimited, such as 1x1, 2x2, 3x3, 4x4…nxn; or 1x2, 2x4, 3x6, 4x8…nx2n; or nxm. Interconnections can be made between each unit on the PCB, as shown in the diagram. Figure 4 As shown, in addition to horizontal and vertical interconnections, units can also be interconnected diagonally as needed.

[0061] When the area ratio of the logic die to the DRAM die is 1:1, the following WoW (Work of the World) solutions exist for 3D packaging based on back-side power supply technology:

[0062] The first approach involves packaging a single logic wafer and a single DRAM wafer together, which can be implemented in several ways:

[0063] 1. The back metal layer of the logic wafer is placed on top of the DRAM wafer, and the two are connected via hybrid bonding. Each logic die corresponds to one DRAM die, and the interconnect signals between the logic die and the DRAM die are also connected via hybrid bonding. This completes the 3D wafer packaging between the logic wafer and the DRAM wafer. The 3D wafer can be viewed as a 3D packaging unit, such as... Figure 2_1 As shown;

[0064] (1) Connect the “3D_wafer” to the PCB using a solder ball, such as Figure 2_1-1 As shown. In the 3D_wafer, the interconnection between the logic wafer and the DRAM wafer is completed, and the power ground and other signals pass through the underlying DRAM wafer in the 3D_wafer and are connected to the PCB board through the solder ball.

[0065] (2) Place multiple 3D wafers on the PCB. Each 3D wafer is connected to the PCB via a solder ball. The number of 3D wafers is unlimited. Figure 2_1-2 As shown.

[0066] In the 3D_wafer, the interconnection between the logic wafer and the DRAM wafer is completed, while power, ground and other signals pass through the underlying DRAM wafer in the 3D_wafer and are connected to the PCB board via solder balls.

[0067] (3) Divide the above 3D_wafer into multiple units, each unit containing a stack of a logic die and a DRAM die; such a unit is called a 3D_IC; Figure 2_3 As shown.

[0068] a. Connect the 3D IC to the substrate via a bump, and then connect it to the PCB via a solder ball through the substrate, as shown below. Figure 2_3-a As shown.

[0069] In the 3D_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the bottom DRAM die in the 3D_IC, are connected to the substrate through the bump, and are then connected to the PCB through the solder ball.

[0070] b. Connect the 3D IC to the substrate via a bump. Consider the "3D IC + substrate" as a single unit. It can be connected to the PCB via a solder ball. Multiple units can be placed on the PCB; the number of units is unlimited. Figure 2_3-b As shown.

[0071] In a 3D IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the bottom DRAM die in the 3D IC, are connected to the substrate through a bump, and then connected to the PCB through a solder ball. The 3D ICs can be interconnected on the PCB through the interconnect IP on the Logic die.

[0072] c. Connect the 3D IC to the PCB using a solder ball, as follows: Figure 2_3-c As shown.

[0073] In the 3D_IC, the interconnection between the Logic die and the DRAM die is completed, while power, ground, and other signals pass through the underlying DRAM die in the 3D_IC and are connected to the PCB via solder balls.

[0074] d. Place multiple 3D ICs on the PCB, each 3D IC connected to the PCB via a solder ball. The number of 3D ICs is unlimited. Figure 2_3-d As shown.

[0075] In a 3D IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3D IC and are connected to the PCB via solder balls. 3D ICs can be interconnected on the PCB through interconnect IPs on the Logic die.

[0076] e. Place multiple 3D ICs on a substrate, with each 3D IC connected to the substrate via a bump, and then connected to the PCB via a solder ball, such as... Figure 2_3-e As shown.

[0077] In a 3D IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the bottom DRAM die in the 3D IC and are connected to the substrate via a bump. The 3D ICs can be interconnected on the substrate through the interconnect IP on the Logic die.

[0078] f. Place multiple 3D ICs on the redistribution layer. Each 3D IC is connected to the redistribution layer via a bump, then connected to the substrate via another bump, and finally connected to the PCB via a solder ball, as shown below. Figure 2_3-f As shown.

[0079] In a 3D IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground, and other signals pass through the underlying DRAM die in the 3D IC and are connected to the redistribution layer via ubump. 3D ICs can be interconnected on the redistribution layer through the interconnection IP on the Logic die.

[0080] g. Place multiple 3D ICs on the redistribution layer. Each 3D IC is connected to the redistribution layer via an ubump, and then connected to the PCB via a solder ball, as shown below. Figure 2_3-g As shown.

[0081] In a 3D IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground, and other signals pass through the underlying DRAM die in the 3D IC and are connected to the redistribution layer via ubump. 3D ICs can be interconnected on the redistribution layer through the interconnection IP on the Logic die.

[0082] 2. In Figure 2_1 Based on this, a redistribution layer is added below the DRAM wafer. The DRAM wafer is connected to the redistribution layer via ubump. Treating the 3D stack with the added redistribution layer as a whole can be called a 3DRDL_wafer, such as... Figure 2_2 As shown;

[0083] (1) Connect the 3DRDL_wafer to the PCB via a solder ball, such as Figure 2_2-1 As shown.

[0084] In the 3DRDL_wafer, the interconnection between the logic wafer and the DRAM wafer is completed. Power ground and other signals pass through the underlying DRAM wafer in the 3DRDL_wafer and are connected to the PCB via the solder ball.

[0085] (2) Place multiple 3DRDL_wafers on the PCB. Each 3DRDL_wafer is connected to the PCB via a solder ball. The number of 3DRDL_wafers is unlimited. Figure 2_2-2 As shown.

[0086] In the 3DRDL_wafer, the interconnection between the logic wafer and the DRAM wafer is completed. Power ground and other signals pass through the underlying DRAM wafer in the 3DRDL_wafer and are connected to the PCB via the solder ball.

[0087] (3) Divide the above 3DRDL_wafer into multiple units, each unit containing a stack of a logic die, a DRAM die, and a redistribution layer; such a unit is called a 3DRDL_IC; for example Figure 2_4 As shown.

[0088] a. Connect the 3DRDL_IC to the substrate via a bump, and then connect it to the PCB via a solder ball through the substrate, as shown below. Figure 2_4-a As shown.

[0089] In the 3DRDL_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the bottom DRAM die in the 3DRDL_IC, are connected to the substrate through the bump, and are then connected to the PCB through the solder ball.

[0090] b. Connect the 3DRDL_IC to the substrate via a bump. Consider the "3DRDL_IC + substrate" as a single unit. It can be connected to the PCB via a solder ball. Multiple units can be placed on the PCB; the number of units is unlimited. Figure 2_4-b As shown.

[0091] In the 3DRDL_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the bottom DRAM die in the 3DRDL_IC, are connected to the substrate through the bump, and are then connected to the PCB through the solder ball. The "3DRDL_IC + substrate" units can be interconnected on the PCB through the interconnection IP on the Logic die.

[0092] c. Connect the 3DRDL_IC to the PCB via a solder ball, as follows: Figure 2_4-c As shown.

[0093] In the 3DRDL_IC, the interconnection between the logic die and the DRAM die is completed, while power ground and other signals pass through the underlying DRAM die in the 3DRDL_IC and are connected to the PCB via solder balls.

[0094] d. Place multiple 3DRDL_ICs on the PCB, each 3DRDL_IC connected to the PCB via a solder ball. The number of 3DRDL_ICs is unlimited. Figure 2_4-d As shown.

[0095] In the 3DRDL_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3DRDL_IC and are connected to the PCB via the solder ball. The 3DRDL_ICs can be interconnected on the PCB through the interconnect IP on the Logic die.

[0096] e. Place multiple 3DRDL_ICs on the substrate. Each 3DRDL_IC is connected to the substrate via a bump, and then connected to the PCB via a solder ball, as shown below. Figure 2_4-e As shown.

[0097] In the 3DRDL_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3DRDL_IC and are connected to the substrate via a bump. The 3DRDL_ICs can be interconnected on the substrate through the interconnect IP on the Logic die.

[0098] f. Place multiple 3DRDL_ICs on the redistribution layer. Each 3DRDL_IC is connected to the redistribution layer via a bump, then connected to the substrate via a bump through the redistribution layer, and finally connected to the PCB via a solder ball, as shown below. Figure 2_4-f As shown.

[0099] In the 3DRDL_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3DRDL_IC and are connected to the redistribution layer via ubump. The 3DRDL_ICs can be interconnected on the redistribution layer through the interconnection IP on the Logic die.

[0100] g. Place multiple 3DRDL_ICs on the redistribution layer. Each 3DRDL_IC is connected to the redistribution layer via an ubump, and then connected to the PCB via a solder ball, as shown below. Figure 2_4-g As shown

[0101] In the 3DRDL_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3DRDL_IC and are connected to the redistribution layer via ubump. The 3DRDL_ICs can be interconnected on the redistribution layer through the interconnection IP on the Logic die.

[0102] In the above structures, the number of 3D_wafer and 3DRDL_wafer on the PCB is unlimited, such as 1x1, 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or in the form of nxm. Each 3D_wafer and 3DRDL_wafer can be considered a package unit, where the logic dies between each unit can be interconnected on the PCB, as shown in the diagram. Figure 4 As shown, in addition to horizontal and vertical interconnections, units can also be interconnected diagonally as needed.

[0103] In the above structures, the number of 3D_ICs and 3DRDL_ICs on the redistribution layer, substrate, and PCB is unlimited, such as 1x1, 2x2, 3x3, 4x4...nxm, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or in the form of nxm. Each 3D_IC and 3DRDL_IC can be considered as a package unit. The logic dies between each unit can be interconnected on the redistribution layer, substrate, or PCB, as shown in the interconnection relationship... Figure 4 As shown, in addition to horizontal and vertical interconnections, units can also be interconnected diagonally as needed.

[0104] The second approach involves packaging a single logic wafer and multiple DRAM wafers together, which can be implemented in several ways.

[0105] 1. Multiple DRAM wafers are stacked together, with each wafer connected via hybrid bonding. Signals are transmitted between the DRAM wafers via (TSV + hybrid bonding). The number of DRAM wafers stacked is unlimited. After the DRAM wafer stacking is complete, they are treated as a single unit. The top DRAM wafer is connected to the back metal layer of the logic wafer via hybrid bonding, with the logic wafer placed on top. Interconnect signals between the logic wafer and the multiple DRAM wafers are connected via hybrid bonding. This completes the 3D packaging between the logic wafer and the multiple DRAM wafers, which can be called a 3D_M_wafer. Figure 3_1 As shown.

[0106] (1) The pre-packaged 3D_M_wafer can be directly connected to the PCB via a solder ball, such as... Figure 3_1-a As shown.

[0107] The interconnection between the Logic wafer and the DRAM wafer in the 3D_M_wafer is complete. Power ground and other signals pass through the underlying DRAM wafer in the 3D_M_wafer and are connected to the PCB board via solder balls.

[0108] (2) Place multiple 3D_M_wafers on the PCB. Each 3D_M_wafer is connected to the PCB via a solder ball. The number of 3D_M_wafers is unlimited. Figure 3_1-b As shown.

[0109] The interconnection between the Logic wafer and the DRAM wafer in the 3D_M_wafer is complete. Power ground and other signals pass through the underlying DRAM wafer in the 3D_M_wafer and are connected to the PCB board via solder balls.

[0110] (3) The packaged 3D_M_wafer is divided into multiple units, each containing one logic die and multiple DRAM dies stacked directly below it. Such a unit is called a 3D_M_IC, such as Figure 3_3 As shown.

[0111] a. Connect the 3D_M_IC to the substrate via a bump, and then connect it to the PCB via a solder ball through the substrate, as shown below. Figure 3_3-a As shown.

[0112] In the 3D_M_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the bottom DRAM die in the 3D_M_IC, are connected to the substrate through the bump, and then connected to the PCB through the solder ball.

[0113] b. Connect the 3D M IC to the substrate via a bump. Consider the "3D M IC + substrate" as a single unit. It can be connected to the PCB via a solder ball. Multiple units can be placed on the PCB; the number of units is unlimited. Figure 3_3-b As shown.

[0114] In 3D_M_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in 3D_M_IC and are connected to the substrate through a bump. The "3D_M_IC + substrate" units can be interconnected on the PCB through the interconnection IP on the Logic die.

[0115] c. Connect the 3D_M_IC to the PCB using a solder ball, such as... Figure 3_3-c As shown.

[0116] In 3D_M_IC, the interconnection between the Logic die and the DRAM die is completed, while power ground and other signals pass through the underlying DRAM die in 3D_M_IC and are connected to the PCB via solder balls.

[0117] d. Place multiple 3D MICs on the PCB, each 3D MIC connected to the PCB via a solder ball. The number of 3D MICs is unlimited. Figure 3_3-d As shown.

[0118] In a 3D_M_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3D_M_IC and are connected to the PCB via solder balls. 3D_M_ICs can be interconnected on the PCB through the interconnect IP on the Logic die.

[0119] e. Place multiple 3D MICs on a substrate, with each 3D MIC connected to the substrate via a bump, and then connected to the PCB via a solder ball, as shown. Figure 3_3-e As shown.

[0120] In a 3D_M_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3D_IC and are connected to the substrate via a bump. The 3D_M_ICs can be interconnected on the substrate through the interconnect IP on the Logic die.

[0121] f. Place multiple 3D_M_ICs on the redistribution layer. Each 3D_M_IC is connected to the redistribution layer via a bump, then connected to the substrate via another bump, and finally connected to the PCB via a solder ball, as shown below. Figure 3_3-f As shown.

[0122] In a 3D_M_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3D_IC and are connected to the redistribution layer via ubump. Interconnection between 3D_M_ICs can be made on the redistribution layer through the interconnection IP on the Logic die.

[0123] g. Place multiple 3D_M_ICs on the redistribution layer. Each 3D_M_IC is connected to the redistribution layer via an ubump, and then connected to the PCB via a solder ball, as shown below. Figure 3_3-g As shown.

[0124] In a 3D_M_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3D_IC and are connected to the redistribution layer via ubump. Interconnection between 3D_M_ICs can be made on the redistribution layer through the interconnection IP on the Logic die.

[0125] 2. In Figure 3_1 Based on this, a redistribution layer is added below the underlying DRAM wafer. The underlying DRAM wafer is connected to the redistribution layer via ubump. Treating the 3D stack with the added redistribution layer as a single unit can be called 3DRDL_M_wafer, such as... Figure 3_2 As shown;

[0126] (1) Connect the 3DRDL_M_wafer to the PCB via a solder ball, such as Figure 3_2-a As shown.

[0127] In the 3DRDL_M_wafer, the interconnection between the logic wafer and the DRAM wafer is completed. Power ground and other signals pass through the underlying DRAM wafer in the 3DRDL_M_wafer and are connected to the PCB via the solder ball.

[0128] (2) Place multiple 3DRDL_M_wafers on the PCB. Each 3DRDL_M_wafer is connected to the PCB via a solder ball. The number of 3DRDL_M_wafers is unlimited. Figure 3_2-b As shown.

[0129] In the 3DRDL_M_wafer, the interconnection between the logic wafer and the DRAM wafer is completed. Power ground and other signals pass through the underlying DRAM wafer in the 3DRDL_M_wafer and are connected to the PCB via the solder ball.

[0130] (3) Divide the above 3DRDL_M_wafer into multiple units. Each unit contains a logic die and multiple RAM dies stacked directly below it, as well as a redistribution layer. Such a unit is called a 3DRDL_M_IC, such as Figure 3_4 As shown.

[0131] a. Connect the 3DRDL_M_IC to the substrate via a bump, and then connect it to the PCB via a solder ball through the substrate, as shown below. Figure 3_4-a As shown.

[0132] In the 3DRDL_M_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the bottom DRAM die in the 3DRDL_M_IC, are connected to the substrate through the bump, and then connected to the PCB through the solder ball.

[0133] b. Connect the 3DRDL_M_IC to the substrate via a bump. Consider the "3DRDL_M_IC + substrate" as a single unit, which is connected to the PCB via a solder ball. Multiple units can be placed on the PCB; the number of units is unlimited. Figure 3_4-b As shown.

[0134] In the 3DRDL_M_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the bottom DRAM die in the 3DRDL_M_IC, are connected to the substrate through the bump, and then connected to the PCB through the solder ball. The "3DRDL_M_IC + substrate" units can be interconnected on the PCB through the interconnection IP on the Logic die.

[0135] c. Connect the 3DRDL_M_IC to the PCB using a solder ball, as follows: Figure 3_4-c As shown.

[0136] In the 3DRDL_M_IC, the interconnection between the logic die and the DRAM die is completed. Power ground and other signals pass through the underlying DRAM die in the 3DRDL_M_IC and are connected to the PCB via the older ball.

[0137] d. Place multiple 3DRDL_M_ICs on the PCB, each 3DRDL_M_IC connected to the PCB via a solder ball. The number of 3DRDL_M_ICs is unlimited. Figure 3_4-d As shown.

[0138] In the 3DRDL_M_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3DRDL_M_IC and are connected to the PCB through the solder ball. The "3DRDL_M_IC + substrate" units can be interconnected on the substrate through the interconnection IP on the Logic die.

[0139] e. Place multiple 3DRDL_M_ICs on the substrate. Each 3DRDL_M_IC is connected to the substrate via a bump, and then connected to the PCB via a solder ball, as shown below. Figure 3_4-e As shown.

[0140] In the 3DRDL_M_IC, the interconnection between the Logic die and the DRAM die is completed. Power, ground and other signals pass through the underlying DRAM die in the 3DRDL_M_IC and are connected to the substrate via a bump. The "3DRDL_M_IC + substrate" units can be interconnected on the substrate through the interconnection IP on the Logic die.

[0141] f. Place multiple 3DRDL_M_ICs on the redistribution layer. Each 3DRDL_M_IC is connected to the redistribution layer via a bump, then connected to the substrate via another bump, and finally connected to the PCB via a solder ball, as shown below. Figure 3_4-f As shown.

[0142] In the 3DRDL_M_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the underlying DRAM die in the 3DRDL_M_IC and are connected to the redistribution layer via ubump. The 3DRDL_M_IC cells can be interconnected on the redistribution layer through the interconnection IP on the Logic die.

[0143] g. Place multiple 3DRDL_M_ICs on the redistribution layer. Each 3DRDL_M_IC is connected to the redistribution layer via an ubump, and then connected to the PCB via a solder ball, as shown below. Figure 3_4-g As shown.

[0144] In the 3DRDL_M_IC, the interconnection between the Logic die and the DRAM die is completed. The power ground and other signals pass through the underlying DRAM die in the 3DRDL_M_IC and are connected to the redistribution layer via ubump. The 3DRDL_M_IC cells can be interconnected on the redistribution layer through the interconnection IP on the Logic die.

[0145] In the above structures, the number of "3D_M_wafer" and "3DRDL_M_wafer" on the PCB is unlimited, such as 1x1, 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or in the form of nxm. Each 3D_M_wafer and 3DRDL_M_wafer can be considered a package unit. The logic dies between each unit can be interconnected on the PCB, as shown in the diagram. Figure 4 As shown, in addition to horizontal and vertical interconnections, units can also be interconnected diagonally as needed.

[0146] In the above structures, the number of "3D_M_IC" and "3DRDL_M_IC" on the redistribution layer, substrate, or PCB is unlimited, such as 1x1, 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or nxm. Each 3D_M_IC and 3DRDL_M_IC can be considered a package unit. The logic dies between each unit can be interconnected on the PCB, as shown in the diagram. Figure 4 As shown, in addition to horizontal and vertical interconnections, units can also be interconnected diagonally as needed.

[0147] The 3D packaging based on back-side power supply technology disclosed in this invention has the following beneficial effects:

[0148] Back-side power supply technology is employed: by moving the entire power distribution network to the back of the silicon wafer, the power supply network is decoupled from the interconnect signal network. All interconnect signals are interconnected on the front of the silicon wafer through traditional metal layer stacking. This allows the power supply network to directly supply power to the standard power source via wider, lower-resistance metal lines on the back of the silicon wafer. Furthermore, the number of stacked layers for the power supply network is significantly less than that of traditional signal and power networks, which are entirely stacked on the front of the wafer. This method reduces wiring congestion, improves voltage drop, and enhances power supply performance, thereby increasing chip computing power. Additionally, by directly connecting to the source and drain of transistors on the back of the wafer via nTSVs, the area occupied by power and ground rails at the standard cell level is reduced, allowing for further scaling of the standard cell height. 3D packaging of the back-side powered chip breaks down the "memory wall" limitation by reducing the path length between the processor and memory and increasing the path bandwidth, further improving computing performance.

[0149] Placing the Logic Die on top of the 3D package: In a 3D package, the Logic Die, as a high-power chip, is placed on the top layer. This allows it to directly contact external heat dissipation devices, such as vapor chambers, heat sinks, or water-cooled plates, through a thermal interface material. Compared to placing the Logic Die on the bottom layer, this significantly shortens the heat dissipation path, reduces heat dissipation resistance, and effectively improves heat dissipation efficiency. Placing the Logic Die on top also prevents its heat from "baking" the chips below, thus controlling the overall temperature within the stack.

[0150] By combining rear-mounted power supply with logic placed at the top of the 3D display, the constraints between the chip's computing power, bandwidth, and power consumption can be further balanced. This minimizes the bottleneck effect of any one factor, thus ensuring the overall system efficiency.

[0151] Compared to traditional front-side metal layer processes, where power enters from the chip edge and must traverse long, thin metal lines (competing for resources with signal lines) horizontally across the entire chip to reach the transistors, resulting in extremely high path resistance, Logic die employs back-side power supply technology. Power enters through a dedicated metal layer on the back of the wafer and reaches the transistors vertically via nanoscale through-silicon vias (nTSVs), resulting in an extremely short path. Furthermore, the wiring is thicker, further reducing impedance. Back-side power supply technology can reduce power voltage drop by at least 30% by reconfiguring the power supply path.

[0152] Compared to packaging solutions that place the Logic die at the bottom of a 3D stack, the enormous heat generated by the Logic die must first pass through the DRAM die stack to be conducted to the heat sink. This long heat dissipation path leads to increased thermal resistance, and the higher the DRAM die stack, the longer the heat dissipation path and the higher the thermal resistance. Placing the Logic die at the top of the 3D stack allows the heat generated by the Logic die to be directly conducted to the heat sink. This results in a shorter heat dissipation path, reduced thermal resistance, and a significant and crucial improvement in heat dissipation efficiency. Typically, this can reduce the junction temperature of the Logic chip by 20°C to over 40°C, depending on the power consumption and thermal design. Attached Figure Description

[0153] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0154] Figure 1a This is a cross-sectional schematic diagram of the first CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0155] Figure 1b This is a cross-sectional schematic diagram of the second CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0156] Figure 1c This is a cross-sectional schematic diagram of the third CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0157] Figure 1d This is a cross-sectional schematic diagram of the fourth CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0158] Figure 1e This is a cross-sectional schematic diagram of the fifth CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0159] Figure 1fThis is a cross-sectional schematic diagram of the sixth CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0160] Figure 1g This is a cross-sectional schematic diagram of the seventh CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0161] Figure 1h This is a cross-sectional schematic diagram of the eighth CoW-type 3D packaging structure based on back-side power supply technology of the present invention;

[0162] Figure 2_1 This is a cross-sectional schematic diagram of the first WoW-type 3D wafer stacking unit of the present invention;

[0163] Figure 2_1-1 For the present invention Figure 2_1 The diagram shows the structure of the 3D wafer stacking unit connected to the PCB.

[0164] Figure 2_1-2 For the present invention multiple Figure 2_1 The diagram shows an array structure connecting 3D wafer stacking units to a PCB.

[0165] Figure 2_2 This is a cross-sectional schematic diagram of the WoW-type 3D wafer stacking unit with redistribution layer of the present invention;

[0166] Figure 2_2-1 For the present invention Figure 2_2 The diagram shows the connection between a 3D wafer stacking unit with a redistribution layer and a PCB.

[0167] Figure 2_2-2 For the present invention multiple Figure 2_2 A schematic diagram of the array structure connecting the 3D wafer stacking unit with the redistribution layer to the PCB.

[0168] Figure 2_3 This is a cross-sectional schematic diagram of the WoW-type 3D integrated circuit unit of the present invention;

[0169] Figure 2_3-a For the present invention Figure 2_3 The diagram shows the structure of the 3D integrated circuit unit connected to the PCB via a substrate.

[0170] Figure 2_3-b For the present invention multiple Figure 2_3 The diagram shows an array structure in which 3D integrated circuit units are connected to a PCB via a substrate.

[0171] Figure 2_3-c For the present invention Figure 2_3 The diagram shows a structure where a 3D integrated circuit unit is directly connected to a PCB.

[0172] Figure 2_3-dFor the present invention multiple Figure 2_3 The diagram shows an array structure where 3D integrated circuit units are directly connected to the PCB.

[0173] Figure 2_3-e For the present invention multiple Figure 2_3 The diagram shows an array structure in which 3D integrated circuit units are connected to a PCB via the same substrate.

[0174] Figure 2_3-f For the present invention multiple Figure 2_3 The diagram shows an array structure in which 3D integrated circuit units are connected to the PCB via a redistribution layer, a substrate, and a PCB.

[0175] Figure 2_3-g For the present invention multiple Figure 2_3 The diagram shows an array structure in which 3D integrated circuit units are connected to the PCB via a redistribution layer.

[0176] Figure 2_4 This is a cross-sectional schematic diagram of the WoW-type 3D integrated circuit cell with a redistribution layer of the present invention;

[0177] Figure 2_4-a For the present invention Figure 2_4 The diagram shows a 3D integrated circuit unit with a redistribution layer connected to a PCB via a substrate.

[0178] Figure 2_4-b For the present invention multiple Figure 2_4 The diagram shows an array structure in which 3D integrated circuit cells with rewiring layers are connected to a PCB via a substrate.

[0179] Figure 2_4-c For the present invention Figure 2_4 The diagram shows a 3D integrated circuit unit with a redistribution layer directly connected to a PCB.

[0180] Figure 2_4-d For the present invention multiple Figure 2_4 The diagram shows an array structure in which 3D integrated circuit cells with rewiring layers are directly connected to a PCB.

[0181] Figure 2_4-e For the present invention multiple Figure 2_4 The diagram shows an array structure in which 3D integrated circuit cells with rewiring layers are connected to a PCB via the same substrate.

[0182] Figure 2_4-f For the present invention multiple Figure 2_4 The diagram shows an array structure in which 3D integrated circuit cells with a redistribution layer are connected to the PCB via the redistribution layer, substrate, and PCB.

[0183] Figure 2_4-g For the present invention multiple Figure 2_4The diagram shows an array structure in which 3D integrated circuit cells with a redistribution layer are connected to the PCB via the redistribution layer.

[0184] Figure 3_1 This is a cross-sectional schematic diagram of the 3D wafer cell of the multilayer memory stack of the present invention;

[0185] Figure 3_1-a For the present invention Figure 3_1 The diagram shows the structure of the multi-layer stacked 3D wafer unit connected to the PCB.

[0186] Figure 3_1-b For the present invention multiple Figure 3_1 The diagram shows an array structure connecting multi-layer stacked 3D wafer units to a PCB.

[0187] Figure 3_2 This is a cross-sectional schematic diagram of the multilayer memory stacked 3D wafer cell with redistribution layer of the present invention;

[0188] Figure 3_2-a For the present invention Figure 3_2 The diagram shows the structure of a multi-layer stacked 3D wafer unit with a redistribution layer connected to a PCB.

[0189] Figure 3_2-b For the present invention multiple Figure 3_2 A schematic diagram of an array structure showing the connection between a multi-layer stacked 3D wafer cell with a redistribution layer and a PCB.

[0190] Figure 3_3 This is a cross-sectional schematic diagram of the 3D integrated circuit cell of the multilayer memory stack of the present invention;

[0191] Figure 3_3-a For the present invention Figure 3_3 The diagram shows a multi-layer stacked 3D integrated circuit unit connected to a PCB via a substrate.

[0192] Figure 3_3-b For the present invention multiple Figure 3_3 The diagram shows an array structure in which multilayer stacked 3D integrated circuit units are connected to a PCB via a substrate.

[0193] Figure 3_3-c For the present invention Figure 3_3 The diagram shows a structure where a multi-layer stacked 3D integrated circuit unit is directly connected to a PCB.

[0194] Figure 3_3-d For the present invention multiple Figure 3_3 The diagram shows an array structure where multi-layer stacked 3D integrated circuit units are directly connected to a PCB.

[0195] Figure 3_3-e For the present invention multiple Figure 3_3The diagram shows an array structure in which multilayer stacked 3D integrated circuit units are connected to a PCB via the same substrate.

[0196] Figure 3_3-f For the present invention multiple Figure 3_3 The diagram shows an array structure in which multilayer stacked 3D integrated circuit units are connected to the PCB via redistribution layers, a substrate, and a PCB.

[0197] Figure 3_3-g For the present invention multiple Figure 3_3 The diagram shows an array structure in which multi-layer stacked 3D integrated circuit units are connected to the PCB via a redistribution layer.

[0198] Figure 3_4 This is a cross-sectional schematic diagram of the multilayer memory stacked 3D integrated circuit cell with redistribution layer of the present invention;

[0199] Figure 3_4-a For the present invention Figure 3_4 The diagram shows a multilayer stacked 3D integrated circuit unit with a redistribution layer connected to a PCB via a substrate.

[0200] Figure 3_4-b For the present invention multiple Figure 3_4 The diagram shows an array structure in which multilayer stacked 3D integrated circuit cells with rewiring layers are connected to a PCB via a substrate.

[0201] Figure 3_4-c For the present invention Figure 3_4 The diagram shows a structure in which a multilayer stacked 3D integrated circuit unit with a redistribution layer is directly connected to a PCB.

[0202] Figure 3_4-d For the present invention multiple Figure 3_4 The diagram shows an array structure in which multi-layer stacked 3D integrated circuit cells with rewiring layers are directly connected to a PCB.

[0203] Figure 3_4-e For the present invention multiple Figure 3_4 The diagram shows an array structure in which multilayer stacked 3D integrated circuit cells with rewiring layers are connected to a PCB via the same substrate.

[0204] Figure 3_4-f For the present invention multiple Figure 3_4 The diagram shows an array structure in which multilayer stacked 3D integrated circuit units with redistribution layers are connected to the PCB via redistribution layers, substrate, and PCB.

[0205] Figure 3_4-g For the present invention multiple Figure 3_4 The diagram shows an array structure in which multilayer stacked 3D integrated circuit cells with rewiring layers are connected to the PCB via the rewiring layers.

[0206] Figure 4 This is a schematic diagram of the interconnection topology between multiple packaging units of the present invention. Detailed Implementation

[0207] The invention will be further described in detail below with reference to the specific embodiments and accompanying drawings. Except for the contents specifically mentioned below, the processes, conditions, and experimental methods for implementing the invention are all common knowledge and general knowledge in the art, and the invention does not have any particular limitations.

[0208] 1. When the area of ​​a single DRAM die is more than twice the area of ​​a single logic die, 3D CoW packaging is used.

[0209] On a DRAM wafer, each DRAM die corresponds to multiple logic dies. The number of logic dies is unlimited, but their total area cannot exceed that of the DRAM dies. The back metal layer of the logic dies is connected to the DRAM dies via hybrid bonding. After each DRAM die on the DRAM wafer is aligned with the logic die, it is diced. Each diced cell contains one DRAM die and multiple logic dies stacked on top of it. Within this cell, the signal interconnection between the DRAM dies and logic dies is completed through hybrid bonding. The diameter of the hybrid bonding pad is 1µm, and the pitch is 3.5µm.

[0210] (1) Connect this unit to the substrate via a bump. Power ground and other signals, except for the interconnect signals mentioned above, pass through the DRAM die via the TSV and are connected to the substrate via the bump, such as... Figure 1a As shown in 1c, multiple logic dies can be interconnected on the substrate via interconnect IPs.

[0211] (2) Connect this unit to the PCB via a solder ball. Power, ground, and other signals, except for the interconnect signals mentioned above, pass through the DRAM die via the TSV and are connected to the PCB via the solder ball, such as... Figure 1e As shown in 1g. Multiple logic dies can be interconnected on the PCB via interconnect IPs.

[0212] (3) Connect this unit to the redistribution layer via ubump. Power ground and other signals, except for the interconnect signals mentioned above, pass through the DRAM die via TSV and are connected to the redistribution layer via ubump. The number of redistribution layers is determined by design requirements and process technology. For example, CoWoS-R can currently achieve a maximum of 8 layers, with polyimide as the dielectric material and a line width / spacing of 2 / 2µm.

[0213] a. The redistribution layer is connected to the substrate via a bump, and then to the PCB via a solder ball, as shown below. Figure 1b As shown in Figure 1d, multiple logic dies can be interconnected at the redistribution layer via interconnect IPs.

[0214] b. The redistribution layer is connected to the PCB via a solder ball, such as... Figure 1f As shown in 1h. Multiple logic dies can be interconnected at the redistribution layer via interconnect IPs.

[0215] 2. The area of ​​a single DRAM die is equal to the area of ​​a single logic die, so we can create 3D WoW packaging for single-layer logic wafers and single-layer DRAM wafers.

[0216] (1) The back metal layer of the logic wafer is stacked with the DRAM wafer via hybrid bonding. This stack is considered as a 3D wafer unit, such as... Figure 2_1 As shown. The signal interconnection between the logic wafer and DRAM wafer within the cell is accomplished through hybrid bonding. Both the logic wafer and the DRAM wafer are 12 inches; the hybrid bonding pad has a size of 1µm and a pitch of 3.5µm.

[0217] a. Connect this 3D_wafer unit to the PCB using a solder ball. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls. Figure 2_1-1 As shown, multiple logic dies on a logic wafer can be interconnected on a PCB via interconnect IPs.

[0218] b. Connect multiple 3D wafer units to the PCB using solder balls. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls. Figure 2_1-2As shown, multiple logic dies within the same unit (the same logic wafer) and logic dies in different units can be interconnected on the PCB using interconnect IPs.

[0219] (2) The back metal layer of the logic wafer is stacked with the DRAM wafer via hybrid bonding, and the signal interconnection between the logic wafer and the DRAM wafer is completed through hybrid bonding. A redistribution layer is added below the DRAM wafer, such as... Figure 2_2 As shown. Power ground and other signals pass through the DRAM wafer via TSV and are connected to the redistribution layer via ubump. The "Logic wafer + DRAM wafer + redistribution layer" is regarded as a 3DRDL_wafer unit.

[0220] a. Connect this 3DRDL_wafer unit to the PCB using a solder ball. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls. Figure 2_2-1 As shown, multiple logic dies on a logic wafer can be interconnected on a PCB via interconnect IPs.

[0221] b. Connect multiple 3DRDL_wafer units to the PCB via solder balls. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls, such as... Figure 2_2-2 As shown, multiple logic dies within the same unit (on the same logic wafer) and logic dies in different units can be interconnected on the PCB using interconnect IPs.

[0222] (3) Cut the 3D_wafer in (1) above. The cut single logic die and single DRAM die are combined into a 3D_IC unit, such as... Figure 2_3 As shown.

[0223] a. Connect a single 3D IC unit to the substrate via a bump, and then connect it to the PCB via a solder ball, as shown below. Figure 2_3-a As shown.

[0224] b. Connect multiple 3D IC units to the substrate via a bump, treating the "3D IC + substrate" as a single unit. Then connect it to the PCB via a solder ball. Multiple such units can be placed on the PCB, such as... Figure 2_3-bAs shown, 3D IC units can be interconnected on the PCB via interconnect IPs on the logic die.

[0225] c. Connect individual 3D IC units to the PCB using solder balls, such as... Figure 2_3-c As shown.

[0226] d. Connect multiple 3D IC units to the PCB using solder balls, such as... Figure 2_3-d As shown, 3D IC units can be interconnected on the PCB via interconnect IPs on the logic die.

[0227] e. Connect multiple 3D IC units to the substrate via a bump, and then connect them to the PCB via a solder ball, such as... Figure 2_3-e As shown, 3D IC units can be interconnected on the substrate via interconnect IPs on the logic die.

[0228] f. Connect multiple 3D IC units to the redistribution layer via a bump, then connect the redistribution layer to the substrate via a bump, and finally connect it to the PCB via a solder ball, as shown below. Figure 2_3-f As shown. 3D_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logic die.

[0229] g. Connect multiple 3D IC units to the redistribution layer via ubump, and then connect them to the PCB via solder balls, such as... Figure 2_3-g As shown. 3D_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logic die.

[0230] (4) Divide the 3DRDL_wafer in (2) above into segments. The resulting segments, "Logic die + DRAM die + RDL", are treated as a single 3DRDL_IC unit, such as... Figure 2_4 As shown.

[0231] a. Connect a single 3DRDL_IC unit to the substrate via a bump, and then connect it to the PCB via a solder ball, as follows: Figure 2_4-a As shown.

[0232] b. Connect multiple 3DRDL_IC units to the substrate via a bump, treating the "3DRDL_IC + substrate" as a single unit, and then connect it to the PCB via a solder ball. Multiple such units can be placed on the PCB, such as... Figure 2_4-b As shown, 3D IC units can be interconnected on the PCB via interconnect IPs on the logic die.

[0233] c. Connect a single 3DRDL_IC unit to the PCB via a solder ball, such as... Figure 2_4-c As shown.

[0234] d. Connect multiple 3DRDL_IC units to the PCB via solder balls, such as... Figure 2_4-d As shown, the 3DRDL_IC units can be interconnected on the PCB via interconnect IPs on the logic die.

[0235] e. Connect multiple 3DRDL_IC units to the substrate via a bump, and then connect them to the PCB via a solder ball, as shown below. Figure 2_4-e As shown, the 3DRDL_IC units can be interconnected on the substrate via interconnect IPs on the logic die.

[0236] f. Connect multiple 3DRDL_IC units to the redistribution layer via a bump, then connect the redistribution layer to the substrate via a bump, and finally connect it to the PCB via a solder ball, as shown below. Figure 2_4-f As shown. 3DRDL_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logic die.

[0237] g. Connect multiple 3DRDL_IC units to the redistribution layer via ubump, and then connect them to the PCB via solder balls, as shown below. Figure 2_4-g As shown. 3DRDL_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logic die.

[0238] 3. With the area of ​​a single DRAM die equal to that of a single Logic die, 3D WoW packaging is used for multi-layer Logic wafers and multi-layer DRAM wafers.

[0239] Multiple DRAM wafers are stacked together, with each wafer connected via hybrid bonding. Signals are transmitted between the DRAM wafers via (TSV + hybrid bonding). The number of DRAM wafers stacked is unlimited. After the DRAM wafers are stacked, they are treated as a single unit. The top DRAM wafer is connected to the back metal layer of the logic wafer via hybrid bonding, with the logic wafer placed on top. Interconnect signals between the logic wafer and the multiple DRAM wafers are connected via hybrid bonding. In this embodiment, the DRAM wafer has a TSV diameter of 2µm and a pitch of 3µm.

[0240] (1) Treat this stack as a 3D_M_wafer unit, such as Figure 3_1 As shown, the signal interconnection between the logic wafer and DRAM wafer within the cell has been achieved through hybrid bonding.

[0241] a. Connect this 3D_M_wafer unit to the PCB via a solder ball. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls, such as... Figure 3_1-a As shown, multiple logic dies on a logic wafer can be interconnected on a PCB via interconnect IPs.

[0242] b. Connect multiple 3D_M_wafer units to the PCB via solder balls. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls, such as... Figure 3_1-b As shown, multiple logic dies within the same unit (on the same logic wafer) and logic dies in different units can be interconnected on the PCB using interconnect IPs.

[0243] (2) A redistribution layer is added below the DRAM wafer. Power, ground, and other signals pass through the DRAM wafer via TSV and are connected to the redistribution layer via ubump. The "Logic wafer + DRAM wafer + redistribution layer" is considered as a single 3DRDL_M_wafer unit, such as... Figure 3_2 As shown.

[0244] a. Connect this 3DRDL_M_wafer unit to the PCB via a solder ball. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls, such as... Figure 3_2-a As shown, multiple logic dies on a logic wafer can be interconnected on a PCB via interconnect IPs.

[0245] b. Connect multiple 3DRDL_M_wafer units to the PCB using solder balls. Power, ground, and other signals besides the interconnect signals mentioned above are also connected to the PCB via solder balls. Figure 3_2-b As shown, multiple logic dies within the same unit (on the same logic wafer) and logic dies in different units can be interconnected on the PCB using interconnect IPs.

[0246] (3) The 3D_M_wafer in (1) above is cut into segments. The resulting single logic die and multiple DRAM dies are combined into a 3D_M_IC unit, such as... Figure 3_3 As shown.

[0247] a. Connect a single 3D_M_IC unit to the substrate via a bump, and then connect it to the PCB via a solder ball, as shown below. Figure 3_3-a As shown.

[0248] b. Connect multiple 3D MIC units to the substrate via a bump, treating the "3D MIC + substrate" as a single unit, and then connect it to the PCB via a solder ball. Multiple such units can be placed on the PCB, such as... Figure 3_3-b As shown, 3D_M_IC cells can be interconnected on the PCB via interconnect IPs on the logic die.

[0249] c. Connect individual 3D_M_IC cells to the PCB via solder balls, such as... Figure 3_3-c As shown.

[0250] d. Connect multiple 3D_M_IC units to the PCB using solder balls, such as... Figure 3_3-d As shown, 3D_M_IC cells can be interconnected on the PCB via interconnect IPs on the logic die.

[0251] e. Connect multiple 3D_M_IC units to the substrate via a bump, and then connect them to the PCB via a solder ball, such as... Figure 3_3-eAs shown, 3D_M_IC cells can be interconnected on the substrate via interconnect IPs on the logic die.

[0252] f. Connect multiple 3D_M_IC cells to the redistribution layer via a bump, then connect the redistribution layer to the substrate via a bump, and finally connect it to the PCB via a solder ball, as shown below. Figure 3_3-f As shown, 3D_M_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logic die.

[0253] g. Connect multiple 3D_M_IC cells to the redistribution layer via ubump, and then connect them to the PCB via solder balls, such as... Figure 3_3-g As shown, 3D_M_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logic die.

[0254] (4) Divide the 3DRDL_M_wafer in (2) above into segments. The resulting segments, "Logic die + multiple DRAM dies + RDL", are treated as a single 3DRDL_M_IC unit, such as... Figure 3_4 As shown.

[0255] a. Connect a single 3DRDL_M_IC unit to the substrate via a bump, and then connect it to the PCB via a solder ball, as follows: Figure 3_4-a As shown.

[0256] b. Connect multiple 3DRDL_M_IC units to the substrate via a bump connection, treating the "3DRDL_M_IC + substrate" as a single unit. Then connect this unit to the PCB via a solder ball. Multiple such units can be placed on the PCB. Figure 3_4-b As shown, the 3DRDL_M_IC units can be interconnected on the PCB via interconnect IPs on the logic die.

[0257] c. Connect a single 3DRDL_M_IC cell to the PCB via a solder ball, such as... Figure 3_4-c As shown.

[0258] d. Connect multiple 3DRDL_M_IC units to the PCB using solder balls, such as... Figure 3_4-d As shown, the 3DRDL_M_IC units can be interconnected on the PCB via interconnect IPs on the logic die.

[0259] e. Connect multiple 3DRDL_M_IC units to the substrate via a bump, and then connect them to the PCB via a solder ball, as shown below. Figure 3_4-eAs shown, the 3DRDL_M_IC cells can be interconnected on the substrate via interconnect IPs on the logic die.

[0260] f. Connect multiple 3DRDL_M_IC cells to the redistribution layer via a bump, then connect the redistribution layer to the substrate via a bump, and finally connect it to the PCB via a solder ball, as shown below. Figure 3_4-f As shown. 3DRDL_M_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logicdie.

[0261] g. Connect multiple 3DRDL_M_IC cells to the redistribution layer via ubump, and then connect them to the PCB via solder balls, as shown below. Figure 3_4-g As shown. 3DRDL_M_IC units can be interconnected at the redistribution layer via interconnect IPs on the Logic die.

[0262] The various 3D packaging and structures listed above all employ back-side power supply technology in logic dies. By moving the entire power distribution network to the back of the silicon wafer, the power supply network is decoupled from the interconnect signal network. All interconnect signals are interconnected on the front of the silicon wafer through traditional metal layer stacking. This allows the power supply network to directly supply power to the standard power supply via wider, lower-resistance metal lines on the back of the silicon wafer. Furthermore, the number of stacked layers for the power supply network is significantly less than the traditional metal layer stacking where both the signal and power networks are entirely on the front of the wafer. This method reduces wiring congestion, improves voltage drop, and enhances power supply performance, thereby increasing chip computing power. Additionally, by directly connecting to the source and drain of transistors on the back of the wafer via nTSVs, the area occupied by power and ground rails at the standard cell level is reduced, allowing for further scaling of the standard cell height. 3D packaging of these back-side powered chips breaks down the "memory wall" by reducing the path length between the processor and memory and increasing path bandwidth, further improving computing performance.

[0263] Meanwhile, the logic die is placed on top of the 3D package: In a 3D package, the logic die, being a high-power chip, is placed on the top layer. This allows it to directly contact external heat dissipation devices, such as vapor chambers, heat sinks, or water-cooled plates, through a thermal interface material. Compared to placing the logic die on the bottom layer, this significantly shortens the heat dissipation path, reduces heat dissipation resistance, and effectively improves heat dissipation efficiency. Placing the logic die on top also prevents its heat from "baking" the chips below, thus controlling the overall temperature within the stack.

[0264] By combining rear-mounted power supply with logic placed at the top of the 3D display, the constraints between the chip's computing power, bandwidth, and power consumption can be further balanced. This minimizes the bottleneck effect of any one factor, thus ensuring the overall system efficiency.

[0265] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0266] As used in this invention, the term "comprising" is an open-ended expression, meaning it includes the contents specified in this invention but does not exclude other aspects.

[0267] As used in this invention, the term "and / or" includes any one or more of the related listed items and all combinations thereof.

[0268] The scope of protection of this invention is not limited to the above embodiments. Any variations and advantages that can be conceived by those skilled in the art without departing from the spirit and scope of the inventive concept are included in this invention and are protected by the appended claims.

Claims

1. A 3D package based on back-side power supply technology, characterized in that, include: Logic processing unit and memory unit; wherein, The logic processing unit is fabricated using a back-side power supply process and has a front metal layer and a back metal layer. The internal interconnection signals of the logic processing unit are interconnected through the front metal layer, and the power transmission network is implemented through the back metal layer. The logic processing unit and the memory unit are stacked in a direction perpendicular to the printed circuit board or substrate, with the logic processing unit located on the top layer of the stacked structure. The back metal layer of the logic processing unit is electrically connected to the memory unit through hybrid bonding.

2. The 3D package based on back-side power supply technology according to claim 1, characterized in that, The logic processing unit includes a logic wafer or a logic chip; the memory unit includes a memory wafer or a memory chip. The logic processing unit has a finned field-effect transistor fabricated in its silicon substrate, and the back metal layer is directly connected to the finned field-effect transistor through nanoscale through-silicon vias.

3. The 3D package based on back-side power supply technology according to claim 2, characterized in that, When the area of ​​a single logic chip is less than half the area of ​​a single memory chip, the package adopts a chip-to-wafer CoW packaging structure. In the CoW packaging structure, multiple logic chips form a unit, the area of ​​which does not exceed the area of ​​a single memory chip. Each unit is evenly placed on top of the memory wafer, and each memory chip is topped with an equal number of logic chips. The back metal layer of the logic chips is connected to the memory wafer through hybrid bonding.

4. The 3D package based on back-side power supply technology according to claim 3, characterized in that, In the CoW packaging structure, after the logic chip and memory wafer are bonded together, the chip is cut. The cut memory chip is connected to the substrate through bumps and then to the printed circuit board through solder balls; or the cut memory chip is directly connected to the printed circuit board through solder balls. And / or, In the CoW packaging structure, a redistribution layer is provided below the memory wafer. The back metal layer of the logic chip is connected to the memory wafer by hybrid bonding and then cut. The power, ground, and signal layers passing through the memory wafer are connected to the redistribution layer through microbumps. The redistribution layer is connected to the substrate through bumps and then connected to the printed circuit board through solder balls from the substrate; or the redistribution layer is directly connected to the printed circuit board through solder balls. And / or, Within the unit of the CoW packaging structure, multiple logic chips are connected by dicing channels. After the unit is diced on the logic wafer, the diced units are evenly placed on top of the memory wafer, with each unit corresponding to one memory chip.

5. The 3D package based on back-side power supply technology according to claim 2, characterized in that, When the areas of the logic chip and the memory chip are equal, the package adopts a wafer-to-wafer WoW packaging structure; in the WoW packaging structure, the back metal layer of a single logic wafer is connected to a single memory wafer through hybrid bonding, and each logic chip corresponds to one memory chip, forming a 3D wafer stacking unit.

6. The 3D package based on back-side power supply technology according to claim 5, characterized in that, The 3D wafer stacking unit is directly connected to the printed circuit board via solder balls; or the 3D wafer stacking unit is cut into 3D integrated circuit units containing a single logic chip and a single memory chip stacked together, the 3D integrated circuit units are connected to the substrate via bumps, and then connected to the printed circuit board via solder balls through the substrate; or the 3D integrated circuit units are directly connected to the printed circuit board via solder balls. And / or, In the WoW packaging structure, a redistribution layer is disposed below the memory wafer. The memory wafer is connected to the redistribution layer through microbumps to form a 3D wafer stacking unit with a redistribution layer. The 3D wafer stacking unit with a redistribution layer is directly connected to the printed circuit board through solder balls. Alternatively, the 3D wafer stacking unit with a redistribution layer is cut into 3D integrated circuit units with redistribution layers. The 3D integrated circuit units with redistribution layers are connected to the substrate through bumps, and then connected to the printed circuit board through solder balls via the substrate. Alternatively, the 3D integrated circuit units with redistribution layers are directly connected to the printed circuit board through solder balls.

7. The 3D package based on back-side power supply technology according to claim 2, characterized in that, The memory cell includes at least two stacked memory wafers, which are connected by hybrid bonding and transmit signals through through-silicon vias. The top-level memory wafer is connected to the back metal layer of the logic wafer via hybrid bonding, with the logic wafer located at the top of the stacked structure.

8. The 3D package based on back-side power supply technology according to claim 7, characterized in that, The stacked structure of the logic wafer and the multilayer memory wafer forms a multilayer stacked 3D wafer unit, which is directly connected to the printed circuit board via solder balls; or the multilayer stacked 3D wafer unit is cut into multilayer stacked 3D integrated circuit units containing a single logic chip and multiple stacked memory chips, which are connected to the substrate via bumps, and then connected to the printed circuit board via solder balls through the substrate; or the multilayer stacked 3D integrated circuit units are directly connected to the printed circuit board via solder balls. And / or, A redistribution layer is disposed beneath the bottom memory wafer of the multi-layer stack. The bottom memory wafer is connected to the redistribution layer through microbumps to form a multi-layer stacked 3D wafer unit with a redistribution layer. The multi-layer stacked 3D wafer unit with a redistribution layer is directly connected to the printed circuit board through solder balls. Alternatively, the multi-layer stacked 3D wafer unit with a redistribution layer is cut into multi-layer stacked 3D integrated circuit units with redistribution layers. The multi-layer stacked 3D integrated circuit units with redistribution layers are connected to the substrate through bumps, and then connected to the printed circuit board through solder balls via the substrate. Alternatively, the multi-layer stacked 3D integrated circuit units with redistribution layers are directly connected to the printed circuit board through solder balls.

9. A working component, characterized in that, The package includes a 3D package based on back-side power supply technology as described in any one of claims 1-8, and further includes a heat dissipation device connected to the package, wherein the heat dissipation device is in direct contact with the logic processing unit on the top layer of the package through a thermal interface material.

10. A computing device, characterized in that, It includes a printed circuit board, a substrate, and a 3D package based on back-side power supply technology as described in any one of claims 1-8, the package being disposed on one side of the printed circuit board.

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