Heterojunction solar cell and manufacturing method therefor, and device

Abstract

Disclosed in the present invention are a heterojunction solar cell and a manufacturing method therefor, and a device. The manufacturing method comprises: respectively forming, on the front face and the rear face of a silicon substrate, at least one front passivation layer made of an intrinsic amorphous silicon-based material and at least one rear passivation layer made of the intrinsic amorphous silicon-based material; respectively forming, on the at least one front passivation layer and the at least one rear passivation layer, at least one front doped layer and at least one rear doped layer, which are made of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; and during the deposition of at least one of the front doped layer and the rear doped layer, placing the silicon substrate on a carrier plate, wherein one or more silicon substrate accommodating regions are provided on the upper surface of the carrier plate, and at least part of the periphery of each accommodating region is provided with a retaining edge. The present invention simplifies the manufacturing process for the heterojunction solar cell and improves the performance of the heterojunction solar cell.

Description

A heterojunction solar cell and its fabrication method and equipment Technical Field

[0001] This invention relates to a heterojunction solar cell and its fabrication method and apparatus. Background Technology

[0002] Heterojunction solar cells combine the advantages of monocrystalline and amorphous silicon solar cells, boasting simple processes, high efficiency, low temperature coefficients, and high conversion efficiency, making them a hot topic in photovoltaic research and development. The heterojunction solar cell process includes four main steps: cleaning and texturing, PECVD thin film deposition, PVD thin film deposition, and electrode metallization. Among these, the PECVD thin film deposition step is particularly critical, being the core process for forming the heterojunction ninip or nipin structure. During the PECVD fabrication of amorphous or microcrystalline silicon thin films, due to limitations in silicon substrate thinning and film deposition precision, the film inevitably extends to the side of the silicon substrate, forming a wrap-around coating. This overlap of two different doped film types causes contact conduction, resulting in shunt resistance and leakage current losses at the edges of the heterojunction solar cell, thus affecting the cell's photoelectric conversion efficiency.

[0003] In current industrial production, some attempts have been made to use specialized etching techniques to remove excess coating from the substrate edges. However, this process is often complex, increasing battery production costs and potentially damaging the battery structure. Other methods utilize masks in PECVD processes to prevent doped layers from forming around the silicon wafer edges, but face challenges in mask alignment accuracy. Furthermore, both etching and masking add extra equipment or steps to the existing PECVD process, increasing complexity and cost. Summary of the Invention

[0004] The purpose of this invention is to provide a heterojunction solar cell and its manufacturing method and apparatus.

[0005] To achieve the objective of this invention, a method for fabricating a heterojunction solar cell is proposed, employing a plate-type capacitor-coupled plasma-enhanced chemical vapor deposition (PECVD) method, comprising the following steps: providing a doped silicon substrate; forming at least one front passivation layer and at least one back passivation layer made of intrinsic amorphous silicon on the front and back sides of the silicon substrate, respectively; forming at least one front doped layer and at least one back doped layer made of microcrystalline silicon or nanocrystalline silicon on the at least one front passivation layer and the at least one back doped layer, respectively; during the deposition of at least one of the front doped layer and the back doped layer, the silicon substrate is placed on a carrier plate, the upper surface of the carrier plate having one or more silicon substrate accommodating regions, and at least a portion of the accommodating regions being surrounded by baffles.

[0006] In a preferred embodiment, the ratio of the height of the retaining edge to the thickness of the silicon substrate is in the range of 1:1 to 15:1.

[0007] In a preferred embodiment, the distance between the stop and the edge of the silicon substrate is less than 3 mm.

[0008] In a preferred embodiment, the front doped layer and the back doped layer are prepared using plate-type capacitively coupled plasma-enhanced chemical vapor deposition (PECVD), wherein the radio frequency power supply frequency is in the range of 2MHz-100MHz, and the radio frequency power supply power density is in the range of 0.05-1W / cm². 2 The range of reactant gases in the process chamber includes SiH4 and H2, with a SiH4:H2 flow ratio in the range of 1:10 to 1:1000, and the reactant gas pressure in the process chamber in the range of 1-20 Torr.

[0009] In a preferred embodiment, on the side edge of the heterojunction solar cell, in the edge region of the silicon substrate, the layers are arranged in the following order from the inside to the outside: at least one front passivation layer, and at least one back passivation layer on the at least one front passivation layer; or, at least one front passivation layer, and at least one back passivation layer on the at least one front passivation layer, and at least one front doped layer on the at least one back passivation layer; or, at least one front passivation layer, and at least one back passivation layer on the at least one front passivation layer, and at least one back doped layer on the at least one back passivation layer; or, at least one back passivation layer, and at least one front passivation layer on the at least one back passivation layer; or, at least one back passivation layer, and at least one front passivation layer on the at least one back passivation layer, and at least one front doped layer on the at least one front passivation layer; or, at least one back passivation layer, and at least one front passivation layer on the at least one back passivation layer, and at least one back doped layer on the at least one front passivation layer.

[0010] In a preferred embodiment, the silicon substrate has a first conductivity type of doping; in the front doping layer and the back doping layer, one doping type is the first conductivity type, and the other doping type is the second conductivity type opposite to the first conductivity type.

[0011] In a preferred embodiment, the method for fabricating a heterojunction solar cell further includes the following sequential steps: forming at least one transparent back conductive layer on at least one back doped layer; forming at least one transparent front conductive layer on at least one front doped layer; forming a back electrode on at least one transparent back conductive layer; and forming a front electrode on at least one transparent front conductive layer.

[0012] The present invention also proposes a heterojunction solar cell, the structure of which includes: a doped silicon substrate; at least one front passivation layer formed on the front side of the silicon substrate, which is made of an intrinsic amorphous silicon-based material; at least one front doped layer formed on the at least one front passivation layer, which is made of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; at least one back passivation layer formed on the back side of the silicon substrate, which is made of an intrinsic amorphous silicon-based material; at least one back doped layer formed on the at least one back passivation layer, which is made of a microcrystalline silicon-based material or a nanocrystalline silicon-based material; and on the side edges of the heterojunction solar cell, on the edge region of the silicon substrate, the layers are present in the following order from the inside to the outside: at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer. Alternatively, at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer, and at least one front doped layer on the at least one back passivation layer; or at least one front passivation layer, at least one back passivation layer on the at least one front passivation layer, and at least one back doped layer on the at least one back passivation layer; or at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer; or at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer, and at least one front doped layer on the at least one front passivation layer; or at least one back passivation layer, at least one front passivation layer on the at least one back passivation layer, and at least one back doped layer on the at least one front passivation layer.

[0013] In a preferred embodiment, the silicon substrate in the solar cell is doped with a first conductivity type; in the front doped layer and the back doped layer, one doping type is the first conductivity type and the other doping type is the second conductivity type opposite to the first conductivity type.

[0014] In a preferred embodiment, the silicon substrate of the solar cell is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type; or, the silicon substrate is a P-type textured silicon wafer, the first conductivity type is P-type, and the second conductivity type is N-type.

[0015] In a preferred embodiment, the solar cell includes at least one transparent front conductive layer formed on the at least one front doped layer; at least one transparent back conductive layer formed on the at least one back doped layer; a front electrode formed on the at least one transparent front conductive layer; and a back electrode formed on the at least one transparent back conductive layer.

[0016] This invention also proposes an apparatus for manufacturing heterojunction solar cells, employing plate-type capacitor-coupled plasma-enhanced chemical vapor deposition (CVD). The apparatus includes: at least one process chamber for depositing a doped layer, a gas diffuser located inside the process chamber, an RF power supply electrically connected to the gas diffuser, and a heating plate for heating. During the deposition of the doped layer, the silicon substrate is placed on a carrier plate, the upper surface of which has one or more silicon substrate accommodating regions, and at least a portion of the accommodating regions is provided with baffles.

[0017] In a preferred embodiment, the height of the baffle is greater than the thickness of the silicon substrate, and the ratio of the height of the baffle to the thickness of the silicon substrate is in the range of 1:1 to 15:1.

[0018] In a preferred embodiment, the device further includes a DC bias device, the gas diffuser serves as the upper electrode plate, and the carrier plate or the heating plate in contact with the carrier plate serves as the lower electrode plate; during the deposition of the doped layer, the DC bias device is electrically connected to the upper electrode plate and outputs a positive DC voltage to the upper electrode plate; or, during the deposition of the doped layer, the DC bias device is electrically connected to the lower electrode plate and outputs a negative DC voltage to the lower electrode plate.

[0019] In a preferred embodiment, the device further includes a heating plate lifting mechanism. During the deposition of the doped layer, the carrier plate is placed on the heating plate, and the heating plate is placed on the heating plate lifting mechanism. The distance between the lower electrode plate and the upper electrode plate is adjusted by adjusting the height of the heating plate lifting mechanism. During the preparation of the front doped layer and the back doped layer, the distance between the upper and lower electrodes is in the range of 5mm-50mm.

[0020] Compared with the prior art, the significant advantages of this invention are:

[0021] (1) In the deposition process of the front or back doped layer, the present invention uses a stop to form an electric field between the stop and the silicon substrate, which can act on charged particles. Under the action of the electric field, the charged particles bombard the edge region of the silicon substrate, preventing the formation of the front or back doped layer in the edge region of the silicon substrate. In this way, during the deposition process of the microcrystalline silicon doped layer on the front or back of the silicon substrate, the formation of the microcrystalline silicon doped layer in the edge region of the silicon substrate is simultaneously prevented, and the etching of the microcrystalline silicon doped layer in the edge region of the silicon substrate is simultaneously achieved, eliminating the need for plating around the substrate. This not only improves the fabrication efficiency of heterojunction solar cells, but also eliminates the need for additional etching or masking equipment and processes on the edge of the silicon substrate, reducing process complexity and manufacturing cost. In addition, the mask alignment accuracy problem when using a mask to prevent the formation of the doped layer in the edge region of the silicon substrate, as in the prior art, is not present, simplifying the fabrication process of heterojunction solar cells and improving the performance of heterojunction solar cells.

[0022] (2) In this invention, the process conditions such as the frequency, power, reaction gas pressure, and H2 ratio of the RF power supply are adjustable. By adjusting these process conditions, the bombardment effect of charged particles on the edge region of the silicon substrate can be enhanced or weakened according to the requirements of the solar cell. This improves the etching precision of the microcrystalline silicon doped layer in the edge region of the silicon substrate and also enables controllability of the thickness of the microcrystalline silicon doped layer in the edge region of the silicon substrate.

[0023] (3) By using a DC bias device, the present invention can apply a DC voltage to the upper or lower electrode plate, thereby changing the sheath thickness, increasing the sheath thickness on the lower electrode plate side and decreasing the sheath thickness on the upper electrode plate side, thereby adjusting the electric field strength and charged ion bombardment effect between the edge and the edge of the silicon substrate, which can further improve the fine control of etching precision intensity and precision of the microcrystalline silicon doped layer.

[0024] (4) In the process of depositing microcrystalline silicon doped layer, the carrier plate is placed on the heating plate and the heating plate is placed on the heating plate lifting mechanism. The distance between the lower electrode plate and the upper electrode plate is adjusted by adjusting the height of the heating plate lifting mechanism, thereby changing the bombardment intensity of charged particles on the edge region of the silicon substrate. This can further improve the fine control of etching precision intensity and precision of microcrystalline silicon doped layer.

[0025] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0026] Figure 1 is a schematic diagram of a solar cell structure according to an embodiment of the present invention.

[0027] Figure 2 is a schematic diagram of another solar cell structure according to an embodiment of the present invention.

[0028] Figure 3 is a schematic diagram of another solar cell structure according to an embodiment of the present invention.

[0029] Figure 4 is a schematic diagram of the principle of the accommodating area shown in an embodiment of the present invention.

[0030] Figure 5 is a schematic diagram illustrating the principle of charged particles bombarding the edge region of a silicon substrate during the fabrication of a solar cell according to an embodiment of the present invention.

[0031] Figure 6 is a schematic diagram of the effect of charged particles bombarding the edge region of the silicon substrate during the fabrication of the solar cell according to an embodiment of the present invention.

[0032] Figure 7 is a schematic diagram of a process cavity and its DC bias device in a solar cell manufacturing equipment according to an embodiment of the present invention.

[0033] Figure 8 is a schematic diagram of another process cavity and its DC bias device in the solar cell manufacturing equipment shown in the embodiment of the present invention.

[0034] Figure reference numerals: 10-Silicon substrate; 11-Front-side passivation layer; 12-Front-side doped layer; 21-Back-side passivation layer; 22-Back-side doped layer; 30-Side guard; 41-Gas diffuser; 42-Carrier plate; 43-Heating plate; 44-Lifting mechanism; 45-Gas source. Detailed Implementation

[0035] It is readily understood that, based on the technical solution of this invention, various embodiments of the invention can be conceived by those skilled in the art without altering the essential spirit of the invention. Therefore, the following detailed embodiments and accompanying drawings are merely illustrative examples of the technical solution of this invention and should not be considered as the entirety of the invention or as limitations or restrictions on the technical solution of this invention. Rather, these embodiments are provided to enable those skilled in the art to gain a more thorough understanding of the invention. Preferred embodiments of the invention are described below in conjunction with the accompanying drawings, which form part of this application and, together with the embodiments of the invention, serve to illustrate the innovative concept of the invention.

[0036] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0037] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0038] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0039] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0040] Referring to Figures 1 to 5, the heterojunction solar cell fabrication method of the present invention employs plate-type capacitor-coupled plasma-enhanced chemical vapor deposition (PECVD) and includes the following steps: providing a doped silicon substrate 10; forming at least one front passivation layer 11 and at least one back passivation layer 21 made of intrinsic amorphous silicon on the front and back sides of the silicon substrate 10, respectively; forming at least one front doped layer 12 and at least one back doped layer 22 made of microcrystalline silicon or nanocrystalline silicon on the at least one front passivation layer 11 and the at least one back passivation layer 21, respectively. In this invention, the aforementioned steps are not specifically ordered, and those skilled in the art can change the order of the aforementioned steps according to specific battery structure requirements. In the aforementioned heterojunction solar cell fabrication process, during the deposition of the front doped layer 12, or the deposition of the back doped layer 22, or both the front doped layer 12 and the back doped layer 22, the silicon substrate 10 is placed on a carrier plate. One or more silicon substrate accommodating regions are formed on the upper surface of the carrier plate, and at least a portion of the accommodating regions is provided with a retaining edge 30. Due to the presence of the retaining edge 30, during the fabrication of the front doped layer 12 or the back doped layer 22 using plate-type capacitively coupled plasma-enhanced chemical vapor deposition, an electric field capable of acting on charged particles is formed between the retaining edge and the silicon substrate 10. Under the action of this electric field, the charged particles bombard the edge region on the edge side of the silicon substrate 10, preventing the formation of the front doped layer 12 and / or the back doped layer 22 on the edge side of the silicon substrate 10. This avoids contact between the front doped layer 12 and the edge region on the edge side of the back doped layer 22 of the silicon substrate 10, improving the shunt resistance and leakage current loss at the edge of the solar cell. Simultaneously, during the deposition of the front doped layer 12 or the back doped layer 22, the present invention utilizes the edge 30 to create an electric field between the edge and the silicon substrate 10, which can act on charged particles. Under the influence of this electric field, the charged particles bombard the edge region of the silicon substrate 10, preventing the formation of the front doped layer 12 and / or the back doped layer 22 on the edge region of the silicon substrate 10. Thus, the present invention simultaneously prevents the formation of the front doped layer 12 and / or the back doped layer 22 on the edge region of the silicon substrate 10 during the deposition of the front doped layer 12 or the back doped layer 22. This not only improves the fabrication efficiency of heterojunction solar cells but also eliminates the need for additional etching or masking equipment and processes on the edge of the silicon substrate 10, reducing process complexity and manufacturing costs.

[0041] The silicon substrate is usually a silicon wafer that has undergone a texturing process. It can be a silicon wafer with texturing on one side or on both sides.

[0042] This invention employs a plate-type capacitively coupled PECVD deposition method. During the deposition of the front doped layer 12 or the back doped layer 22 in the process chamber, within the region formed by the upper electrode plate (e.g., a gas diffuser) and the lower electrode plate (e.g., a heating plate or a carrier plate), process gases such as silane and hydrogen are dissociated into plasma via radio frequency. Neutral groups and charged particles undergo a chemical reaction on the surface of the silicon substrate 10 to deposit a film, forming a microcrystalline structure under the action of high-energy ions and high hydrogen dilution. Although the plasma is electrically neutral, there is a very thin positively charged region between it and the upper and lower electrode plates, called a sheath layer. A baffle 30 is provided on the carrier plate to fix the position of the silicon wafer, and the carrier plate serves as the lower electrode plate adjacent to the sheath layer. Because the edge on the carrier plate has different electrical properties than the silicon substrate 10 material itself, there is a difference in charge accumulation, which leads to different potentials between the edge 30 and the silicon substrate 10. The potential on the silicon substrate side is low, and the potential on the edge side is high. The potential difference between the two generates a local electrostatic field. Under the action of the electric field, charged particles move towards the silicon substrate 10 with acceleration, which bombards the edge area of ​​the silicon substrate 10 and prevents the formation of the front doped layer 12 or the back doped layer 22 on the edge area of ​​the silicon substrate 10. This achieves the effect of etching the edge of the silicon substrate 10, thereby eliminating the phenomenon of plating around the edge of the silicon substrate 10 during the doping layer deposition process, that is, avoiding the overlap or contact of the front doped layer 12 and the back doped layer 22 at the edge of the silicon substrate 10.

[0043] The height of the baffle 30 is greater than the thickness of the silicon substrate 10, and the ratio of the height of the baffle 30 to the thickness of the silicon substrate 10 is in the range of 1:1 to 15:1.

[0044] The distance between the retaining edge 30 and the edge of the silicon substrate 10 is less than 3 mm.

[0045] The front doped layer 12 and the back doped layer 22 are prepared by plate-type capacitively coupled plasma-enhanced chemical vapor deposition. The radio frequency power supply frequency is in the range of 2MHz-100MHz, meaning the plasma is excited by a radio frequency power supply with a frequency of 2MHz-100MHz, and the power density of the radio frequency power supply is 0.05-1W / cm³. 2 The process chamber reactant gases include SiH4 and H2, with a SiH4:H2 flow ratio ranging from 1:10 to 1:1000, and a process chamber reactant gas pressure ranging from 1 to 20 Torr. In this invention, by adjusting the process conditions, the bombardment effect of charged particles on the edge region of the silicon substrate can be enhanced or weakened according to the requirements of the solar cell. For example, increasing the frequency, power, reactant gas pressure, and H2 content of the RF power supply can enhance the bombardment and etching effects. Conversely, decreasing these parameters weakens the bombardment and etching effects.

[0046] Under the bombardment of charged particles, different structures can be formed on the side edges of the heterojunction solar cell. For example, on the edge region of the silicon substrate 10, the layers are arranged in the following order from the inside to the outside, resulting in several different structures:

[0047] As shown in Figure 1, there is at least one front passivation layer 11 and at least one back passivation layer 21 on the at least one front passivation layer 11. That is, during the deposition of the front doped layer 12 and the back doped layer 22, charged particles are used to bombard the edge region of the silicon substrate 10, and the front doped layer 12 and the back doped layer 22 are not formed on the edge region of the silicon substrate 10. In this structure, as shown in Figure 6, a bombardment effect can also be formed locally near the side edge of the silicon substrate 10, forming an etching phenomenon on the front doped layer 12 on the front side or the back doped layer 22 on the back side of the silicon substrate 10 (the front passivation layer / back passivation layer is not shown in the figure), and the etching width varies from 0-1 mm.

[0048] Alternatively, as shown in Figure 2, there is at least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, and at least one front doped layer 12 on the at least one back passivation layer 21. That is, during the deposition of the back doped layer 22, charged particles are used to bombard the edge region of the silicon substrate 10, so that the back doped layer 22 is not formed on the edge region of the silicon substrate 10. During the deposition of the front doped layer 12, by controlling the process parameters, the electric field between the silicon substrate 10 and the carrier edge is weakened, the etching rate is lower than the deposition rate, and the front doped layer is deposited on the sidewall of the silicon substrate 10. In this way, the back doped layer 22 is not formed on the edge region of the silicon substrate 10, and only the front doped layer 12 exists.

[0049] Alternatively, as shown in Figure 3, there is at least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, and at least one back doped layer 22 on the at least one back passivation layer 21. That is, during the deposition of the back doped layer 22, by controlling process parameters, the electric field between the silicon substrate 10 and the carrier edge is weakened, the etching rate is lower than the deposition rate, and a back doped layer is deposited on the sidewall of the silicon substrate 10. During the deposition of the front doped layer 12, charged particles are used to bombard the edge region of the silicon substrate 10, and no front doped layer 12 is formed on the edge region of the silicon substrate 10. Thus, no front doped layer 12 is formed on the edge region of the silicon substrate 10, and only the back doped layer 22 exists.

[0050] Alternatively, at least one back passivation layer 21, and at least one front passivation layer 11 on the at least one back passivation layer 21. This structure differs from the structure shown in FIG1 in that the back passivation layer 21 is close to the silicon substrate 10 on the edge region of the silicon substrate 10, that is, the back passivation layer 21 is formed first, and then the front passivation layer 11 is formed. On the edge region of the silicon substrate 10, the front passivation layer 11 is located on the side surface of the back passivation layer 21 facing away from the silicon substrate 10.

[0051] Alternatively, there may be at least one back passivation layer 21, at least one front passivation layer 11 on the at least one back passivation layer 21, and at least one front doped layer 12 on the at least one front passivation layer 11. This structure differs from the structure shown in FIG2 in that the back passivation layer 21 is located close to the silicon substrate 10 in the edge region of the silicon substrate 10.

[0052] Alternatively, there may be at least one back passivation layer 21, at least one front passivation layer 11 on the at least one back passivation layer 21, and at least one back doped layer 22 on the at least one front passivation layer 11. This structure differs from the structure shown in FIG3 in that the back passivation layer 21 is located close to the silicon substrate 10 in the edge region of the silicon substrate 10.

[0053] The various specific structures described above can be selected by those skilled in the art based on the concept of this invention and in combination with specific application scenarios.

[0054] In this invention, the silicon substrate 10 is doped with a first conductivity type; in the front doped layer 12 and the back doped layer 22, one doping type is the first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type. For example, the silicon substrate 10 is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type. Alternatively, the silicon substrate 10 is a P-type textured silicon wafer, the first conductivity type is P-type, and the second conductivity type is N-type.

[0055] The fabrication process of a heterojunction solar cell is described here with reference to one embodiment. First, a crystalline silicon substrate of a first doping type is provided. At least one front passivation layer 11 and at least one back passivation layer 21, both made of intrinsic amorphous silicon, are formed on the front and back sides of the silicon substrate 10 using vacuum thin-film deposition. The front passivation layer 11 is formed by wrap-around plating, covering the sides and partial edges of the back side of the silicon substrate 10. Similarly, the back passivation layer 21 is formed by wrap-around plating, covering the sides and partial edges of the front side of the silicon substrate 10. A first microcrystalline silicon doped layer (e.g., a front doped layer) of the same doping type and a second microcrystalline silicon doped layer (e.g., a back doped layer) of the opposite doping type are formed on the front and back sides of the silicon substrate 10 using vacuum thin-film deposition. The deposition of the front and back doped layers is completed within a silicon substrate accommodating region on a carrier plate. At least a portion of the accommodating region is surrounded by a baffle 30, the height of which is greater than the thickness of the silicon wafer, and the distance between the baffle and the edge of the substrate is less than 3 mm. The doped layer is prepared using a plate-type capacitively coupled plasma-enhanced chemical vapor deposition method, with plasma excited by an RF power supply with a frequency of 2MHz-100MHz and a power density ranging from 0.05-1W / cm². 2 During the deposition of the front doped layer 12 and the back doped layer 22, charged particles are used to bombard the edge region of the silicon substrate 10. The front doped layer 12 and the back doped layer 22 are not formed on the edge region of the silicon substrate 10, i.e., no overlay is formed on the edge region of the silicon substrate 10.

[0056] For the different heterojunction solar cell fabrication methods shown in the foregoing embodiments, preferably, the conductive layers and electrodes on the front and back sides of the silicon substrate 10 are formed in the following sequence: forming at least one transparent back conductive layer (not shown in the figure) on at least one back doped layer 22; forming at least one transparent front conductive layer (not shown in the figure) on at least one front doped layer 12; forming a back electrode (not shown in the figure) on at least one transparent back conductive layer; forming a front electrode (not shown in the figure) on at least one transparent front conductive layer. The aforementioned front and back conductive layers and electrodes are conventional structures of heterojunction solar cells and will not be further described here. However, it should be noted that during the manufacturing process of the solar cell, the substrate will absorb moisture from the air. This moisture will also provide oxygen during each deposition step. However, the incident light front side of the solar cell is sensitive to oxygen and requires high oxygen control. Therefore, this invention first deposits the conductive layer on the back side of the silicon substrate 10, and then deposits the conductive layer on the front side. This facilitates further control of moisture during the front deposition process of the solar cell.

[0057] Based on various embodiments of the heterojunction solar cell fabrication method described above in this invention, heterojunction solar cells with the following structures can be prepared.

[0058] The heterojunction solar cell structure includes: a doped silicon substrate 10; at least one front passivation layer 11 formed on the front side of the silicon substrate 10, made of intrinsic amorphous silicon; at least one front doped layer 12 formed on the at least one front passivation layer 11, made of microcrystalline silicon or nanocrystalline silicon; at least one back passivation layer 21 formed on the back side of the silicon substrate 10, made of intrinsic amorphous silicon; and at least one back doped layer 22 formed on the at least one back passivation layer 21, made of microcrystalline silicon or nanocrystalline silicon. On the side edges of the heterojunction solar cell, in the edge region of the silicon substrate 10, the layers are arranged in the following different structures from the inside out:

[0059] At least one front passivation layer 11, and at least one back passivation layer 21 on the at least one front passivation layer 11; or,

[0060] At least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, and at least one front doped layer 12 on the at least one back passivation layer 21; or,

[0061] At least one front passivation layer 11, at least one back passivation layer 21 on the at least one front passivation layer 11, and at least one back doped layer 22 on the at least one back passivation layer 21; or,

[0062] At least one back passivation layer 21, and at least one front passivation layer 11 on the at least one back passivation layer 21; or,

[0063] At least one back passivation layer 21, at least one front passivation layer 11 on the at least one back passivation layer 21, and at least one front doped layer 12 on the at least one front passivation layer 11; or,

[0064] At least one back passivation layer 21, at least one front passivation layer 11 on the at least one back passivation layer 21, and at least one back doped layer 22 on the at least one front passivation layer 11.

[0065] In the heterojunction solar cells with the above-described structures, at least one transparent front conductive layer is formed on the at least one front doped layer 12; at least one transparent back conductive layer is formed on the at least one back doped layer 22; a front electrode is formed on the at least one transparent front conductive layer; and a back electrode is formed on the at least one transparent back conductive layer. The aforementioned front and back conductive layers and electrodes are conventional structures of heterojunction solar cells and will not be further described here.

[0066] In the heterojunction solar cells with the above-described structures, the silicon substrate 10 is doped with a first conductivity type; in the front doped layer 12 and the back doped layer 22, one doping type is the first conductivity type, and the other doping type is a second conductivity type opposite to the first conductivity type. Specifically, the silicon substrate 10 is an N-type textured silicon wafer, the first conductivity type is N-type, and the second conductivity type is P-type; or, the silicon substrate 10 is a P-type textured silicon wafer, the first conductivity type is P-type, and the second conductivity type is N-type.

[0067] The present invention also proposes an apparatus for manufacturing heterojunction solar cells applicable to the aforementioned fabrication method and battery structure, employing plate-type capacitor-coupled plasma-enhanced chemical vapor deposition. The apparatus includes: at least one process cavity for depositing a doped layer, a gas diffuser located inside the process cavity, a radio frequency power supply RF electrically connected to the gas diffuser, and a heating plate for heating. During the deposition of the doped layer, the silicon substrate 10 is placed on a carrier plate, and one or more silicon substrate accommodating regions are provided on the upper surface of the carrier plate, with at least a portion of the accommodating regions surrounded by a retaining edge 30.

[0068] The height of the retaining edge 30 is greater than the thickness of the silicon substrate 10, and the ratio of the height of the retaining edge 30 to the thickness of the silicon substrate 10 is in the range of 1:1 to 15:1. The distance between the retaining edge 30 and the edge of the silicon substrate 10 is less than 3 mm.

[0069] The radio frequency power supply has a frequency range of 2MHz-100MHz, and the plasma is excited by the radio frequency power supply with a frequency range of 2MHz-100MHz. The power density of the radio frequency power supply is 0.05-1W / cm³. 2 The process chamber reactant gases include SiH4 and H2, with a SiH4:H2 flow ratio ranging from 1:10 to 1:1000, and the process chamber reactant gas pressure ranging from 1 to 20 Torr. The bombardment intensity of charged particles on the edge region of the silicon substrate 10 can be altered by adjusting at least one of the RF power supply frequency, RF power supply power density, process chamber reactant gas pressure, and H2 flow ratio.

[0070] As shown in Figure 7 or Figure 8, the process cavity adopts planar capacitor coupling technology. The process cavity is externally connected to an RF power supply, a vacuum system, and a gas source 45. Internally, there is a discharge structure connected to the RF power supply, a heating plate 43, and a carrier plate 42 for holding the silicon substrate.

[0071] As shown in Figure 4, the upper surface of the carrier plate 42 has multiple silicon substrate accommodating regions. Each accommodating region is surrounded by a retaining edge 30, the height of which is greater than the thickness of the silicon substrate 10. The distance between the retaining edge 30 and the edge of the silicon substrate 10 is less than 3 mm. A ratio of 1:1 to 15:1 is preferred for the height of the retaining edge 30 to the thickness of the silicon substrate 10. If the ratio is too low, the electric field area is too small, preventing charged particles from bombarding and etching to the edge area of ​​the silicon substrate. If the ratio is too high, the retaining edge will have a shadowing effect, leading to abnormal doped layer deposition in localized areas near the edge on the front or back side of the silicon substrate, or even no doped layer formation at all.

[0072] As shown in Figure 7 or Figure 8, the discharge structure includes a gas diffuser 41 serving as an upper electrode plate, a carrier plate 42 serving as a lower electrode plate, or a heating plate 43 in contact with the carrier plate.

[0073] Preferably, the device further includes a heating plate lifting mechanism 44. The position of the lower electrode plate is adjusted via the heating plate lifting mechanism 44, thereby adjusting the distance between the upper and lower electrode plates during the process, and better controlling the deposition quality of the microcrystalline silicon thin film and the bombardment and etching effects at the edges. During the deposition of the doped layer, the carrier plate 42 is placed on the heating plate, and the heating plate 43 is placed on the heating plate lifting mechanism 44. The distance between the lower and upper electrode plates is adjusted by regulating the height of the heating plate lifting mechanism 44, thereby changing the bombardment intensity of charged particles on the edge region of the silicon substrate 10.

[0074] As an optimization method, the device further includes a DC bias device DC, the gas diffuser 41 serves as the upper electrode plate, and the carrier plate 42 or the heating plate 43 in contact with the carrier plate serves as the lower electrode plate; during the deposition of the doped layer, the DC bias device DC is electrically connected to the upper electrode plate and outputs a positive DC voltage to the upper electrode plate; or, during the deposition of the doped layer, the DC bias device is electrically connected to the lower electrode plate and outputs a negative DC voltage to the lower electrode plate.

[0075] By applying a DC bias device (DC) to the upper electrode plate (gas diffuser) or the lower electrode plate (heating plate or carrier plate), the sheath thickness can be further changed, making the sheath thickness on the lower electrode plate side thicker and the sheath thickness on the upper electrode plate side thinner. This adjusts the electric field strength and charged ion bombardment effect between the edge of the barrier and the edge of the silicon substrate, thereby controlling the intensity of the etching effect.

[0076] In one implementation, when preparing N-type and P-type doped layers using a microcrystalline process, as shown in Figure 7, during the deposition of the doped layers, the DC bias device (DC) is electrically connected to the upper electrode plate (gas diffuser 41), outputting a positive DC voltage to the upper electrode plate. At this time, the positive DC voltage cancels out the sheath voltage near the upper electrode plate, resulting in thinning of the sheath layer at the upper electrode plate. Based on the sheath symmetry theory, the sheath layer near the lower electrode plate thickens, enhancing the electric field between the carrier plate edge and the silicon substrate edge. This strengthens the bombardment effect of charged ions on the silicon substrate edge, thus enhancing the etching process.

[0077] In another implementation, when preparing N-type and P-type doped layers using a microcrystalline process, as shown in Figure 8, during the deposition of the doped layers, the DC bias device (DC) is electrically connected to the lower electrode plate (heating plate 43 or carrier plate 42), outputting a negative DC voltage to the lower electrode plate. At this time, the negative DC voltage enhances the sheath voltage near the lower electrode plate, also increasing the sheath thickness near the lower electrode plate. This similarly enhances the electric field between the carrier plate edge and the silicon substrate edge, strengthening the bombardment effect of charged ions on the silicon substrate edge and intensifying the etching process.

[0078] As a preferred embodiment, the DC bias device outputs a DC power supply voltage ranging from 0 to 1000V, and as the DC voltage increases, the area of ​​the silicon substrate without encapsulation at the edge expands.

[0079] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

[0080] It should be understood that, in order to simplify the present invention and help those skilled in the art understand its various aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes described in a single embodiment or with reference to a single figure. However, the present invention should not be construed as including all features included in the exemplary embodiments as essential technical features of the claims of this patent.

Claims

1. A method for fabricating a heterojunction solar cell, employing plate-type capacitor-coupled plasma-enhanced chemical vapor deposition, comprising the following steps: Provided a doped silicon substrate (10); At least one front passivation layer (11) made of intrinsic amorphous silicon-based material and at least one back passivation layer (21) made of intrinsic amorphous silicon-based material are formed on the front and back sides of the silicon substrate (10), respectively. At least one front doped layer (12) and at least one back doped layer (22) made of microcrystalline silicon-based material or nanocrystalline silicon-based material are formed on the at least one front passivation layer (11) and the at least one back passivation layer (21), respectively. Its features are, During the deposition of at least one of the front doped layer (12) and the back doped layer (22), the silicon substrate (10) is placed on a carrier plate having one or more silicon substrate receiving regions on the upper surface of the carrier plate, and at least a portion of the receiving regions having a retaining edge (30).

2. The method of claim 1, wherein, The ratio of the height of the retaining edge (30) to the thickness of the silicon substrate (10) is in the range of 1:1 to 15:

1.

3. The method of claim 1, wherein, The distance between the stop (30) and the edge of the silicon substrate (10) is less than 3 mm.

4. The method of claim 1, wherein, The front doped layer (12) and the back doped layer (22) are prepared by plate-type capacitively coupled plasma-enhanced chemical vapor deposition, wherein the radio frequency power supply frequency is in the range of 2MHz-100MHz and the radio frequency power supply power density is 0.05-1W / cm². 2 The range of reactant gases in the process chamber includes SiH4 and H2, with a SiH4:H2 flow ratio in the range of 1:10 to 1:1000, and the reactant gas pressure in the process chamber in the range of 1-20 Torr.

5. The method of claim 1, wherein, On the side edges of the heterojunction solar cell, and on the edge region of the silicon substrate (10), the film layers exist in the following order from the inside to the outside: At least one front passivation layer (11), and at least one back passivation layer (21) on the at least one front passivation layer (11); or, At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one front doped layer (12) on the at least one back passivation layer (21); or, At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one back doped layer (22) on the at least one back passivation layer (21); or, At least one back passivation layer (21), and at least one front passivation layer (11) on the at least one back passivation layer (21); or, At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), and at least one front doped layer (12) on the at least one front passivation layer (11); or, At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), and at least one back doped layer (22) on the at least one front passivation layer (11).

6. The method according to claim 1, characterized in that, The silicon substrate (10) has a first conductivity type of doping; in the front doping layer (12) and the back doping layer (22), one of the doping types is the first conductivity type and the other doping type is the second conductivity type opposite to the first conductivity type.

7. The method of claim 6, wherein, It also includes the following steps in sequence: At least one transparent back conductive layer is formed on at least one back doped layer (22); At least one transparent front conductive layer is formed on at least one front doped layer (12); A back electrode is formed on at least one transparent back conductive layer; A front electrode is formed on at least one transparent front conductive layer.

8. A heterojunction solar cell, characterized by, The structure of the heterojunction solar cell includes: A doped silicon substrate (10); At least one front passivation layer (11) made of intrinsic amorphous silicon-based material is formed on the front side of the silicon substrate (10). At least one front-side doped layer (12) formed on the at least one front-side passivation layer (11) and composed of microcrystalline silicon-based material or nanocrystalline silicon-based material; At least one back passivation layer (21) made of intrinsic amorphous silicon-based material is formed on the back side of the silicon substrate (10); At least one back doped layer (22) formed on the at least one back passivation layer (21) and composed of microcrystalline silicon-based material or nanocrystalline silicon-based material; On the side edges of the heterojunction solar cell, and on the edge region of the silicon substrate (10), the layers exist in the following order from the inside to the outside: At least one front passivation layer (11), and at least one back passivation layer (21) on the at least one front passivation layer (11); or, At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one front doped layer (12) on the at least one back passivation layer (21); or, At least one front passivation layer (11), at least one back passivation layer (21) on the at least one front passivation layer (11), and at least one back doped layer (22) on the at least one back passivation layer (21); or, At least one back passivation layer (21), and at least one front passivation layer (11) on the at least one back passivation layer (21); or, At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), and at least one front doped layer (12) on the at least one front passivation layer (11); or, At least one back passivation layer (21), at least one front passivation layer (11) on the at least one back passivation layer (21), and at least one back doped layer (22) on the at least one front passivation layer (11).

9. The solar cell according to claim 8, characterized in that, The silicon substrate (10) has a first conductivity type of doping; in the front doping layer (12) and the back doping layer (22), one of the doping types is the first conductivity type and the other doping type is the second conductivity type opposite to the first conductivity type.

10. The solar cell according to claim 9, characterized in that, The silicon substrate (10) is an N-type textured silicon wafer, wherein the first conductivity type is N-type and the second conductivity type is P-type; or, The silicon substrate (10) is a P-type textured silicon wafer, with the first conductivity type being P-type and the second conductivity type being N-type.

11. The solar cell according to claim 8, characterized in that, At least one transparent front conductive layer is formed on the at least one front doped layer (12); At least one transparent back conductive layer is formed on the at least one back doped layer (22); A front electrode is formed on the at least one transparent front conductive layer; A back electrode is formed on the at least one transparent back conductive layer.

12. An apparatus for manufacturing heterojunction solar cells, employing plate-type capacitor-coupled plasma-enhanced chemical vapor deposition, the apparatus comprising: At least one process cavity for depositing doped layers, The gas diffuser is located inside the process chamber. The radio frequency power supply electrically connected to the gas diffuser, Heating plate for heating, Its features are, During the deposition of the doped layer, the silicon substrate (10) is placed on a carrier plate, and one or more silicon substrate receiving regions are provided on the upper surface of the carrier plate, with at least a portion of the receiving regions surrounded by a retaining edge (30).

13. The apparatus of claim 12, wherein, The height of the baffle (30) is greater than the thickness of the silicon substrate (10), and the ratio of the height of the baffle (30) to the thickness of the silicon substrate (10) is in the range of 1:1 to 15:

1.

14. The apparatus of claim 12, wherein, The distance between the stop (30) and the edge of the silicon substrate (10) is less than 3 mm.

15. The apparatus of claim 12, wherein, The front doped layer (12) and the back doped layer (22) are prepared by plate-type capacitively coupled plasma-enhanced chemical vapor deposition. The radio frequency power supply frequency is in the range of 2MHz-100MHz, and the radio frequency power supply power density is in the range of 0.05-1W / cm². 2 The range of reactant gases in the process chamber includes SiH4 and H2, with a SiH4:H2 flow ratio in the range of 1:10 to 1:1000, and the reactant gas pressure in the process chamber in the range of 1-20 Torr.

16. The apparatus of claim 12, wherein, The device also includes a DC bias device, the gas diffuser (41) serves as the upper electrode plate, and the carrier plate (42) or the heating plate (43) in contact with the carrier plate serves as the lower electrode plate. During the deposition of the doped layer, the DC bias device is electrically connected to the upper electrode plate, outputting a positive DC voltage to the upper electrode plate; or, During the deposition of the doped layer, the DC bias device is electrically connected to the lower electrode plate and outputs a negative DC voltage to the lower electrode plate.

17. The device according to claim 16, characterized in that, It also includes a heating plate lifting mechanism (44). During the deposition of the doped layer, the carrier plate (42) is placed on the heating plate (43), and the heating plate (43) is placed on the heating plate lifting mechanism (44). The distance between the lower electrode plate and the upper electrode plate is adjusted by adjusting the height of the heating plate lifting mechanism (44). During the preparation of the front doped layer (12) and the back doped layer (22), the distance between the upper and lower electrodes is in the range of 5mm-50mm.

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