Display panel and display apparatus

Abstract

A display panel, comprising a plurality of first data lines (D1) and a plurality of second data lines (D2), which all extend in a first direction (DR1) in a display region (AA) and are alternately arranged in a second direction (DR2) that is different from the first direction (DR1), wherein the first data line (D1), the projection of which from the first direction (DR1) to the second direction (DR2) overlaps with the projections of a through hole (TH) and / or a winding region (RA) from the first direction (DR1) to the second direction (DR2), comprises a first data line subsection (D1-1) and a second data line subsection (D1-2), which are respectively located on two sides of the winding region (RA) in the first direction (DR1) and are connected by means of a first connection line (CL1), and the first connection line (CL1) is located in the winding region (RA); and the second data line (D2), the projection of which from the first direction (DR1) to the second direction (DR2) overlaps with the projections of the through hole (TH) and / or the winding region (RA) from the first direction (DR1) to the second direction (DR2), comprises a third data line subsection (D2-1) and a fourth data line subsection (D2-2), which are respectively located on the two sides of the winding region (RA) in the first direction (DR1) and are connected by means of a second connection line (CL2), and the second connection line (CL2) is located in the display region (AA).

Description

Display panel and display device Technical Field

[0001] This invention relates to display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous iteration and upgrading of display technology, organic light-emitting diode (OLED) display panels are gradually replacing liquid crystal (LCD) display panels. Currently, the production cost of OLED display panels is still relatively high, therefore reducing production costs is an important consideration in the development of display panels. Summary of the Invention

[0003] On one hand, this disclosure provides a display panel, including: a through hole; a display area surrounding the through hole and configured to display an image; and a winding area located between the through hole and the display area, wherein the display panel includes a plurality of first data lines and a plurality of second data lines, the plurality of first data lines and the plurality of second data lines extending along a first direction in the display area and alternately arranged along a second direction, the first direction being different from the second direction; the first data lines whose projection along the first direction onto the second direction overlaps with the projections of the through hole and / or the winding area along the first direction onto the second direction, including a first branch of the data line. The data cable includes a first part and a second part, wherein the first part and the second part are respectively located on both sides of the winding area along the first direction and connected by a first connecting line located in the winding area; and a second data cable, including a third part and a fourth part, wherein the third part and the fourth part are respectively located on both sides of the winding area along the first direction and connected by a second connecting line located in the display area.

[0004] Optionally, the minimum spacing between two adjacent first connecting lines is in the range of 2.0 μm to 2.5 μm.

[0005] Optionally, the minimum spacing between two adjacent second connecting lines is in the range of 2.0 μm to 2.5 μm.

[0006] Optionally, the first data line is configured to provide a data signal to the green sub-pixel, and the second data line is configured to provide a data signal to the red sub-pixel and / or the blue sub-pixel.

[0007] Optionally, the first data line is provided with a first multiplexer switch, which is configured to control the conduction and cutoff of data signals on the first data line; the second data line is provided with a second multiplexer switch, which is configured to control the conduction and cutoff of data signals on the second data line; and the first data line and an adjacent second data line are connected to the same signal lead.

[0008] Optionally, the second connecting line includes a first connecting line portion, a second connecting line portion, and a third connecting line portion connected to each other, wherein the third connecting line portion is connected to the first connecting line portion and the third connecting line portion is connected to the fourth connecting line portion, wherein the first connecting line portion and the third connecting line portion are parallel to each other and / or the first connecting line portion and the third connecting line portion are parallel to each other and have the same length.

[0009] Optionally, the first portion and the third portion of the connecting line extend along the second direction; and the second portion of the connecting line extends along the first direction.

[0010] Optionally, the display panel includes: a substrate; a gate insulating layer located on the substrate; a first gate metal layer located on the side of the gate insulating layer away from the gate insulating layer; a second insulating layer located on the side of the first gate metal layer away from the gate insulating layer; a second gate metal layer located on the side of the second insulating layer away from the gate insulating layer; an interlayer dielectric layer located on the side of the second gate metal layer away from the gate insulating layer; a first signal line layer located on the side of the interlayer dielectric layer away from the gate insulating layer; a passivation layer and / or a first planarization layer located on the side of the first signal line layer away from the gate insulating layer; and a second signal layer located on the side of the passivation layer and / or the first planarization layer away from the gate insulating layer.

[0011] Optionally, the third portion of the data line is located in the second signal line layer and connected to the second connecting line through a first via, at least a portion of the second connecting line connected to the third portion of the data line is located in the first signal line layer, and the first via extends through the passivation layer and / or the first planarization layer; and the second connecting line is connected to the fourth portion of the data line through a second via, the third portion of the data line is located in the second signal line layer, at least a portion of the second connecting line connected to the fourth portion of the data line is located in the first signal line layer, and the second via extends through the passivation layer and / or the first planarization layer.

[0012] Optionally, the second connection line includes a first connection line portion, a second connection line portion, and a third connection line portion connected to each other, wherein the first connection line portion and the third connection line portion are both located on the first signal line layer, the third data line portion is connected to the first connection line portion through the first via, and the third connection line portion is connected to the fourth data line portion through the second via.

[0013] Optionally, the second connecting line includes a first connecting line portion, a second connecting line portion, and a third connecting line portion connected to each other. The first connecting line portion and the third connecting line portion are located on the same layer, and the second connecting line portion is located on a layer different from the first connecting line portion and the third connecting line portion. The first connecting line portion is connected to the second connecting line portion through a third via, and the second connecting line portion is connected to the third connecting line portion through a fourth via.

[0014] Optionally, the first portion and the third portion of the connecting line are both located in the first signal line layer, the second portion of the connecting line is located in the second signal line layer, and the fourth via and the third via both extend through the passivation layer and / or the first planarization layer.

[0015] Optionally, the first portion and the second portion of the data line are both located in the second signal line layer, the first connecting line is located in the second signal line layer, and the first portion, the second portion, and the first connecting line form an integral structure.

[0016] Optionally, the first portion and the second portion of the data line are both located in the second signal line layer, the first connecting line is located in the first signal line layer, and the first portion of the data line is connected to the first connecting line through a fifth via, the first connecting line is connected to the second portion of the data line through a sixth via, and the fifth via and the sixth via both extend through the passivation layer and / or the first planarization layer.

[0017] Optionally, the first portion and the second portion of the data line are both located in the second signal line layer, the first connecting line is located in the second gate metal layer, and the first portion of the data line is connected to the first connecting line through a seventh via, the first connecting line is connected to the second portion of the data line through an eighth via, and the seventh via and the eighth via both extend through the passivation layer and / or the first planarization layer, and the interlayer dielectric layer.

[0018] Optionally, the first portion and the second portion of the data line are both located on the second signal line layer, the first connecting line is located on the first gate metal layer, and the first portion of the data line is connected to the first connecting line through a ninth via, the first connecting line is connected to the second portion of the data line through a tenth via, and the ninth and tenth vias both extend through the passivation layer and / or the first planarization layer, the interlayer dielectric layer, and the second insulating layer.

[0019] On the other hand, this disclosure provides a display device including the array substrate described herein, one or more integrated circuits connected to the array substrate, and a power supply component that provides power to the display panel and the integrated circuits. Attached Figure Description

[0020] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0021] Figure 1 is a plan view of a display panel according to some embodiments of the present disclosure.

[0022] Figure 2 illustrates the connection of data lines and signal leads in a display panel according to some embodiments of the present disclosure.

[0023] Figure 3 is a schematic diagram showing the connecting lines in the winding area of ​​a display panel according to some embodiments of the present disclosure.

[0024] Figure 4 is a cross-sectional view showing a detailed structure in a display area of ​​a display panel according to some embodiments of the present disclosure.

[0025] Figure 5 is a plan view illustrating the structure in the winding region of a display panel according to some embodiments of the present disclosure.

[0026] Figure 6 is an enlarged view showing the structure in region Z1 of Figure 5.

[0027] Figure 7 is an enlarged view showing the structure in region Z2 of Figure 5.

[0028] Figure 8 shows a comparison between the normal screen and the overloaded screen.

[0029] Figure 9 illustrates a defect in the display panel of some embodiments of the present disclosure when displaying a heavy load screen.

[0030] Figure 10 shows the switch drive signal that drives the multiplexer switch shown in Figure 2 and the gate drive signal that drives the gate lines in the display panel.

[0031] Figure 11 is a plan view of a display panel according to some embodiments of the present disclosure.

[0032] Figure 12 illustrates the connection of data lines and signal leads in a display panel according to some embodiments of the present disclosure.

[0033] Figure 13 is a schematic diagram showing the connecting lines in the winding area of ​​a display panel according to some embodiments of the present disclosure.

[0034] Figure 14 is a cross-sectional view showing a detailed structure in a display area of ​​a display panel according to some embodiments of the present disclosure.

[0035] Figure 15 is a plan view showing the structure of a first connecting line in a display panel according to some embodiments of the present disclosure.

[0036] Figure 16 is an enlarged view showing the structure in region Z3 of Figure 15.

[0037] Figure 17 is an enlarged view showing the structure in region Z4 of Figure 15.

[0038] Figure 18 is a plan view showing the structure of a second data line in a display panel according to some embodiments of the present disclosure.

[0039] Figure 19 is a plan view showing the structure of a second connecting line in a display panel according to some embodiments of the present disclosure.

[0040] Figure 20 is an enlarged view showing the structure in region Z5 of Figure 19.

[0041] Figure 21 is an enlarged view showing the structure in region Z6 of Figure 19.

[0042] Figure 22 is a plan view showing the structure of a first connecting line in a display panel according to some embodiments of the present disclosure.

[0043] Figure 23 is an enlarged view showing the structure in region Z7 of Figure 22.

[0044] Figure 24 is an enlarged view showing the structure in region Z8 of Figure 22.

[0045] Figure 25 is a plan view showing the structure of a first connecting line in a display panel according to some embodiments of the present disclosure.

[0046] Figure 26 is an enlarged view showing the structure in region Z9 of Figure 25.

[0047] Figure 27 is an enlarged view showing the structure in region Z10 of Figure 25.

[0048] Figure 28 is a plan view showing the structure of a first connecting line in a display panel according to some embodiments of the present disclosure.

[0049] Figure 29 is an enlarged view showing the structure in region Z11 of Figure 28.

[0050] Figure 30 is an enlarged view showing the structure in region Z12 of Figure 28. Detailed Implementation

[0051] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0052] Figure 1 is a plan view of a display panel according to some embodiments of the present disclosure. Referring to Figure 1, the display panel includes: a through-hole TH configured to accommodate external electronic components such as a camera; a display area AA surrounding the through-hole TH and configured to display an image; and a winding area RA located between the through-hole TH and the display area AA.

[0053] In some embodiments, the display panel includes a plurality of first data lines D1 and a plurality of second data lines D2. In some embodiments, as shown in FIG1, the plurality of first data lines D1 and the plurality of second data lines D2 all extend along a first direction DR1 in the display area and are alternately arranged along a second direction DR2. In some embodiments, the first direction DR1 is different from the second direction DR2; for example, the first direction DR1 is perpendicular to the second direction DR2.

[0054] As shown in Figure 1, the first data line D1, whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through-hole TH and / or the winding region RA along the first direction DR1 onto the second direction DR2, includes a first data line portion D1-1 and a second data line portion D1-2. In some embodiments, the first data line portion D1-1 and the second data line portion D1-2 are located on both sides of the winding region TH along the first direction DR1, and are connected by a first connecting line CL1, wherein the first connecting line CL1 is located in the winding region RA.

[0055] As shown in Figure 1, the second data line D2, whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through-hole TH and / or the winding region RA along the first direction DR1 onto the second direction DR2, includes a third data line portion D2-1 and a fourth data line portion D2-2. In some embodiments, the third data line portion D2-1 and the fourth data line portion D2-2 are located on both sides of the winding region RA along the first direction DR1, and are connected by a second connecting line CL2, wherein the second connecting line CL2 is located in the winding region RA.

[0056] As shown in Figure 1, in some embodiments, a first data line D1 and an adjacent second data line D2 are connected to the same signal lead SL, which is connected to the data drive circuit DDC via a fan-out line FL located in the fan-out region.

[0057] Figure 2 illustrates the connection of data lines and signal leads in a display panel according to some embodiments of the present disclosure. Referring to Figure 2, in a first data line D1 and a second data line D2 connected to the same signal lead SL, the first data line D1 is configured to provide a data signal to the green sub-pixel g; the second data line D2 is configured to provide a data signal to the red sub-pixel r and / or the blue sub-pixel b. As shown in Figure 2, a first multiplexer switch MUX1 is provided in the first data line D1, which is configured to control the on and off of the data signal on the first data line D1. As shown in Figure 2, a second multiplexer switch MUX2 is provided in the second data line D2, which is configured to control the on and off of the data signal on the second data line D2.

[0058] By connecting the first data line D1 and its adjacent second data line D2 to the same signal lead SL, the number of signal leads SL can be halved. This means that the size of the data drive circuit DDC can be reduced, thereby reducing the cost of the data drive circuit DDC and thus reducing the production cost of the display panel.

[0059] Figure 3 is a schematic diagram showing the connecting lines in the winding area of ​​a display panel according to some embodiments of the present disclosure. As shown in Figure 3, in some embodiments, a first data line D1 whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through hole TH and / or the projection of the winding area RA along the first direction DR1 onto the second direction DR2 includes a first data line portion D1-1 and a second data line portion D1-2. In some embodiments, the first data line portion D1-1 and the second data line portion D1-2 are respectively located on both sides of the winding area RA along the first direction DR1 and connected by a first connecting line CL1, wherein the first connecting line CL is located in the winding area RA. As shown in Figure 3, in some embodiments, a second data line D2 whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through hole TH and / or the projection of the winding area RA along the first direction DR1 onto the second direction DR2 includes a third data line portion D2-1 and a fourth data line portion D2-2. In some embodiments, the third data line portion D2-1 and the fourth data line portion D2-2 are located on both sides of the winding region RA along the first direction DR1, and are connected by a second connecting line CL2, wherein the second connecting line CL2 is located in the winding region RA.

[0060] Figure 4 is a cross-sectional view illustrating a detailed structure in a display region of a display panel according to some embodiments of the present disclosure. Referring to Figure 4, in some embodiments, the display panel includes in the display region: a substrate BS (e.g., a flexible substrate); an active layer ACT of each thin-film transistor in a plurality of thin-film transistors (TFTs) located on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both part of a first gate metal layer Gate1) located on the side of the gate insulating layer GI away from the substrate BS; a second insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second gate metal layer Gate2) located on the side of the second insulating layer IN away from the gate insulating layer GI; and an interlayer dielectric layer ILD located on the side of the second capacitor electrode... Ce2 on the side away from the gate insulating layer GI; source S and drain D (part of the first signal line layer SD1), located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; passivation layer PVX, located on the side of the source S and drain D away from the interlayer dielectric layer ILD; first planarization layer PLN1, located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; relay electrode RE (part of the second signal layer SD2), located on the side of the first planarization layer PLN1 away from the passivation layer PVX; second planarization layer PLN2, located on the side of the relay electrode RE away from the first planarization layer PLN1; pixel defining layer PDL, defining a sub-pixel opening and located on the side of the second planarization layer PLN2 away from the substrate BS; and light-emitting element LE, located in the sub-pixel opening. The light-emitting element LE includes: an anode AD located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light-emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display panel also includes an encapsulation layer EN in the display area, which encapsulates the light-emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.

[0061] Referring to Figure 4, the display panel includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SD1, and a second signal line layer SD2. The display panel also includes: a gate insulating layer GI located between the active layer ACT and the second gate metal layer Gate2; a second insulating layer IN located between the first gate metal layer Gate1 and the second gate metal layer Gate2; an interlayer dielectric layer ILD located between the second gate metal layer Gate2 and the first signal line layer SML1; and a passivation layer PVX and a first planarization layer PLN1 located between the first signal line layer SD1 and the second signal line layer SD2. Optionally, the display panel does not include the passivation layer PVX in the display area; for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0062] In some embodiments, the first data line portion D1-1, the second data line portion D1-2, the third data line portion D2-1, and the fourth data line portion D2-2 are all located on the second signal line layer SD2.

[0063] Figure 5 is a plan view showing the structure in the winding region of a display panel according to some embodiments of the present disclosure. Figure 6 is an enlarged view showing the structure in region Z1 of Figure 5. Figure 7 is an enlarged view showing the structure in region Z2 of Figure 5.

[0064] As shown in Figures 5 and 6, the edge EG of the through-hole TH forms the boundary between the through-hole TH and the winding area RA. The through-hole TH is formed by cutting the display panel; therefore, the edge EG of the through-hole TH is the cutting line when cutting the display panel.

[0065] Furthermore, Figures 5 and 6 also show a virtual dividing line DBL between the winding area RA and the display area AA. It should be noted that, unlike the edge EG of the via TH, the virtual dividing line DBL is a virtual line created to more clearly show the division between the winding area RA and the display area AA, and does not actually exist.

[0066] As shown in Figures 5 and 6, the first section D1-1 of the data line is connected to the first connecting line CL1; the third section D2-1 of the data line is connected to the second connecting line CL2. Multiple first connecting lines CL1 and multiple second connecting lines CL2 are arranged alternately in the direction from the virtual boundary line DBL to the edge EG.

[0067] In some embodiments, as shown in Figures 5 to 7, the first connection line CL1 is located on the second signal line layer SD2, and the second connection line CL2 is located on the first signal line layer SD1. The first data line segment D1-1 and the first connection line CL1 are integral structures located on the same layer; the third data line segment D2-1 is connected to the second connection line CL2 through a via extending through the first planarization layer PLN1 and the passivation layer PVX shown in Figure 4.

[0068] In an alternative embodiment, the first connection line CL1 may be located on the first signal line layer SD1, and the second connection line CL2 may be located on the first signal line layer. The third data line portion D2-1 and the second connection line CL2 are integral structures located on the same layer; the first data line portion D1-1 is connected to the first connection line CL1 through a via extending through the first planarization layer PLN1 and the passivation layer PVX.

[0069] As shown in Figures 5 and 6, a plurality of isolation pillars SP are provided on the side of the first connecting line CL1 and the second connecting line CL2 near the edge EG. In some embodiments, as shown in Figure 6, the plurality of isolation pillars SP includes seven isolation pillars SP disposed near the edge EG and four isolation pillars SP disposed near the first connecting line CL1 and the second connecting line CL2, with a barrier region WA between the seven isolation pillars SP and the four isolation pillars SP. One or more barriers (not shown) are provided in the barrier region WA. The isolation pillars SP are in contact with the encapsulation layer EN shown in Figure 4 and are configured to prevent external water and oxygen from entering the display panel. The barriers (not shown) are in contact with the encapsulation layer EN shown in Figure 4 and are configured to prevent the organic encapsulation sublayer IJP shown in Figure 4 from overflowing during the formation process.

[0070] As shown in Figures 5 and 7, multiple first connection lines CL1 and multiple second connection lines CL2 are arranged alternately in the direction from the virtual boundary line DBL to the edge EG. The orthographic projections of adjacent first connection lines CL1 and second connection lines CL2 on the substrate BS partially overlap each other. Furthermore, the trace lengths of the first connection lines CL1 and second connection lines CL2 in the winding region RA are relatively long. Therefore, there is a large coupling capacitance between adjacent first connection lines CL1 and second connection lines CL2.

[0071] It should be noted that there are no connecting wires for the gate wires in the winding area RA. Because the gate wires in the display panel are driven on both sides, even if the gate wires are broken at the via TH, they can still be driven by the gate drive circuits on both sides of the display panel. Therefore, there is no need to set connecting wires for the gate wires in the winding area RA, thereby reducing the difficulty of wiring.

[0072] Figure 8 shows a comparison between the normal and overloaded screens. As shown in Figure 8, in the normal screen, each sub-pixel is illuminated according to its corresponding grayscale. However, in the overloaded screen, as shown in Figure 8, the top two rows of sub-pixels are not illuminated, thus displaying black lines, while the bottom two rows of sub-pixels are illuminated, thus displaying white lines; throughout the entire display panel, the two rows of sub-pixels that are not illuminated alternate with the two rows of illuminated sub-pixels.

[0073] The inventors of this disclosure discovered that the display panel does not exhibit any display defects when displaying normal images. However, when the display panel displays heavy-load images, vertical white bars appear.

[0074] Figure 9 illustrates a defect in the display panel when displaying a heavy-load screen according to some embodiments of the present disclosure. In Figure 9, the left side shows a schematic diagram of the defect, and the right side shows the actual defect. As shown in Figure 9, when the display panel displays a heavy-load screen, a vertical white bar appears at the position where it overlaps with the through-hole vertically. This vertical white bar is marked with a dashed box in the right side of Figure 9. In addition, there are also horizontal bright lines in the right side of Figure 9, which are other defects unrelated to the defects discussed in this disclosure and will not be described in detail.

[0075] The reasons for the appearance of the vertical white bars in Figure 9 will be analyzed in detail below.

[0076] Figure 10 shows the switch drive signals that drive the multiplexer switches shown in Figure 2 and the gate drive signals that drive the gate lines in the display panel. Referring to Figures 2 and 10, both the first multiplexer switch MUX1 and the second multiplexer switch MUX2 in Figure 2 are active low. That is, when a low level is applied to the gate of the first multiplexer switch MUX1, the first multiplexer switch MUX1 is turned on; when a high level is applied to the gate of the first multiplexer switch MUX1, the first multiplexer switch MUX1 is turned off. When a low level is applied to the gate of the second multiplexer switch MUX2, the second multiplexer switch MUX2 is turned on; when a high level is applied to the gate of the second multiplexer switch MUX2, the second multiplexer switch MUX2 is turned off.

[0077] Furthermore, as shown in Figure 10, the thin-film transistors (TFTs) connected to the gate and gate lines in each sub-pixel are also active low. That is, when a low-level signal is applied to the gate line, a low level is applied to the gate G of the TFT, and the TFT is turned on; when a high-level signal is applied to the gate line, a high level is applied to the gate G of the TFT, and the TFT is turned off.

[0078] As shown in Figures 2, 4, 9 and 10, the driving process includes a first stage t1 and a second stage t2.

[0079] In the first stage t1, the gate of the first multiplexer switch MUX1 is applied with a low level, and the gate of the second multiplexer switch MUX2 is applied with a high level. At this time, the first multiplexer switch MUX1 is turned on, and the second multiplexer switch MUX2 is turned off. The signal on the data lead SL is written to the first data line D1 through the first multiplexer switch MUX2. At this time, the loading signal Gate_P on the gate line is high, the gate G of the thin-film transistor TFT is applied with a high level, the thin-film transistor TFT is turned off, and the first data line D1 is in a floating state.

[0080] In the second stage t2, a high level is applied to the gate of the first multiplexer switch MUX1, and a low level is applied to the gate of the second multiplexer switch MUX2. At this time, the first multiplexer switch MUX1 is turned off, and the second multiplexer switch MUX2 is turned on. The signal on the data lead SL is written to the second data line D2 through the second multiplexer switch MUX2. Subsequently, the loading signal Gate_P on the gate line changes from high to low, the gate G of the thin-film transistor TFT is applied low, the thin-film transistor TFT is turned on, and the signals on the first data line D1 and the second data line D2 are simultaneously written to the corresponding sub-pixels through the corresponding thin-film transistor TFTs.

[0081] When displaying a heavy-load image on the display panel, as shown in Figure 8, the top two rows of sub-pixels are not lit, thus displaying black lines, while the bottom two rows of sub-pixels are lit, thus displaying white lines. Throughout the display panel, the two rows of sub-pixels that are not lit alternate with the two rows that are lit. The data signal corresponding to the top two rows of sub-pixels is at a high level, and the data signal corresponding to the bottom two rows of sub-pixels is at a low level. When writing data to the third row of sub-pixels, the first data line D1 is in a floating state in the first stage t1, while the data signal of the second data line D2 in the second stage t2 jumps from the high level corresponding to the second row of sub-pixels to a low level. Due to the large coupling capacitance between the adjacent first connection line CL1 and the second connection line CL2, the level change on the second data line D2 will pull the level of the first data line D1 low, resulting in the vertical white bar defect shown in Figure 9.

[0082] Therefore, this disclosure provides, in particular, a display panel and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display panel. In some embodiments, the display panel includes: a through-hole; a display area surrounding the through-hole and configured to display an image; and a winding area located between the through-hole and the display area. In some embodiments, the display panel includes a plurality of first data lines and a plurality of second data lines, all extending along a first direction in the display area and alternately arranged along a second direction, the first direction being different from the second direction; the first data lines whose projections along the first direction onto the second direction overlap with the projections of the through-hole and / or the winding area along the first direction onto the second direction include a first data line portion and a second data line portion, the first data line portion and the second data line portion being located on opposite sides of the winding area along the first direction and connected by a first connecting line, the first connecting line being located in the winding area; and the second data lines whose projections along the first direction onto the second direction overlap with the projections of the through-hole and / or the winding area along the first direction onto the second direction include a third data line portion and a fourth data line portion, the third data line portion and the fourth data line portion being located on opposite sides of the winding area along the first direction and connected by a second connecting line, the second connecting line being located in the display area.

[0083] Figure 11 is a plan view of a display panel according to some embodiments of the present disclosure. Referring to Figure 11, the display panel includes: a through-hole TH configured to accommodate external electronic components such as a camera; a display area AA surrounding the through-hole TH and configured to display an image; and a winding area RA located between the through-hole TH and the display area AA.

[0084] In some embodiments, the display panel includes a plurality of first data lines D1 and a plurality of second data lines D2. In some embodiments, as shown in FIG11, the plurality of first data lines D1 and the plurality of second data lines D2 all extend along a first direction DR1 in the display area and are alternately arranged along a second direction DR2. In some embodiments, the first direction DR1 is different from the second direction DR2; for example, the first direction DR1 is perpendicular to the second direction DR2.

[0085] As shown in Figure 11, the first data line D1, whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through-hole TH and / or the winding region RA along the first direction DR1 onto the second direction DR2, includes a first data line portion D1-1 and a second data line portion D1-2. In some embodiments, the first data line portion D1-1 and the second data line portion D1-2 are located on both sides of the winding region RA along the first direction DR1, and are connected by a first connecting line CL1, wherein the first connecting line CL1 is located in the winding region RA.

[0086] As shown in Figure 11, the second data line D2, whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through-hole TH and / or the winding region RA along the first direction DR1 onto the second direction DR2, includes a third data line portion D2-1 and a fourth data line portion D2-2. In some embodiments, the third data line portion D2-1 and the fourth data line portion D2-2 are located on both sides of the winding region RA along the first direction DR1, and are connected by a second connecting line CL2, wherein the second connecting line CL2 is located in the display area AA.

[0087] As shown in Figure 11, in some embodiments, a first data line D1 and an adjacent second data line D2 are connected to the same signal lead SL, which is connected to the data drive circuit DDC via a fan-out line FL located in the fan-out region.

[0088] Figure 12 illustrates the connection of data lines and signal leads in a display panel according to some embodiments of the present disclosure. Referring to Figure 12, in a first data line D1 and a second data line D2 connected to the same signal lead SL, the first data line D1 is configured to provide a data signal to the green sub-pixel g; the second data line D2 is configured to provide a data signal to the red sub-pixel r and / or the blue sub-pixel b. As shown in Figure 12, a first multiplexer switch MUX1 is provided in the first data line D1, which is configured to control the on and off of the data signal on the first data line D1. As shown in Figure 2, a second multiplexer switch MUX2 is provided in the second data line D2, which is configured to control the on and off of the data signal on the second data line D2.

[0089] By connecting the first data line D1 and its adjacent second data line D2 to the same signal lead SL, the number of signal leads SL can be halved. This means that the size of the data drive circuit DDC can be reduced, thereby reducing the cost of the data drive circuit DDC and thus reducing the production cost of the display panel.

[0090] Figure 13 is a schematic diagram showing the connecting lines in the winding area of ​​a display panel according to some embodiments of the present disclosure. As shown in Figure 13, in some embodiments, a first data line D1 whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through hole TH and / or the projection of the winding area RA along the first direction DR1 onto the second direction DR2 includes a first data line portion D1-1 and a second data line portion D1-2. In some embodiments, the first data line portion D1-1 and the second data line portion D1-2 are respectively located on both sides of the winding area RA along the first direction DR1 and connected by a first connecting line CL1, wherein the first connecting line CL is located in the winding area RA. As shown in Figure 13, in some embodiments, a second data line D2 whose projection along the first direction DR1 onto the second direction DR2 overlaps with the projection of the through hole TH and / or the projection of the winding area RA along the first direction DR1 onto the second direction DR2 includes a third data line portion D2-1 and a fourth data line portion D2-2. In some embodiments, the third data line portion D2-1 and the fourth data line portion D2-2 are located on both sides of the winding area RA along the first direction DR1, and are connected by a second connecting line CL2, wherein the second connecting line CL2 is located in the display area AA.

[0091] Figure 13 also shows the edge EG of the through-hole TH and the virtual boundary line DBL between the winding area RA and the display area AA. The edge EG of the through-hole TH forms the boundary line between the through-hole TH and the winding area RA. The through-hole TH is formed by cutting the display panel; therefore, the edge EG of the through-hole TH is the cutting line when cutting the display panel. It should be noted that, unlike the edge EG of the through-hole TH, the virtual boundary line DBL is a virtual line created to more clearly show the division between the winding area RA and the display area AA, and does not actually exist.

[0092] Figure 14 is a cross-sectional view illustrating a detailed structure in a display region of a display panel according to some embodiments of the present disclosure. Referring to Figure 14, in some embodiments, the display panel includes in the display region: a substrate BS (e.g., a flexible substrate); an active layer ACT of each thin-film transistor in a plurality of thin-film transistors (TFTs) located on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both part of a first gate metal layer Gate1) located on the side of the gate insulating layer GI away from the substrate BS; a second insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second gate metal layer Gate2) located on the side of the second insulating layer IN away from the gate insulating layer GI; and an interlayer dielectric layer ILD located on the side of the second capacitor electrode... Ce2 on the side away from the gate insulating layer GI; source S and drain D (part of the first signal line layer SD1), located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; passivation layer PVX, located on the side of the source S and drain D away from the interlayer dielectric layer ILD; first planarization layer PLN1, located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; relay electrode RE (part of the second signal layer SD2), located on the side of the first planarization layer PLN1 away from the passivation layer PVX; second planarization layer PLN2, located on the side of the relay electrode RE away from the first planarization layer PLN1; pixel defining layer PDL, defining a sub-pixel opening and located on the side of the second planarization layer PLN2 away from the substrate BS; and light-emitting element LE, located in the sub-pixel opening. The light-emitting element LE includes: an anode AD located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light-emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display panel also includes an encapsulation layer EN in the display area, which encapsulates the light-emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.

[0093] Referring to Figure 14, the display panel includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SD1, and a second signal line layer SD2. The display panel also includes: a gate insulating layer GI located between the active layer ACT and the second gate metal layer Gate2; a second insulating layer IN located between the first gate metal layer Gate1 and the second gate metal layer Gate2; an interlayer dielectric layer ILD located between the second gate metal layer Gate2 and the first signal line layer SML1; and a passivation layer PVX and a first planarization layer PLN1 located between the first signal line layer SD1 and the second signal line layer SD2. Optionally, the display panel does not include the passivation layer PVX in the display area; for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0094] In some embodiments, the first data line portion D1-1, the second data line portion D1-2, the third data line portion D2-1, and the fourth data line portion D2-2 are all located on the second signal line layer SD2.

[0095] Figure 15 is a plan view showing the structure of a first connecting line in a display panel according to some embodiments of the present disclosure. Figure 16 is an enlarged view showing the structure in region Z3 of Figure 15. Figure 17 is an enlarged view showing the structure in region Z4 of Figure 15. For clarity, the first data line segment D1-1 and the third data line segment D2-1 are omitted in Figure 15; the first data line segment D1-1 and the third data line segment D2-1 are shown in Figure 16.

[0096] As shown in Figures 15 and 16, the edge EG of the through-hole TH forms the boundary between the through-hole TH and the winding area RA. The through-hole TH is formed by cutting the display panel; therefore, the edge EG of the through-hole TH is the cutting line when cutting the display panel.

[0097] Furthermore, Figures 15 and 16 also show a virtual dividing line DBL between the winding area RA and the display area AA. It should be noted that, unlike the edge EG of the via TH, the virtual dividing line DBL is a virtual line created to more clearly show the division between the winding area RA and the display area AA, and does not actually exist.

[0098] As shown in Figures 15 and 16, the first portion of the data line D1-1 is connected to the first connecting line CL1. In some embodiments, as shown in Figures 15 to 17, the first connecting line CL1 is located on the second signal line layer SD2, and the first portion of the data line D1-1 and the first connecting line CL1 are located on the same layer and are part of the overall structure.

[0099] In some embodiments, the first connecting line CL1 is connected to the second portion D1-2 of the data line. Similarly, the first connecting line CL1 and the second portion D1-2 of the data line are located on the same layer and are part of the overall structure. In some embodiments, the first portion D1-1 of the data line, the first connecting line CL1, and the second portion D1-2 of the data line are formed as an integral structure.

[0100] As shown in Figures 15 and 16, a plurality of isolation pillars SP are provided on the side of the first connecting line CL1 near the edge EG. In some embodiments, as shown in Figure 16, the plurality of isolation pillars SP includes seven isolation pillars SP disposed near the edge EG and four isolation pillars SP disposed near the first connecting line CL1, with a barrier region WA between the seven isolation pillars SP and the four isolation pillars SP. One or more barriers (not shown) are provided in the barrier region WA. The isolation pillars SP are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent external water and oxygen from entering the display panel. The barriers (not shown) are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent the organic encapsulation sublayer IJP shown in Figure 14 from overflowing during formation.

[0101] It should be noted that there are no connecting wires for the gate wires in the winding area RA. Because the gate wires in the display panel are driven on both sides, even if the gate wires are broken at the via TH, they can still be driven by the gate drive circuits on both sides of the display panel. Therefore, there is no need to set connecting wires for the gate wires in the winding area RA, thereby reducing the difficulty of wiring.

[0102] As shown in Figure 17, the minimum spacing d1 between two adjacent first connecting lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum spacing d1 between two adjacent first connecting lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0103] Figure 18 is a plan view showing the structure of a second data line in a display panel according to some embodiments of the present disclosure. Figure 19 is a plan view showing the structure of a second connecting line in a display panel according to some embodiments of the present disclosure. Figure 20 is an enlarged view showing the structure in region Z5 of Figure 19. Figure 21 is an enlarged view showing the structure in region Z6 of Figure 19.

[0104] As shown in Figure 18, the third section D2-1 of the data line is connected to the second connecting line CL2 through a first via, and the second connecting line CL2 is connected to the fourth section D2-2 of the data line through a second via. The second connecting line CL2 includes the first connecting line CL2-1, the second connecting line CL2-2, and the third connecting line CL2-3, which are connected to each other. The third section D2-1 of the data line is connected to the first connecting line CL2-1 through a first via v1, and the third connecting line CL2-3 is connected to the fourth section D2-2 of the data line through a second via v2.

[0105] In some embodiments, the third data line portion D2-1 and the fourth data line portion D2-2 are both located in the second signal line layer SD2; the first connection portion CL2-1 and the third connection portion CL2-3 are both located in the second signal line layer SD2; and the first via v1 and the second via v2 extend through the first planarization layer PLN1 and the passivation layer PVX shown in FIG14, respectively.

[0106] As shown in Figure 18, the minimum spacing d2 between two adjacent second connecting lines CL2 is in the range of 2.0 μm to 2.5 μm. For example, the minimum spacing d2 between two adjacent first connecting lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0107] In some embodiments, the first portion CL2-1 of the connecting line extends from the third portion D2-1 of the data line along the second direction DR2 to the second portion CL2-2 of the connecting line; the third portion CL2-3 of the connecting line extends from the fourth portion D2-2 of the data line along the second direction DR2 to the second portion CL2-2 of the connecting line. That is, the first portion CL2-1 and the third portion CL2-3 of the connecting line are parallel to each other.

[0108] In some embodiments, the second portion CL2-2 of the connecting line extends from the first portion CL2-1 of the connecting line along the first direction DR1 to the second portion CL2-2 of the connecting line. In some embodiments, the first portion CL2-1 of the connecting line and the third portion CL2-3 of the connecting line have the same length.

[0109] In some embodiments, as shown in Figures 18 and 19, the first section CL2-1, the second section CL2-2, and the third section CL2-3 of the connecting line are axially symmetrical about the perpendicular bisector OO' of the second section CL2-2.

[0110] As shown in Figures 18 and 19, the first section CL2-1 of the connecting line is connected to the second section CL2-2 of the connecting line through the third via v3, and the second section CL2-2 of the connecting line is connected to the third section CL2-3 of the connecting line through the fourth via v4.

[0111] As shown in Figure 20, the third segment CL2-3 of the connector is located on the second signal line layer SD2, and the second segment CL2-2 of the connector is located on the first signal line layer SD1. The second segment CL2-2 of the connector is connected to the third segment CL2-3 of the connector through a fourth via v4, which extends through the first planarization layer PLN1 and the passivation layer PVX shown in Figure 14.

[0112] As shown in Figure 21, the first segment CL2-1 of the connector is located on the second signal line layer SD2, and the second segment CL2-2 of the connector is located on the first signal line layer SD1. The first segment CL2-1 of the connector is connected to the second segment CL2-2 of the connector through a third via v3, which extends through the first planarization layer PLN1 and the passivation layer PVX shown in Figure 14.

[0113] In the display panel according to this disclosure, only the first connecting line CL1 is provided in the winding area RA, while the second connecting line CL2 is provided in the display area AA. This avoids the generation of coupling capacitance between the first connecting line CL1 and the second connecting line CL2, and therefore, when the display panel displays a heavy-load image, the vertical white bar shown in Figure 9 will not appear.

[0114] Furthermore, in the display panel according to this disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the screen brightness. Simultaneously, since the first data line D1 is in a floating state during the first stage t1 shown in Figure 10, while the second data line D2 is not in a floating state, the anti-interference capability of the first data line D1 is weaker than that of the second data line D2. By placing the first connecting line CL1 connected to the first data line D1 in the winding area RA, interference from other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a stronger anti-interference capability, placing the second connecting line CL2 connected to the second data line D2 in the display area AA2 will not affect normal display.

[0115] Figure 22 is a plan view showing the structure of the first connecting line in a display panel according to some embodiments of the present disclosure. Figure 23 is an enlarged view showing the structure in region Z7 of Figure 22. Figure 24 is an enlarged view showing the structure in region Z8 of Figure 22. For clarity, the first data line segment D1-1 and the third data line segment D2-1 are omitted in Figure 22; the first data line segment D1-1 and the third data line segment D2-1 are shown in Figure 23.

[0116] As shown in Figures 22 and 23, the edge EG of the through-hole TH forms the boundary between the through-hole TH and the winding region RA. The through-hole TH is formed by cutting the display panel; therefore, the edge EG of the through-hole TH is the cutting line when cutting the display panel.

[0117] Furthermore, Figures 22 and 23 also show a virtual dividing line DBL between the winding area RA and the display area AA. It should be noted that, unlike the edge EG of the via TH, the virtual dividing line DBL is a virtual line created to more clearly show the division between the winding area RA and the display area AA, and does not actually exist.

[0118] As shown in Figures 22 and 23, the first portion of the data line D1-1 is connected to the first connection line CL1. In some embodiments, as shown in Figures 22 to 24, the first connection line CL1 is located on the first signal line layer SD1, and the first portion of the data line D1-1 is connected to the first connection line CL1 through a fifth via v5, which extends through the first planarization layer PLN1 and the passivation layer PVX shown in Figure 14.

[0119] Alternatively, the display panel may not include the passivation layer PVX in the display area. In this case, the fifth via v5 extends only through the first planarization layer PLN1. Alternatively, without the first planarization layer PLN1, the fifth via v5 extends only through the passivation layer PVX. That is, the fifth via v5 extends through the first planarization layer PLN1 and / or the passivation layer PVX.

[0120] Similarly, as shown in Figures 22 to 24, the first connecting line CL1 is connected to the second data line segment D1-2 through the sixth via v6, which extends through the first planarization layer PLN1 and / or the passivation layer PVX.

[0121] As shown in Figures 22 and 23, a plurality of isolation pillars SP are provided on the side of the first connecting line CL1 near the edge EG. In some embodiments, as shown in Figure 23, the plurality of isolation pillars SP includes seven isolation pillars SP disposed near the edge EG and four isolation pillars SP disposed near the first connecting line CL1, with a barrier region WA between the seven isolation pillars SP and the four isolation pillars SP. One or more barriers (not shown) are provided in the barrier region WA. The isolation pillars SP are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent external water and oxygen from entering the display panel. The barriers (not shown) are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent the organic encapsulation sublayer IJP shown in Figure 14 from overflowing during formation.

[0122] It should be noted that there are no connecting wires for the gate wires in the winding area RA. Because the gate wires in the display panel are driven on both sides, even if the gate wires are broken at the via TH, they can still be driven by the gate drive circuits on both sides of the display panel. Therefore, there is no need to set connecting wires for the gate wires in the winding area RA, thereby reducing the difficulty of wiring.

[0123] As shown in Figure 24, the minimum spacing d1 between two adjacent first connecting lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum spacing d1 between two adjacent first connecting lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0124] In the display panel according to this disclosure, only the first connecting line CL1 is provided in the winding area RA, while the second connecting line CL2 is provided in the display area AA. This avoids the generation of coupling capacitance between the first connecting line CL1 and the second connecting line CL2, and therefore, when the display panel displays a heavy-load image, the vertical white bar shown in Figure 9 will not appear.

[0125] Furthermore, in the display panel according to this disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the screen brightness. Simultaneously, since the first data line D1 is in a floating state during the first stage t1 shown in Figure 10, while the second data line D2 is not in a floating state, the anti-interference capability of the first data line D1 is weaker than that of the second data line D2. By placing the first connecting line CL1 connected to the first data line D1 in the winding area RA, interference from other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a stronger anti-interference capability, placing the second connecting line CL2 connected to the second data line D2 in the display area AA2 will not affect normal display.

[0126] Figure 25 is a plan view showing the structure of the first connecting line in a display panel according to some embodiments of the present disclosure. Figure 26 is an enlarged view showing the structure in region Z9 of Figure 25. Figure 27 is an enlarged view showing the structure in region Z10 of Figure 25. For clarity, the first data line segment D1-1 and the third data line segment D2-1 are omitted in Figure 25; the first data line segment D1-1 and the third data line segment D2-1 are shown in Figure 26.

[0127] As shown in Figures 25 and 26, the edge EG of the through-hole TH forms the boundary between the through-hole TH and the winding region RA. The through-hole TH is formed by cutting the display panel; therefore, the edge EG of the through-hole TH is the cutting line when cutting the display panel.

[0128] Furthermore, Figures 25 and 26 also show a virtual dividing line DBL between the winding area RA and the display area AA. It should be noted that, unlike the edge EG of the via TH, the virtual dividing line DBL is a virtual line created to more clearly show the division between the winding area RA and the display area AA, and does not actually exist.

[0129] As shown in Figures 25 and 26, the first portion of the data line D1-1 is connected to the first connection line CL1. In some embodiments, as shown in Figures 25 to 27, the first connection line CL1 is located in the second gate metal layer Gate2, and the first portion of the data line D1-1 is connected to the first connection line CL1 through a seventh via v7. The seventh via v7 extends through the first planarization layer PLN1 and the passivation layer PVX shown in Figure 14, as well as the interlayer dielectric layer ILD.

[0130] Alternatively, the display panel may not include the passivation layer PVX in the display area. In this case, the fifth via v5 extends through the first planarization layer PLN1 and the interlayer dielectric layer ILD. Alternatively, without the first planarization layer PLN1, the fifth via v5 extends through the passivation layer PVX and the interlayer dielectric layer ILD. That is, the fifth via v5 extends through the first planarization layer PLN1 and / or the passivation layer PVX, as well as the interlayer dielectric layer ILD.

[0131] Similarly, as shown in Figures 22 to 24, the first connection line CL1 is connected to the second data line segment D1-2 through the eighth via v8, which extends through the first planarization layer PLN1 and / or the passivation layer PVX, as well as the interlayer dielectric layer ILD.

[0132] As shown in Figures 25 and 26, a plurality of isolation pillars SP are provided on the side of the first connecting line CL1 near the edge EG. In some embodiments, as shown in Figure 26, the plurality of isolation pillars SP includes seven isolation pillars SP disposed near the edge EG and four isolation pillars SP disposed near the first connecting line CL1, with a barrier region WA between the seven isolation pillars SP and the four isolation pillars SP. One or more barriers (not shown) are provided in the barrier region WA. The isolation pillars SP are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent external water and oxygen from entering the display panel. The barriers (not shown) are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent the organic encapsulation sublayer IJP shown in Figure 14 from overflowing during formation.

[0133] It should be noted that there are no connecting wires for the gate wires in the winding area RA. Because the gate wires in the display panel are driven on both sides, even if the gate wires are broken at the via TH, they can still be driven by the gate drive circuits on both sides of the display panel. Therefore, there is no need to set connecting wires for the gate wires in the winding area RA, thereby reducing the difficulty of wiring.

[0134] As shown in Figure 27, the minimum spacing d1 between two adjacent first connecting lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum spacing d1 between two adjacent first connecting lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0135] In the display panel according to this disclosure, only the first connecting line CL1 is provided in the winding area RA, while the second connecting line CL2 is provided in the display area AA. This avoids the generation of coupling capacitance between the first connecting line CL1 and the second connecting line CL2, and therefore, when the display panel displays a heavy-load image, the vertical white bar shown in Figure 9 will not appear.

[0136] Furthermore, in the display panel according to this disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the screen brightness. Simultaneously, since the first data line D1 is in a floating state during the first stage t1 shown in Figure 10, while the second data line D2 is not in a floating state, the anti-interference capability of the first data line D1 is weaker than that of the second data line D2. By placing the first connecting line CL1 connected to the first data line D1 in the winding area RA, interference from other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a stronger anti-interference capability, placing the second connecting line CL2 connected to the second data line D2 in the display area AA2 will not affect normal display.

[0137] Figure 28 is a plan view showing the structure of a first connecting line in a display panel according to some embodiments of the present disclosure. Figure 29 is an enlarged view showing the structure in region Z11 of Figure 28. Figure 30 is an enlarged view showing the structure in region Z12 of Figure 28. For clarity, the first data line segment D1-1 and the third data line segment D2-1 are omitted in Figure 28; the first data line segment D1-1 and the third data line segment D2-1 are shown in Figure 29.

[0138] As shown in Figures 28 and 29, the edge EG of the through-hole TH forms the boundary between the through-hole TH and the winding region RA. The through-hole TH is formed by cutting the display panel; therefore, the edge EG of the through-hole TH is the cutting line when cutting the display panel.

[0139] Furthermore, Figures 28 and 29 also show a virtual dividing line DBL between the winding area RA and the display area AA. It should be noted that, unlike the edge EG of the via TH, the virtual dividing line DBL is a virtual line created to more clearly show the division between the winding area RA and the display area AA, and does not actually exist.

[0140] As shown in Figures 28 and 29, the first portion of the data line D1-1 is connected to the first connection line CL1. In some embodiments, as shown in Figures 28 to 30, the first connection line CL1 is located on the first signal line layer SD1, and the first portion of the data line D1-1 is connected to the first connection line CL1 through a ninth via v9. The ninth via v9 extends through the first planarization layer PLN1 and the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN shown in Figure 14.

[0141] Alternatively, the display panel may not include the passivation layer PVX in the display area. In this case, the ninth via v9 extends through the first planarization layer PLN1, the interlayer dielectric layer ILD, and the second insulating layer IN. Alternatively, without the first planarization layer PLN1, the ninth via v9 extends through the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN. That is, the fifth via v5 extends through the first planarization layer PLN1 and / or the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN.

[0142] Similarly, as shown in Figures 22 to 24, the first connecting line CL1 is connected to the second data line segment D1-2 through the tenth via v10. The tenth via v10 extends through the first planarization layer PLN1 and / or the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN.

[0143] As shown in Figures 28 and 29, a plurality of isolation pillars SP are provided on the side of the first connecting line CL1 near the edge EG. In some embodiments, as shown in Figure 29, the plurality of isolation pillars SP includes seven isolation pillars SP disposed near the edge EG and four isolation pillars SP disposed near the first connecting line CL1, with a barrier region WA between the seven isolation pillars SP and the four isolation pillars SP. One or more barriers (not shown) are provided in the barrier region WA. The isolation pillars SP are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent external water and oxygen from entering the display panel. The barriers (not shown) are in contact with the encapsulation layer EN shown in Figure 14 and are configured to prevent the organic encapsulation sublayer IJP shown in Figure 14 from overflowing during formation.

[0144] It should be noted that there are no connecting wires for the gate wires in the winding area RA. Because the gate wires in the display panel are driven on both sides, even if the gate wires are broken at the via TH, they can still be driven by the gate drive circuits on both sides of the display panel. Therefore, there is no need to set connecting wires for the gate wires in the winding area RA, thereby reducing the difficulty of wiring.

[0145] As shown in Figure 30, the minimum spacing d1 between two adjacent first connecting lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum spacing d1 between two adjacent first connecting lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0146] In the display panel according to this disclosure, only the first connecting line CL1 is provided in the winding area RA, while the second connecting line CL2 is provided in the display area AA. This avoids the generation of coupling capacitance between the first connecting line CL1 and the second connecting line CL2, and therefore, when the display panel displays a heavy-load image, the vertical white bar shown in Figure 9 will not appear.

[0147] Furthermore, in the display panel according to this disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the screen brightness. Simultaneously, since the first data line D1 is in a floating state during the first stage t1 shown in Figure 10, while the second data line D2 is not in a floating state, the anti-interference capability of the first data line D1 is weaker than that of the second data line D2. By placing the first connecting line CL1 connected to the first data line D1 in the winding area RA, interference from other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a stronger anti-interference capability, placing the second connecting line CL2 connected to the second data line D2 in the display area AA2 will not affect normal display.

[0148] On the other hand, the present invention provides a display device comprising a display panel manufactured as described herein or by means of the methods described herein, one or more integrated circuits connected to the display panel, and a power supply component for providing power to the display panel and the integrated circuits. Examples of suitable display devices include, but are not limited to, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Examples of suitable power supply components may be batteries in small-to-medium-sized products such as mobile phones and tablets, or power input components in large-sized products such as computers and televisions.

[0149] On the other hand, this disclosure provides a method for manufacturing a display panel. In some embodiments, the method includes forming a through-hole in the display panel. Optionally, the through-hole is formed by cutting the display panel. Optionally, the display panel further includes: a display area surrounding the through-hole and configured to display an image; and a winding area located between the through-hole and the display area. Optionally, the display panel includes a plurality of first data lines and a plurality of second data lines, all extending along a first direction in the display area and alternately arranged along a second direction different from the second direction; the first data lines whose projections along the first direction onto the second direction overlap with the projections of the through-hole and / or the winding area along the first direction onto the second direction include a first data line portion and a second data line portion, which are respectively located on both sides of the winding area along the first direction and connected by a first connecting line, which is located in the winding area; and the second data lines whose projections along the first direction onto the second direction overlap with the projections of the through-hole and / or the winding area along the first direction onto the second direction include a third data line portion and a fourth data line portion, which are respectively located on both sides of the winding area along the first direction and connected by a second connecting line, which is located in the display area.

[0150] For purposes of illustration and description, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to specific examples, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display panel, comprising: Through hole; A display area surrounds the through-hole and is configured to display an image; as well as The winding area is located between the through-hole and the display area. The display panel includes a plurality of first data lines and a plurality of second data lines. The plurality of first data lines and the plurality of second data lines extend along a first direction in the display area and are alternately arranged along a second direction, wherein the first direction is different from the second direction. A first data line whose projection along the first direction onto the second direction overlaps with the projection of the through-hole and / or the winding region along the first direction onto the second direction, includes a first data line portion and a second data line portion. The first data line portion and the second data line portion are respectively located on both sides of the winding region along the first direction and connected by a first connecting line located in the winding region; and The second data line, whose projection along the first direction onto the second direction overlaps with the projection of the through hole and / or the winding area along the first direction onto the second direction, includes a third data line portion and a fourth data line portion. The third data line portion and the fourth data line portion are respectively located on both sides of the winding area along the first direction and are connected by a second connecting line located in the display area.

2. The display panel according to claim 1, wherein, The minimum spacing between two adjacent first connecting lines is in the range of 2.0 μm to 2.5 μm.

3. The display panel according to claim 1, wherein, The minimum spacing between two adjacent second connecting lines is in the range of 2.0 μm to 2.5 μm.

4. The display panel according to claim 1, wherein, The first data line is configured to provide a data signal to the green sub-pixel, and the second data line is configured to provide a data signal to the red sub-pixel and / or the blue sub-pixel.

5. The display panel according to any one of claims 1 to 4, wherein, The first data line is provided with a first multiplexer switch, which is configured to control the conduction and cutoff of data signals on the first data line. The second data line is provided with a second multiplexer switch, which is configured to control the on and off of the data signal on the second data line; and The first data line and an adjacent second data line are connected to the same signal lead.

6. The display panel according to claim 1, wherein, The second connecting line includes a first connecting line portion, a second connecting line portion, and a third connecting line portion that are connected to each other, and The third section of the data cable is connected to the first section of the connecting cable, and the third section of the connecting cable is connected to the fourth section of the data cable. Wherein, the first portion of the connecting line and the third portion of the connecting line are parallel to each other, and / or The first and third portions of the connecting line are parallel to each other and have the same length.

7. The display panel according to claim 6, wherein, The first portion and the third portion of the connecting line extend along the second direction; and The second portion of the connecting line extends along the first direction.

8. The display panel according to claim 1, comprising: Substrate; A gate insulating layer located on the substrate; A first gate metal layer is located on the side of the gate insulating layer away from the gate insulating layer; A second insulating layer is located on the side of the first gate metal layer away from the gate insulating layer; The second gate metal layer is located on the side of the second insulating layer away from the gate insulating layer; An interlayer dielectric layer is located on the side of the second gate metal layer away from the gate insulating layer; The first signal line layer is located on the side of the interlayer dielectric layer away from the gate insulating layer; A passivation layer and / or a first planarization layer, which are located on the side of the first signal line layer away from the gate insulating layer; as well as The second signal layer is located on the side of the passivation layer and / or the first planarization layer away from the gate insulating layer.

9. The display panel according to claim 8, wherein, The third portion of the data line is located in the second signal line layer and is connected to the second connection line through the first via. At least a portion of the second connection line connected to the third portion of the data line is located in the first signal line layer. The first via extends through the passivation layer and / or the first planarization layer. as well as The second connecting line is connected to the fourth portion of the data line through a second via. The third portion of the data line is located in the second signal line layer. At least a portion of the second connecting line connected to the fourth portion of the data line is located in the first signal line layer. The second via extends through the passivation layer and / or the first planarization layer.

10. The display panel according to claim 9, wherein, The second connecting line includes a first connecting line portion, a second connecting line portion, and a third connecting line portion that are connected to each other, and Both the first and third portions of the connecting line are located on the first signal line layer. The third portion of the data line is connected to the first portion of the connecting line through the first via, and the third portion of the connecting line is connected to the fourth portion of the data line through the second via.

11. The display panel according to claim 9, wherein, The second connecting line includes a first connecting line section, a second connecting line section, and a third connecting line section that are connected to each other. The first and third portions of the connecting line are located on the same layer, and The second portion of the connecting line is located on a layer different from the first and third portions of the connecting line. Wherein, the first portion of the connecting line is connected to the second portion of the connecting line through a third via; and The second section of the connecting line is connected to the third section of the connecting line through a fourth via.

12. The display panel according to claim 11, wherein, Both the first and third portions of the connecting line are located in the first signal line layer. The second portion of the connecting line is located on the second signal line layer, and Both the fourth via and the third via extend through the passivation layer and / or the first planarization layer.

13. The display panel according to claim 8, wherein, Both the first portion and the second portion of the data line are located in the second signal line layer. The first connection line is located on the second signal line layer, and The first part of the data line, the second part of the data line, and the first connecting line form an integral structure.

14. The display panel according to claim 8, wherein, Both the first portion and the second portion of the data line are located in the second signal line layer. The first connection line is located on the first signal line layer, and The first portion of the data line is connected to the first connecting line through a fifth via, and the first connecting line is connected to the second portion of the data line through a sixth via. Both the fifth and sixth vias extend through the passivation layer and / or the first planarization layer.

15. The display panel according to claim 8, wherein, Both the first portion and the second portion of the data line are located in the second signal line layer. The first connection line is located in the second gate metal layer, and The first portion of the data line is connected to the first connecting line through a seventh via, and the first connecting line is connected to the second portion of the data line through an eighth via. Both the seventh and eighth vias extend through the passivation layer and / or the first planarization layer, as well as the interlayer dielectric layer.

16. The display panel according to claim 8, wherein, Both the first portion and the second portion of the data line are located in the second signal line layer. The first connection line is located in the first gate metal layer, and The first portion of the data line is connected to the first connecting line through a ninth via, and the first connecting line is connected to the second portion of the data line through a tenth via. Both the ninth and tenth vias extend through the passivation layer and / or the first planarization layer, the interlayer dielectric layer, and the second insulating layer.

17. A display device comprising a display panel according to any one of claims 1 to 16, one or more integrated circuits connected to the display panel, and a power supply component for providing power to the display panel and the integrated circuits.

Images