Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises pixel driving circuits arranged in an array, a plurality of data signal lines and a plurality of data transfer lines, wherein at least one pixel driving circuit is electrically connected to at least one data signal line, and at least part of the at least one data signal line extends in a first direction; at least one data transfer line is electrically connected to at least one data signal line; the at least one data transfer line comprises a first transfer line, at least part of which extends in the first direction; and the distance between the orthographic projection of at least part of the first transfer line from among the at least one data transfer line on a substrate and the orthographic projection, on the substrate, of at least part of an active pattern of at least one transistor that extends in the first direction is less than a first threshold distance value, or the distance between a film layer where the first transfer line from among the at least one data transfer line is located and a film layer where the active pattern of the at least one transistor is located is greater than a second threshold distance value.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411709221.6, filed on November 26, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and a display device.

[0006] In a first aspect, this disclosure provides a display substrate, comprising: a substrate and an array of pixel driving circuits, multiple data signal lines and multiple data transfer lines disposed on the substrate, wherein at least one pixel driving circuit is electrically connected to at least one data signal line, and the at least one data signal line extends at least partially along a first direction;

[0007] At least one data adapter cable is electrically connected to at least one data signal line;

[0008] The at least one data adapter cable includes: a first adapter cable extending at least partially along the first direction; the pixel driving circuit includes: at least one transistor, the at least one transistor including: an active pattern.

[0009] The distance between the orthographic projection of at least a portion of the first adapter wire of the at least one data adapter wire on the substrate and the orthographic projection of at least a portion of the active pattern of the at least one transistor extending along the first direction on the substrate is less than a first threshold distance, or the distance between the film layer where the first adapter wire of the at least one data adapter wire is located and the film layer where the active pattern of the at least one transistor is located is greater than a second threshold distance.

[0010] In an exemplary embodiment, the at least one data adapter cable further includes: a second adapter cable extending at least partially along a second direction, wherein the first direction intersects the second direction;

[0011] The first adapter cable and the second adapter cable located in the same data adapter cable are electrically connected, and the orthographic projection of the second adapter cable of the at least one data adapter cable on the substrate at least partially overlaps with the orthographic projection of the at least one data signal line on the substrate.

[0012] In an exemplary embodiment, the at least one transistor further includes: a first electrode and a second electrode;

[0013] The first threshold distance is less than 1 micrometer;

[0014] The second threshold distance is the distance between the film layer containing the active pattern of the at least one transistor and the film layer containing the first electrode and the second electrode of the at least one transistor.

[0015] In an exemplary embodiment, when the distance between at least a portion of the first adapter wire of the at least one data adapter wire and the orthographic projection of at least a portion of the active pattern of the at least one transistor extending along the first direction onto the substrate is less than a first threshold, the first adapter wire and the second adapter wire of the at least one data adapter wire are disposed on the same layer.

[0016] In an exemplary embodiment, the system further includes: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0017] The first and second adapter wires of at least one data adapter wire, as well as the first and second terminals of the at least one transistor, are located on the third conductive layer, and the data signal line is located on the fifth conductive layer.

[0018] In an exemplary embodiment, the at least one pixel driving circuit includes: a second transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein the third transistor is a driving transistor, the second terminal of the second transistor and the first terminal of the sixth transistor are electrically connected to the second terminal of the third transistor, the first terminal of the second transistor is electrically connected to the control terminal of the third transistor, the first terminal of the fourth transistor is electrically connected to the data signal line, and the second terminal of the fourth transistor is electrically connected to the first terminal of the third transistor.

[0019] The active pattern of the at least one transistor includes: a channel region and a first region and a second region located on both sides of the channel region, the first electrode of the at least one transistor is electrically connected to the first region of the active pattern of the at least one transistor, and the second electrode of the at least one transistor is electrically connected to the second region of the active pattern of the at least one transistor.

[0020] In at least one pixel driving circuit, the second region of the active pattern of the second transistor, the second region of the active pattern of the third transistor, and the first region of the active pattern of the sixth transistor are integral structures. At least one of the patterns in the second region of the active pattern of the second transistor and the active pattern of the sixth transistor extends at least partially along the first direction, and the second region of the active pattern of the second transistor and the active pattern of the sixth transistor are arranged along the second direction.

[0021] The first adapter cable of the at least one data adapter cable is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit, and they are an integral structure.

[0022] The distance between the orthographic projection of at least a portion of the first adapter cable of the at least one data adapter cable on the substrate and the orthographic projection of at least a portion of the second region of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction on the substrate is less than the first threshold distance.

[0023] The row containing the first pixel driving circuit is the same row as the row containing the second pixel driving circuit, and the column containing the second pixel driving circuit is the next column after the column containing the first pixel driving circuit.

[0024] In an exemplary embodiment, the first adapter cable of the at least one data adapter cable is in the shape of a broken line and includes: a first adapter portion, a second adapter portion and a third adapter portion;

[0025] The first adapter extends at least partially along the first direction and is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit. The second adapter is electrically connected to the first adapter and the third adapter, respectively. The third adapter extends at least partially along the first direction and is electrically connected to the second adapter wire.

[0026] In an exemplary embodiment, the orthographic projection of the third adapter portion of the first adapter of the at least one data adapter on the substrate at least partially overlaps with the orthographic projection of at least a portion of the active pattern of the sixth transistor in the second pixel driving circuit extending along the first direction on the substrate.

[0027] In an exemplary embodiment, at least a portion of the first adapter portion of the first adapter of the at least one data adapter cable has its orthographic projection on the substrate located on the side of the second region of the active pattern of the second transistor in the second pixel driving circuit and the orthographic projection of at least one active pattern of the sixth transistor on the substrate away from the first pixel driving circuit.

[0028] In an exemplary embodiment, at least a portion of the first adapter portion of the first adapter cable of the at least one data adapter cable is projected onto the substrate between the orthographic projection of the active pattern of the fourth transistor in the first pixel driving circuit onto the substrate and the orthographic projection of the active pattern of the second transistor in the second pixel driving circuit onto the substrate.

[0029] The active pattern of the fourth transistor in at least one pixel driving circuit extends at least partially along the first direction, and the distance between the orthographic projection of at least a portion of the first adapter portion of the first adapter of the at least one data adapter on the substrate and the orthographic projection of the active pattern of the fourth transistor in the first pixel driving circuit on the substrate is less than a first threshold distance.

[0030] In an exemplary embodiment, it further includes: a plurality of scanning signal lines and a plurality of light emission signal lines disposed on the substrate, wherein the scanning signal lines and the light emission signal lines extend at least partially along the second direction;

[0031] The control electrode of the second transistor and the control electrode of the fourth transistor in the at least one pixel driving circuit are respectively electrically connected to at least one scan signal line, and the sixth transistor in the at least one pixel driving circuit is electrically connected to at least one light emission signal line.

[0032] The orthographic projection of the first adapter portion of the first adapter of the at least one data adapter on the substrate at least partially overlaps the orthographic projection of the scan signal line connected to at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate.

[0033] The orthographic projection of the second adapter portion of the first adapter of the at least one data adapter on the substrate is located between the orthographic projection of the scan signal line connected to the first pixel driving circuit on the substrate and the orthographic projection of the light emission signal line connected to the first pixel driving circuit on the substrate.

[0034] The orthographic projection of the third adapter portion of the first adapter of the at least one data adapter on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line connected to the first pixel driving circuit on the substrate.

[0035] In an exemplary embodiment, when the distance between the film layer where the first adapter of the at least one data adapter is located and the film layer where the active pattern of the at least one transistor is located is greater than the second threshold distance, the first adapter of the at least one data adapter is located on the side of the second adapter away from the substrate.

[0036] In an exemplary embodiment, the system further includes: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0037] The second adapter wire in the at least one data adapter wire and the first and second terminals of the at least one transistor are located in the third conductive layer, the first adapter wire in the at least one data adapter wire is located in the fourth conductive layer, and the data signal line is located in the fifth conductive layer.

[0038] In an exemplary embodiment, the at least one pixel driving circuit includes: a second transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein the third transistor is a driving transistor, the second terminal of the second transistor and the first terminal of the sixth transistor are electrically connected to the second terminal of the third transistor, the first terminal of the second transistor is electrically connected to the control terminal of the third transistor, the first terminal of the fourth transistor is electrically connected to the data signal line, and the second terminal of the fourth transistor is electrically connected to the first terminal of the third transistor.

[0039] The first adapter cable of the at least one data adapter cable is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit.

[0040] The orthographic projection of at least a portion of the first adapter cable of the at least one data adapter cable onto the substrate at least partially overlaps with the orthographic projection of at least a portion of the second region of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction and the orthographic projection of at least a portion of the active pattern of the sixth transistor extending along the first direction onto the substrate.

[0041] The row containing the first pixel driving circuit is the same row as the row containing the second pixel driving circuit, and the column containing the second pixel driving circuit is the next column after the column containing the first pixel driving circuit.

[0042] In an exemplary embodiment, it further includes: a plurality of scan signal lines and a plurality of light emission signal lines disposed on the substrate, wherein the control electrode of the second transistor and the control electrode of the fourth transistor in the at least one pixel driving circuit are respectively electrically connected to at least one scan signal line, and the sixth transistor in the at least one pixel driving circuit is electrically connected to at least one light emission signal line.

[0043] The first adapter cable of the at least one data adapter cable is a straight type;

[0044] The orthographic projection of the first adapter line of the at least one data adapter line on the substrate at least partially overlaps the orthographic projections of the scan signal line and the light emission signal line connected to at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate.

[0045] In an exemplary embodiment, it further includes: a plurality of first reset signal lines disposed on the substrate;

[0046] The at least one pixel driving circuit includes: a first transistor and a seventh transistor, wherein the control electrode of the first transistor is electrically connected to at least one first reset signal line, and the second electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor and the light-emitting device connected to the pixel driving circuit.

[0047] The orthographic projection of the second adapter line of the at least one data adapter line on the substrate lies between the orthographic projection of the light-emitting signal line connected to the first pixel driving circuit on the substrate and the orthographic projection of the first reset signal line connected to the next row of pixel driving circuits of the first pixel driving circuit on the substrate.

[0048] In an exemplary embodiment, it further includes: a plurality of first power lines disposed on the substrate, wherein the first power lines are located on the side of the data signal lines closer to the substrate;

[0049] At least one pixel driving circuit includes: a capacitor, the capacitor including: a first plate and a second plate, the second plate of the capacitor having an opening, the orthographic projection of the opening on the substrate being within the range of the orthographic projection of the first plate of the capacitor on the substrate;

[0050] The orthographic projection of the at least one first power line on the substrate covers the orthographic projection of the opening of the second plate of the capacitor in the pixel driving circuit to which the first power line is connected on the substrate.

[0051] In an exemplary embodiment, the display area includes a first display area and a second display area located at least one side of the first display area. The first and second display areas each include an array of light-emitting devices disposed on the substrate, and an array of pixel driving circuits and multiple data signal lines disposed in the second display area.

[0052] At least one light-emitting device located in the first display area is electrically connected to at least one pixel driving circuit located in the second display area;

[0053] The light-emitting device located in at least one of the first display area and the second display area includes: a first light-emitting device, a second light-emitting device, and a third light-emitting device;

[0054] In the same display area, the light-emitting area of ​​the first light-emitting device is larger than that of the second light-emitting device, but smaller than that of the third light-emitting device;

[0055] The light-emitting area of ​​the first light-emitting device located in the first display area is smaller than the light-emitting area of ​​the first light-emitting device located in the second display area; the light-emitting area of ​​the second light-emitting device located in the first display area is smaller than the light-emitting area of ​​the second light-emitting device located in the second display area; and the light-emitting area of ​​the third light-emitting device located in the first display area is smaller than the light-emitting area of ​​the third light-emitting device located in the second display area.

[0056] At least two second light-emitting devices located in the first display area are connected to the same pixel driving circuit located in the second display area.

[0057] In an exemplary embodiment, it further includes: a plurality of anode connection lines;

[0058] At least one anode connection line is electrically connected to at least one light-emitting device located in the first display area and at least one pixel driving circuit located in the second display area, respectively;

[0059] The anode connection wire is a transparent conductive wire.

[0060] In an exemplary embodiment, the orthographic projection of the at least one data signal line on the substrate is located in the second display area, and the at least one data signal line is at least partially surrounding the periphery of the first display area.

[0061] In an exemplary embodiment, it further includes: a plurality of second power lines and a plurality of power conversion lines disposed on the substrate; at least one light-emitting device is electrically connected to at least one second power line, and the at least one second power line extends at least partially along the first direction;

[0062] The second power line is arranged on the same layer as the data signal line, and at least one power adapter cable is electrically connected to the at least one second power line.

[0063] Secondly, this disclosure also provides a display device, including: the above-mentioned display substrate and a photosensor;

[0064] The photosensitive sensor is located within the first display area of ​​the display substrate, and is located on the side away from the light-emitting side of the display substrate.

[0065] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0066] Overview of the attached figures

[0067] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0068] Figure 1 is a schematic diagram of a display device;

[0069] Figure 2 is a schematic diagram of the structure of a display substrate;

[0070] Figure 3 is an equivalent circuit diagram of a pixel driving circuit;

[0071] Figure 4 is a timing diagram of the pixel driving circuit provided in Figure 3;

[0072] Figure 5 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0073] Figure 6 is a schematic diagram of the display substrate provided in the second display area according to an embodiment of the present disclosure;

[0074] Figure 7 is a second schematic diagram of the display substrate provided in the second display area according to an embodiment of the present disclosure;

[0075] Figure 8 is a schematic diagram of the display substrate provided in the second display area according to an embodiment of this disclosure;

[0076] Figure 9 is a schematic diagram of the arrangement of light-emitting devices in the display area;

[0077] Figure 10 is a schematic diagram showing the connection between the pixel driving circuit of the second display area and the light-emitting device of the first display area;

[0078] Figure 11 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure.

[0079] Detailed Explanation

[0080] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0081] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0082] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0083] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0084] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0085] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0086] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0087] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0088] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0089] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0090] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0091] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0092] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0093] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0094] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include: a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (e.g., D1 to Dn), the scan driver is connected to multiple scan signal lines (e.g., S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (e.g., E1 to Eo). Here, n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include: a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit may include at least a pixel driving circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines respectively.

[0095] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, transmit stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. An LED driver can generate LED control signals to be provided to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, an LED driver can sequentially provide transmit signals with off-level pulses to LED signal lines E1 to Eo. For example, an LED driver can be configured as a shift register and can generate LED control signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal.

[0096] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area AA, a bonding area CC located on one side of the display area AA, and a border area BB located on the other sides of the display area AA.

[0097] In an exemplary embodiment, the display area AA may be a flat area comprising a plurality of sub-pixels Pxij that make up the pixel array. The plurality of sub-pixels Pxij may be configured to display moving or still images, and the display area AA may be referred to as the effective area (AA). In some examples, the display substrate may be a flexible substrate, and thus, the display substrate may be deformable, such as being rolled up, bent, folded, or rolled up.

[0098] In an exemplary embodiment, the bonding area may include a lead area, a bending area, and a composite circuit area arranged sequentially along a direction away from the display area, with the lead area connected to the display area, the bending area connected to the lead area, and the composite circuit area connected to the bending area.

[0099] In an exemplary embodiment, the lead area can be provided with multiple leads. One end of the multiple leads is connected to multiple data signal lines in the display area, and the other end of the multiple leads crosses the bend area and connects to the integrated circuit in the composite circuit area, so that the integrated circuit applies data signal lines through the leads.

[0100] In an exemplary embodiment, the bending area can be bent with a curvature, which can reverse the surface of the composite circuit area. That is, the upward-facing surface of the composite circuit area can be transformed into a downward-facing surface by bending the bending area, with the third direction intersecting the first direction. In an exemplary embodiment, when the bending area is bent, the composite circuit area can overlap with the display area in the thickness direction.

[0101] In an exemplary embodiment, the composite circuit region may include an anti-static region, a driver chip region, and a bonding pin region. An integrated circuit (IC) may be bonded to the driver chip region, and a flexible printed circuit (FPC) may be bonded to the bonding pin region. In an exemplary embodiment, the integrated circuit can generate driving signals required to drive sub-pixels and can provide these driving signals to the sub-pixels in the display area. For example, the driving signal may be a data signal that drives the brightness of the sub-pixels. In an exemplary embodiment, the integrated circuit may be bonded to the driver chip region via an anisotropic conductive film or other means. The width of the integrated circuit in the second direction may be smaller than the width of the composite circuit region in the second direction, and the second direction intersects the first direction. In an exemplary embodiment, the bonding pin region may be provided with pads including multiple pins, and the flexible printed circuit board may be bonded to the pads.

[0102] In an exemplary embodiment, the bezel region BB may include a circuit region, a power line region, a crack dam region, and a cutting region arranged sequentially along a direction away from the display region AA. The circuit region, connected to the display region AA, may include at least a scan driver and a light-emitting driver. The power line region, connected to the circuit region, may include at least bezel power leads extending in a direction parallel to the edge of the display region. The crack dam region, connected to the power line region, may include at least a plurality of cracks formed on the composite insulating layer. The cutting region, connected to the crack dam region, may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting grooves respectively.

[0103] The display area may include multiple pixel units arranged in a matrix. At least one pixel unit may include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third and fourth sub-pixels emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit may be configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device, thereby driving the light-emitting device to emit light. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0104] In an exemplary embodiment, at least one pixel driving circuit may be electrically connected to at least one light-emitting device.

[0105] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light.

[0106] In some examples, the shape of the light-emitting area of ​​the light-emitting device of at least one sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal.

[0107] In an exemplary embodiment, the pixel driving circuit may include a plurality of transistors and at least one capacitor. For example, the pixel driving circuit may be a 3T1C (3 transistors and 1 capacitor) structure, a 5T1C (5 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or an 8T1C (8 transistors and 1 capacitor) structure.

[0108] In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel driving circuit. The emitted color of the light-emitting device can be determined as needed. The light-emitting device may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting device can be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited in this respect.

[0109] Figure 3 is an equivalent circuit diagram of a pixel driving circuit. Figure 3 illustrates the pixel driving circuit with a 7T1C structure as an example. As shown in Figure 3, at least one pixel driving circuit is electrically connected to the scan signal line Gate, the first reset signal line Reset1, the second reset signal line Reset2, the data signal line Data, the light emission signal line EM, the first initial signal line INIT1, the second initial signal line INIT2, and the first power supply line VDD, respectively. The light emission device L is electrically connected to the pixel driving circuit and the second power supply line VSS, respectively. In some examples, the first power supply line VDD is configured to provide a constant first power signal to the pixel driving circuit, which is a positive voltage signal, and the second power supply line VSS is configured to provide a constant second power signal to the pixel driving circuit, which is a negative voltage signal. The scan signal line Gate is configured to provide a scan signal to the pixel driving circuit. The first reset signal line Reset1 is configured to provide a first reset signal to the pixel driving circuit. The second reset signal line Reset2 is configured to provide a second reset signal to the pixel driving circuit. The data signal line Data is configured to provide a data signal to the pixel driving circuit. The light emission signal line EM is configured to provide a light emission control signal to the pixel driving circuit. The first initial signal line INIT1 is configured to provide a first initial signal to the pixel driving circuit. The second initial signal line INIT2 is configured to provide a second initial signal to the pixel driving circuit.

[0110] In some examples, the signal received by the second reset signal line connected to at least one row of pixel driving circuits is the same as the signal received by the scan signal line connected to at least one row of pixel driving circuits, and the signal received by the first reset signal line connected to at least one row of pixel driving circuits is the same as the signal received by the scan signal line connected to at least one row of pixel driving circuits. For example, the signal received by the second reset signal line connected to the nth row of pixel driving circuits is the same as the signal received by the scan signal line connected to the (n-1)th row of pixel driving circuits, and the signal received by the first reset signal line connected to the nth row of pixel driving circuits is the same as the signal received by the scan signal line connected to the (n-2)th row of pixel driving circuits. Since the signal received by at least one of the first and second reset signal lines connected to at least one row of pixel driving circuits is the same as the signal received by the scan signal line connected to at least one row of pixel driving circuits, the scan driver located in the bezel area can include: a gate driving circuit, which is electrically connected to the first reset signal line, the second reset signal line, and the scan signal line connected to the at least one row of pixel driving circuits, respectively. This reduces the area occupied by the circuit area and improves the resolution of the display substrate. Resolution (Pixels Per Inch, or PPI for short) refers to the number of pixels per unit area, also known as pixel density. The higher the PPI value, the higher the density at which the display substrate can display the image, and the richer the details of the image.

[0111] In some examples, the signal received by the first reset signal line connected to the n+1 row pixel driving circuit is the same as the signal received by the second reset signal line connected to the nth row pixel driving circuit. That is, the first reset signal line connected to the n+1 row pixel driving circuit and the second reset signal line connected to the nth row pixel driving circuit can be the same signal. In this way, the number of signal lines of the display substrate can be reduced, and a high PPI of the display substrate can be achieved.

[0112] In some examples, the signal received by the first initial signal line connected to the nth row pixel driving circuit is the same as the signal received by the second initial signal line connected to the nth row pixel driving circuit. That is, the first initial signal line connected to the nth row pixel driving circuit and the second initial signal line connected to the nth row pixel driving circuit can be the same signal. In this way, the number of signal lines of the display substrate can be reduced, and a high PPI of the display substrate can be achieved.

[0113] In an exemplary embodiment, as shown in FIG3, at least one pixel driving circuit includes: a first transistor T1 to a seventh transistor T7 and a capacitor C, wherein the capacitor C includes: a first plate and a second plate. The control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5. The control electrode of the second transistor T2 is electrically connected to the scan signal line Gate, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first plate of capacitor C is electrically connected to the first node N1, and the second plate of capacitor C is electrically connected to the first power supply line VDD.

[0114] In this disclosure, the first node N1 is the connection point of capacitor C, first transistor T1, second transistor T2 and third transistor T3. Specifically, the first node N1 is the connection point of the first plate of capacitor C, the second electrode of first transistor T1, the first electrode of second transistor T2 and the control electrode of third transistor T3.

[0115] In this disclosure, the second node N2 is the connection point of the third transistor T3, the fourth transistor T4 and the fifth transistor T5. Specifically, the second node N2 is the connection point of the first terminal of the third transistor, the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5.

[0116] In this disclosure, the third node N3 is the connection point of the second transistor T2, the third transistor T3 and the sixth transistor T6. Specifically, the third node N3 is the connection point of the second terminal of the second transistor T2, the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6.

[0117] In this disclosure, the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting device L. Specifically, the fourth node N4 is the connection point of the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the anode of the light-emitting device L.

[0118] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0119] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0120] In an exemplary embodiment, the seven transistors of the pixel driving circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0121] Figure 4 is a timing diagram of the pixel driving circuit shown in Figure 3. The operation of the pixel driving circuit shown in Figure 3 will be described below with reference to Figure 4. In the figure, the first transistor T1 to the seventh transistor T7 of the pixel driving circuit are P-type transistors.

[0122] In some exemplary embodiments, as shown in Figures 3 and 4, the operation of the pixel driving circuit during a frame display time period may include: a first stage P1, a second stage P2, a third stage P3, and a fourth stage P4.

[0123] In the first stage P1, also known as the first reset stage, the signal on the first reset signal line Reset1 is low, while the signals on the scan signal line Gate, the second reset signal line Reset2, and the light emission signal line EM are high. The first transistor T1 is turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0124] The first transistor T1 is turned on, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1, clear its internal pre-stored voltage, and complete the initialization.

[0125] In the second stage (P2), the second reset stage, the signal on the second reset signal line Reset2 is low, while the signals on the scan signal line Gate, the first reset signal line Reset1, and the light emission signal line EM are high. The seventh transistor T7 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0126] The seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4 to initialize (reset) the anode of the light-emitting device L, clear its internal pre-stored voltage, complete the initialization, and ensure that the light-emitting device L does not emit light.

[0127] The third stage, P3, is called the data writing stage or threshold compensation stage. The Gate signal is low, while the Reset1, Reset2, and EM signals are high. The Data signal line outputs the data signal. The second transistor T2 and the fourth transistor T4 are turned on, while the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0128] The second transistor T2 and the fourth transistor T4 are turned on. The data signal output from the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the turned-on third transistor T3, and the turned-on second transistor T2, until the signal at the first node satisfies Vdata-|Vth|, where Vdata is the voltage value of the data signal output from the data signal line Data, and Vth is the threshold voltage of the third transistor T3.

[0129] The fourth stage, P4, is called the light-emitting stage. The light-emitting signal line EM is a low-level signal, while the first reset signal line Reset1, the second reset signal line Reset2, and the scan signal line Gate are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off.

[0130] When the fifth transistor T5 and the sixth transistor T6 are turned on, the power signal output from the first power line VDD provides a driving voltage to the fourth node N4 (which is the anode of the light-emitting device L) through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, driving the light-emitting device L to emit light.

[0131] During the pixel driving circuit's operation, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode and its first electrode. Since the voltage at the first node N1 is Vdata - |Vth|, the driving current of the third transistor T3 is: I = K × (Vgs - Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×(Vdd-Vdata) 2

[0132] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vdd is the voltage value of the power signal output by the first power line VDD.

[0133] The concept of full-screen phones has garnered widespread attention in the mobile phone market and represents the future direction of mobile phone development. Full-screen phones employ a Full Display with Camera (FDC) structure, where the camera area is also displayed. This FDC structure allows the almost entirely visible front area to be screen, providing users with a superior display experience.

[0134] With the development of OLED display technology, consumers have increasingly higher demands for display effects, and ultra-narrow bezels have become a new trend in display product development. Therefore, narrow bezels and even bezel-less designs are receiving increasing attention in OLED display product design. To achieve narrow bezels, the display substrate employs a Fanout-in-Panel (FIP) structure, where one end of multiple data adapters connects to multiple data signal lines in the display area, and the other end extends to the bonding area, connecting to the integrated circuits in the bonding area. Since the bonding area does not require fan-shaped diagonal lines, the width of the fan-out area is reduced, effectively decreasing the width of the bottom bezel.

[0135] The load between at least one data transfer line in the display substrate and the active pattern of at least one transistor (e.g., the active pattern of the second transistor, the active pattern of the third transistor, and the active pattern of the sixth transistor) is large, which causes the voltage value of the first node in at least one pixel driving circuit to decrease. This results in a larger driving voltage output by at least one pixel driving circuit, leading to higher brightness in some areas of the display substrate. This reduces the brightness uniformity of the display substrate and affects the display effect of the display substrate.

[0136] Therefore, this disclosure provides a display substrate that can improve the brightness uniformity of the display substrate and enhance the display effect of the display substrate.

[0137] Figure 5 is a schematic diagram of the structure of the display substrate provided in the embodiments of this disclosure; Figure 6 is a schematic diagram of the display substrate provided in the embodiments of this disclosure in the second display area (first diagram); Figure 7 is a schematic diagram of the display substrate provided in the embodiments of this disclosure in the second display area (second diagram); and Figure 8 is a schematic diagram of the display substrate provided in the embodiments of this disclosure in the second display area (third diagram). As shown in Figure 5, the display substrate provided in the embodiments of this disclosure includes a substrate and pixel driving circuits arranged in an array on the substrate, multiple data signal lines (Data), and multiple data transfer lines (FL). At least one data transfer line (FL) is electrically connected to at least one data signal line (Data).

[0138] The second display area A2 includes: at least one pixel driving circuit disposed on a substrate, electrically connected to at least one of a plurality of data signal lines Data, wherein at least one of the plurality of data signal lines Data extends at least partially along a first direction D1.

[0139] In an exemplary embodiment, as shown in FIG5, the display substrate includes: having a display area AA, the display area AA including: a first display area A1 and a second display area A2 located on at least one side of the first display area A1, the first display area A1 and the second display area A2 including: light-emitting devices arranged in an array on the substrate, and pixel driving circuits arranged in an array and multiple data signal lines Data located in the second display area A2.

[0140] As shown in Figures 6 to 8, at least one data adapter cable FL includes: a first adapter cable FL1 extending at least partially along a first direction D1.

[0141] In an exemplary embodiment, the pixel driving circuit includes at least one transistor and a capacitor. The at least one transistor includes an active pattern, a control electrode, a first electrode, and a second electrode. The capacitor includes a first electrode plate and a second electrode plate. The pixel driving circuit can be the pixel driving circuit provided in FIG3.

[0142] In this disclosure, the distance between A and B can refer to the distance between the boundary of A near B and the boundary of B near A, or it can be the distance between the boundary of A away from B and the boundary of B away from A, or it can be the distance between any part of A and any part of B. This disclosure does not limit it in any way.

[0143] In this disclosure, the distance L1 between at least a portion of the orthographic projection of the first adapter FL1 of at least one data adapter on the substrate and at least a portion of the orthographic projection of the active pattern of at least one transistor extending along the first direction D1 on the substrate is less than a first threshold distance, or the distance between the film layer containing the first adapter FL1 of at least one data adapter and the film layer containing the active pattern of at least one transistor is greater than a second threshold distance. Figures 6 and 7 illustrate the case where the distance between at least a portion of the orthographic projection of the first adapter FL1 of at least one data adapter on the substrate and at least a portion of the orthographic projection of the active pattern of at least one transistor extending along the first direction D1 on the substrate is less than the first threshold distance, and Figure 8 illustrates the case where the distance between the film layer containing the first adapter FL1 of at least one data adapter and the film layer containing the active pattern of at least one transistor is greater than the second threshold distance.

[0144] This disclosure reduces or eliminates the load between the data adapter and a portion of the active pattern in the pixel driving circuit by means of a first threshold distance between the orthographic projection of at least a portion of the first adapter of at least one data adapter on the substrate and the orthographic projection of at least a portion of the active pattern of at least one transistor extending along a first direction on the substrate, or a second threshold distance between the film layer where the first adapter of at least one data adapter is located and the film layer where the active pattern of at least one transistor is located.

[0145] In an exemplary embodiment, the second display area A2 is configured to display images, and the position of the first display area A1 may correspond to the position of the optical device. The first display area A1 is configured to display images and transmit light, and the transmitted light is received by the optical device. In an exemplary embodiment, the first display area may be referred to as a light-transmitting display area or an under-display camera (UDC) area, and the second display area may be referred to as a normal display area.

[0146] In an exemplary embodiment, the position of the first display area A1 in the second display area A2 is not limited. It may be located at the upper or lower part of the second display area A2, or at the edge of the second display area A2. This disclosure does not limit it in any way.

[0147] In an exemplary embodiment, the shape of the first display area A1 in a plane parallel to the display device can be any one or more of the following: rectangular, polygonal, circular, and elliptical. The optical device can be an optical sensor such as a fingerprint recognition device, a camera device, or a 3D imaging device. For example, the first display area A1 can be circular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area can be rectangular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the inscribed circle of the first display area.

[0148] In some exemplary embodiments, the display area AA can be rectangular, such as a rounded rectangle. The second display area A2 can be circular or elliptical. However, this embodiment is not limited to this. For example, the second display area A2 can be other shapes such as rectangle, pentagon, or hexagon.

[0149] In an exemplary embodiment, the resolutions of the first display area A1 and the second display area A2 can be the same, or the resolution of the first display area A1 can be lower than the resolution of the second display area A2. For example, the resolution of the first display area A1 can be approximately 50% to 70% of the resolution of the second display area A2. Resolution (Pixels Per Inch, abbreviated as PPI) refers to the number of pixels per unit area, also known as pixel density. The higher the PPI value, the higher the density at which the display substrate can display the image, and the richer the detail of the image.

[0150] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The display substrate includes a plurality of sub-pixels, each sub-pixel including a pixel driving circuit composed of a plurality of transistors and capacitors, and a light-emitting device.

[0151] In exemplary embodiments, the light-emitting device may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). Typical dimensions (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. Typical dimensions (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0152] In an exemplary embodiment, the light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode of the light-emitting device is connected to a pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and the cathode.

[0153] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0154] In an exemplary embodiment, as shown in Figures 6 to 8, at least one data adapter cable FL further includes a second adapter cable FL2 that extends at least partially along the second direction D2.

[0155] In this disclosure, the first direction D1 intersects with the second direction D2, wherein the intersection of the first direction D1 and the second direction D2 means that the included angle between the first direction D1 and the second direction D2 is approximately 70 degrees to 90 degrees. The first direction D1 and the second direction D2 may be located in the same plane. For example, the first direction D1 may be an extension direction parallel to the data signal line Data; the second direction may be an extension direction parallel to the scan signal line or the light emission signal line.

[0156] In an exemplary embodiment, a first adapter cable FL1 and a second adapter cable FL2 located in the same data adapter cable FL are electrically connected, and the orthographic projection of the second adapter cable FL2 of at least one data adapter cable FL on the substrate at least partially overlaps with the orthographic projection of at least one data signal line of a plurality of data signal lines on the substrate.

[0157] In an exemplary embodiment, at least one data adapter cable FL further includes a third adapter cable (not shown) extending at least partially along a first direction D1. The third adapter cable is electrically connected to a signal line in a lead area within the bonding region.

[0158] In an exemplary embodiment, the second display area can be divided into a first sub-display area and a second sub-display area. The first sub-display area is the region where a data transfer cable is provided, and the second sub-display area is the remaining display area excluding the first sub-display area. The second sub-display area is provided with a virtual transfer cable, which is not electrically connected to at least one data signal line. The provision of the virtual transfer cable can improve the etching uniformity of the display substrate.

[0159] In an exemplary embodiment, the first threshold distance may be less than 1 micrometer.

[0160] In an exemplary embodiment, the second threshold distance is the distance between the film layer containing the active pattern of at least one transistor and the film layer containing the first and second electrodes of at least one transistor.

[0161] In an exemplary embodiment, as shown in Figures 6 and 7, when the distance between at least a portion of the first adapter FL1 of at least one data adapter and at least a portion of the active pattern of at least one transistor extending along the first direction D1 and projected onto the substrate is less than a first threshold, the first adapter FL1 and the second adapter FL2 of at least one data adapter FL are disposed on the same layer.

[0162] In an exemplary embodiment, as shown in Figures 6 to 8, the second display area A2 further includes: multiple scan signal lines Gate, multiple light emission signal lines EM, multiple first reset signal lines Reset1, and multiple second reset signal lines Reset2. At least one of the multiple scan signal lines Gate, multiple light emission signal lines EM, multiple first reset signal lines Reset1, and multiple second reset signal lines Reset2 extends at least partially along the second direction D2. In Figures 6 to 8, Gate(n) refers to the scan signal line connected to the nth row pixel driving circuit, EM(n) refers to the light emission signal line connected to the nth row pixel driving circuit, Reset1(n) refers to the first reset signal line connected to the nth row pixel driving circuit, Reset2(n) refers to the second reset signal line connected to the nth row pixel driving circuit, and Reset1(n) and Reset2(n-1) connected to the (n-1)th row pixel driving circuit are the same signal line.

[0163] In an exemplary embodiment, as shown in Figures 6 to 8, at least one of the multiple scan signal lines Gate, multiple light emission signal lines EM, multiple first reset signal lines Reset1, and multiple second reset signal lines Reset2 is located on the side of the film layer containing the data transfer line FL that is closer to the substrate.

[0164] In an exemplary embodiment, the display substrate may include: a circuit structure layer disposed on the substrate, the circuit structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer.

[0165] In an exemplary embodiment, the semiconductor layer may include at least an active pattern located on at least one transistor. The active pattern located on at least one transistor may include: active pattern 11 of the first transistor to active pattern 71 of the seventh transistor.

[0166] In an exemplary embodiment, the first conductive layer may include at least: multiple scan signal lines Gate, multiple light emission signal lines EM, multiple first reset signal lines Reset1, multiple second reset signal lines Reset2, and a first electrode C1 located at the control electrode of at least one transistor and a capacitor.

[0167] In an exemplary embodiment, the second conductive layer may include at least the first electrode of a capacitor.

[0168] In an exemplary embodiment, the third conductive layer may include at least: a first electrode and a second electrode of at least one transistor. The first electrode and the second electrode of at least one transistor may include: a first electrode 13 and a second electrode 24 of a first transistor, a first electrode 23 of a second transistor, a first electrode 43 of a fourth transistor, a first electrode 53 of a fifth transistor, a second electrode 63 of a sixth transistor, and a first electrode 73 and a second electrode 74 of a seventh transistor.

[0169] In an exemplary embodiment, the fourth conductive layer may include at least a first power line.

[0170] In an exemplary embodiment, the fifth conductive layer may include at least: data signal lines.

[0171] In an exemplary embodiment, the display substrate may further include a light-emitting structure layer disposed on the side of the circuit structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate, on a plane perpendicular to the display substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0172] In an exemplary embodiment, the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and the cathode.

[0173] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0174] In an exemplary embodiment, the touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0175] In an exemplary embodiment, the active pattern of at least one transistor includes: a channel region and a first region and a second region located on both sides of the channel region. The first electrode of at least one transistor is electrically connected to the first region of the active pattern of at least one transistor, and the second electrode of at least one transistor is electrically connected to the second region of the active pattern of at least one transistor. In the at least one pixel driving circuit, the second region 21-2 of the active pattern of the second transistor, the second region 31-2 of the active pattern of the third transistor, and the first region 61-1 of the active pattern of the sixth transistor are integral structures. At least one pattern in the second region 21-2 of the active pattern of the second transistor and the active pattern 61 of the sixth transistor extends at least partially along a first direction D1, and the second region 21-2 of the active pattern of the second transistor and the active pattern 61 of the sixth transistor are arranged along a second direction D2.

[0176] As shown in Figures 6 and 7, at least one data transfer cable's first transfer cable FL1 is electrically connected to the first terminal 43 of the fourth transistor in the first pixel driving circuit, and they are an integral structure.

[0177] As shown in Figures 6 and 7, the distance L1 between at least a portion of the orthographic projection of the first adapter FL1 of at least one data adapter on the substrate and the orthographic projection of at least a portion of the second region 21-2 of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction D1 on the substrate is less than a first threshold distance.

[0178] As shown in Figures 6 and 7, the row containing the first pixel driving circuit is the same as the row containing the second pixel driving circuit, and the column containing the second pixel driving circuit is the next column after the column containing the first pixel driving circuit. In Figures 6 and 7, the pixel driving circuit in the nth row and mth column is the first pixel driving circuit, and the pixel driving circuit in the nth row and (m+1)th column is the second pixel driving circuit.

[0179] In an exemplary embodiment, as shown in Figures 6 and 7, the first adapter cable FL1 of at least one data adapter cable is in the shape of a broken line and includes: a first adapter portion FL11, a second adapter portion FL12 and a third adapter portion FL13.

[0180] In an exemplary embodiment, as shown in Figures 6 and 7, the first adapter FL11 extends at least partially along the first direction D1 and is electrically connected to the first pole 43 of the fourth transistor in the first pixel driving circuit. The second adapter FL12 is electrically connected to the first adapter FL11 and the third adapter FL13, respectively. The third adapter FL13 extends at least partially along the first direction D1 and is electrically connected to the second adapter line FL2.

[0181] In an exemplary embodiment, as shown in Figures 6 and 7, for the same first adapter cable FL1, the first adapter portion FL11 and the second adapter portion FL12 are set at an obtuse angle, and the second adapter portion FL12 and the third adapter portion FL13 are set at an obtuse angle.

[0182] In an exemplary embodiment, as shown in Figures 6 and 7, the orthographic projection of the third adapter portion FL13 of the first adapter FL1 of at least one data adapter cable onto the substrate at least partially overlaps with the orthographic projection of at least a portion of the active pattern 61 of the sixth transistor in the second pixel driving circuit extending along the first direction D1 onto the substrate. Since the sixth transistor is not electrically connected to any signal line, the orthographic projection of the third adapter portion FL13 of the first adapter FL1 of the at least one data adapter cable in this disclosure onto the substrate does not overlap with the orthographic projection of the signal line connected to at least one pixel driving circuit onto the substrate. This reduces the coupling capacitance between the data adapter cable and the signal line connected to at least one pixel driving circuit, thus ensuring the reliability of the display substrate.

[0183] In an exemplary embodiment, as shown in FIG6, at least a portion of the orthographic projection of the first adapter portion FL11 of the first adapter cable of at least one data adapter cable onto the substrate is located on the side of the orthographic projection of at least one of the active patterns of the second region 21-2 of the active pattern of the second transistor and the active pattern 61 of the sixth transistor in the second pixel driving circuit away from the first pixel driving circuit. The distance between the first adapter portion FL11 of the first adapter cable of the first adapter cable of at least one data adapter cable and the first plate of the capacitor in the first pixel driving circuit is relatively large, which can prevent crosstalk between signals.

[0184] In an exemplary embodiment, as shown in FIG7, at least a portion of the first adapter portion FL11 of the first adapter cable FL1 of at least one data adapter cable is projected onto the substrate between the orthogonal projection of the active pattern 41 of the fourth transistor in the first pixel driving circuit onto the substrate and the orthogonal projection of the active pattern 21 of the second transistor in the second pixel driving circuit onto the substrate.

[0185] In an exemplary embodiment, as shown in FIG7, the active pattern 41 of the fourth transistor in at least one pixel driving circuit extends at least partially along the first direction D1, and the distance L2 between the orthographic projection of at least a portion of the first adapter portion FL11 of the first adapter cable FL1 of at least one data adapter cable on the substrate and the orthographic projection of the active pattern 41 of the fourth transistor in the first pixel driving circuit on the substrate is less than a first threshold distance.

[0186] In an exemplary embodiment, as shown in Figures 6 and 7, the orthographic projection of the first adapter portion FL11 of the first adapter cable FL1 of at least one data adapter cable on the substrate at least partially overlaps with the orthographic projection of the scan signal line Gate connected to at least one of the pixel driving circuits in the first pixel driving circuit and the second pixel driving circuit on the substrate.

[0187] In an exemplary embodiment, as shown in Figures 6 and 7, the orthographic projection of the second adapter portion FL12 of the first adapter FL1 of at least one data adapter on the substrate is located between the orthographic projection of the scan signal line Gate connected to the first pixel driving circuit on the substrate and the orthographic projection of the light emission signal line EM connected to the first pixel driving circuit on the substrate.

[0188] In an exemplary embodiment, as shown in Figures 6 and 7, the orthographic projection of the third adapter portion FL13 of the first adapter FL1 of at least one data adapter on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line EM connected to the first pixel driving circuit on the substrate.

[0189] The arrangement of the first to third adapters in at least one data adapter in this disclosure can improve the reliability of the display substrate by reducing the coupling capacitance between the signal line connecting at least one data adapter and at least one pixel driving circuit.

[0190] In an exemplary embodiment, as shown in FIG8, when the distance between the film layer where the first adapter FL1 of at least one data adapter line is located and the film layer where the active pattern of at least one transistor is located is greater than a second threshold distance, the first adapter FL1 of at least one data adapter line FL is located on the side of the second adapter FL2 away from the substrate.

[0191] In an exemplary embodiment, as shown in FIG8, the third conductive layer further includes at least: a second adapter FL2 in at least one data adapter FL.

[0192] In an exemplary embodiment, as shown in FIG8, the fourth conductive layer includes at least: a first adapter line FL1 in at least one data adapter line FL.

[0193] In an exemplary embodiment, as shown in FIG8, at least one data transfer cable's first transfer cable FL1 is electrically connected to the first terminal 43 of the fourth transistor in the first pixel driving circuit.

[0194] In an exemplary embodiment, as shown in FIG8, at least a portion of the orthographic projection of the first adapter line FL1 of at least one data adapter line onto the substrate at least partially overlaps with at least a portion of the second region 21-2 of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction D1 and at least a portion of the active pattern of the sixth transistor 61 extending along the first direction D1 onto the substrate. The row containing the first pixel driving circuit and the row containing the second pixel driving circuit are in the same row, and the column containing the second pixel driving circuit is the next column after the column containing the first pixel driving circuit. In FIG8, the pixel driving circuit in the nth row and mth column is the first pixel driving circuit, and the pixel driving circuit in the nth row and (m+1)th column is the second pixel driving circuit.

[0195] In an exemplary embodiment, as shown in FIG8, the first adapter cable FL1 of at least one data adapter cable is a straight type.

[0196] In an exemplary embodiment, as shown in FIG8, the orthographic projection of the first adapter line FL1 of at least one data adapter line on the substrate at least partially overlaps with the orthographic projections of the scan signal line Gate and the light emission signal line EM connected to at least one of the pixel driving circuits in the first pixel driving circuit and the second pixel driving circuit on the substrate.

[0197] In an exemplary embodiment, as shown in FIG8, the orthographic projection of the second adapter line FL2 of at least one data adapter line on the substrate at least partially overlaps with the orthographic projection of the active pattern 71 of the seventh transistor in at least one pixel driving circuit on the substrate, and is located between the orthographic projection of the light emission signal line EM connected to the first pixel driving circuit on the substrate and the orthographic projection of the first reset signal line Reset1 connected to the next row of pixel driving circuits of the first pixel driving circuit on the substrate.

[0198] The arrangement of the first and second adapters in at least one data adapter in this disclosure can improve the reliability of the display substrate by reducing the coupling capacitance between the signal line connecting the at least one data adapter and at least one pixel driving circuit.

[0199] The data transfer cable configuration in this disclosure makes efficient use of the layout space.

[0200] In an exemplary embodiment, as shown in FIG8, the display substrate further includes: a plurality of first power lines VDD disposed on the substrate, wherein the first power lines VDD are located on the side of the data signal line Data close to the substrate.

[0201] In an exemplary embodiment, the second plate of the capacitor has an opening V, and the orthographic projection of the opening V on the substrate is within the range of the orthographic projection of the first plate C1 of the capacitor on the substrate.

[0202] In an exemplary embodiment, the orthographic projection of at least one first power line VDD on the substrate covers the orthographic projection of the opening V on the second plate of the capacitor in the pixel driving circuit to which the first power line VDD is connected. This coverage of the opening V on the second plate of the capacitor by the orthographic projection of at least one first power line VDD on the substrate avoids the influence of other signal lines on the first plate of the capacitor, thus ensuring the stability of the signal at the first node in the pixel driving circuit.

[0203] In an exemplary embodiment, at least one light-emitting device located in the first display area A1 is electrically connected to at least one pixel driving circuit located in the second display area A2. The first display area A1 in this disclosure does not have a pixel driving circuit, which can improve the light transmittance of the first display area.

[0204] Figure 9 is a schematic diagram of the arrangement of light-emitting devices in the display area. As shown in Figure 9, the light-emitting devices located in at least one of the first display area A1 and the second display area A2 include: a first light-emitting device, a second light-emitting device, and a third light-emitting device. For example, the wavelength of light emitted by the second light-emitting device is greater than the wavelength of light emitted by the third light-emitting device, but less than the wavelength of light emitted by the first light-emitting device. For instance, the first light-emitting device can be a red light-emitting device, the second light-emitting device can be a green light-emitting device, and the third light-emitting device can be a blue light-emitting device. However, this embodiment is not limited in this respect.

[0205] In an exemplary embodiment, as shown in FIG9, in the first display area A1 or the second display area A2, a plurality of second light-emitting devices are arranged at certain intervals in the i-th row, the first light-emitting devices and the third light-emitting devices are alternately arranged in the (i+1)-th row adjacent to the i-th row, the plurality of second light-emitting devices are arranged at certain intervals in the (i+2)-th row adjacent to the (i+1)-th row, and the first light-emitting devices and the third light-emitting devices are alternately arranged in the (i+3)-th row adjacent to the (i+2)-th row. Multiple rows of light-emitting devices can be repeatedly arranged according to the above pattern.

[0206] In an exemplary embodiment, as shown in FIG9, within the same display area, the light-emitting area of ​​the first light-emitting device is larger than that of the second light-emitting device and smaller than that of the third light-emitting device. For example, in the first display area A1, the light-emitting area of ​​the first light-emitting device A11 is larger than that of the second light-emitting device A12 and smaller than that of the third light-emitting device A13; in the second display area A2, the light-emitting area of ​​the first light-emitting device A21 is larger than that of the second light-emitting device A22 and smaller than that of the third light-emitting device A23.

[0207] In an exemplary embodiment, as shown in FIG9, the light-emitting area of ​​the first light-emitting device A11 located in the first display area A1 is smaller than the light-emitting area of ​​the first light-emitting device A21 located in the second display area A2, the light-emitting area of ​​the second light-emitting device A12 located in the first display area A1 is smaller than the light-emitting area of ​​the second light-emitting device A22 located in the second display area A2, and the light-emitting area of ​​the third light-emitting device A13 located in the first display area A1 is smaller than the light-emitting area of ​​the third light-emitting device A23 located in the second display area A2.

[0208] In an exemplary embodiment, as shown in FIG9, at least two second light-emitting devices located in the first display area A1 are connected to the same pixel driving circuit located in the second display area A2. Connecting at least two second light-emitting devices located in the first display area A1 to the same pixel driving circuit located in the second display area A2 can reduce the number of signal lines in the display area, thereby improving the light transmittance of the first display area.

[0209] In an exemplary embodiment, FIG10 is a schematic diagram of the connection between the pixel driving circuit of the second display area and the light-emitting device of the first display area. As shown in FIG10, the display substrate further includes: a plurality of anode connection lines EL. At least one anode connection line EL is electrically connected to at least one light-emitting device located in the first display area A1 and at least one pixel driving circuit located in the second display area A2, respectively;

[0210] In an exemplary embodiment, the anode connection line EL is a transparent conductive line.

[0211] In an exemplary embodiment, the pixel driving circuit may include a first type of pixel driving circuit and a second type of pixel driving circuit. The first type of pixel driving circuit is electrically connected to a light-emitting device located in the first display area, and the second type of pixel driving circuit is electrically connected to a light-emitting device located in the second display area.

[0212] In an exemplary embodiment, the orthographic projection of at least one second-type pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the anode of at least one light-emitting device located in the second display area on the substrate.

[0213] In an exemplary embodiment, there is no overlap between the orthographic projection of at least one first-type pixel driving circuit on the substrate and the orthographic projection of the anode of at least one light-emitting device located in the first display area on the substrate.

[0214] In an exemplary embodiment, at least one first-type pixel driving circuit and a plurality of second-type pixel driving circuits may be arranged alternately. Figure 10 illustrates an example of an alternating arrangement of a first-type pixel driving circuit HP and four second-type pixel driving circuits P.

[0215] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0216] In an exemplary embodiment, as shown in FIG5, at least one data signal line Data has its orthographic projection on the substrate located in the second display area A2, and at least one data signal line Data is at least partially surrounding the periphery of the first display area A1.

[0217] In an exemplary embodiment, the second display area A2 further includes: a plurality of second power lines and a plurality of power adapter lines disposed on the substrate; at least one light-emitting device is electrically connected to at least one of the second power lines, and the at least one second power line extends at least partially along the first direction D1. The power adapter lines in this disclosure can improve the problem of image retention when the screen is off.

[0218] In an exemplary embodiment, the display substrate may include: a via exposing the cathode of at least one light-emitting device, and at least one second power line electrically connected to the cathode of at least one light-emitting device through the via exposing the cathode of at least one light-emitting device.

[0219] In an exemplary embodiment, the display substrate may further include: a second power bus located in a non-display area, and at least one second power line electrically connected to the second power bus.

[0220] In an exemplary embodiment, the power adapter cable may be configured in the same way as the data adapter cable, and this disclosure does not limit this in any way.

[0221] In an exemplary embodiment, the second power line may be arranged on the same layer as the data signal line, and at least one power adapter cable may be electrically connected to at least one second power line.

[0222] Figure 11 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. As shown in Figure 11, the display device provided in an embodiment of this disclosure may include: a display substrate 1 and a photosensor 2 provided in any of the foregoing embodiments. The photosensor 2 is located in the first display area A1 of the display substrate 1, and is located on the side away from the light-emitting side of the display substrate 1.

[0223] In an exemplary embodiment, the display substrate may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.

[0224] In an exemplary embodiment, when the light-transmitting display area A1 is rectangular, the orthographic projection area of ​​the photosensitive sensor 2 on the substrate is less than or equal to the area of ​​the inscribed circle of the light-transmitting display area A1.

[0225] In an exemplary embodiment, the photosensitive sensor 2 may include at least one of a camera module (e.g., a front-facing camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), and an infrared sensing module (e.g., an infrared sensing sensor).

[0226] In an exemplary embodiment, the front-facing camera module is typically activated when the user takes a selfie or makes a video call, and the display area of ​​the display device displays the image obtained from the selfie for the user to view. The front-facing camera module includes, for example, a lens, an image sensor, and an image processing chip. An optical image of the scene generated by the lens is projected onto the surface of the image sensor (image sensors include CCD and CMOS), converted into an electrical signal, and then converted into a digital image signal by the image processing chip. This digital signal is then processed by the processor and output as an image of the scene on the display screen.

[0227] In an exemplary embodiment, a 3D structured light sensor and a Time of Flight (ToF) sensor can be used for facial recognition to unlock a display device.

[0228] The display device provided in this disclosure embodiment can display images in the light-transmitting display area to maintain the display integrity of the entire display device.

[0229] Furthermore, the display device can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it is text or a picture. More specifically, it is contemplated that embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, etc., and this application does not limit the embodiments in any way.

[0230] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0231] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0232] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

A display substrate, comprising: The substrate and an array of pixel driving circuits, multiple data signal lines and multiple data transfer lines arranged on the substrate, wherein at least one pixel driving circuit is electrically connected to at least one data signal line, and the at least one data signal line extends at least partially along a first direction; At least one data adapter cable is electrically connected to at least one data signal line; The at least one data adapter cable includes: a first adapter cable extending at least partially along the first direction; the pixel driving circuit includes: at least one transistor, the at least one transistor including: an active pattern. The distance between the orthographic projection of at least a portion of the first adapter wire of the at least one data adapter wire on the substrate and the orthographic projection of at least a portion of the active pattern of the at least one transistor extending along the first direction on the substrate is less than a first threshold distance, or the distance between the film layer where the first adapter wire of the at least one data adapter wire is located and the film layer where the active pattern of the at least one transistor is located is greater than a second threshold distance. The display substrate according to claim 1, wherein The at least one data adapter cable further includes: a second adapter cable extending at least partially along a second direction, wherein the first direction intersects the second direction; The first adapter cable and the second adapter cable located in the same data adapter cable are electrically connected, and the orthographic projection of the second adapter cable of the at least one data adapter cable on the substrate at least partially overlaps with the orthographic projection of the at least one data signal line on the substrate. The display substrate according to claim 1, wherein The at least one transistor further includes: a first electrode and a second electrode; The first threshold distance is less than 1 micrometer; The second threshold distance is the distance between the film layer containing the active pattern of the at least one transistor and the film layer containing the first electrode and the second electrode of the at least one transistor. The display substrate according to claim 2, wherein When the distance between at least a portion of the first adapter wire of the at least one data adapter wire and at least a portion of the active pattern of the at least one transistor extending along the first direction on the substrate is less than a first threshold, the first adapter wire and the second adapter wire of the at least one data adapter wire are disposed on the same layer. The display substrate according to claim 4, further comprising: A circuit structure layer disposed on the substrate includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; The first and second adapter wires of at least one data adapter wire, as well as the first and second terminals of the at least one transistor, are located on the third conductive layer, and the data signal line is located on the fifth conductive layer. The display substrate according to claim 4, wherein The at least one pixel driving circuit includes: a second transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein the third transistor is a driving transistor, the second terminal of the second transistor and the first terminal of the sixth transistor are electrically connected to the second terminal of the third transistor, the first terminal of the second transistor is electrically connected to the control terminal of the third transistor, the first terminal of the fourth transistor is electrically connected to the data signal line, and the second terminal of the fourth transistor is electrically connected to the first terminal of the third transistor. The active pattern of the at least one transistor includes: a channel region and a first region and a second region located on both sides of the channel region, the first electrode of the at least one transistor is electrically connected to the first region of the active pattern of the at least one transistor, and the second electrode of the at least one transistor is electrically connected to the second region of the active pattern of the at least one transistor. In at least one pixel driving circuit, the second region of the active pattern of the second transistor, the second region of the active pattern of the third transistor, and the first region of the active pattern of the sixth transistor are integral structures. At least one of the patterns in the second region of the active pattern of the second transistor and the active pattern of the sixth transistor extends at least partially along the first direction, and the second region of the active pattern of the second transistor and the active pattern of the sixth transistor are arranged along the second direction. The first adapter cable of the at least one data adapter cable is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit, and they are an integral structure. The distance between the orthographic projection of at least a portion of the first adapter cable of the at least one data adapter cable on the substrate and the orthographic projection of at least a portion of the second region of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction on the substrate is less than the first threshold distance. The row containing the first pixel driving circuit is the same row as the row containing the second pixel driving circuit, and the column containing the second pixel driving circuit is the next column after the column containing the first pixel driving circuit. The display substrate according to claim 6, wherein The first adapter cable of the at least one data adapter cable is in the shape of a broken line and includes: a first adapter section, a second adapter section and a third adapter section; The first adapter portion extends at least partially along the first direction and is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit. The second adapter portion is electrically connected to both the first adapter portion and the third adapter portion. The third adapter portion extends at least partially along the first direction and is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit. The second adapter cable is electrically connected. The display substrate according to claim 7, wherein, The orthographic projection of the third adapter portion of the first adapter of the at least one data adapter on the substrate at least partially overlaps with the orthographic projection of at least a portion of the active pattern of the sixth transistor in the second pixel driving circuit extending along the first direction on the substrate. The display substrate according to claim 7, wherein At least a portion of the first adapter portion of the first adapter of the at least one data adapter cable has its orthographic projection on the substrate located on the side of the second region of the active pattern of the second transistor in the second pixel driving circuit and the orthographic projection of at least one active pattern of the sixth transistor on the substrate away from the first pixel driving circuit. The display substrate according to claim 7, wherein At least a portion of the first adapter portion of the first adapter cable of the at least one data adapter cable is projected onto the substrate between the orthographic projection of the active pattern of the fourth transistor in the first pixel driving circuit onto the substrate and the orthographic projection of the active pattern of the second transistor in the second pixel driving circuit onto the substrate. The active pattern of the fourth transistor in at least one pixel driving circuit extends at least partially along the first direction, and the distance between the orthographic projection of at least a portion of the first adapter portion of the first adapter of the at least one data adapter on the substrate and the orthographic projection of the active pattern of the fourth transistor in the first pixel driving circuit on the substrate is less than a first threshold distance. The display substrate according to claim 7, further comprising: Multiple scan signal lines and multiple light emission signal lines are disposed on the substrate, wherein the scan signal lines and the light emission signal lines extend at least partially along the second direction; The control electrode of the second transistor and the control electrode of the fourth transistor in the at least one pixel driving circuit are respectively electrically connected to at least one scan signal line, and the sixth transistor in the at least one pixel driving circuit is electrically connected to at least one light emission signal line. The orthographic projection of the first adapter portion of the first adapter of the at least one data adapter on the substrate at least partially overlaps the orthographic projection of the scan signal line connected to at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate. The orthographic projection of the second adapter portion of the first adapter of the at least one data adapter on the substrate is located between the orthographic projection of the scan signal line connected to the first pixel driving circuit on the substrate and the orthographic projection of the light emission signal line connected to the first pixel driving circuit on the substrate. The orthographic projection of the third adapter portion of the first adapter of the at least one data adapter on the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line connected to the first pixel driving circuit on the substrate. The display substrate according to claim 2, wherein When the distance between the film layer containing the first adapter of the at least one data adapter and the film layer containing the active pattern of the at least one transistor is greater than the second threshold distance, the first adapter of the at least one data adapter is located on the side of the second adapter away from the substrate. The display substrate according to claim 12, further comprising: A circuit structure layer disposed on the substrate includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; The second adapter wire in the at least one data adapter wire and the first and second terminals of the at least one transistor are located in the third conductive layer, the first adapter wire in the at least one data adapter wire is located in the fourth conductive layer, and the data signal line is located in the fifth conductive layer. The display substrate according to claim 6, wherein The at least one pixel driving circuit includes: a second transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein the third transistor is a driving transistor, the second terminal of the second transistor and the first terminal of the sixth transistor are electrically connected to the second terminal of the third transistor, the first terminal of the second transistor is electrically connected to the control terminal of the third transistor, the first terminal of the fourth transistor is electrically connected to the data signal line, and the second terminal of the fourth transistor is electrically connected to the first terminal of the third transistor. The first adapter cable of the at least one data adapter cable is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit. The orthographic projection of at least a portion of the first adapter cable of the at least one data adapter cable onto the substrate at least partially overlaps with the orthographic projection of at least a portion of the second region of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction and the orthographic projection of at least a portion of the active pattern of the sixth transistor extending along the first direction onto the substrate. The row containing the first pixel driving circuit is the same row as the row containing the second pixel driving circuit, and the column containing the second pixel driving circuit is the next column after the column containing the first pixel driving circuit. The display substrate according to claim 14, further comprising: Multiple scan signal lines and multiple light emission signal lines are disposed on the substrate. The control electrode of the second transistor and the control electrode of the fourth transistor in the at least one pixel driving circuit are electrically connected to at least one scan signal line, and the sixth transistor in the at least one pixel driving circuit is electrically connected to at least one light emission signal line. The first adapter cable of the at least one data adapter cable is a straight type; The orthographic projection of the first adapter line of the at least one data adapter line on the substrate at least partially overlaps the orthographic projections of the scan signal line and the light emission signal line connected to at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate. The display substrate according to claim 6, further comprising: Multiple first reset signal lines are disposed on the substrate; The at least one pixel driving circuit includes: a first transistor and a seventh transistor, wherein the control electrode of the first transistor is electrically connected to at least one first reset signal line, and the second electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor and the light-emitting device connected to the pixel driving circuit. The orthographic projection of the second adapter line of the at least one data adapter line on the substrate lies between the orthographic projection of the light-emitting signal line connected to the first pixel driving circuit on the substrate and the orthographic projection of the first reset signal line connected to the next row of pixel driving circuits of the first pixel driving circuit on the substrate. The display substrate according to claim 1, further comprising: Multiple first power lines are disposed on the substrate, and the first power lines are located on the side of the data signal lines closer to the substrate; At least one pixel driving circuit includes: a capacitor, the capacitor including: a first plate and a second plate, the second plate of the capacitor having an opening, the orthographic projection of the opening on the substrate being within the range of the orthographic projection of the first plate of the capacitor on the substrate; The orthographic projection of the at least one first power line on the substrate covers the orthographic projection of the opening of the second plate of the capacitor in the pixel driving circuit to which the first power line is connected on the substrate. The display substrate according to claim 1, wherein include: The display area includes: a first display area and a second display area located at least one side of the first display area. The first display area and the second display area include: an array of light-emitting devices disposed on the substrate, and an array of pixel driving circuits and multiple data signal lines disposed in the second display area. At least one light-emitting device located in the first display area is electrically connected to at least one pixel driving circuit located in the second display area; The light-emitting device located in at least one of the first display area and the second display area includes: a first light-emitting device, a second light-emitting device, and a third light-emitting device; In the same display area, the light-emitting area of ​​the first light-emitting device is larger than that of the second light-emitting device, but smaller than that of the third light-emitting device; The light-emitting area of ​​the first light-emitting device located in the first display area is smaller than the light-emitting area of ​​the first light-emitting device located in the second display area; the light-emitting area of ​​the second light-emitting device located in the first display area is smaller than the light-emitting area of ​​the second light-emitting device located in the second display area; and the light-emitting area of ​​the third light-emitting device located in the first display area is smaller than the light-emitting area of ​​the third light-emitting device located in the second display area. At least two second light-emitting devices located in the first display area are connected to the same pixel driving circuit located in the second display area. The display substrate according to claim 18, further comprising: Multiple anode connection wires; At least one anode connection line is electrically connected to at least one light-emitting device located in the first display area and at least one pixel driving circuit located in the second display area, respectively; The anode connection wire is a transparent conductive wire. The display substrate according to claim 18, wherein, The orthographic projection of the at least one data signal line on the substrate is located in the second display area, and the at least one data signal line is at least partially surrounding the periphery of the first display area. The display substrate according to claim 1, further comprising: Multiple second power lines and multiple power adapter cables are disposed on the substrate; At least one light-emitting device is electrically connected to at least one second power line, and the at least one second power line extends at least partially along the first direction; The second power line is arranged on the same layer as the data signal line, and at least one power adapter cable is electrically connected to the at least one second power line. A display device comprising: The display substrate and photosensor as described in any one of claims 1 to 21; The photosensitive sensor is located within the first display area of ​​the display substrate, and is located on the side away from the light-emitting side of the display substrate.

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