A memory chip, logic chip, chip stack structure and memory

Abstract

This disclosure belongs to the field of semiconductor technology and addresses the problem of complex signal interconnections between memory chips and logic chips in three-dimensional chip stacking structures. It provides a memory chip, a logic chip, a chip stacking structure, and a memory. The memory chip includes 2A channel signal regions arranged sequentially along a first direction. Each channel signal region includes a first data signal region and a second data signal region arranged along the first direction. The first data signal region in the i-th channel signal region is symmetrical to the first data signal region in the (2A-i+1)-th channel signal region about a second axis, and the second data signal region in the i-th channel signal region is symmetrical to the second data signal region in the (2A-i+1)-th channel signal region about the second axis. Thus, after forming a three-dimensional chip stacking structure, the positions of the first and second data signal regions of the memory chip and the logic chip are aligned along a third direction, reducing the complexity of signal routing.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to a memory chip, a logic chip, a chip stack structure, and a memory. Background Technology

[0002] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limitations of existing development techniques, and limits of stored electron density. Against this backdrop, to address the difficulties encountered in two-dimensional semiconductor devices and to pursue lower production costs per unit memory cell, bonding processes (such as hybrid bonding, bumping, and wire bonding) can be used to stack multiple chips to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still suffers from problems such as large parasitic capacitance and resistance, affecting signal transmission quality. Summary of the Invention

[0003] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a memory chip, wherein the active surface of the memory chip has a first axis and a second axis, the first axis and the second axis intersecting perpendicularly at the midpoint of the active surface; the memory chip includes 2A channels arranged sequentially along a first direction, each channel including one channel signal area, the 2A channel signal areas being arranged sequentially along the first direction; the first axis extends along the first direction;

[0006] Each of the aforementioned channel signal regions includes 2n conductive path groups, and the 2n conductive path groups in each of the aforementioned channel signal regions are symmetrical about the first axis; all conductive path groups in the 2A channel signal regions of the memory chip are symmetrical about the second axis as a whole;

[0007] Each of the channels includes a first pseudo channel and a second pseudo channel, and each channel signal area includes a first data signal area and a second data signal area arranged along a first direction. The conductive path group in the first data signal area is used to transmit the data signal of the corresponding first pseudo channel, and the conductive path group in the second data signal area is used to transmit the data signal of the corresponding second pseudo channel.

[0008] The first data signal area in the i-th channel signal area is symmetrical to the first data signal area in the (2A-i+1)-th channel signal area about the second axis, and the second data signal area in the i-th channel signal area is symmetrical to the second data signal area in the (2A-i+1)-th channel signal area about the second axis, where A≥i≥1, and i, n, and A are all positive integers.

[0009] In some embodiments, each of the channel signal regions further includes a control signal region; in the same channel signal region: along the first direction, the control signal region is disposed between the first data signal region and the second data signal region; wherein, the conductive path group in the control signal region is used to transmit the control signals of the corresponding first pseudo-channel and the corresponding second pseudo-channel.

[0010] In some embodiments, each of the channel signal regions further includes a fifth axis, which intersects the first axis perpendicularly at the center of the channel signal region; the 2n conductive path groups in the same channel signal region are symmetrical about the fifth axis and about the first axis.

[0011] In some embodiments, each of the conductive path groups has a third axis and a fourth axis, the third axis and the fourth axis being perpendicular to each other and intersecting at the center of the conductive path group, the third axis being parallel to the first axis; each conductive path group includes four conductive paths arranged in a 2×2 array, the four conductive paths being symmetrical about the third axis and about the fourth axis; the conductive paths penetrate the substrate of the memory chip along a third direction, the third direction being perpendicular to the active surface.

[0012] In some embodiments, each of the conductive path groups includes a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path; in each conductive path group, the first conductive path and the second conductive path are symmetrical about the third axis, the third conductive path and the fourth conductive path are symmetrical about the third axis, and the first conductive path and the fourth conductive path are symmetrical about the fourth axis.

[0013] In some embodiments, the active surface is divided into a first region, a second region, a third region, and a fourth region by the first axis and the second axis;

[0014] (1) The first conductive path located in the first region is symmetrical to the second conductive path located in the second region about the first axis, and the first conductive path located in the first region is also symmetrical to the fourth conductive path located in the fourth region about the second axis; the third conductive path located in the third region is symmetrical to the fourth conductive path located in the fourth region about the first axis, and the third conductive path located in the third region is also symmetrical to the second conductive path located in the second region about the second axis;

[0015] (2) The second conductive path located in the first region is symmetrical to the first conductive path located in the second region about the first axis, and the second conductive path located in the first region is also symmetrical to the third conductive path located in the fourth region about the second axis; the fourth conductive path located in the third region is symmetrical to the third conductive path located in the fourth region about the first axis, and the fourth conductive path located in the third region is also symmetrical to the first conductive path located in the second region about the second axis;

[0016] (3) The third conductive path located in the first region is symmetrical to the fourth conductive path located in the second region about the first axis, and the third conductive path located in the first region is also symmetrical to the second conductive path located in the fourth region about the second axis; the first conductive path located in the third region is symmetrical to the second conductive path located in the fourth region about the first axis, and the first conductive path located in the third region is also symmetrical to the fourth conductive path located in the fourth region about the second axis;

[0017] (4) The fourth conductive path located in the first region is symmetrical to the third conductive path located in the second region about the first axis, and the fourth conductive path located in the first region is also symmetrical to the first conductive path located in the fourth region about the second axis; the second conductive path located in the third region is symmetrical to the first conductive path located in the fourth region about the first axis, and the second conductive path located in the third region is also symmetrical to the third conductive path located in the second region about the second axis.

[0018] In some embodiments, each channel further includes 2n first transceivers; each first transceiver is coupled to a first conductive path within the corresponding channel; the first transceiver is configured to receive signals transmitted through the corresponding coupled first conductive path; or to generate signals transmitted outward via the corresponding coupled first conductive path.

[0019] In some embodiments, each of the conductive path groups is used to transmit two different types of signals; for the same channel signal region, two conductive paths symmetrical about the first axis are used to transmit the same type of signal; for different channel signal regions, two conductive paths symmetrical about the second axis are used to transmit the same type of signal.

[0020] In some embodiments, the conductive path includes a conductive via, which is fabricated by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last; different conductive paths in the same memory chip are electrically isolated.

[0021] Secondly, embodiments of this disclosure provide a logic chip, wherein the active surface of the logic chip has a first axis and a second axis, the first axis and the second axis intersecting perpendicularly at the midpoint of the active surface; the logic chip includes 2A channel signal regions, the 2A channel signal regions being arranged along a first direction; the first axis extends along the first direction;

[0022] Each of the aforementioned channel signal regions includes 2n conductive path groups, and the 2n conductive path groups in each of the aforementioned channel signal regions are symmetrical about the first axis; all conductive path groups in the 2A channel signal regions of the logic chip are symmetrical about the second axis as a whole;

[0023] The 2A channel signal areas of the logic chip correspond one-to-one with the 2A channels of the memory chip. Each channel signal area is divided into a first data signal area and a second data signal area arranged along a first direction. The conductive path group in the first data signal area is used to transmit the data signal of the first pseudo channel in the corresponding channel, and the conductive path group in the second data signal area is used to transmit the data signal of the second pseudo channel in the corresponding channel.

[0024] The first data signal area in the i-th channel signal area is symmetrical to the first data signal area in the (2A-i+1)-th channel signal area about the second axis, and the second data signal area in the i-th channel signal area is symmetrical to the second data signal area in the (2A-i+1)-th channel signal area about the second axis, where A≥i≥1, and i, n, and A are all positive integers.

[0025] In some embodiments, each of the channel signal regions further includes a control signal region; for the same channel signal region, along the first direction, the control signal region is disposed between the first data signal region and the second data signal region; wherein, the conductive path group in the control signal region is used to transmit the control signals of the corresponding first pseudo-channel and the corresponding second pseudo-channel.

[0026] In some embodiments, each of the channel signal regions further includes a fifth axis, which intersects the first axis perpendicularly at the center of the channel signal region; the 2n conductive path groups in the same channel signal region are symmetrical about the fifth axis and about the first axis.

[0027] In some embodiments, each of the conductive path groups has a third axis and a fourth axis, the third axis and the fourth axis being perpendicular to each other and intersecting at the center of the conductive path group, the third axis being parallel to the first axis; each of the conductive path groups includes four conductive paths arranged in a 2×2 array, the four conductive paths being symmetrical about the third axis and about the fourth axis; the conductive paths extend along a third direction, the third direction being perpendicular to the active surface.

[0028] In some embodiments, each of the conductive path groups includes a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path; in each conductive path group, the first conductive path and the second conductive path are symmetrical about the third axis, the third conductive path and the fourth conductive path are symmetrical about the third axis, and the first conductive path and the fourth conductive path are symmetrical about the fourth axis.

[0029] In some embodiments, the active surface is divided into a first region, a second region, a third region, and a fourth region by the first axis and the second axis;

[0030] (1) The first conductive path located in the first region is symmetrical to the second conductive path located in the second region about the first axis, and the first conductive path located in the first region is also symmetrical to the fourth conductive path located in the fourth region about the second axis; the third conductive path located in the third region is symmetrical to the fourth conductive path located in the fourth region about the first axis, and the third conductive path located in the third region is also symmetrical to the second conductive path located in the second region about the second axis;

[0031] (2) The second conductive path located in the first region is symmetrical to the first conductive path located in the second region about the first axis, and the second conductive path located in the first region is also symmetrical to the third conductive path located in the fourth region about the second axis; the fourth conductive path located in the third region is symmetrical to the third conductive path located in the fourth region about the first axis, and the fourth conductive path located in the third region is also symmetrical to the first conductive path located in the second region about the second axis;

[0032] (3) The third conductive path located in the first region is symmetrical to the fourth conductive path located in the second region about the first axis, and the third conductive path located in the first region is also symmetrical to the second conductive path located in the fourth region about the second axis; the first conductive path located in the third region is symmetrical to the second conductive path located in the fourth region about the first axis, and the first conductive path located in the third region is also symmetrical to the fourth conductive path located in the fourth region about the second axis;

[0033] (4) The fourth conductive path located in the first region is symmetrical to the third conductive path located in the second region about the first axis, and the fourth conductive path located in the first region is also symmetrical to the first conductive path located in the fourth region about the second axis; the second conductive path located in the third region is symmetrical to the first conductive path located in the fourth region about the first axis, and the second conductive path located in the third region is also symmetrical to the third conductive path located in the second region about the second axis.

[0034] In some embodiments, each channel further includes (2n×4) second transceivers; each second transceiver is coupled one-to-one with a conductive path in the corresponding channel; the second transceiver is used to receive signals transmitted by the corresponding conductive path; or to generate signals transmitted outward via the corresponding conductive path.

[0035] In some embodiments, each of the conductive path groups is used to transmit two different types of signals; for the same channel signal region, two conductive paths symmetrical about the first axis are used to transmit the same type of signal; for different channel signal regions, two conductive paths symmetrical about the second axis are used to transmit the same type of signal.

[0036] In some embodiments, the conductive path includes a through-silicon via (TSV), which is fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last; different conductive paths in the same memory chip are electrically isolated.

[0037] Thirdly, embodiments of this disclosure provide a chip stacking structure, the chip stacking structure including a logic chip as described in the first aspect and at least one stacking unit, the logic chip and at least one stacking unit being stacked sequentially along a third direction, each stacking unit including a first memory chip, a second memory chip, a third memory chip and a fourth memory chip being stacked sequentially along a third direction, the third direction being perpendicular to the active surface of each memory chip, the first memory chip, the second memory chip, the third memory chip and the fourth memory chip being memory chips as described in the second aspect;

[0038] The logic chip and the first memory chip are stacked in a face-to-back or back-to-back manner; the first memory chip and the second memory chip are stacked face-to-face; the second memory chip and the third memory chip are stacked back-to-back; the third memory chip and the fourth memory chip are stacked face-to-face; the 2A first data signal areas of the logic chip and the 2A first data signal areas of each memory chip are projected in a corresponding third direction and overlap one-to-one; the 2A second data signal areas of the logic chip and the 2A second data signal areas of each memory chip are projected in a corresponding third direction and overlap one-to-one.

[0039] In some embodiments, the i-th channel signal region in the first memory chip, the (2A-i+1)-th channel signal region in the second memory chip, the (2A+1-i)-th channel signal region in the third memory chip, and the i-th channel signal region in the fourth memory chip are aligned along a third direction.

[0040] In some embodiments, the i-th channel signal region in the first memory chip, the i-th channel signal region in the second memory chip, the (2A+1-i)-th channel signal region in the third memory chip, and the (2A-i+1)-th channel signal region in the fourth memory chip are aligned along a third direction.

[0041] In some embodiments, when the logic chip and the first memory chip are stacked back-to-back, the i-th channel signal region in the logic chip is aligned with the i-th channel signal region in the first memory chip along a third direction; or, the i-th channel signal region in the logic chip is aligned with the (2A-i+1)-th channel signal region in the first memory chip along a third direction.

[0042] In some embodiments, when the logic chip and the first memory chip are stacked face-to-back, the i-th channel signal region in the logic chip is aligned with the (2A-i+1)-th channel signal region in the first memory chip along a third direction; or, the i-th channel signal region in the logic chip is aligned with the i-th channel signal region in the first memory chip along a third direction.

[0043] In some embodiments, for two chips connected face-to-face, the positions where the conductive paths are aligned along a third direction are electrically connected using a hybrid bonding process; for two chips connected back-to-back or face-to-back, the positions where the conductive paths are aligned along a third direction are electrically connected using a conductive bump bonding process; or, for two chips connected face-to-face, back-to-back, or face-to-back, the vias where the conductive paths are aligned along a third direction are electrically connected using a hybrid bonding process; or, for two chips connected face-to-face, back-to-back, or face-to-back, the vias where the conductive paths are aligned along a third direction are electrically connected using a conductive bump bonding process.

[0044] Fourthly, embodiments of this disclosure provide a memory comprising a chip stacking structure as described in the third aspect.

[0045] This disclosure provides a memory chip, a logic chip, a chip stack structure, and a memory. For the memory chip and the logic chip, since the conductive path groups symmetrical along the second axis transmit signals from the same pseudo-channel, they can be perfectly matched after stacking. At the same time, for the logic chip, the distance between the channel signal area and the corresponding signal processing area is also closer, eliminating the need for cross-wiring and reducing the possibility of design errors. Moreover, since the channel signal areas on both sides of the second axis are symmetrical, both the design layout of the conductive path and the layout of the wiring can be reused. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a conductive via;

[0047] Figure 2 These are schematic diagrams illustrating signal transmission in two different chip stacking structures.

[0048] Figure 3 This is a schematic diagram of the active surface of a memory chip provided in an embodiment of this disclosure;

[0049] Figure 4 This is a schematic diagram of the specific structure of the channel signal region in the memory chip provided in this embodiment of the disclosure;

[0050] Figure 5 This is a schematic diagram showing the specific location of the conductive path of the memory chip provided in the embodiments of this disclosure;

[0051] Figure 6 This is a schematic diagram of the first type of channel signal area provided in the embodiments of this disclosure;

[0052] Figure 7 This is a schematic diagram of the second type of channel signal region provided in the embodiments of this disclosure;

[0053] Figure 8 This is a schematic diagram of the third type of channel signal area provided in the embodiments of this disclosure;

[0054] Figure 9 This is a schematic diagram of a memory chip using the WOW architecture provided in an embodiment of this disclosure. Figure 1 ;

[0055] Figure 10 This is a schematic diagram of a memory chip using the WOW architecture provided in an embodiment of this disclosure. Figure 2 ;

[0056] Figure 11 This is a schematic diagram of the specific structure of the active surface of the logic chip provided in the embodiments of this disclosure;

[0057] Figure 12 This is a schematic diagram of the specific structure of the channel signal region of the logic chip provided in this embodiment of the disclosure;

[0058] Figure 13 This is a schematic diagram showing the specific locations of the conductive paths in the logic chip provided in this embodiment of the disclosure;

[0059] Figure 14 This is a schematic diagram of the first chip stacking structure provided in the embodiments of this disclosure;

[0060] Figure 15 This is a schematic diagram of a specific channel of the first chip stacking structure provided in this embodiment of the present disclosure;

[0061] Figure 16 This is a schematic diagram of the conductive path of the first chip stacking structure provided in the embodiments of this disclosure;

[0062] Figure 17 This is a schematic diagram of the second chip stacking structure provided in the embodiments of this disclosure;

[0063] Figure 18 This is a schematic diagram of a specific channel of the second chip stacking structure provided in this embodiment of the present disclosure;

[0064] Figure 19 This is a wiring diagram of a logic chip provided in an embodiment of this disclosure;

[0065] Figure 20 This is a schematic diagram of the signal distribution of different memory chips provided in the embodiments of this disclosure;

[0066] Figure 21 This is a schematic diagram of the signal distribution of the logic chip provided in an embodiment of this disclosure;

[0067] Figure 22 This is a schematic diagram showing the connection of some signals of the logic chip provided in this embodiment. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0069] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0071] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0072] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0073] First, the nouns and terms used in the embodiments of this disclosure will be explained:

[0074] Dynamic Random Access Memory (DRAM);

[0075] Synchronous Dynamic Random Access Memory (SDRAM);

[0076] Double Data Rate SDRAM (DDR);

[0077] Low-power DDR (LPDDR);

[0078] Pseudo Channel (PC).

[0079] Before introducing the embodiments of this disclosure, we first define three directions that may be used in the plane to describe the three-dimensional structure in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include the first direction X, the second direction Y, and the third direction Z.

[0080] Please see Figure 1 A semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side (opposite to the front side). Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction Z. On the top surface of the semiconductor chip, two mutually perpendicular directions are defined: a first direction X and a second direction Y. The first direction X is perpendicular to one edge of the semiconductor chip, and the second direction Y is perpendicular to the other edge of the semiconductor chip. The third direction Z is perpendicular to both the first direction X and the second direction Y.

[0081] Please see Figure 1 A semiconductor chip includes a substrate. One side of the substrate used to fabricate devices (such as transistors and capacitors) forms the active surface (the side of the substrate opposite to the active surface is the non-active surface, i.e., ...). Figure 1 The bottom surface has multiple metal layers distributed between its substrate and top surface, such as M1, M2, M3, etc. Figure 1 The diagram also shows two types of conductive vias (e.g., through-silicon vias), both used to enable signal connections between different stacked chips.

[0082] like Figure 1As shown, for a type 1 conductive via, it penetrates the bottom surface and the top surface along the third direction Z. The conductive via is connected to the internal circuitry of the chip through a metal layer.

[0083] like Figure 1 As shown, for type 2 conductive vias, which penetrate the substrate only along the third direction Z (penetrating both the active surface and the bottom surface), a contact structure that penetrates the top surface along the third direction Z is required to achieve signal transmission. The contact structure and the conductive via are not directly electrically connected, but rather indirectly connected through a metal layer. For example: Figure 1 The contact structure in the middle is connected to M4, and M4 is connected to M1 via M3 and M2 in sequence. M1 is then connected to the conductive via; or... Figure 1 The conductive vias in the chip are connected to the internal circuitry via M1-M4. Figure 1 The input terminal of the device in the substrate, the output signal processed by the internal circuitry of the chip, is then output to the corresponding contact structure via metal layers M1-M4. Similarly, Figure 1 The contact structure in the chip can also be connected to the internal circuitry via M1-M4. Figure 1 The input terminal of the device in the substrate, after processing by the internal circuitry of the chip, outputs the signal to the corresponding conductive via via M1-M4. Of course, in other embodiments, the contact structure and conductive via can also be designed for direct electrical connection. Furthermore, the types of conductive vias are not limited to the two types mentioned above; the above are merely examples.

[0084] In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments. Therefore, the illustrations are not necessarily to scale.

[0085] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0086] In one embodiment, a memory chip and a logic chip are provided. Both the memory chip and the logic chip include multiple conductive paths extending Z-direction through the active surface of the chip. These conductive paths are used to enable signal transmission between different chips. Specifically, the conductive paths may include one or more of the following: such as... Figure 1 The diagram shows any type of conductive via, contact structure, and metal interconnect layer between the conductive via and the contact structure. Adjacent contact structures or adjacent conductive vias are interconnected using a bump process or a hybrid bonding (HB) process.

[0087] All conductive paths can be located at any position, and every four conductive paths can be considered as a group of conductive paths, but there are no restrictions on the position of each of the four conductive paths.

[0088] In one specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. Simultaneously, the conductive paths of each of the eight memory chips are aligned along the Z-direction, and these nine aligned conductive paths are connected to form a signal transmission channel. See also... Figure 2 (a) shows a schematic diagram of signal transmission in a chip stacking structure. Figure 2 As shown in (a), the chip stacking structure includes memory chips 0-7 and logic chips. Figure 2 In (a), only four conductive paths D0 to D3 are shown for each memory chip, and these four conductive paths D0 to D3 belong to the same conductive path group. At this time, the conductive paths D0 in the eight memory chips and one logic chip are aligned to form one electrical path, the conductive paths D1 in the eight memory chips and one logic chip are aligned to form one electrical path, and so on. The other conductive paths are similar.

[0089] In addition, each memory chip and logic chip is also equipped with multiple transceivers. Figure 2 In (a) of the diagram, only one transceiver is shown in a dashed box; the others are not shown. Each conductive path is connected to one transceiver. Each memory chip also has multiple data selectors (e.g., Figure 2 In (a) of the diagram, mux0~7), each conductive path group corresponds to one data selector. That is, all conductive paths in a conductive path group are connected to the data port of the data selector through their respective transceivers. In this way, the data selector can choose which conductive path transmits the signal to be output to the inside of the memory chip or which conductive path outputs the signal from the memory chip.

[0090] For the overall storage device, different regions in different memory chips will be managed by different channels (e.g., CH0, CH1, CH4, CH5). The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "conductive path D0 in logic chip, conductive path D0 in memory chip 0, conductive path D0 in memory chip 1, conductive path D0 in memory chip 2, conductive path D0 in memory chip 3, conductive path D0 in memory chip 4, conductive path D0 in memory chip 5, conductive path D0 in memory chip 6, and conductive path D0 in memory chip 7". The selection signal of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 is SEL_C0. That is, the signal Signal_CH0 can enter memory chip 0 and memory chip 4 through the aforementioned electrical path; the signal output process can be understood similarly.

[0091] As can be seen from the above, memory chip 0 only needs to obtain signals from conductive path D0, memory chip 1 only needs to obtain signals from conductive path D1, and so on. That is, each memory chip only needs to obtain signals from one of the conductive paths in a group of conductive paths. It is worth noting that different memory chips may need to obtain signals from different conductive paths. However, since all memory chips need to be designed with the exact same structure during manufacturing (to maximize cost and labor savings), all conductive paths in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using... Figure 2 In the chip stacking structure shown in (a), each conductive path corresponds to a transceiver. During the operation of this chip stacking structure, it is necessary to drive all transceivers in all memory chips in the same channel. The load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts the transmission efficiency and increases power consumption. It also restricts the number of chips stacked in the three-dimensional device.

[0092] In another embodiment, please refer to Figure 2 (b) illustrates a signal transmission diagram of another chip stacking structure. Specifically, Figure 2 In section (b), only a portion of the electrical conductivity (D0~D3) is marked, while the rest is omitted. However, for... Figure 2 In (b) of this example, the identifiers for conductive paths aligned Z-axis along a third direction are the same. For example... Figure 2 As shown in (b), the chip stack structure also includes 8 memory chips and 1 logic chip aligned along the third direction Z. However, the conductive path in each memory chip is rotated to connect to another conductive path at a different position in another memory chip, achieving a spiral upward connection as a whole. That is, the signal Signal_CH0 of channel CH0 is transmitted through “conductive path D0 in logic chip —— conductive path D1 in memory chip 0 —— conductive path D2 in memory chip 1 —— conductive path D3 in memory chip 2 —— conductive path D0 in memory chip 3 —— conductive path D1 in memory chip 4 —— conductive path D2 in memory chip 5 —— conductive path D3 in memory chip 6 —— conductive path D0 in memory chip 7”, and the other signals are similar.

[0093] In this way, memory chip 0 can obtain the signal Signal_CH0 through the output terminal of conductive path D0 in the logic chip, memory chip 1 can obtain the signal Signal_CH1 through the input terminal of conductive path D0 in memory chip 0, memory chip 2 can obtain the signal Signal_CH4 through the input terminal of conductive path D0 in memory chip 1, memory chip 3 can obtain the signal Signal_CH5 through the input terminal of conductive path D0 in memory chip 2, and so on. For each memory chip, only one conductive path in each conductive path group needs to be connected to the transceiver, and no data selector is required, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to Figure 2 The conductive path in (a) is a direct connection configuration. Figure 2 The process of rotating the conductive path in (b) is more complex, specifically... Figure 2 In (b) of the diagram, a horizontal interconnect structure needs to be set between adjacent conductive paths in each memory chip. Figure 2 (In section (b), only one of them is marked with a pentagram). The signal interconnection structure can be a metal interconnect, a conductive path, etc. In order to achieve a rotating connection of the conductive path, the input signal signal_CH0 must first be transmitted upward from the conductive path D0 of the logic chip to the interconnection structure below the conductive path D0 of the memory chip 0 (not connected to the conductive path D0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive path D0 of the memory chip 0 to the conductive path D1 of the memory chip 0. That is: Figure 2 The structure shown in (b) requires the signal to pass through the interconnect structure in each memory chip during the signal process, and the output signal is similar. This inevitably leads to an increase in parasitic resistance and also increases the complexity of the process.

[0094] In particular, Figure 2 (a) and Figure 2 In the chip stacking structure in (b), all chips are sampled with the top surface facing upwards. That is to say, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the bottom surface of the upper chip is in contact with the top surface of the lower chip.

[0095] In summary, on the one hand, Figure 2 The chip stacking structure in (a) requires a large number of conductive vias to transmit the corresponding signals. Combined with the corresponding transceivers and data selectors, this results in a large load and parasitic capacitance. Figure 2 The chip stacking structure in (b) exhibits a large parasitic resistance due to its rotational configuration; on the other hand, Figure 2 (a) and Figure 2The stacking structure in (b) has certain problems and cannot be directly applied to face-to-face stacking structures. Specifically, if a face-to-face chip stacking structure is to be further realized, one approach is to use two sets of masks to manufacture two different chips, one as the active-facing chip and the other as the active-facing chip. This approach has high process complexity and uncontrollable cost. Another approach is to add an extra set of conductive vias and connect both sets of conductive vias to the same transceiver inside the memory chip. However, this will lead to complex internal wiring of the memory chip, which will not only increase process complexity but also increase power consumption.

[0096] In another embodiment of this disclosure, a memory chip 10 is provided, comprising 2A channels arranged along a first direction X, where A is a positive integer. See also Figure 3 The diagram illustrates a cross-sectional view of the active surface of a memory chip 10 provided in this embodiment, with A=2 as an example. Figure 3 As shown, the memory chip 10 includes four channels CHa, CHb, CHc and CHd arranged sequentially along the first direction X.

[0097] like Figure 3 As shown, the memory chip 10 also includes a global signal area located between the A-th channel CHb and the (A+1)-th channel CHc. This global signal area is used to transmit global signals, which are shared by all channels in the memory chip 10. In other words, all channels in the memory chip 10 may use the aforementioned global signals.

[0098] It should be understood that Figure 3 This is merely an example of one location for the global signal area and does not constitute a limitation. For example, the global signal area could also be located on either side of the channel along the second direction Y, on the side of channel Cha away from channel Chb, on the side of channel CHa closer to channel CHb, or in other internal areas. Furthermore, the size of the global signal area is determined by the number of global signals, and its sides can be used to distribute fuse modules, analog circuits such as voltage generation circuits, guard ring test circuits, etc.

[0099] like Figure 3 As shown, each channel includes one channel signal area 110. The 2A channel signal areas 110 are also arranged along the first direction X, and the projections of each channel signal area 110 along the first direction X overlap. The channel signal area 110 is used to transmit channel signals, which are used only by the channel to which it belongs. In other words, each channel operates in response to its own channel signal and the aforementioned global signal.

[0100] like Figure 3As shown, each channel also includes two device regions 120. For the same channel, the first device region 120, the channel signal region 110, and the second device region 120 are arranged sequentially along the second direction Y. Here, the device region 120 may include at least one or more of the following: a memory array, a sense amplifier SA, and other necessary control logic devices. The memory array includes multiple memory cells, multiple word lines, and multiple bit lines arranged in an array layout. The memory cells may adopt a 1T1C (1 Transistor 1 Capacitor) structure, a 2T1C structure, a 2T0C structure, etc. For a specific example, please refer to [link to example]. Figure 3 The first device area 120 and the second device area 120 in the same channel can be set with a symmetrical structure about the first axis AA', which can save design work.

[0101] In this way, the eight device areas 120 are symmetrical about the first axis AA', and the four channel signal areas 110 are also symmetrical about the first axis AA'. The wiring between the device areas 120 and the channel signal areas 110 is also relatively simple.

[0102] In another specific example, the memory arrays in the first device area 120 and the second device area in the same channel can also be designed with the exact same structure and layout (i.e., overlapping after translation), which also saves design effort.

[0103] In some embodiments, for design simplicity, the device areas 120 of different channels are symmetrical about the second axis BB'. In this way, both the device area 120 and the channel signal area 110 are symmetrical about the second axis BB', which facilitates wiring.

[0104] Please see Figure 4 It shows the specific structure of the channel signal area 110, and Figure 4 The global signal area and device area 120 have been omitted. For example... Figure 4 As shown, each channel signal region 110 includes 2n conductive path groups 20, where n is any positive integer and can be selected according to the actual application scenario. It should be understood that... Figure 4 Each channel signal area 110 illustrates 6 conductive path groups 20, but the actual number of conductive path groups 20 is much larger, depending on the number of signals to be transmitted; Figure 4 The first data signal area PC0_Dword and the second data signal area PC1_Dword each show two conductive path groups 20, which are also just examples and not the actual number.

[0105] For ease of explanation, a first axis AA' and a second axis BB' are introduced. The first axis AA' and the second axis BB' intersect perpendicularly at the midpoint O of the active surface of the memory chip 10. The first axis AA' is parallel to the first side of the active surface, and the second axis BB' is parallel to the second side of the active surface. Alternatively, the first axis AA' extends along the first direction X, and the second axis BB' extends along the second direction Y.

[0106] Please see Figure 4 Within the same channel signal region 110, 2n conductive path groups 20 are symmetrical about the first axis AA'; and all conductive path groups 20 in the 2A channel signals 110 of the memory chip 10 are symmetrical about the second axis BB'. Figure 4 As shown, the 2n conductive path groups 20 in the channel signal region 110 of channel CHa are symmetrical about the second axis BB' with the 2n conductive path groups 20 in the channel signal region 110 of channel CHd; the 2n conductive path groups 20 in the channel signal region 110 of channel CHb are symmetrical about the second axis BB' with the 2n conductive path groups 20 in the channel signal region 110 of channel CHd.

[0107] Thus, all conductive path groups 20 in the 2A channel signals 110 of the memory chip 10 are symmetrical about the first axis AA' and about the second axis BB'. It can also be said that the conductive path groups 20 in the memory chip 10 as a whole have the characteristics of four-quadrant symmetry.

[0108] In this embodiment of the present disclosure, each conductive path in the conductive path group 20 penetrates the substrate of the memory chip 10 along the third direction Z.

[0109] Please refer to Figure 4 Each conductive path group 20 has a third axis CC' and a fourth axis DD' (taking conductive path group 20 in channel CHa as an example for illustration). The third axis CC' is parallel to the first axis AA', and the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive path group 20. Each conductive path group 20 includes 4 conductive paths D0~D3 arranged in a 2×2 array. The 4 conductive paths are symmetrical about the third axis CC' and about the fourth axis DD' of the conductive path group 20.

[0110] Thus, this embodiment of the present disclosure provides a memory 10 in which the 2A channel signal regions 110 have four-quadrant symmetry (symmetric about the first axis AA' and about the second axis BB'), which is easy to design the layout and also brings advantages in signal transmission after forming a chip stack structure (see the following description of the chip stack structure for details).

[0111] Please see Figure 3Each channel's storage array can be divided into a first pseudo-channel PC0 and a second pseudo-channel PC1. It should be understood that a channel can be viewed as a physical structural concept, meaning that different channels are relatively independent structures; however, a pseudo-channel is a functional concept, a virtualization of the same channel to increase bandwidth, and therefore the two may share a physical structure.

[0112] like Figure 3 As shown, each channel signal area 110 includes a first data signal area PC0_Dword and a second data signal area PC1_Dword arranged along a first direction X. The conductive path group 20 in the first data signal area PC0_Dword is used to transmit the data signal of the corresponding first pseudo-channel PC0, and the conductive path group 20 in the second data signal area PC1_Dword is used to transmit the data signal of the corresponding second pseudo-channel PC1. Here, the data signal can be understood at least as: data written to the aforementioned memory array; and data read from the aforementioned memory array.

[0113] The first data signal area PC0_Dword in the i-th channel signal area 110 is symmetrical to the first data signal area PC0_Dword in the (2A-i+1)-th channel signal area 110 about the second axis BB', and the second data signal area PC1_Dword in the i-th channel signal area is symmetrical to the second data signal area PC1_Dword in the (2A-i+1)-th channel signal area about the second axis BB'. In the above description, A≥i≥1, and i is a positive integer.

[0114] In each device region 120, the storage array is also divided into a first subarray and a second subarray along the first direction X. The first subarray is used to store the data of the first pseudo-channel PC0, and the second subarray is used to store the data of the second pseudo-channel PC1. The first subarray in the i-th channel and the first subarray in the (2A-i+1)-th channel are symmetrical about the second axis BB', and the second subarray in the i-th channel and the second subarray in the (2A-i+1)-th channel are symmetrical about the second axis BB'.

[0115] That is, the first data signal area PC0_Dword corresponding to channel CHa is symmetrical to the first data signal area PC0_Dword corresponding to channel CHd, the second data signal area PC1_Dword corresponding to channel CHa is symmetrical to the second data signal area PC1_Dword corresponding to channel CHd, and so on. Thus, the conductive path group 20 symmetrical about the second axis BB' transmits the same type of signal from the same pseudo-channels PC0 / PC1 in different channels.

[0116] Thus, due to the symmetry of the conductive path groups 20 in the different channel signal areas 110, it is more friendly to control and wiring. Moreover, it is consistent with the symmetry of each pseudo-channel control circuit in the logic chip (see the following description), which reduces the deviation / mismatch of the trace length between the control circuit of each pseudo-channel in the logic chip and the corresponding signal transmission path, and facilitates the formation of a three-dimensional chip stack structure of multiple memory chips and logic chips.

[0117] In some embodiments, please refer to Figure 4 Each channel signal area 110 also includes a control signal area Aword. Within the same channel signal area 110: along the first direction X, the control signal area Aword is located between the first data signal area PC0_Dword and the second data signal area PC1_Dword; wherein, the conductive path group 20 in the control signal area Aword is used to transmit the control signals of the corresponding first pseudo-channel PC0 and the corresponding second pseudo-channel PC1, that is, the first pseudo-channel PC0 and the second pseudo-channel PC1 share the conductive path group 20 in the control signal area Aword. Here, the control signal is used to indicate at least the following information: operation commands (e.g., read commands, write commands, refresh commands, etc.), operation addresses, etc.

[0118] In this embodiment of the disclosure, the control signal area Aword in the i-th channel signal area is symmetrical to the control signal area Aword in the (2A-i+1)-th channel signal area about the second axis BB'.

[0119] In this way, for the same channel, the two pseudo channels transmit data signals through their respective corresponding conductive paths (i.e., the conductive paths in their respective data signal areas Dword), but multiplex the same part of the conductive path (i.e., the conductive paths in the control signal area Aword) to transmit control signals.

[0120] In some embodiments, such as Figure 4 As shown, each conductive path group 20 includes a first conductive path D0, a second conductive path D1, a third conductive path D2, and a fourth conductive path D3; in each conductive path group 20, the first conductive path D0 and the second conductive path D1 are symmetrical about the third axis CC', the third conductive path D2 and the fourth conductive path D3 are symmetrical about the third axis CC', and the first conductive path D0 and the fourth conductive path D3 are symmetrical about the fourth axis DD'.

[0121] It should be noted that the relative positions of all conductive paths within their respective conductive path groups 20 are identical. Figure 4 For example, all the first conductive paths D0 are located at the upper left corner of their respective conductive path groups 20, and all the second conductive paths D1 are located at the lower left corner of their respective conductive path groups 20...

[0122] It should be understood that the first conductive path D0, the second conductive path D1, the third conductive path D2, and the fourth conductive path D3 mentioned above are all essentially "conductive paths." The designations "first, second, third, and fourth" are merely positional numbers for ease of subsequent description, but the physical structure of the conductive paths is the same. Therefore, the statements "the first conductive path D0 in one conductive path group 20 and the fourth conductive path D3 in another conductive path group 20 are symmetrical about the second axis BB'" and "the four conductive paths in one conductive path group 20 and the four conductive paths in another conductive path group 20 are symmetrical about the second axis BB'" are not contradictory.

[0123] because Figure 4 The conductive vias 20 are too densely packed, thus limiting the information they can convey. Figure 5 A further illustration is given using a group of two conductive paths, 20, as an example. For instance... Figure 5 As shown, the active surface of the memory chip 10 is divided into a first region, a second region, a third region, and a fourth region by the first axis AA' and the second axis BB'.

[0124] (1) Please see Figure 5 The black-filled portion is located in the first region, containing multiple first conductive paths D0 ( Figure 5 (Only one example is shown, and similar examples will follow) The multiple second conductive paths D1 located in the second region are symmetrical about the first axis AA', and the multiple first conductive paths D0 located in the first region are also symmetrical about the multiple fourth conductive paths D3 located in the fourth region about the second axis BB'.

[0125] Continue to refer to Figure 5 In the black-filled portion, the multiple third conductive paths D2 in the third region and the multiple fourth conductive paths D3 in the fourth region are symmetrical about the first axis AA'. The multiple third conductive paths D2 in the third region are also symmetrical about the multiple second conductive paths D1 in the second region about the second axis BB'.

[0126] It should be understood that the black-filled parts are only for ease of reading and understanding. The other conductive vias also have the above characteristics, so please understand accordingly.

[0127] (2) Similarly, the multiple second conductive paths D1 located in the first region are symmetrical about the first conductive path D0 located in the second region about the first axis AA', and the second conductive path D1 located in the first region is symmetrical about the third conductive path D2 located in the fourth region about the second axis BB'.

[0128] The multiple fourth conductive paths D3 located in the third region are symmetrical with the multiple third conductive paths D2 located in the fourth region about the first axis AA'. The multiple fourth conductive paths D3 located in the third region are also symmetrical with the multiple first conductive paths D0 located in the second region about the second axis BB'.

[0129] (3) Similarly, the multiple third conductive paths D2 located in the first region and the multiple fourth conductive paths D3 located in the second region are symmetrical about the first axis AA', and the multiple third conductive paths D2 located in the first region and the multiple second conductive paths D1 located in the fourth region are symmetrical about the second axis BB'.

[0130] The multiple first conductive paths D0 located in the third region are symmetrical with the multiple second conductive paths D1 located in the fourth region about the first axis AA', and the multiple first conductive paths D0 located in the third region are also symmetrical with the multiple fourth conductive paths D3 located in the fourth region about the second axis BB'.

[0131] (4) Similarly, the multiple fourth conductive paths D3 located in the first region are symmetrical with the multiple third conductive paths D2 located in the second region about the first axis AA', and the multiple fourth conductive paths D3 located in the first region are also symmetrical with the multiple first conductive paths D0 located in the fourth region about the second axis BB'.

[0132] The multiple second conductive paths D1 located in the third region are symmetrical with the multiple first conductive paths D0 located in the fourth region about the first axis AA', and the multiple second conductive paths D1 located in the third region are symmetrical with the multiple third conductive paths D2 located in the second region about the second axis BB'.

[0133] As can be seen from the above, for the memory chip 10, there must be a first conductive path D0, a second conductive path D1, a third conductive path D2, and a fourth conductive path D3 that are symmetrical about the first axis AA' and about the second axis BB', which can also be called four-quadrant symmetry; this positional feature will provide the basis for signal transmission for the subsequent chip stacking structure.

[0134] In some embodiments, please refer to Figure 5 Each channel also includes 2n first transceivers 21; each first transceiver 21 is coupled to a corresponding first conductive path D0 (in the channel signal area 110 of that channel). That is, for each channel, the 2n first transceivers 21 are coupled to the 2n first conductive paths D0 in a one-to-one correspondence.

[0135] The first transceiver 21 is used to receive signals transmitted through the corresponding connected first conductive path D0; or to generate signals transmitted outward through the corresponding connected first conductive path D0.

[0136] Here, the first transceiver 21 can be understood as a device with one or more of the following functions: signal amplification, signal filtering, gain control, signal shaping, and analog-to-digital / digital-to-analog conversion.

[0137] Taking "the first transceiver 21 is capable of performing analog-to-digital / digital-to-analog conversion" as an example, the first conductive path D0 is used to transmit analog signals, and the first transceiver 21 has bidirectional transmission functions for signal reception and signal transmission. In some embodiments, during signal reception, the first transceiver 21 performs analog-to-digital conversion on the analog signal in the first conductive path D0 to generate a digital signal, which is then sent to the internal circuit for processing; signal transmission is the reverse process.

[0138] It should be understood that Figure 5 The first transceiver 21 shown is for logical illustration only. In reality, the first transceiver 21 may be located in the device area 120 or at the edge or in an empty area of ​​the channel signal area 110. Moreover, the first transceivers 21 of different channels can be made mirror-symmetrical (i.e., overlapping after rotation), or they can be made completely identical (i.e., overlapping after displacement), or they can be designed separately without following any related positional relationship.

[0139] In this way, only the signal of the first conductive path D0 in each conductive path group 20 in the memory chip 10 will be transmitted to the internal circuit via the first transceiver 21, without the need to design transceivers for the remaining second conductive paths D1 to fourth conductive paths D3, saving circuit area and reducing the load on the signal transmission path in the chip stack structure.

[0140] As mentioned above, please refer to Figure 1 The conductive pathways provided in this disclosure include one or more of the following devices: (1) conductive vias; (2) contact structures. Here, the contact structures of adjacent chips or the conductive vias can be electrically connected by one of the following process types: bump process; hybrid bonding (HB) process.

[0141] The conductive via can be a metal via, a glass via, a silicon via, etc. The silicon via can be fabricated by any one or more of the following processes: via-first, via-middle, via-last, and back side via-last. Different conductive paths in the same memory chip are electrically isolated.

[0142] In some embodiments, please refer to Figure 4For different channel signal regions 110 located on the same side of the second axis BB', the distribution positions of their conductive path groups 20 are the same. That is, the 2n conductive path groups 20 of channel CHa coincide with the 2n conductive path groups 20 of channel CHb after translation (Shift), and the 2n conductive path groups 20 of channel CHc coincide with the 2n conductive path groups 20 of channel CHd after translation (Shift).

[0143] Please refer to Figure 5 Taking the channel signal area 110 of channel CHa and channel CHb as examples, "the distribution positions of (any) conductive path group 20 are the same" specifically means that: the distance between the center of a conductive path group 20 in channel CHa and the first edge of channel CHa is L1, and the distance between the center and the second edge of channel CHa is L2; ​​then, there must be a conductive path group 20 in channel CHb whose center is at a distance of L1 from the first edge of channel CHb and at a distance of L2 from the second edge of channel CHb; these two conductive path groups 20 can also be said to have the same coordinates or the same relative position. At this time, the channel signal areas 110 of channels CHa and CHb are completely identical, and they can adopt a unified layout design, without the need for separate wiring connections, simulation measurements, and other steps.

[0144] It should be understood that if the distribution positions of the two conductive path groups 20 are the same, it means that the distribution positions of all conductive paths in these two conductive path groups 20 are also the same.

[0145] In other embodiments, please refer to Figure 6 For different channel signal areas 110 located on the same side of the second axis BB', the distribution position of their conductive path groups 20 can be set differently as needed. That is, the positions of the 2n conductive path groups 20 of channel CHa and the 2n conductive path groups 20 of channel CHb are unrelated, and the positions of the 2n conductive path groups 20 of channel CHc and the 2n conductive path groups 20 of channel CHd are unrelated.

[0146] For ease of explanation, please refer to Figure 7 A fifth axis EE' is introduced into the channel signal region 110. The fifth axis EE' and the first axis AA' intersect perpendicularly at the center of the channel signal region 110, meaning that the distance between the fifth axis EE' and the two sides of its corresponding channel is the same, L3. For the same channel signal region 110, the distribution location of the conductive path also has the following possibilities:

[0147] For the first example, please see Figure 7The conductive path group 20 located on one side of the fifth axis EE' and the conductive path group 20 located on the other side of the fifth axis EE' have no specific positional relationship and can be designed independently of each other.

[0148] For the second example, please see Figure 8 For the same channel signal region 110, the n conductive path groups 20 located on one side of the fifth axis EE' and the n conductive path groups 20 located on the other side of the fifth axis EE' are symmetrical about the fifth axis EE'. In particular, in this scenario, n is an even number.

[0149] In this way, the 2n conductive path groups in the same channel signal region 110 are symmetrical about the first axis AA' and about the fifth axis EE'. Thus, by reusing the same layout for all channel signal regions 110, it can be ensured that all conductive path groups in all channel signal regions 110 are symmetrical about the first axis AA' and about the second axis BB'.

[0150] Thus, the conductive vias in each channel signal region 110 possess four-quadrant symmetry (symmetric about the fifth axis EE' and about the first axis AA'), which means that the conductive path groups in the 2A channel signal regions 110 actually adopt the exact same arrangement. Therefore, all channel signal regions 110 can use the same layout design, eliminating the need for redesign (e.g., rotation or mirroring), further simplifying the layout design of the conductive path groups. However, note that although the layout of the conductive path groups 20 in different channels is the same, i.e., their physical locations are the same, their electrical connections to the circuitry within the channel and the transmitted signals are not entirely identical. For the two channel signal regions 110 located on either side of the second axis BB', the two conductive path groups 20 transmitting the same signal are symmetrical about the second axis BB', rather than being two conductive path groups 20 with the same physical location.

[0151] In the foregoing description, memory chip 10 is a single physical chip; for other examples, please refer to [link to other examples]. Figure 9 The memory chip 10 may include two sub-chips, which can be stacked and bonded together using wafer-on-wafer bonding technology. Specifically, the memory chip 10 includes a first sub-chip (also called an array die) 810 and a second sub-chip (also called a CMOS die) 820 stacked along the third direction Z, and the first sub-chip 810 and the second sub-chip 820 are bonded together.

[0152] like Figure 9As shown, the active surface of the first sub-chip 810 includes a first device region 811 and a first channel signal region 812, and the active surface of the second sub-chip 820 includes a second device region 821 and a second channel signal region 822. In this embodiment, the first device region 811 is fabricated with the aforementioned memory array; the second device region 821 includes a plurality of sense amplifiers SA arranged in an array, and the sense amplifiers SA are electrically connected to the corresponding memory cells.

[0153] As mentioned above, the memory chip 10 contains 2A channels (with A=2 as an example in the attached diagram), please refer to... Figure 10 , Figure 10 (a) shows a schematic diagram of the active surface of the first sub-chip 810. Figure 10 (b) shows a schematic diagram of the active surface of the second sub-chip 820. Figure 10 As shown, in this scenario, the first sub-chip 810 actually includes 4A first device regions 811, and the second sub-chip 820 actually includes 4A second device regions 821. For Figure 10 The first sub-chip 810 and the second sub-chip 820 are stacked face-to-face, so the positioning marks of the first device area 811 and the second device area 821 are oriented in opposite directions. However, this is only an example, and the actual stacking method depends on the application scenario.

[0154] After the first sub-chip 810 and the second sub-chip 820 are stacked, the projections of one first device region 811 and one second device region 821 along the third direction Z at least partially overlap, and the first device region 811 and the second device region 821 aligned along the third direction Z together constitute... Figure 3 One device region 120. Similarly, the projections of a first channel signal region 812 and a second channel signal region 822 along the third direction Z at least partially overlap, and the first channel signal region 812 and the second channel signal region 822 aligned along the third direction Z together correspond to one device region 120. Figure 3 One channel signal area 110 in the middle.

[0155] In some embodiments, the second sub-chip 820 may further include one or more of the following circuits: Sub-word line drive circuit SWD; Switch control (SWC); Bank Level Control; Line decoder (XDEC); YDEC (Yellow Decoder); Second-stage sensing amplifier; First, the power supply control circuit is used; Power control circuit; Error checking and correcting circuits (ECC), etc.

[0156] It should be noted that the substrate of the first sub-chip 810 (first device region 811) and the substrate of the second sub-chip 820 (second device region 821) are each fabricated with in-layer circuit devices, and the in-layer circuit devices of the first sub-chip 810 are correspondingly connected to the in-layer circuit devices in the second sub-chip 820 (of the same memory chip 10). Specifically:

[0157] (1) The in-layer circuit devices of the first sub-chip 810 include one or more of the following: memory cells (word lines, bit lines).

[0158] (2) The in-layer circuit devices of the second sub-chip 820 include one or more of the following: sense amplifier SA, word line drive unit SWD.

[0159] The substrate of the second sub-chip 820 (the vacant area / near area within the second device region 821 or the second channel signal region 822) is also fabricated with interlayer circuitry, which is electrically connected to interlayer circuitry in other memory chips 10, and / or, which is electrically connected to circuitry in logic chips.

[0160] (3) The interlayer circuitry of the second sub-chip 820 includes one or more of the following: input / output ports (IO). Here, the input / output ports are used to transmit data signals, address signals, and operation command signals. These input / output ports are connected to one or more of the following circuits: Memory-level control logic; Line decoder; Column decoder; Second-stage sensing amplifier; First, the power supply control circuit is used; Power control circuit; Other circuits (error correction circuit, clock control circuit, test circuit).

[0161] The above is just one example of intra-layer and inter-layer circuit devices. When the device distribution of the first sub-chip 810 and the second sub-chip 820 is changed, the relevant circuit devices will also change accordingly. Please understand this accordingly.

[0162] For ease of explanation, the surface of the first sub-chip 810 adjacent to the second sub-chip 820 is referred to as the first surface, and the surface of the second sub-chip 820 adjacent to the first sub-chip 810 is referred to as the second surface. It should be understood that the first surface can be either the top or bottom surface; the second surface can also be either the top or bottom surface, depending on the arrangement of the first and second sub-chips 810 and 820. For example, in a scenario where "the first sub-chip 810 and the second sub-chip 820 are stacked face-to-face (see subsequent explanation)," both the first and second surfaces are the top surfaces; the rest can be understood similarly.

[0163] like Figure 9 As shown, both the first and second surfaces are penetrated by X interconnect structures (located in the first device region 811 and the second device region 821) and Y conductive paths (located in the first channel signal region 812 and the second channel signal region 822). The interconnect structures and conductive paths extend along the third direction Z. Wherein, X and Y are both positive integers. The interconnect structures are used to electrically connect the intra-layer circuit devices in the first device region 811 and the intra-layer circuit devices in the second device region 821. The conductive paths penetrate the substrates of the first sub-chip 810 and the second sub-chip 820 along the third direction Z. The conductive paths are electrically isolated from the circuit devices in the first sub-chip 810 and are used to electrically connect the inter-layer circuit devices in the second sub-chip 820 to other chips outside the memory chip.

[0164] In short, the interconnect structure is used to realize signal transmission between the first sub-chip 810 and the second sub-chip within the same memory chip 10, and the conductive path is used to realize signal transmission between different memory chips 10 (including the second sub-chip 820), and signal transmission between the memory chip 10 and the logic chip (Base Die, see subsequent description), thereby providing a structural basis for stacking multiple memory chips 10. Thus, the memory chip 10 provided in this embodiment of the disclosure increases the density of memory cells through the WOW structure, while also allowing multiple memory chips 10 to be stacked in three dimensions, further improving the data integration of the memory and enhancing data storage and transmission capabilities.

[0165] like Figure 9 As shown, the projections of the Y conductive paths along the third direction Z are located in the first channel signal area 812 / the second channel signal area 822.

[0166] like Figure 9 As shown, the projections of the X interconnect structures along the third direction Z are located in the first device region 811 / second device region 821, resulting in shorter traces. However, this does not constitute a limitation; the projections of the interconnect structures can also be located in the first channel signal region 812 / second channel signal region 822.

[0167] Here, the interconnect structure may include, but is not limited to: hybrid bonding (HB) structure, contact structure, metal layer trace, etc., depending on the stacking method used by the first sub-chip and the second sub-chip.

[0168] In another embodiment of this disclosure, a logic chip 30 is provided. See also... Figure 11 This illustrates a schematic diagram of the active surface of the logic chip 30 provided in an embodiment of this disclosure. For example... Figure 11 As shown, the logic chip 30 also includes a global signal area and 2A channel signal areas 310. The 2A channel signal areas 310 of the logic chip 30 correspond one-to-one with the 2A channels in the memory chip 10, and are also arranged along the first direction X.

[0169] It should be understood that the active surfaces of the logic chip 30 and the memory chip 10 may differ in size and shape, but the global signal area of ​​the logic chip 30 and the global signal area of ​​the memory chip 10 have the same area and the same positional distribution of the conductive paths. The 2A channel signal areas 310 of the logic chip 30 and the 2A channel signal areas 310 of the memory chip 10 have the same area and the same positional distribution of the conductive paths, so that after forming a 3D stacked structure, the conductive paths in the logic chip 30 and the conductive paths in the memory chip 10 can be coupled one-to-one to transmit signals (see subsequent description) to realize the transmission of global signals and channel signals.

[0170] Please refer to Figure 11 The active surface of the logic chip 30 also has a first axis AA' and a second axis BB'. The first axis AA' and the second axis BB' intersect perpendicularly at the midpoint of its active surface. The first axis AA' is parallel to the first side of the active surface, and the second axis BB' is parallel to the second side of the active surface. The first axis AA' extends along the first direction X, and the second axis BB' extends along the second direction Y.

[0171] Please refer to Figure 12 Within the same channel signal region 310, there are 2n conductive path groups 40 ( Figure 12 (Only 6 examples are shown) symmetrical about the first axis AA'; and all conductive path groups 40 (a total of 2A×2n) in the 2A channel signal regions 310 of the logic chip 30 are symmetrical about the second axis BB'. That is to say, all conductive path groups 40 (a total of 2A×2n) in the 2A channel signal regions 310 of the logic chip 30 are symmetrical about the first axis AA' and about the second axis BB', or it can be said that all conductive path groups 40 (a total of 2A×2n) in the 2A channel signal regions 310 of the logic chip 30 as a whole have the characteristic of four-quadrant symmetry.

[0172] In one example, when forming a chip stack structure, the back side of the logic chip 30 is close to the memory chip 10, then each conductive path in the conductive path group 40 may consist only of a conductive via, and the conductive via penetrates the substrate of the logic chip 30 along the third direction Z.

[0173] In another example, in the case of forming a chip stack structure, the top surface of the logic chip 30 is close to the memory chip 10, then the conductive path group 40 may only include contact structures, without having to penetrate the substrate of the logic chip 30 along the third direction Z.

[0174] like Figure 12 As shown, each conductive path group 40 has a third axis CC' and a fourth axis DD'. The third axis CC' is parallel to the first axis AA', and the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive path group 40. Each conductive path group 40 includes four conductive paths arranged in a 2×2 array. The four conductive paths are symmetrical about the third axis CC' of the conductive path group 40 and about the fourth axis DD' of the conductive path group 40.

[0175] As mentioned above, each channel is virtually designated as a first pseudo-channel PC0 and a second pseudo-channel PC1, and each channel in the logic chip 30 is also virtually designated as a first pseudo-channel PC0 and a second pseudo-channel PC1. Each channel signal region 310 in the logic chip 30 includes a first data signal region PC0_Dword and a second data signal region PC1_Dword arranged along the first direction X. The conductive path group in the first data signal region PC0_Dword is used to transmit the data signal of the corresponding first pseudo-channel PC0, and the conductive path group in the second data signal region PC1_Dword is used to transmit the data signal of the corresponding second pseudo-channel PC1.

[0176] In some embodiments, for the logic chip 30, the first data signal area PC0_Dword in the i-th channel signal area is symmetrical to the first data signal area PC0_Dword in the (2A-i+1)-th channel signal area about the second axis BB', and the second data signal area PC1_Dword in the i-th channel signal area is symmetrical to the second data signal area PC1_Dword in the (2A-i+1)-th channel signal area about the second axis BB'.

[0177] In simple terms, the conductive paths in the logic chip 30 and the memory chip 10 are in one-to-one correspondence so that after the chip stack structure is formed, the multiple conductive paths of the logic chip 30 and the multiple conductive paths of the memory chip 10 are aligned one-to-one along the projection of the third direction Z, and then electrically connected to form a signal transmission path. This part will be explained in more detail later.

[0178] In some embodiments, for the logic chip 30, each channel signal region 310 further includes a control signal region Aword. In the same channel signal region 310: along the first direction X, the control signal region Aword is located between the first data signal region PC0_Dword and the second data signal region PC1_Dword; wherein, the conductive path group 40 in the control signal region Aword is used to transmit the control signals of the corresponding first pseudo-channel PC0 and the corresponding second pseudo-channel PC1.

[0179] In some embodiments, please refer to Figure 12 Each conductive path group 40 includes a first conductive path D0, a second conductive path D1, a third conductive path D2, and a fourth conductive path D3; in each conductive path group 40, the first conductive path D0 and the second conductive path D1 are symmetrical about the third axis CC', the third conductive path D2 and the fourth conductive path D3 are symmetrical about the third axis CC', and the first conductive path D0 and the fourth conductive path D3 are symmetrical about the fourth axis DD'.

[0180] Please refer to Figure 12 The active surface of the logic chip 30 is divided into a first region, a second region, a third region, and a fourth region by the first axis AA' and the second axis BB'.

[0181] (1) The multiple first conductive paths D0 located in the first region are symmetrical with the multiple second conductive paths D1 located in the second region about the first axis AA', and the multiple first conductive paths D0 located in the first region are also symmetrical with the multiple fourth conductive paths D3 located in the fourth region about the second axis BB';

[0182] The multiple third conductive paths D2 located in the third region are symmetrical with the multiple fourth conductive paths D3 located in the fourth region about the first axis AA'. The multiple third conductive paths D2 located in the third region are also symmetrical with the multiple second conductive paths D1 located in the second region about the second axis BB'.

[0183] (2) The multiple second conductive paths D1 located in the first region are symmetrical with the multiple first conductive paths D0 located in the second region about the first axis AA', and the second conductive path D1 located in the first region is symmetrical with the third conductive path D2 located in the fourth region about the second axis BB';

[0184] The multiple fourth conductive paths D3 located in the third region are symmetrical with the multiple third conductive paths D2 located in the fourth region about the first axis AA'. The multiple fourth conductive paths D3 located in the third region are also symmetrical with the multiple first conductive paths D0 located in the second region about the second axis BB'.

[0185] (3) The multiple third conductive paths D2 located in the first region and the multiple fourth conductive paths D3 located in the second region are symmetrical about the first axis AA', and the multiple third conductive paths D2 located in the first region and the multiple second conductive paths D1 located in the fourth region are symmetrical about the second axis BB'.

[0186] The multiple first conductive paths D0 located in the third region are symmetrical with the multiple second conductive paths D1 located in the fourth region about the first axis AA', and the multiple first conductive paths D0 located in the third region are also symmetrical with the multiple fourth conductive paths D3 located in the fourth region about the second axis BB'.

[0187] (4) The multiple fourth conductive paths D3 located in the first region are symmetrical with the multiple third conductive paths D2 located in the second region about the first axis AA', and the multiple fourth conductive paths D3 located in the first region are also symmetrical with the multiple first conductive paths D0 located in the fourth region about the second axis BB'.

[0188] The multiple second conductive paths D1 located in the third region are symmetrical with the multiple first conductive paths D0 located in the fourth region about the first axis AA', and the multiple second conductive paths D1 located in the third region are symmetrical with the multiple third conductive paths D2 located in the second region about the second axis BB'.

[0189] In some embodiments, see Figure 13 Each channel signal area 310 in the logic chip 30 also includes (2n×4) second transceivers 41. For each channel signal area 310, the (2n×4) second transceivers 41 are coupled to (2n×4) conductive paths in a one-to-one correspondence. The second transceivers 41 are used to receive signals transmitted from the corresponding coupled conductive paths to the logic chip 30; or, generate signals transmitted outward via the corresponding conductive paths.

[0190] In some embodiments, please refer to Figure 1 The conductive pathways provided in this disclosure include one or more of the following devices: (1) conductive vias; (2) contact structures; the contact structures of adjacent chips or the conductive vias can be electrically connected by one of the following process types: bump process; hybrid bonding (HB) process.

[0191] The conductive via can be a silicon via, which can be fabricated using any one or more of the following processes: via-first, via-middle, via-last, and back side via-last; different conductive paths in the same logic chip 30 are electrically isolated.

[0192] In some embodiments, see Figure 12 For different channel signal regions 310 located on the same side of the second axis BB', the distribution positions of their conductive path groups 40 are the same. That is, the 2n conductive path groups 40 corresponding to channel CHa coincide with the 2n conductive path groups 40 corresponding to channel CHb after translation (Shift), and the 2n conductive path groups 40 corresponding to channel CHc coincide with the 2n conductive path groups 40 corresponding to channel CHd after translation (Shift).

[0193] In other embodiments, the distribution positions of the conductive path groups 40 of different channel signal regions 310 located on the same side of the second axis BB' can be set differently as needed. That is, the positions of the 2n conductive path groups 40 of channel CHa and the 2n conductive path groups 40 of channel CHb are unrelated, and the positions of the 2n conductive path groups 40 of channel CHc and the 2n conductive path groups 40 of channel CHd are unrelated.

[0194] For ease of explanation, a fifth axis is introduced for the channel signal region 310. This fifth axis intersects the first axis perpendicularly at the center of the channel signal region 310. Please refer to the fifth axis of the memory chip 10 for further understanding. For the same channel signal region 310, the distribution of conductive paths may also include the following possibilities:

[0195] In the first example, the conductive path group 40 located on one side of the fifth axis and the conductive path group 40 located on the other side of the fifth axis have no specific positional relationship and can be designed independently of each other.

[0196] In the second example, for the same channel signal region 310, the n conductive path groups 40 located on one side of the fifth axis and the n conductive path groups 40 located on the other side of the fifth axis are symmetrical about the fifth axis. In particular, in this scenario, n is an even number.

[0197] In this way, the 2n conductive path groups in the same channel signal region 310 are symmetrical about the first axis AA' and about the fifth axis. Thus, by reusing the same layout for all channel signal regions 310, it can be ensured that all conductive path groups in all channel signal regions 310 are symmetrical about the first axis AA' and about the second axis BB'.

[0198] Thus, this embodiment of the disclosure provides a logic chip 30, in which the conductive paths in the logic chip 30 and the conductive paths in the memory chip 10 are aligned one-to-one along the third direction Z, which facilitates signal transmission after the signal transmission path between the logic chip 30 and the memory chip 10 is formed in the chip stack structure.

[0199] In yet another embodiment of this disclosure, a chip stacking structure 50 is provided. See also... Figure 14 , Figure 14 A three-dimensional structural schematic diagram of the first chip stacking structure 50 provided in the embodiments of this disclosure is shown. Figure 14 The control signal area Aword is omitted.

[0200] like Figure 14 As shown, the chip stacking structure 50 includes the logic chip 30 as described above and at least one stacking unit. The logic chip 30 and at least one stacking unit are stacked sequentially along a third direction Z. Each stacking unit includes a first memory chip 10A, a second memory chip 10B, a third memory chip 10C, and a fourth memory chip 10D stacked sequentially along the third direction Z. The third direction Z is perpendicular to the active surface of each memory chip. The first memory chip 10A, the second memory chip 10B, the third memory chip 10C, and the fourth memory chip all adopt the structure of the aforementioned memory chip 10.

[0201] It should be understood that there is no specific limitation on the active surface size of the memory chip 10 and the logic chip 30, and they are allowed to be different. However, after forming the chip stack structure 50, the first axis AA' of the memory chip 10 and the first axis AA' of the logic chip 30 are aligned along the third direction Z, and the second axis BB' of the memory chip 10 and the second axis BB of the logic chip 30 are aligned along the third direction Z.

[0202] like Figure 14 As shown, the first memory chip 10A and the second memory chip 10B are stacked face to face, the second memory chip 10B and the third memory chip 10C are stacked back to back, and the third memory chip 10C and the fourth memory chip 10D are stacked face to face.

[0203] In the embodiments of this disclosure, face-to-face stacking means that the top surfaces of two chips are approximately aligned along the third direction Z; back-to-back stacking means that the bottom surfaces of two chips are approximately aligned along the third direction Z; face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along the third direction Z. Unless otherwise specified, "chip" can refer to either a logic chip or a memory chip.

[0204] It should be noted that, in one possibility, for two chips connected face-to-face, the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) are electrically connected using a hybrid bonding (also known as bonding pillar) process; for two chips connected back-to-back or for two chips connected face-to-back, the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) are electrically connected using a conductive bump (UBump, also known as microbump) process.

[0205] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected face-to-back, the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) of both are connected using a hybrid bonding process. That is, the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) between two face-to-face connected chips are electrically connected using a hybrid bonding process, and the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) between two back-to-back connected chips and between two face-to-back connected chips are also electrically connected using a hybrid bonding process.

[0206] In another possibility, for two chips connected face-to-face, or for two chips connected back-to-back or face-to-back, the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) are connected using a conductive bump process. That is, the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) between two face-to-face connected chips are connected using a conductive bump process, and the bonding surfaces (the positions where the central conductive vias are aligned along the third direction Z) between two back-to-back connected chips and between two face-to-back connected chips are also connected using a conductive bump process.

[0207] Here, the above chip can refer to either logic chip 30 or memory chip 10.

[0208] It's worth noting that compared to conductive bump bonding, face-to-face bonding using hybrid bonding allows for a much tighter fit between adjacent chips, virtually eliminating gaps. This significantly reduces the height of the chip stack structure, which is one of the advantages of face-to-face stacking. Of course, two chips connected back-to-back can also be joined using hybrid bonding, but the connection performance is weaker than that achieved through conductive bump bonding, potentially affecting yield.

[0209] Thus, each memory chip needs to include conductive vias and contact structures that penetrate the substrate. For two memory chips stacked face-to-face, the aforementioned first to fourth conductive paths are specifically manifested as conductive vias; for two memory chips stacked back-to-back, the aforementioned first to fourth conductive paths are specifically manifested as contact structures. For the overall chip stack structure 50, the conductive path of the first memory chip 10A, the contact structure of the first memory chip 10A, the contact structure of the second memory chip 10B, the conductive path of the second memory chip 10B, the conductive path of the third memory chip 10C, the contact structure of the third memory chip 10C, the contact structure of the fourth memory chip 10D, the conductive path of the fourth memory chip 10D… are sequentially connected to form a signal transmission channel.

[0210] In this embodiment of the disclosure, for the chip stack structure 50, the projections of the 2A first data signal areas PC0_Dword of the logic chip 30 and the 2A first data signal areas PC0_Dword of each memory chip along a third direction overlap one-to-one; the projections of the 2A second data signal areas PC1_Dword of the logic chip 30 and the 2A second data signal areas PC1_Dword of each memory chip along a third direction overlap one-to-one.

[0211] Because the conductive path group 20 in the memory chip 10 has the characteristic of four-quadrant symmetry, even if different memory chips 10 are placed in different directions, for the chip stack structure 50, the multiple conductive paths in the logic chip 30 can be aligned one-to-one with the multiple conductive paths in each memory chip 10 along the third direction Z, and the conductive paths aligned along the third direction are coupled to form a signal transmission channel, thereby realizing the signal transmission between the logic chip 30 and each memory chip 10.

[0212] While adhering to the aforementioned principles, there are still various ways to stack memory chips and logic chips, which are explained in detail below.

[0213] I. The first stacking method for memory chips:

[0214] Please refer to Figure 15 The i-th channel signal area 110 in the first memory chip 10A, the i-th channel signal area 110 in the second memory chip 10B, the (2A+1-i)-th channel signal area 110 in the third memory chip 10C, and the (2A+1-i)-th channel signal area 110 in the fourth memory chip 10D are aligned along the third direction Z.

[0215] like Figure 15 As shown, when A=2:

[0216] (1) The first channel signal area 110 corresponding to CHa in the first memory chip 10A, the first channel signal area 110 corresponding to CHa in the second memory chip 10B, the fourth channel signal area 110 corresponding to CHd in the third memory chip 10C, and the fourth channel signal area 110 corresponding to CHd in the fourth memory chip 10D are aligned along the third direction Z;

[0217] (2) The second channel signal area 110 corresponding to CHb in the first memory chip 10A, the second channel signal area 110 corresponding to CHb in the second memory chip 10B, the third channel signal area 110 corresponding to CHc in the third memory chip 10C, and the third channel signal area 110 corresponding to CHc in the fourth memory chip 10D are aligned along the third direction Z.

[0218] (3) The third channel signal area 110 corresponding to CHc in the first memory chip 10A, the third channel signal area 110 corresponding to CHc in the second memory chip 10B, the second channel signal area 110 corresponding to CHb in the third memory chip 10C, and the second channel signal area 110 corresponding to CHb in the fourth memory chip 10D are aligned along the third direction Z.

[0219] (4) The fourth channel signal area 110 corresponding to CHd in the first memory chip 10A, the fourth channel signal area 110 corresponding to CHd in the second memory chip 10B, the first channel signal area 110 corresponding to CHa in the third memory chip 10C, and the first channel signal area 110 corresponding to CHa in the fourth memory chip 10D are aligned along the third direction Z.

[0220] The alignment of the first data signal area PC0_Dword and the second data signal area PC1_Dword in different memory chips is as follows:

[0221] (1) The first data signal area PC0_Dword in the first channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the first channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the fourth channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the fourth channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0222] The second data signal area PC1_Dword in the first channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the first channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the fourth channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the fourth channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0223] (2) The first data signal area PC0_Dword in the second channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the second channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the third channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the third channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0224] The second data signal area PC1_Dword in the second channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the second channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the third channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the third channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0225] (3) The first data signal area PC0_Dword in the third channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the third channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the second channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the second channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0226] The second data signal area PC1_Dword in the third channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the third channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the second channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the second channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0227] (4) The first data signal area PC0_Dword in the fourth channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the fourth channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the first channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the first channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0228] The second data signal area PC1_Dword in the fourth channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the fourth channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the first channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the first channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0229] For this stacking method, the alignment rules for the regions of different memory chips are as follows:

[0230] (1) The first region of the first memory chip 10A, the second region of the second memory chip 10B, the third region of the third memory chip 10C, and the fourth region of the fourth memory chip 10D are aligned along the third direction Z.

[0231] (2) The second region of the first memory chip 10A, the first region of the second memory chip 10B, the fourth region of the third memory chip 10C, and the third region of the fourth memory chip 10D are aligned along the third direction Z.

[0232] (3) The third region of the first memory chip 10A, the fourth region of the second memory chip 10B, the first region of the third memory chip 10C, and the second region of the fourth memory chip 10D are aligned along the third direction Z.

[0233] (4) The fourth region of the first memory chip 10A, the third region of the second memory chip 10B, the second region of the third memory chip 10C, and the first region of the fourth memory chip 10D are aligned along the third direction Z.

[0234] Please see Figure 16 It provides targeted Figure 15 The alignment of conductive vias in the memory chip. For this stacking method, the alignment rules for the conductive paths of different memory chips are as follows:

[0235] (a) The first conductive path D0 of the first memory chip 10A, the second conductive path D1 of the second memory chip 10B, the third conductive path D2 of the third memory chip 10C, and the fourth conductive path D3 of the fourth memory chip 10D are aligned along the third direction Z.

[0236] (b) The second conductive path D1 of the first memory chip 10A, the first conductive path D0 of the second memory chip 10B, the fourth conductive path D3 of the third memory chip 10C, and the third conductive path D2 of the fourth memory chip 10D are aligned along the third direction Z.

[0237] (c) The third conductive path D2 of the first memory chip 10A, the fourth conductive path D3 of the second memory chip 10B, the first conductive path D0 of the third memory chip 10C, and the second conductive path D1 of the fourth memory chip 10D are aligned along the third direction Z.

[0238] (d) The fourth conductive path D3 of the first memory chip 10A, the third conductive path D2 of the second memory chip 10B, the second conductive path D1 of the third memory chip 10C, and the first conductive path D0 of the fourth memory chip 10D are aligned along the third direction Z.

[0239] For memory chips, multiple conductive paths aligned Z-axis along a third direction are coupled to form a signal transmission channel, with different signal transmission channels electrically isolated.

[0240] II. The second stacking method of memory chips 10:

[0241] exist Figure 14 Based on this, a second stacking method is generated by swapping the positions of the second memory chip 10B and the fourth memory chip 10D, as shown in the specific illustration. Figure 17 Specifically, Figure 18 A schematic diagram of the channel numbering of each chip in the second chip stacking structure 50 provided in this embodiment of the present disclosure is shown.

[0242] like Figure 18 As shown, in some embodiments, the i-th channel signal region 110 in the first memory chip, the (2A+1-i)-th channel signal region 110 in the second memory chip 10B, the (2A+1-i)-th channel signal region 110 in the third memory chip 10C, and the i-th channel signal region 110 in the fourth memory chip 10D are aligned along the third direction Z; wherein, when a=1, b=2; when a=2, b=1; A≥i≥1.

[0243] (1) The first channel signal area 110 corresponding to CHa in the first memory chip 10A, the fourth channel signal area 110 corresponding to CHd in the second memory chip 10B, the fourth channel signal area 110 corresponding to CHd in the third memory chip 10C, and the first channel signal area 110 corresponding to CHa in the fourth memory chip 10D are aligned along the third direction Z;

[0244] (2) The second channel signal area 110 corresponding to CHb in the first memory chip 10A, the third channel signal area 110 corresponding to CHc in the second memory chip 10B, the third channel signal area 110 corresponding to CHc in the third memory chip 10C, and the second channel signal area 110 corresponding to CHb in the fourth memory chip 10D are aligned along the third direction Z.

[0245] (3) The third channel signal area 110 corresponding to CHc in the first memory chip 10A, the second channel signal area 110 corresponding to CHb in the second memory chip 10B, the second channel signal area 110 corresponding to CHb in the third memory chip 10C, and the third channel signal area 110 corresponding to CHc in the fourth memory chip 10D are aligned along the third direction Z.

[0246] (4) The fourth channel signal area 110 corresponding to CHd in the first memory chip 10A, the first channel signal area 110 corresponding to CHa in the second memory chip 10B, the first channel signal area 110 corresponding to CHa in the third memory chip 10C, and the fourth channel signal area 110 corresponding to CHd in the fourth memory chip 10D are aligned along the third direction Z.

[0247] The alignment of the first data signal area PC0_Dword and the second data signal area PC1_Dword in different memory chips is as follows:

[0248] (1) The first data signal area PC0_Dword in the first channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the fourth channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the fourth channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the first channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0249] The second data signal area PC1_Dword in the first channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the fourth channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the fourth channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the first channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0250] (2) The first data signal area PC0_Dword in the second channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the third channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the third channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the second channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0251] The second data signal area PC1_Dword in the second channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the third channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the third channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the second channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0252] (3) The first data signal area PC0_Dword in the third channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the second channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the second channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the third channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0253] The second data signal area PC1_Dword in the third channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the second channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the second channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the third channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0254] (4) The first data signal area PC0_Dword in the fourth channel signal area 110 of the first memory chip 10A, the first data signal area PC0_Dword in the first channel signal area 110 of the second memory chip 10B, the first data signal area PC0_Dword in the first channel signal area 110 of the third memory chip 10C, and the first data signal area PC0_Dword in the fourth channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z;

[0255] The second data signal area PC1_Dword in the fourth channel signal area 110 of the first memory chip 10A, the second data signal area PC1_Dword in the first channel signal area 110 of the second memory chip 10B, the second data signal area PC1_Dword in the first channel signal area 110 of the third memory chip 10C, and the second data signal area PC1_Dword in the fourth channel signal area 110 of the fourth memory chip 10D are aligned along the third direction Z.

[0256] In this scenario, the alignment rules for different memory chip regions are as follows:

[0257] (a) The first region of the first memory chip 10A, the fourth region of the second memory chip 10B, the third region of the third memory chip 10C, and the second region of the fourth memory chip 10D are aligned along the third direction Z.

[0258] (b) The second region of the first memory chip 10A, the third region of the second memory chip 10B, the fourth region of the third memory chip 10C, and the first region of the fourth memory chip 10D are aligned along the third direction Z.

[0259] (c) The third region of the first memory chip 10A, the second region of the second memory chip 10B, the first region of the third memory chip 10C, and the fourth region of the fourth memory chip 10D are aligned along the third direction Z.

[0260] (d) The fourth region of the first memory chip 10A, the first region of the second memory chip 10B, the second region of the third memory chip 10C, and the third region of the fourth memory chip 10D are aligned along the third direction Z.

[0261] In this scenario, the alignment rules for the conductive paths of different memory chips are as follows:

[0262] (1) The first conductive path D0 of the first memory chip 10A, the fourth conductive path D3 of the second memory chip 10B, the third conductive path D2 of the third memory chip 10C, and the second conductive path D1 of the fourth memory chip 10D are aligned along the third direction Z.

[0263] (2) The second conductive path D1 of the first memory chip 10A, the third conductive path D2 of the second memory chip 10B, the fourth conductive path D3 of the third memory chip 10C, and the first conductive path D0 of the fourth memory chip 10D are aligned along the third direction Z.

[0264] (3) The third conductive path D2 of the first memory chip 10A, the second conductive path D1 of the second memory chip 10B, the first conductive path D0 of the third memory chip 10C, and the fourth conductive path D3 of the fourth memory chip 10D are aligned along the third direction Z.

[0265] (4) The fourth conductive path D3 of the first memory chip 10A, the first conductive path D0 of the second memory chip 10B, the second conductive path D1 of the third memory chip 10C, and the third conductive path D2 of the fourth memory chip 10D are aligned along the third direction Z.

[0266] For memory chips, multiple conductive paths aligned Z-axis along a third direction are coupled to form a signal transmission channel, with different signal transmission channels electrically isolated.

[0267] III. The first stacking method for logic chip 30:

[0268] The logic chip 30 is stacked face-down, meaning the logic chip 30 and the first memory chip 10A are stacked back-to-back. In this scenario, the logic chip 30 needs to have conductive vias that penetrate the substrate as conductive paths. The conductive vias of the logic chip 30 and the first memory chip 10A can be electrically connected using a hybrid bonding (HB) process.

[0269] In the first example, please refer to Figure 15 The i-th channel signal area 310 in the logic chip 30 and the i-th channel signal area 110 in the first memory chip 10A are aligned along the third direction Z, that is, the logic chip 30 and the second memory chip 10B are arranged in the same way.

[0270] At this time, the first data signal area PC0_Dword in the i-th channel signal area 310 of the logic chip 30 and the first data signal area PC0_Dword in the i-th channel signal area 110 of the first memory chip 10A are aligned along the third direction Z, and the second data signal area PC1_Dword in the i-th channel signal area 310 of the logic chip 30 and the second data signal area PC1_Dword in the i-th channel signal area 110 of the first memory chip 10A are aligned along the third direction Z.

[0271] In this scenario, the "second region, first region, fourth region, and third region in logic chip 30" and the "first region, second region, third region, and fourth region in first memory chip 10A" are aligned along the third direction Z.

[0272] In this scenario, please refer to Figure 16 The second conductive path D1, the first conductive path D0, the fourth conductive path D3, and the third conductive path D2 in the logic chip 30 are aligned along the third direction Z to correspond one-to-one with the first conductive path D0, the second conductive path D1, the third conductive path D2, and the fourth conductive path D3 in the first memory chip 10A.

[0273] Thus, for the overall chip stack structure 50, the following applies:

[0274] (1) such as Figure 16 As shown, a second conductive path D1 in the logic chip 30, a first conductive path D0 in the first memory chip 10A, a second conductive path D1 in the second memory chip 10B, a third conductive path D2 in the third memory chip 10C, and a fourth conductive path D3 in the fourth memory chip 10D are aligned along the third direction Z and coupled to form a signal transmission path.

[0275] (2) For example Figure 16As shown, a first conductive path D0 in logic chip 30, a second conductive path D1 in first memory chip 10A, a third conductive path D2 in second memory chip 10B, a fourth conductive path D3 in third memory chip 10C, and a first conductive path D0 in fourth memory chip 10D are aligned along the third direction Z and coupled to form a signal transmission path.

[0276] (3) such as Figure 16 As shown, a fourth conductive path D3 in logic chip 30, a third conductive path D2 in first memory chip 10A, a second conductive path D1 in second memory chip 10B, a first conductive path D0 in third memory chip 10C, and a fourth conductive path D3 in fourth memory chip 10D are aligned along the third direction Z and coupled to form a signal transmission path.

[0277] (4) such as Figure 16 As shown, a third conductive path D2 in logic chip 30, a fourth conductive path D3 in first memory chip 10A, a first conductive path D0 in second memory chip 10B, a second conductive path D1 in third memory chip 10C, and a third conductive path D2 in fourth memory chip 10D are aligned along the third direction Z and coupled to form a signal transmission path.

[0278] Here, different signal transmission paths are electrically isolated.

[0279] The following describes the signal processing for the overall chip stack structure 50.

[0280] It should be noted that, please refer to Figure 11 The logic chip 30 also includes 2A signal processing areas 320, which are arranged along the first direction X.

[0281] Thus, the i-th signal processing area 320 and the i-th channel signal area 310 are arranged along the second direction Y and their projections at least partially overlap. The devices in the i-th signal processing area 320 are used to process the signals transmitted by the conductive path group 40 in the i-th channel signal area 310. The traces are shorter and easier to arrange.

[0282] Here, Figure 11 Therefore Figure 15 The following diagram illustrates the channel numbering of a chip stack structure 50 as an example. Please refer to... Figure 15 The rightmost channel signal area 110 of the first memory chip 10A corresponds to CH0, the rightmost channel signal area 110 of the second memory chip 10B corresponds to CH4, the rightmost channel signal area 110 of the third memory chip 10C corresponds to CH8, and the rightmost channel signal area 110 of the fourth memory chip 10D corresponds to CH12.

[0283] Therefore, please refer to Figure 11 The rightmost channel signal area 310 in logic chip 30 is used to transmit channel signals CH0, CH4, CH8, and CH12. These channel signals originate from the signal processing area 320 above the rightmost channel signal area 310 and are transmitted to the corresponding memory chips, or these channel signals originate from the stacked memory chips and are ultimately transmitted to the corresponding signal processing area 320 above the rightmost channel signal area 310. Please refer to the following for further understanding.

[0284] In some embodiments, such as Figure 11 As shown, each signal processing area 320 includes four sub-processing areas distributed sequentially along the second direction Y: taking the first signal processing area 320 on the right as an example, it specifically includes a sub-processing area for CH0, a sub-processing area for CH4, a sub-processing area for CH8, and a sub-processing area for CH12. Different signal processing sub-areas correspond to different channels, and the internal circuit of each sub-processing area is used to process / generate the channel signal of the corresponding channel.

[0285] In some implementations, please refer to Figure 11 Each sub-processing area includes a PC0 data processing area, a control processing area, and a PC1 data processing area arranged along the first direction X.

[0286] Still with Figure 11 Taking the first channel signal area 310 on the right and the first signal processing area 320 on the right as examples:

[0287] (1) All first conductive vias D0 in the first data signal area PC0_Dword transmit channel signals (specifically data signals) for the first pseudo channel PC0 of CH0, which are further sent to (or generated in) the PC0 data processing area in the sub-processing area for CH0;

[0288] All the first conductive vias D0 in the second data signal area PC1_Dword transmit the channel signal (specifically, the data signal) of the second pseudo-channel PC1 for CH0. This channel signal is further sent to (or generated in) the PC1 data processing area in the sub-processing area for CH0.

[0289] All first conductive vias D0 in the control signal area Aword transmit channel signals (specifically control signals) for CH0. These channel signals are generated in the control processing area of ​​the sub-processing area for CH0 and are used by the first pseudo channel PC0 or the second pseudo channel PC1 of CH0.

[0290] (2) All the second conductive vias D1 in the first data signal area PC0_Dword transmit the channel signal (specifically, the data signal) of the first pseudo channel PC0 for CH4. This channel signal is further sent to (or generated in) the PC0 data processing area in the sub-processing area for CH4;

[0291] All the second conductive vias D1 in the second data signal area PC1_Dword transmit the channel signal (specifically, the data signal) of the second pseudo-channel PC1 for CH4. This channel signal is further sent to (or generated in) the PC1 data processing area in the sub-processing area for CH4.

[0292] All the second conductive vias D1 in the control signal area Aword transmit channel signals (specifically control signals) for CH4. These channel signals are generated in the control processing area of ​​the sub-processing area for CH4 and are used by the first pseudo channel PC0 or the second pseudo channel PC1 of CH4.

[0293] (3) All the third conductive vias D2 in the first data signal area PC0_Dword transmit the channel signal (specifically, the data signal) for the first pseudo channel PC0 of CH8, which is further sent to (or generated in) the PC0 data processing area in the sub-processing area for CH8;

[0294] All the third conductive vias D2 in the second data signal area PC1_Dword transmit the channel signal (specifically, the data signal) for the second pseudo-channel PC1 of CH8. This channel signal is further sent to (or generated in) the PC1 data processing area in the sub-processing area for CH8.

[0295] All third conductive vias D2 in the control signal area Aword transmit channel signals (specifically control signals) for CH8. These channel signals are generated in the control processing area of ​​the sub-processing area for CH8 and are used by the first pseudo-channel PC0 or the second pseudo-channel PC1 of CH8.

[0296] (4) All fourth conductive vias D3 in the first data signal area PC0_Dword transmit the channel signal (specifically, the data signal) of the first pseudo channel PC0 for CH12. This channel signal is further sent to (or generated in) the PC0 data processing area in the sub-processing area for CH12;

[0297] All fourth conductive vias D3 in the second data signal area PC1_Dword transmit the channel signal (specifically, the data signal) of the second pseudo-channel PC1 for CH12. This channel signal is further sent to (or generated in) the PC1 data processing area in the sub-processing area for CH12.

[0298] All fourth conductive vias D3 in the control signal area Aword transmit channel signals (specifically control signals) for CH12. These channel signals are generated in the control processing area of ​​the sub-processing area for CH12 and are used by the first pseudo-channel PC0 or the second pseudo-channel PC1 of CH12.

[0299] It should be understood that, according to industry standards, the i-th signal processing region 320 and the (2A-i+1)-th signal processing region 320 are symmetrical along the second axis BB', as can be seen in [reference needed]. Figure 11 The orientation markers in the diagram. Therefore, in this embodiment, the first data signal area PC0_Dword in the i-th channel signal area 310 and the first data signal area PC0_Dword in the (2A-i+1)-th channel signal area 310 are designed to be symmetrical, and the second data signal area PC1_Dword in the i-th channel signal area 310 and the second data signal area PC1_Dword in the (2A-i+1)-th channel signal area 310 are designed to be symmetrical. This makes the data signal area PC0_Dword corresponding to the first pseudo-channel PC0 close to the PC0 data processing area, and makes the data signal area PC1_Dword corresponding to the second pseudo-channel PC1 close to the PC1 data processing area. There is no need for cross routing, the design complexity of the routing is significantly reduced, and the possibility of design errors is avoided.

[0300] like Figure 19 As shown, the two signal processing areas 320 located on the same side of the second axis BB' can sample the same routing design. The routing of the signal processing areas 320 located on opposite sides of the second axis BB' is mirror symmetrical (but this does not constitute a limitation), thus significantly reducing the design complexity. Please refer to... Figure 11 The routing here includes: the routing between the first data signal area PC0_Dword and the corresponding pseudo-channel PC0 data processing area, the routing between the second data signal area PC1_Dword and the corresponding pseudo-channel PC1 data processing area, and the routing between the control signal area Aword and the corresponding control processing area.

[0301] Based on this, please see Figure 20 It shows a schematic diagram of the signals transmitted through the conductive paths in the first memory chip 10A to the fourth memory chip 10D. Please refer to [link / reference]. Figure 21 It shows a schematic diagram of the signals transmitted through the conductive paths in a logic chip 30 that is stacked face down. Figure 20 and Figure 21 All with Figure 15 The stacking arrangement shown is illustrated.

[0302] It should be understood that, regardless of Figure 20 and Figure 21 The example only shows four conductive path groups 20 and 40 for each channel signal region 110 / channel signal region 310, but in reality, the number of conductive path groups is much larger, and the signal types are not limited to these. Figure 20 and Figure 21 Examples.

[0303] It should be understood that, for Figure 20 and Figure 21 The conductive path containing the gray-filled CS_0 is aligned along the third direction Z. Specifically, after CS_0 is generated by the sub-signal processing area corresponding to CHO in the logic chip 30, it is transmitted upwards sequentially through the second conductive path D1 of the logic chip 30, the first conductive path D0 of the first memory chip 10A, the second conductive path D1 of the second memory chip 10B, the third conductive path D2 of the third memory chip 10C, the fourth conductive path D3 of the fourth memory chip 10D, and so on. In this signal transmission channel, since only the first conductive path D0 in the memory chip is connected to the first transceiver 21, CS_0 only enters the channel CH0 of the first memory chip 10A through the first conductive path D0 and the first transceiver 21 connected to it, thereby playing a control role on the corresponding part. However, since the second conductive path D1, the third conductive path D2, and the fourth conductive path D3 are not equipped with transceivers, they are electrically isolated from the internal circuits of their respective memory chips. Therefore, CS_0 will not enter the second memory chip 10B, the third memory chip 10C, or the fourth memory chip 10D.

[0304] Similarly, please refer to Figure 22For logic chip 30, signals of the same type are distributed to their respective corresponding channels: CS_0 can only enter channel CH0 of the first memory chip 10A via the second conductive path D1 and the first transceiver 21 connected thereto; CS_4 enters channel CH4 of the second memory chip 10B via the first conductive path D0 and the first transceiver 21 connected thereto; CS_8 enters channel CH8 of the third memory chip 10C via the fourth conductive path D3 and the first transceiver 21 connected thereto; CS_12 enters channel CH12 of the fourth memory chip 10D via the third conductive path D2 and the first transceiver 21 connected thereto... At the same time, different types of signals for the same channel are distributed to the same memory chip: CS_0 / WE_0 / BA_0 / PC_0 are all transmitted to channel CH0 of the first memory chip 10A via different first conductive paths D0 in the corresponding channel signal area.

[0305] The signals sent from the memory chip 10 to the logic chip 30 are similar. The signals to be sent by the first memory chip 10A are transmitted via the first transceiver 21 and its connected first conductive path D0, and then via the second conductive path D1 of the logic chip 30 and its connected second transceiver 41 to the logic chip 30 for processing. The signals to be sent by the second memory chip 10B are transmitted via the first transceiver 21 and its connected first conductive path D0, and then via the first conductive path D0 of the logic chip 30 and its connected second transceiver 41 to the logic chip 30 for processing. The signals to be sent by the third memory chip 10C are transmitted via the first transceiver 21 and its connected first conductive path D0, and then via the fourth conductive path D3 of the logic chip 30 and its connected second transceiver 41 to the logic chip 30 for processing. The signals to be sent by the fourth memory chip 10D are transmitted via the first transceiver 21 and its connected first conductive path D0, and then via the third conductive path D2 of the logic chip 30 and its connected second transceiver 41 to the logic chip 30 for processing.

[0306] Thus, for the chip stack structure 50, based on the four-quadrant symmetrical channel signal region (conductive path group) of the chip and the specific stacking method between chips, from a physical perspective, the conductive vias are still in a direct-connect configuration. However, from the perspective of the absolute position of the conductive vias on the active surface, the conductive vias can also be regarded as a functional rotation configuration, that is, achieving a similar physical direct-connect configuration. Figure 2 The signal transmission effect in (b) (i.e., the rotational transmission effect of through hole D0-through hole D1-through hole D2-through hole D3...). Simply put, Figure 2The chip stacking structure in (b) requires a physical spiral structure, which necessarily includes lateral interconnects. However, the chip stacking structure 50 is physically a direct connection structure, which does not require lateral interconnects. This significantly reduces parasitic resistance and greatly improves transmission speed and performance. In addition, for the logic chip, the signal transmitted by the channel signal area 310 is generated (or sent to) the signal processing area 320 above it. The projections of the two along the second direction Y overlap, which optimizes the logic chip's traces and eliminates the need for cross-wiring, reducing the possibility of design errors. Furthermore, since the channel signal area 310 and the signal processing area 320 on both sides of the second axis BB' are symmetrical, the layout of the traces can be reused.

[0307] In some embodiments, for Figure 20 and Figure 21 For either memory chip 10 or logic chip 30, the following conditions must be met:

[0308] (1) Each conductive path group 20 / 40 can be used to transmit two different types of signals, for example Figure 20 One of the conductive path groups 20, designated by the central reference numeral, is used to transmit the CS signal and the WE signal;

[0309] (2) For the same channel signal area 110 / 310, two conductive paths symmetrical about the first axis AA' are used to transmit the same type of signal; for example Figure 20 In the middle, the upper conductive path transmits the CS_11 signal, and the lower symmetrical conductive path is used to transmit the CS_15 signal;

[0310] (3) For different channel signal regions, two conductive paths symmetrical about the second axis BB' are used to transmit the same type of signal; for example Figure 20 In the diagram, a conductive path on the left transmits the CS_11 signal, and a symmetrical conductive path on the right is used to transmit the CS_8 signal.

[0311] Thus, four conductive paths, symmetrical about the first axis AA' and about the second axis BB', are used to transmit the same type of signal.

[0312] (4) When the relative positions of the 2n conductive path groups 20 / 40 in the same channel signal area are the same, the conductive paths in the same position are used to transmit the same type of signal. For example Figure 20 The group of conductive paths is shown in the dashed box.

[0313] It should be understood that the same area contains a total of A channel signal areas. Assuming that the coordinates of the conductive path groups in each channel signal area are determined by taking the center of each channel signal area as the origin, then the conductive path groups with the same coordinates in the A channel signal areas (i.e., the A conductive path groups) are the aforementioned "A conductive path groups with the same relative position (in their respective channel signal areas)".

[0314] IV. The second stacking method for logic chips 30:

[0315] In this scenario, the logic chip 30 still adopts a face-down stacking method.

[0316] The channel signal area 110 of the (2A+1-i)th logic chip 30 is aligned with the channel signal area 110 of the i-th first memory chip 10A along the third direction Z, that is, the logic chip 30 and the fourth memory chip 10D are arranged in the same way.

[0317] At this time, the first data signal area PC0_Dword in the (2A+1-i)th channel signal area 310 of the logic chip 30 and the first data signal area PC0_Dword in the i-th channel signal area 110 of the first memory chip 10A are aligned along the third direction Z, and the second data signal area PC1_Dword in the (2A+1-i)th channel signal area 310 of the logic chip 30 and the second data signal area PC1_Dword in the i-th channel signal area 110 of the first memory chip 10A are aligned along the third direction Z.

[0318] The fourth, third, second, and first regions in the logic chip 30 and the first, second, third, and fourth regions in the first region are aligned one-to-one along the third direction Z and coupled sequentially to form a signal transmission channel.

[0319] The fourth conductive path D3, the third conductive path D2, the second conductive path D1 and the first conductive path D0 in the logic chip 30 and the first conductive path D0, the second conductive path D1, the third conductive path D2 and the fourth conductive path D3 in the first memory chip 10A are aligned along the third direction Z and coupled in sequence to form a signal transmission channel.

[0320] V. The third stacking method for logic chip 30:

[0321] In this scenario, the logic chips 30 are stacked face-up.

[0322] Please see Figure 18The i-th channel signal area 110 in the logic chip 30 and the i-th channel signal area 110 in the first memory chip 10A are aligned along the third direction Z, that is, the logic chip 30 and the first memory chip 10A are arranged in the same way.

[0323] At this time, the first data signal area PC0_Dword in the i-th channel signal area 310 of the logic chip 30 and the first data signal area PC0_Dword in the i-th channel signal area 110 of the first memory chip 10A are aligned along the third direction Z, and the second data signal area PC1_Dword in the i-th channel signal area 310 of the logic chip 30 and the second data signal area PC1_Dword in the i-th channel signal area 110 of the first memory chip 10A are aligned along the third direction Z.

[0324] The first, second, third, and fourth regions in the logic chip 30 and the first, second, third, and fourth regions in the first memory chip 10A are aligned one-to-one along the third direction Z and coupled sequentially to form a signal transmission channel.

[0325] The first conductive path D0, the second conductive path D1, the third conductive path D2 and the fourth conductive path D3 in the logic chip 30 and the first conductive path D0, the second conductive path D1, the third conductive path D2 and the fourth conductive path D3 in the first memory chip 10A are aligned along the third direction Z and coupled sequentially to form a signal transmission channel.

[0326] Similarly, the logic chip 30 can also be arranged in the same way as the third memory chip 10C, as can be understood by referring to the above.

[0327] Furthermore, different stacking methods of the memory chips and the stacking method of the logic chips 30 can be combined with each other, that is... Figure 18 The logic chips 30 in the chip stacking structure 50 can be adjusted to be stacked face down (corresponding to...). Figure 15 (Stacking scheme).

[0328] In another embodiment of this disclosure, a memory is also provided, including the aforementioned chip stack structure 50, which can follow transmission protocols such as DRAM and LPDRAM.

[0329] In another embodiment of this disclosure, an electronic device is provided, which includes the aforementioned memory. The electronic device may be a user equipment (UE), a mobile device, a handheld device, a computing device, an in-vehicle device, a wearable device, etc.

[0330] Examples include: personal computers (PCs), mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), enterprise digital assistants (EDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, server computers, data centers, workstations, mobile phones, smartphones, and tablets.

[0331] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0332] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0333] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0334] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0335] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0336] The features disclosed in the several method or circuit embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or circuit embodiments.

[0337] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory chip, characterized in that, The active surface of the memory chip has a first axis and a second axis, which intersect perpendicularly at the midpoint of the active surface; the memory chip includes 2A channels arranged sequentially along a first direction, each channel including one channel signal area, and the 2A channel signal areas are arranged sequentially along the first direction; the first axis extends along the first direction; Each of the aforementioned channel signal regions includes 2n conductive path groups, and the 2n conductive path groups in each of the aforementioned channel signal regions are symmetrical about the first axis; all conductive path groups in the 2A channel signal regions of the memory chip are symmetrical about the second axis as a whole; Each of the channels includes a first pseudo channel and a second pseudo channel, and each channel signal area includes a first data signal area and a second data signal area arranged along a first direction. The conductive path group in the first data signal area is used to transmit the data signal of the corresponding first pseudo channel, and the conductive path group in the second data signal area is used to transmit the data signal of the corresponding second pseudo channel. The first data signal area in the i-th channel signal area is symmetrical to the first data signal area in the (2A-i+1)-th channel signal area about the second axis, and the second data signal area in the i-th channel signal area is symmetrical to the second data signal area in the (2A-i+1)-th channel signal area about the second axis, A≥i≥1, and i, n, and A are all positive integers; Each of the channel signal regions further includes a control signal region, wherein the conductive path group in the control signal region is used to transmit the control signals of the corresponding first pseudo channel and the corresponding second pseudo channel.

2. The memory chip according to claim 1, characterized in that, In the same channel signal area: along the first direction, the control signal area is located between the first data signal area and the second data signal area.

3. The memory chip according to claim 1, characterized in that, Each of the channel signal regions further includes a fifth axis, which intersects the first axis perpendicularly at the center of the channel signal region; the 2n conductive path groups in the same channel signal region are symmetrical about the fifth axis and about the first axis.

4. The memory chip according to claim 1, characterized in that, Each of the conductive path groups has a third axis and a fourth axis, which are perpendicular to each other and intersect at the center of the conductive path group. The third axis is parallel to the first axis. Each conductive path group includes four conductive paths arranged in a 2×2 array. The four conductive paths are symmetrical about the third axis and about the fourth axis. The conductive paths penetrate the substrate of the memory chip along a third direction, which is perpendicular to the active surface.

5. The memory chip according to claim 4, characterized in that, Each of the conductive path groups includes a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path; in each of the conductive path groups, the first conductive path and the second conductive path are symmetrical about the third axis, the third conductive path and the fourth conductive path are symmetrical about the third axis, and the first conductive path and the fourth conductive path are symmetrical about the fourth axis.

6. The memory chip according to claim 5, characterized in that, The active surface is divided into a first region, a second region, a third region, and a fourth region by the first axis and the second axis; (1) The first conductive path located in the first region is symmetrical to the second conductive path located in the second region about the first axis, and the first conductive path located in the first region is also symmetrical to the fourth conductive path located in the fourth region about the second axis; The third conductive path located in the third region is symmetrical to the fourth conductive path located in the fourth region about the first axis, and the third conductive path located in the third region is also symmetrical to the second conductive path located in the second region about the second axis; (2) The second conductive path located in the first region is symmetrical to the first conductive path located in the second region about the first axis, and the second conductive path located in the first region is also symmetrical to the third conductive path located in the fourth region about the second axis; The fourth conductive path located in the third region is symmetrical to the third conductive path located in the fourth region about the first axis, and the fourth conductive path located in the third region is also symmetrical to the first conductive path located in the second region about the second axis; (3) The third conductive path located in the first region is symmetrical to the fourth conductive path located in the second region about the first axis, and the third conductive path located in the first region is also symmetrical to the second conductive path located in the fourth region about the second axis; The first conductive path located in the third region is symmetrical to the second conductive path located in the fourth region about the first axis, and the first conductive path located in the third region is also symmetrical to the fourth conductive path located in the fourth region about the second axis; (4) The fourth conductive path located in the first region is symmetrical to the third conductive path located in the second region about the first axis, and the fourth conductive path located in the first region is also symmetrical to the first conductive path located in the fourth region about the second axis; The second conductive path located in the third region is symmetrical to the first conductive path located in the fourth region about the first axis, and the second conductive path located in the third region is also symmetrical to the third conductive path located in the second region about the second axis.

7. The memory chip according to claim 5, characterized in that, Each channel further includes 2n first transceivers; each first transceiver is coupled to a first conductive path within the corresponding channel; The first transceiver is used to receive signals transmitted through the corresponding coupled first conductive path; Alternatively, a signal may be generated and transmitted outward via the corresponding coupled first conductive path.

8. The memory chip according to claim 6, characterized in that, Each of the conductive path groups is used to transmit two different types of signals; for the same channel signal region, two conductive paths symmetrical about the first axis are used to transmit the same type of signal; for different channel signal regions, two conductive paths symmetrical about the second axis are used to transmit the same type of signal.

9. The memory chip according to any one of claims 1-8, characterized in that, The conductive path includes conductive vias, which are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and backside via-last; different conductive paths in the same memory chip are electrically isolated.

10. A logic chip, characterized in that, The active surface of the logic chip has a first axis and a second axis, which intersect perpendicularly at the midpoint of the active surface; the logic chip includes 2A channel signal regions, which are arranged along a first direction; the first axis extends along the first direction; Each of the aforementioned channel signal regions includes 2n conductive path groups, and the 2n conductive path groups in each of the aforementioned channel signal regions are symmetrical about the first axis; all conductive path groups in the 2A channel signal regions of the logic chip are symmetrical about the second axis as a whole; The 2A channel signal areas of the logic chip correspond one-to-one with the 2A channels of the memory chip. Each channel signal area is divided into a first data signal area and a second data signal area arranged along a first direction. The conductive path group in the first data signal area is used to transmit the data signal of the first pseudo channel in the corresponding channel, and the conductive path group in the second data signal area is used to transmit the data signal of the second pseudo channel in the corresponding channel. The first data signal area in the i-th channel signal area is symmetrical to the first data signal area in the (2A-i+1)-th channel signal area about the second axis, and the second data signal area in the i-th channel signal area is symmetrical to the second data signal area in the (2A-i+1)-th channel signal area about the second axis, A≥i≥1, and i, n, and A are all positive integers; Each of the channel signal regions further includes a control signal region, wherein the conductive path group in the control signal region is used to transmit the control signals of the corresponding first pseudo channel and the corresponding second pseudo channel.

11. The logic chip according to claim 10, characterized in that, Each of the aforementioned channel signal areas also includes a control signal area; For the same channel signal area, along the first direction, the control signal area is located between the first data signal area and the second data signal area.

12. The logic chip according to claim 11, characterized in that, Each of the channel signal regions further includes a fifth axis, which intersects the first axis perpendicularly at the center of the channel signal region; the 2n conductive path groups in the same channel signal region are symmetrical about the fifth axis and about the first axis.

13. The logic chip according to claim 12, characterized in that, Each of the conductive path groups has a third axis and a fourth axis, which are perpendicular to each other and intersect at the center of the conductive path group. The third axis is parallel to the first axis. Each conductive path group includes four conductive paths arranged in a 2×2 array. The four conductive paths are symmetrical about the third axis and about the fourth axis. The conductive paths extend along a third direction, which is perpendicular to the active surface.

14. The logic chip according to claim 13, characterized in that, Each of the conductive path groups includes a first conductive path, a second conductive path, a third conductive path, and a fourth conductive path; in each of the conductive path groups, the first conductive path and the second conductive path are symmetrical about the third axis, the third conductive path and the fourth conductive path are symmetrical about the third axis, and the first conductive path and the fourth conductive path are symmetrical about the fourth axis.

15. The logic chip according to claim 14, characterized in that, The active surface is divided into a first region, a second region, a third region, and a fourth region by the first axis and the second axis; (1) The first conductive path located in the first region is symmetrical to the second conductive path located in the second region about the first axis, and the first conductive path located in the first region is also symmetrical to the fourth conductive path located in the fourth region about the second axis; The third conductive path located in the third region is symmetrical to the fourth conductive path located in the fourth region about the first axis, and the third conductive path located in the third region is also symmetrical to the second conductive path located in the second region about the second axis; (2) The second conductive path located in the first region is symmetrical to the first conductive path located in the second region about the first axis, and the second conductive path located in the first region is also symmetrical to the third conductive path located in the fourth region about the second axis; The fourth conductive path located in the third region is symmetrical to the third conductive path located in the fourth region about the first axis, and the fourth conductive path located in the third region is also symmetrical to the first conductive path located in the second region about the second axis; (3) The third conductive path located in the first region is symmetrical to the fourth conductive path located in the second region about the first axis, and the third conductive path located in the first region is also symmetrical to the second conductive path located in the fourth region about the second axis; The first conductive path located in the third region is symmetrical to the second conductive path located in the fourth region about the first axis, and the first conductive path located in the third region is also symmetrical to the fourth conductive path located in the fourth region about the second axis; (4) The fourth conductive path located in the first region is symmetrical to the third conductive path located in the second region about the first axis, and the fourth conductive path located in the first region is also symmetrical to the first conductive path located in the fourth region about the second axis; The second conductive path located in the third region is symmetrical to the first conductive path located in the fourth region about the first axis, and the second conductive path located in the third region is also symmetrical to the third conductive path located in the second region about the second axis.

16. The logic chip according to claim 14, characterized in that, Each channel further includes (2n×4) second transceivers; each second transceiver is coupled one-to-one with a conductive path in the corresponding channel. The second transceiver is used to receive signals transmitted through the corresponding connected conductive path; or to generate signals transmitted outward via the corresponding connected conductive path.

17. The logic chip according to claim 14, characterized in that, Each of the conductive path groups is used to transmit two different types of signals; for the same channel signal region, two conductive paths symmetrical about the first axis are used to transmit the same type of signal; for different channel signal regions, two conductive paths symmetrical about the second axis are used to transmit the same type of signal.

18. The logic chip according to any one of claims 10-17, characterized in that, The conductive path includes through-silicon vias (TSVs), which are fabricated using any one or more of the following processes: via-first, via-middle, via-last, and backside via-last. Different conductive paths within the same memory chip are electrically isolated.

19. A chip stacking structure, characterized in that, The chip stacking structure includes a logic chip as described in any one of claims 10-18 and at least one stacking unit, wherein the logic chip and at least one stacking unit are stacked sequentially along a third direction, and each stacking unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip stacked sequentially along a third direction, wherein the third direction is perpendicular to the active surface of each memory chip, and the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips as described in any one of claims 1-9; The logic chip and the first memory chip are stacked in a face-to-back or back-to-back manner. The first memory chip and the second memory chip are stacked face-to-face. The second and third memory chips are stacked back-to-back. The third and fourth memory chips are stacked face-to-face. The projections of the 2A first data signal regions of the logic chip and the 2A first data signal regions of each memory chip along a third direction overlap one-to-one; the projections of the 2A second data signal regions of the logic chip and the 2A second data signal regions of each memory chip along a third direction overlap one-to-one.

20. The chip stacking structure according to claim 19, characterized in that, The i-th channel signal area in the first memory chip, the (2A-i+1)-th channel signal area in the second memory chip, the (2A+1-i)-th channel signal area in the third memory chip, and the i-th channel signal area in the fourth memory chip are aligned along a third direction.

21. The chip stacking structure according to claim 19, characterized in that, The i-th channel signal area in the first memory chip, the i-th channel signal area in the second memory chip, the (2A+1-i)-th channel signal area in the third memory chip, and the (2A-i+1)-th channel signal area in the fourth memory chip are aligned along a third direction.

22. The chip stacking structure according to claim 20 or 21, characterized in that, When the logic chip and the first memory chip are stacked back to back, the i-th channel signal area in the logic chip is aligned with the i-th channel signal area in the first memory chip along a third direction; or, the i-th channel signal area in the logic chip is aligned with the (2A-i+1)-th channel signal area in the first memory chip along a third direction.

23. The chip stacking structure according to any one of claim 20 or 21, characterized in that, When the logic chip and the first memory chip are stacked face-to-back, the i-th channel signal area in the logic chip is aligned with the (2A-i+1)-th channel signal area in the first memory chip along a third direction; or, the i-th channel signal area in the logic chip is aligned with the i-th channel signal area in the first memory chip along a third direction.

24. The chip stacking structure according to any one of claims 19-21, characterized in that, For two chips connected face-to-face, the conductive paths aligned along a third direction are electrically connected using a hybrid bonding process; for two chips connected back-to-back or face-to-back, the conductive paths aligned along a third direction are electrically connected using a conductive bump bonding process; or... For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected face-to-back, the vias with the conductive paths aligned along a third direction are electrically connected using a hybrid bonding process; or, For two chips connected face-to-face, or for two chips connected back-to-back, or for two chips connected face-to-back, the vias of the conductive paths aligned along a third direction are electrically connected through a conductive bump bonding process.

25. A memory, characterized in that, Includes the chip stacking structure as described in any one of claims 19-24.

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