Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a base (10), sub-pixels (PX), and a plurality of data lines (DL). The base (10) comprises a display area (AA) and a first bezel area (C1). The plurality of data lines (DL) are located in the display area (AA) and extend from the display area (AA) to the first bezel area (C1). Any one of the data lines (DL) comprises a fan-out line (300) located in the first bezel area (C1). The resistance of the fan-out line (300) is set as R1, and preset resistance is set as R0, wherein R1≤R0, and 2.5 kΩ≤R0≤10 kΩ.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411732835.6, filed on November 28, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to display technology, and in particular to a display substrate and display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices, possessing advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Currently, display substrates exhibit a reddish tinge across the entire surface under heavy screen loads. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a display substrate, including:

[0006] The substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a first border area located on one side of the display area;

[0007] Multiple sub-pixels are located in the display area;

[0008] Multiple data lines are located in the display area and extend from the display area to the first border area. The multiple data lines are electrically connected to the multiple sub-pixels. Each of the multiple data lines includes a fan-out line located in the first border area. The resistance of the fan-out line is set to R1, and the preset resistance is set to R0, where R1≤R0 and 2.5kΩ≤R0≤10kΩ.

[0009] In some exemplary embodiments, the first border area includes a first fan-out area, and the fan-out line includes a first fan-out line located in the first fan-out area;

[0010] The first fan-out line includes a first connecting line and a second connecting line. One end of the first connecting line extends toward the display area, and the other end of the first connecting line is connected to the second connecting line. The cross-sectional area of ​​the first connecting line is larger than that of the second connecting line.

[0011] In some exemplary embodiments, the first fan-out area includes a first corner area and a second corner area, and the junction of the first connecting line and the second connecting line is located in one of the first corner area and the second corner area;

[0012] The line width of the first connecting line is greater than the line width of the second connecting line.

[0013] In some exemplary embodiments, the line width of the first connecting line is set to remain consistent along the extension direction of the first connecting line.

[0014] In some exemplary embodiments, the line width of the first connecting line is set to gradually decrease along the direction away from the display area.

[0015] In some exemplary embodiments, the first connecting line includes a plurality of sub-connecting lines arranged sequentially along the extension direction of the first connecting line, and the line width of the plurality of sub-connecting lines is configured to decrease sequentially from the end near the display area to the end connected to the second connecting line.

[0016] In some exemplary embodiments, the first fan-out line is configured as a broken line, both the first connecting line and the second connecting line extend along a straight line, and the included angle between the first connecting line and the second connecting line is set to α, where 100°≤α≤175°.

[0017] In some exemplary embodiments, the first fan-out line is provided with multiple lines, and the multiple first fan-out lines are arranged at intervals in a direction parallel to the base. The distance between the first connecting lines of adjacent first fan-out lines is a first distance, and the distance between the second connecting lines of adjacent first fan-out lines is a second distance. The first distance is greater than the second distance.

[0018] The line width of the first connecting line is equal to the line width of the second connecting line;

[0019] The first connecting line includes a first routing layer and a second routing layer stacked in a direction perpendicular to the substrate, and the second connecting line includes a third routing layer, which is configured to be arranged in the same layer as the first routing layer or the second routing layer.

[0020] In some exemplary embodiments, the first fan-out line is provided with multiple lines, and the multiple first fan-out lines are arranged at equal intervals in a direction parallel to the base.

[0021] The distance between the first connecting lines of adjacent first fan-out lines is the first distance, and the distance between the second connecting lines of adjacent first fan-out lines is the second distance. The first distance is equal to the second distance.

[0022] In some exemplary embodiments, the linewidth of the first fan-out line is set to be greater than 2 micrometers;

[0023] The linewidth of the first fan-out line is set to L0, where 2μm≤L0≤5μm.

[0024] In some exemplary embodiments, R1 ≤ 2.5kΩ.

[0025] In some exemplary embodiments, the display substrate further includes a plurality of parallel driving circuit traces located in the first bezel area. The plurality of driving circuit traces are configured to be electrically connected to a plurality of gate driving circuits. The plurality of driving circuit traces include AC signal lines and DC signal lines, and the line width of the DC signal lines is greater than the line width of the AC signal lines.

[0026] In some exemplary embodiments, the first border area includes a circuit trace area located on the side of the first fan-out area away from the display area;

[0027] The circuit trace area includes a first area and a second area, which are arranged sequentially along the circumference of the display area. The minimum distance between the edge of the first area near the display area and the edge away from the display area is set as a third distance, and the minimum distance between the edge of the second area near the display area and the edge away from the display area is set as a fourth distance. The third distance is less than the fourth distance.

[0028] At least one of the multiple drive circuit traces includes a first trace and a second trace, the first trace being located in the first region and the second trace being located in the second region, and the line width of the first trace being smaller than the line width of the second trace.

[0029] In some exemplary embodiments, the first border area further includes a second fan-out area, the second fan-out area being located on the side of the first fan-out area away from the display area;

[0030] The fan-out line also includes a second fan-out line located in the second fan-out area. There are multiple second fan-out lines, including a third line and a fourth line. The length of the third line is greater than the length of the fourth line, and the width of the third line is greater than the width of the fourth line.

[0031] In some exemplary embodiments, at least one of the second fan-out lines includes a fourth routing layer and a fifth routing layer stacked in a direction perpendicular to the substrate.

[0032] In some exemplary embodiments, the display substrate includes a plurality of first power lines and a first power pin, the plurality of first power lines being located in the display area and electrically connected to the plurality of sub-pixels, the first power pin being located in the first border area, and the plurality of first power lines being electrically connected to the first power pin;

[0033] At least one portion of the second fan-out line is located on the side of the first power pin near the edge of the display substrate, and the orthographic projection of at least one second fan-out line on the substrate overlaps with the orthographic projection of the first power pin on the substrate.

[0034] In some exemplary embodiments, the display substrate includes a second power line and a second power pin, the second power line being located in the peripheral area and at least partially surrounding the display area, the second power pin being located in the first frame area, and the second power line and the second power pin being connected.

[0035] At least one portion of the second fan-out line is located on the side of the second power pin away from the first power pin, and the orthographic projection of at least one second fan-out line on the substrate overlaps with the orthographic projections of the first power pin and the second power pin on the substrate.

[0036] In some exemplary embodiments, the system also includes a plurality of drive circuit traces located in the peripheral area, wherein at least a portion of the at least one second fan-out line is located between the second power supply pin and the plurality of drive circuit traces.

[0037] This application provides a display device including the display substrate described above.

[0038] The display substrate of this embodiment can reduce the impedance of the traces and reduce crosstalk, thereby solving the problem of reddish tinge on heavily loaded screens. The display substrate of this exemplary embodiment can reduce the space occupied by AC signal lines without reducing the number of DC signal lines, ensuring that the drive circuit traces are not burned, and also freeing up space for widening data lines. The display substrate of this exemplary embodiment can take advantage of the large free space in the second fan-out area to reduce the trace resistance in the second fan-out area, further reducing the impedance of the data lines.

[0039] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0040] Overview of the attached figures

[0041] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0042] Figure 1 is a schematic diagram of a display device;

[0043] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0044] Figure 3 is a schematic diagram of a display substrate according to an exemplary embodiment of the present invention;

[0045] Figure 4 is a magnified view of part A in Figure 3;

[0046] Figure 5 is a partial cross-sectional schematic diagram of aa in Figure 3;

[0047] Figure 6 is a magnified view of part C in Figure 4;

[0048] Figure 7 is a magnified view of part B in Figure 3;

[0049] Figure 8 is a magnified view of part D in Figure 6;

[0050] Figure 9 is a schematic diagram of a first sector outgoing line in this exemplary embodiment;

[0051] Figure 10 is a partial schematic diagram of a first border area in this exemplary embodiment;

[0052] Figure 11 is a partial schematic diagram of another first border area of ​​this exemplary embodiment;

[0053] Figure 12 is a partial schematic diagram of another first border region of this exemplary embodiment;

[0054] Figure 13 is a schematic diagram of the GG-direction section in Figure 12;

[0055] Figure 14 is a schematic diagram of the JJ-direction section in Figure 12;

[0056] Figure 15 is a partial schematic diagram of another first border area of ​​this exemplary embodiment;

[0057] Figure 16 is a partial schematic diagram of another first border area of ​​this exemplary embodiment;

[0058] Figure 17 is a magnified view of part E in Figure 6;

[0059] Figure 18 is a schematic diagram of the FF section in Figure 7;

[0060] Figure 19 is a schematic diagram of the HH-direction section in Figure 7;

[0061] Figure 20 is a schematic diagram of the KK-direction section in Figure 7.

[0062] Detailed Explanation

[0063] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0064] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0065] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0066] In some exemplary embodiments, a display substrate includes:

[0067] The substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a first border area located on one side of the display area;

[0068] Multiple sub-pixels are located in the display area;

[0069] Multiple data lines are located in the display area and extend from the display area to the first border area. The multiple data lines are electrically connected to the multiple sub-pixels. Each of the multiple data lines includes a fan-out line located in the first border area. The resistance of the fan-out line is set to R1, and the preset resistance is set to R0, where R1≤R0 and 2.5kΩ≤R0≤10kΩ.

[0070] In some exemplary embodiments, the first border area includes a first fan-out area, and the fan-out line includes a first fan-out line located in the first fan-out area;

[0071] The first fan-out line includes a first connecting line and a second connecting line. One end of the first connecting line extends toward the display area, and the other end of the first connecting line is connected to the second connecting line. The cross-sectional area of ​​the first connecting line is larger than that of the second connecting line.

[0072] In some exemplary embodiments, the first fan-out area includes a first corner area and a second corner area, and the junction of the first connecting line and the second connecting line is located in one of the first corner area and the second corner area;

[0073] The line width of the first connecting line is greater than the line width of the second connecting line.

[0074] In some exemplary embodiments, the line width of the first connecting line is set to gradually decrease along the direction away from the display area.

[0075] In some exemplary embodiments, the first fan-out line is configured as a broken line, both the first connecting line and the second connecting line extend along a straight line, and the included angle between the first connecting line and the second connecting line is set to α, where 100°≤α≤175°.

[0076] In some exemplary embodiments, the first fan-out line is provided with multiple lines, and the multiple first fan-out lines are arranged at intervals in a direction parallel to the base. The distance between the first connecting lines of adjacent first fan-out lines is a first distance, and the distance between the second connecting lines of adjacent first fan-out lines is a second distance. The first distance is greater than the second distance.

[0077] The line width of the first connecting line is equal to the line width of the second connecting line;

[0078] The first connecting line includes a first routing layer and a second routing layer stacked in a direction perpendicular to the substrate, and the second connecting line includes a third routing layer, which is configured to be arranged in the same layer as the first routing layer or the second routing layer.

[0079] In some exemplary embodiments, R1 ≤ 2.5kΩ.

[0080] In some exemplary embodiments, the display substrate further includes a plurality of parallel driving circuit traces located in the first bezel area. The plurality of driving circuit traces are configured to be electrically connected to a plurality of gate driving circuits. The plurality of driving circuit traces include AC signal lines and DC signal lines, and the line width of the DC signal lines is greater than the line width of the AC signal lines.

[0081] In some exemplary embodiments, the first border area includes a circuit trace area located on the side of the first fan-out area away from the display area;

[0082] The circuit trace area includes a first area and a second area, which are arranged sequentially along the circumference of the display area. The minimum distance between the edge of the first area near the display area and the edge away from the display area is set as a third distance, and the minimum distance between the edge of the second area near the display area and the edge away from the display area is set as a fourth distance. The third distance is less than the fourth distance.

[0083] At least one of the multiple drive circuit traces includes a first trace and a second trace, the first trace being located in the first region and the second trace being located in the second region, and the line width of the first trace being smaller than the line width of the second trace.

[0084] In some exemplary embodiments, the first border area further includes a second fan-out area, the second fan-out area being located on the side of the first fan-out area away from the display area;

[0085] The fan-out line also includes a second fan-out line located in the second fan-out area. There are multiple second fan-out lines, including a third line and a fourth line. The length of the third line is greater than the length of the fourth line, and the width of the third line is greater than the width of the fourth line.

[0086] In some exemplary embodiments, at least one of the second fan-out lines includes a fourth routing layer and a fifth routing layer stacked in a direction perpendicular to the substrate.

[0087] In some exemplary embodiments, the display substrate includes a plurality of first power lines and a first power pin, the plurality of first power lines being located in the display area and electrically connected to the plurality of sub-pixels, the first power pin being located in the first border area, and the plurality of first power lines being electrically connected to the first power pin;

[0088] At least one of the second fan-out lines is located on the side of the first power pin near the edge of the display substrate, and the orthographic projection of at least one of the second fan-out lines on the substrate overlaps with the orthographic projection of the first power pin on the substrate.

[0089] In some exemplary embodiments, the display substrate includes a second power line and a second power pin, the second power line being located in the peripheral area and at least partially surrounding the display area, the second power pin being located in the first frame area, and the second power line and the second power pin being connected.

[0090] At least one portion of the second fan-out line is located on the side of the second power pin away from the first power pin, and the orthographic projection of at least one second fan-out line on the substrate overlaps with the orthographic projections of the first power pin and the second power pin on the substrate.

[0091] In some exemplary embodiments, the system also includes a plurality of drive circuit traces located in the peripheral area, wherein at least a portion of the at least one second fan-out line is located between the second power supply pin and the plurality of drive circuit traces.

[0092] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn in unit rows, where n can be a natural number. The scan driver can receive clock signals, scan start signals, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The LED driver can receive clock signals, transmit stop signals, etc., from the timing controller to generate transmit signals to LED signal lines E1, E2, E3, ..., Eo. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0093] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0094] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0095] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0096] Figure 3 is a schematic diagram of a display substrate according to this exemplary embodiment. Figure 4 is a partially enlarged schematic diagram of point A in Figure 3. Figure 5 is a partially cross-sectional schematic diagram of line aa in Figure 3. Figure 6 is a partially enlarged schematic diagram of point C in Figure 4. Figure 5 illustrates the structure of a sub-pixel in the display area as an example. Figure 5 also illustrates the pixel circuit of each sub-pixel, which includes a transistor 21 and a capacitor 22 as an example. The transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor.

[0097] In some exemplary embodiments, as shown in FIG5, the display area of ​​the display substrate may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least: pixel circuits of multiple sub-pixels, and the pixel circuit of each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements of multiple sub-pixels. In other examples, a touch structure layer may be disposed on the side of the encapsulation structure layer away from the substrate 10 to integrate touch functionality.

[0098] In some exemplary embodiments, as shown in FIG5, the circuit structure layer 12 of the display area may include: a shielding layer 200 disposed on the substrate 10, a semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source / drain metal layer) and a fourth conductive layer (also referred to as a second source / drain metal layer). A first insulating layer (also called a buffer layer) 101 may be disposed between the shielding layer 200 and the semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be disposed between the semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be disposed between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be disposed between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first planarization layer) 106 may be disposed between the third conductive layer and the fourth conductive layer, wherein the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 10; and a seventh insulating layer (also called a second planarization layer) 107 may be disposed on the side of the fourth conductive layer away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be inorganic insulating layers, while the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers. However, this embodiment is not limited to these limitations. In other examples, the fifth insulating layer may be omitted between the third and fourth conductive layers, and only the sixth insulating layer may be provided between the third and fourth conductive layers.

[0099] In some exemplary embodiments, as shown in FIG5, the semiconductor layer of the display area may include: an active layer 210 of the transistor 21 of the pixel circuit. The active layer 210 of the transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first conductive layer may include: a first gate 213 of the transistor 21 and a first electrode 221 of the capacitor 22. The orthographic projection of the first gate 213 of the transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 10. The second conductive layer may include: a second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 10 may at least partially overlap, for example, they may coincide.

[0100] In some exemplary embodiments, as shown in FIG5, the third conductive layer of the display area may include a first source 211 and a first drain 212 of transistor 21. The first source 211 of transistor 21 may be electrically connected to the first region 2101 of active layer 210, and the first drain 212 may be electrically connected to the second region 2102 of first active layer 210. The fourth conductive layer may include at least a first anode transition electrode 241. The first anode transition electrode 241 may be electrically connected to the first drain 212 of transistor 21 of pixel circuit through vias formed in fifth insulating layer 105 and sixth insulating layer 106. In this example, the electrical connection between pixel circuit and light-emitting element can be achieved through the first anode transition electrode 241.

[0101] In some exemplary embodiments, as shown in FIG5, the light-emitting structure layer 13 may include a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode, and the first electrode 131 may be disposed on a seventh insulating layer 107 and electrically connected to a first anode transfer electrode 241 through a via formed in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may have a plurality of pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0102] In some exemplary embodiments, the organic light-emitting layer 132 of the light-emitting element may include at least one emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be utilized to emit light at the required grayscale.

[0103] In some exemplary embodiments, the light-emitting layers of light-emitting elements of different colors can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer located on one side of the light-emitting layer can be common layers, and the electron injection layer and electron transport layer located on the other side of the light-emitting layer can be common layers. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0104] In some exemplary embodiments, as shown in FIG5, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0105] In some exemplary embodiments, as shown in Figures 3 to 6, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. In some exemplary embodiments, the display area AA may include a plurality of sub-pixels PX arranged in a matrix, and the sub-pixels PX may include pixel driving circuits and light-emitting devices. The peripheral area BB may have isolation dams (Dam1 and Dam2), a gate driver on array (GOA) circuit, and power lines for transmitting voltage signals to the plurality of sub-pixels PX. The isolation dams of the peripheral area BB form a ring structure surrounding the display area AA. For example, the peripheral area BB may include: a first border area C1 located on one side of the display area AA in a first direction, a second border area C2 located on the other side of the first direction, a third border area C3 located on one side of the display area AA in a second direction, and a fourth border area C4 located on the other side of the second direction. Both the first and second directions are parallel to the substrate 10, and the first direction is perpendicular to the second direction. The first border area C1 can be the lower border of the display substrate, the second border area C2 can be the upper border of the display substrate, the third border area C3 can be the left border of the display substrate, and the fourth border area C4 can be the right border of the display substrate.

[0106] In some exemplary embodiments, as shown in Figures 3 to 6, the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The gate lines GL may extend along a second direction, and the data lines DL may extend along a first direction. The orthographic projections of the gate lines GL and the data lines DL onto the substrate intersect to form a plurality of sub-pixel regions, each sub-pixel region containing one sub-pixel PX. The data lines DL are electrically connected to the plurality of sub-pixels PX, for example, one data line DL is electrically connected to a row of sub-pixels PX. The data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The data lines DL may extend to a bonding area. The gate lines GL are electrically connected to the plurality of sub-pixels PX, for example, one gate line GL is electrically connected to a row of sub-pixels PX. The gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals.

[0107] In some exemplary embodiments, as shown in Figures 3 to 6, the first frame area C1 includes a first fan-out area B11, a bending area B12, a second fan-out area B13, a first circuit area B14, a third fan-out area B15, a chip bonding area B16, and a circuit board bonding area B17, arranged sequentially along a direction away from the display area AA. The first fan-out area B11 can be connected to the display area AA, and multiple data lines DL of the display area AA can extend to the first fan-out area B11 in a fan-out routing manner. The first power bus of the first fan-out area B11 can be configured to connect to the first power line (VDD) of the display area AA, and the second power line (VSS) can be located in the peripheral area BB. The first power line (VDD) is a high-level power line or a positive-level power line, and the second power line (VSS) is a low-level power line or a negative-level power line. The bending area B12 connects between the first fan-out area B11 and the second fan-out area B13, and can be configured to bend to the back of the display area AA. Multiple data lines DL of the display area AA can extend to the first circuit area B14 via the second fan-out area B13. The first circuit area B14 may include at least one first circuit group, which may include multiple test circuits configured to be electrically connected to the multiple data lines DL and provide test data signals to the multiple data lines DL of the display area AA during the testing phase. The first circuit group may also include an electrostatic discharge circuit. The chip bonding area B16 may include at least one driver chip area, each driver chip area may include multiple conductive bumps (also called contact pads), which may be configured to bond to at least one driver chip (IC, Integrated Circuit). The driver chip may be configured to generate drive signals required to drive sub-pixels, such as data drive signals. The data drive signals are provided to multiple sub-pixels PX of the display area via the multiple data lines DL. The circuit board bonding area B17 may include at least one bonding pin area, each bonding pin area may include multiple bonding pins, which may be configured to bond to at least one corresponding circuit board, such as a flexible printed circuit board (FPC).

[0108] As shown in Figure 3, the gate drive circuit of the display panel includes multiple shift register units GOA0, GOA1, ... and GOAn. Multiple gate drive signal lines (i.e., drive circuit traces 600) GSTV, GCK, and GCB are electrically connected to the gate drive circuit. Each GOA unit is electrically connected to a gate line GL. The multiple gate drive signal lines GSTV, GCK, and GCB extend to the chip bonding area B16 and are connected to the pads corresponding to the chip bonding area B16.

[0109] The applicant discovered that the display substrate exhibited a reddish tinge across the entire surface under heavy screen loads, and this problem could not be resolved through timing adjustments. Currently, the combined resistance of the data lines in the first and second fan-out zones is typically no less than 5KΩ. Through multiple experiments, the applicant found that reducing the resistance of the data lines effectively alleviated the reddish tinge, and the lower the resistance of the data lines, the less noticeable the reddish tinge became under heavy screen loads. Therefore, it can be confirmed that excessive resistance of the data lines is the main cause of the reddish tinge under heavy screen loads.

[0110] The technical solutions of the embodiments of the present invention will be described in detail below through specific examples.

[0111] In some exemplary embodiments, a display substrate, as shown in Figures 3 to 6, may include a substrate 10, sub-pixels PX, and multiple data lines DL. The substrate 10 may include a display area AA and a peripheral area surrounding the display area AA. The peripheral area includes a first border area C1 located on one side of the display area AA. The multiple data lines DL are located in the display area AA and extend from the display area AA to the first border area C1. At least one of the multiple data lines DL includes a fan-out line 300 located in the first border area C1. The resistance of the fan-out line 300 is set to R1, and a preset resistance is set to R0, where R1 ≤ R0, and 2.5kΩ ≤ R0 ≤ 10kΩ. Thus, the display substrate of this embodiment can reduce the impedance of the traces and reduce crosstalk, thereby solving the problem of reddish tinge on heavy-load screens.

[0112] Figure 7 is a partially enlarged schematic diagram of point B in Figure 3. In some exemplary embodiments, as shown in Figures 3 to 7, the fan-out line 300 leading from the display area AA may include a first fan-out line 301 located in the first fan-out area B11 and a second fan-out line 302 located in the second fan-out area B13. The end of the first fan-out line 301 away from the display area AA may be electrically connected to one end of the second fan-out line 302. In some exemplary embodiments, the sum of the resistances of the first fan-out line 301 and the second fan-out line 302 may be R1, and R1 may be less than or equal to 2.5kΩ. In this example, the value of R1 may be 1.5kΩ, but it is not limited to this. For example, R1 = 1kΩ, or R1 = 2kΩ, or R1 = 2.3kΩ.

[0113] In some exemplary embodiments, as shown in Figures 3 to 6, the first frame area C1 further includes a circuit trace area B18 on which drive circuit traces are arranged, and a partition area B19. The circuit trace area B18 is located on the side of the first fan-out area B11 away from the display area AA, and the partition area B19 is located on the side of the circuit trace area B18 away from the display area AA. The edge of the partition area B19 away from the circuit trace area B18 is the position of the cutting channel. The distance between the edge of the first fan-out area B11 near the display area and the edge of the circuit routing area B18 can be a first width M1. The distance between the edge of the circuit routing area B18 near the first fan-out area B11 and the edge of the partition area B19 can be a second width M2. The distance between the edge of the partition area B19 near the first fan-out area B11 and the edge away from the first fan-out area B11 can be a third width M3. Wherein, M1:M2:M3=5:(3~3.5):(1.5~2), which can satisfy the requirement that the first fan-out area B11 has sufficient width to arrange the widened first fan-out line 301 and also meet the wiring requirements of the drive circuit, ensuring that there will be no reliability issues from the boundary to the drive circuit routing.

[0114] In some exemplary embodiments, as shown in Figures 3 to 6, the peripheral area BB surrounds the display area AA. The area of ​​the first border area C1 corresponding to the corner position of the display area AA can form a first corner area B20 and a second corner area B21. The first corner area B20 and the second corner area B21 are symmetrically arranged in the second direction. The minimum distance between the edge of the first corner area B20 and the edge of the second corner area B21 near the display area AA and the edge of the first corner area B21 away from the display area AA can be set to be smaller than the minimum distance between the edges of other areas of the first border area C1 near the display area AA and the edges of other areas of the first border area C1, so that the width of the first corner area B20 and the second corner area B21 is relatively narrower than other areas of the first border area C1.

[0115] In some exemplary embodiments, as shown in Figures 3 to 6, multiple first fan-out lines 301 may be provided, and these multiple first fan-out lines 301 may be arranged at equal intervals parallel to the substrate direction. The linewidth of each first fan-out line 301 may be the dimension of the first fan-out line 301 in the direction parallel to the substrate 10 and perpendicular to the extension direction of the first fan-out line 301. Similarly, the linewidth of other traces may be the dimension of the trace in the direction parallel to the substrate 10 and perpendicular to the extension direction of the trace. The linewidth of the first fan-out line 301 may be greater than 2 micrometers, which increases the linewidth of the data line DL and reduces the resistance of the first fan-out line 301 while keeping the thickness unchanged. In some exemplary embodiments, the linewidth of the first fan-out line 301 is L0, where 2μm≤L0≤5μm. In this example, L0=2.3μm, but it is not limited to this. For example, L0=3μm, L0=3.3μm, L0=2.5μm, or L0=2.8μm.

[0116] In some exemplary embodiments, as shown in Figures 3 to 6, the first fan-out line 301 may include a first connecting line 301' and a second connecting line 301". The first connecting line 301' and the second connecting line 301" may be an integral piece, and the first connecting line 301' and the second connecting line 301" may be manufactured in a single patterning process. One end of the first connecting line 301' extends toward the display area AA, and the other end connects to the second connecting line 301". The junction of the first connecting line 301' and the second connecting line 301" is located in the first corner area B20 or the second corner area B21. The cross-sectional area of ​​the first connecting line 301' is larger than the cross-sectional area of ​​the second connecting line 301".

[0117] Figure 8 is a partially enlarged schematic diagram of point D in Figure 6. In some exemplary embodiments, as shown in Figures 3, 4, 5, 6, and 8, the linewidth of the first connecting line 301' can be greater than the linewidth of the second connecting line 301" (i.e., L1 > L2). The linewidth (L1) of the first connecting line 301' can be kept consistent along the extension direction of the first connecting line 301', so that the width of the first fan-out line 301 changes abruptly at the junction of the first connecting line 301' and the second connecting line 301" (i.e., L1 > L2). In this example, L1 = 3.3 μm and L2 = 2.3 μm, which reduces the resistance of a single first fan-out line 301 by about 40%, but is not limited to this. For example, L1 = 2.8 μm and L2 = 2.3 μm; or L1 = 2.5 μm and L2 = 2.3 μm; or L1 = 3 μm and L2 = 2.5 μm.

[0118] In some exemplary embodiments, as shown in Figures 3, 4, 5, 6, and 8, the edges at the junction of the first connecting line 301' and the second connecting line 301" are stepped. For example, the edge of the first fan-out line 301 on one side of the line width direction is the first edge 303. The orthographic projection of the first edge 303 on the substrate at the junction of the first connecting line 301' and the second connecting line 301" can extend as an auxiliary line T1 to form a stepped shape. The auxiliary line T1 can be a zigzag line. The first fan-out line 301 in the line width direction can be perpendicular to the extension direction of the first fan-out line 301 and parallel to the substrate.

[0119] In some exemplary embodiments, as shown in Figures 3, 4, 5, 6 and 8, the minimum distance between the edges of the first connecting lines 301' of adjacent first fan-out lines 301 is a first distance S', and the distance between the edges of the first connecting lines 301' of adjacent first fan-out lines 301 remains unchanged along the extension direction of the first fan-out lines 301, that is, the distance between the edges of the first connecting lines 301' of adjacent first fan-out lines 301 is the first distance S' along the extension direction of the first fan-out lines 301. The minimum distance between the edges of the second connecting lines 301” of adjacent first fan-out lines 301 is the second distance S”. The distance between the edges of adjacent second connecting lines 301” remains unchanged along the extension direction of the first fan-out line 301, that is, the distance between the edges of adjacent second connecting lines 301” is the second distance S” along the extension direction of the first fan-out line 301. In some exemplary embodiments, the spacing between the center points of the multiple first fan-out lines 301 is equal, so that the spacing between the center points of adjacent first fan-out lines 301 remains unchanged. The line width of the first connecting line 301’ is greater than the line width of the second connecting line 301”, so that the first distance S’ is less than the second distance S”.

[0120] Figure 9 is a schematic diagram of a first fan-out line of this exemplary embodiment. In some exemplary embodiments, as shown in Figures 3, 4, 5, 6 and 9, the second connecting line 301” of adjacent first fan-out lines 301 converges at the end away from the first connecting line 301'. The minimum distance between the edges of the first connecting lines 301' of adjacent first fan-out lines 301 is the first distance S', and the minimum distance between the edges of the second connecting lines 301” of adjacent first fan-out lines 301 is the second distance S”. The first distance S' is equal to the second distance S”.

[0121] Figure 10 is a partial schematic diagram of a first border area of ​​this exemplary embodiment. In some exemplary embodiments, as shown in Figures 3, 4, 5, 6 and 10, the line width of the first connecting line 301' may gradually decrease along the direction away from the display area AA. In some exemplary embodiments, the first connecting line 301' includes a plurality of sub-connecting lines 400 arranged sequentially along the extension direction of the first connecting line 301'. The linewidth of the plurality of sub-connecting lines 400 may decrease sequentially from the end near the display area AA to the end connecting to the second connecting line 301'". The number of sub-connecting lines 400 may be N, where N > 2. The difference between the linewidths of adjacent sub-connecting lines 400 may be a fixed value, so that the linewidth of the first connecting line 301' gradually changes along the extension direction, which is beneficial to the smooth design of the first fan-out line 301. In this exemplary embodiment, the plurality of sub-connecting lines 400 may include a first sub-connecting line 401, a second sub-connecting line 402, a third sub-connecting line 403, and a fourth sub-connecting line 404. The first sub-connecting line 401, the second sub-connecting line 402, the third sub-connecting line 403, and the fourth sub-connecting line 404 may be arranged sequentially in a direction away from the second connecting line 301'. One end of the first sub-connector 401 is connected to the second connecting line 301", and the other end is connected to the second sub-connector 402. The linewidth of the first sub-connector 401 is L3, the linewidth of the second sub-connector 402 is L4, the linewidth of the third sub-connector 403 is L5, and the linewidth of the fourth sub-connector 404 is L6, where L6 > L5 > L4 > L3. In this example, L3 = 2.6 μm, L4 = 2.7 μm, and L5 = 2.8 μm. μm, L6 = 2.9μm, the line width difference between adjacent sub-connecting lines 400 is 0.1μm, but not limited to this, for example, the line width difference between adjacent sub-connecting lines 400 can be a fixed value and is 0.2μm, 0.05μm or 0.5μm, etc., or for example, the line width difference between adjacent sub-connecting lines 400 can be a non-fixed value, L3 = 2.6μm, L4 = 2.7μm, L5 = 2.9μm, L6 = 3.3μm.

[0122] Figure 11 is a partial schematic diagram of another first border area of ​​this exemplary embodiment. In some exemplary embodiments, as shown in Figure 11, among the multiple first fan-out lines 301, the first connecting lines 301' of some first fan-out lines 301 may have a constant line width, while the first connecting lines 301' of other first fan-out lines 301 may have a structure with gradually changing line width, that is, including multiple sub-connecting lines 400 with different line widths.

[0123] Figure 12 is a partial schematic diagram of another first border area of ​​this exemplary embodiment, Figure 13 is a cross-sectional schematic diagram of the GG direction in Figure 12, and Figure 14 is a cross-sectional schematic diagram of the JJ direction in Figure 12. In some exemplary embodiments, as shown in Figures 12 to 14, the distance between adjacent first fan-out lines 301 gradually expands from the end of the first connecting line 301' connecting the second connecting line 301" to the end away from the second connecting line 301", so that the distance between adjacent first connecting lines 301' is greater than the distance between adjacent second connecting lines 301". That is, the minimum distance between the edges of the first connecting lines 301' of adjacent first fan-out lines 301 is the first distance S', and the minimum distance between the edges of the second connecting lines 301" of adjacent first fan-out lines 301 is the second distance S'. The first distance S' is greater than the second distance S. In some exemplary embodiments, the line width of the first connecting line 301' may be L1, and the line width of the second connecting line 301" may be L2, wherein L1 = L2, that is, the line width of the first connecting line 301' is equal to the line width of the second connecting line 301".

[0124] In some exemplary embodiments, as shown in Figures 12 to 14, the first connection line 301' includes a first trace layer 501 and a second trace layer 502 stacked in a direction perpendicular to the substrate (third direction). The first trace layer 501 may be located on the side of the second trace layer 502 closest to the substrate 10. The materials of the first trace layer 501 and the second trace layer 502 may be the same or different. The first trace layer 501 may be a first gate metal layer, and the second trace layer 502 may be a second gate metal layer. The first connection line 301' forms a double-layer structure, which increases the thickness of the first connection line 301' and can also reduce the resistance of the first fan-out line 301. The third direction is perpendicular to the aforementioned first and second directions. The second connection line 301" may include a third trace layer 503. The third trace layer 503 may be arranged in the same layer as the first trace layer 501 or the second trace layer 502. The second connection line 301" may be a single-layer structure. With the first connecting line 301' and the second connecting line 301" having the same line width, the thickness of the first connecting line 301' is greater than the thickness of the second connecting line 301" (the thickness of both refers to the dimension in the third direction), so that the cross-sectional area of ​​the first connecting line 301' is greater than the cross-sectional area of ​​the second connecting line 301".

[0125] Figure 15 is a partial schematic diagram of another first fan-out area according to this exemplary embodiment. In some exemplary embodiments, as shown in Figure 15, the first fan-out line 301 may be a broken line. The first fan-out line 301 may include a first connecting line 301' and a second connecting line 301"". The first connecting line 301' and the second connecting line 301" are set at an angle. Both the first connecting line 301' and the second connecting line 301" extend along a straight line. The angle between the first connecting line 301' and the second connecting line 301" is α, where the value of α can be from 100° to 175°. In this example, α = 150°, but it is not limited to this. For example, α = 130°, α = 160°, or α = 170°. The line width of the first connecting line 301' may be greater than the line width of the second connecting line 301" (i.e., L1 > L2), so that the line width of the first fan-out line 301 changes abruptly at the junction of the first connecting line 301' and the second connecting line 301". In some exemplary embodiments, the spacing between the centers of the multiple first fan-out lines 301 is equal, such that the spacing between the centers of adjacent first fan-out lines 301 remains unchanged, and the line width of the first connecting line 301' is greater than the line width of the second connecting line 301", such that the first distance S' is less than the second distance S".

[0126] Figure 16 is a partial schematic diagram of another first fan-out region according to this exemplary embodiment. In some exemplary embodiments, as shown in Figure 16, the first fan-out line 301 may be a broken line. The first fan-out line 301 may include a first connecting line 301' and a second connecting line 301", which are angled together. The line width of the first connecting line 301' may be greater than the line width of the second connecting line 301", i.e., L1 > L2. The line width of the first fan-out line 301 at the junction of the first connecting line 301' and the second connecting line 301" increases linearly in the direction away from the second connecting line 301". The first fan-out line 301 is trumpet-shaped at the junction of the first connecting line 301' and the second connecting line 301", so that the line shape of the first fan-out line 301 can smoothly transition at the junction of the first connecting line 301' and the second connecting line 301".

[0127] Figure 17 is a partially enlarged schematic diagram of point E in Figure 6. In some exemplary embodiments, as shown in Figures 3, 6, and 17, the display substrate may include multiple driving circuit traces 600. The multiple driving circuit traces 600 may be located in the circuit trace area B18, and the multiple driving circuit traces 600 are arranged in parallel and spaced apart. The multiple driving circuit traces 600 may include AC signal lines 602 and DC signal lines 601. The line width of DC signal line 601 may be L7, and the line width of AC signal line 602 may be L8. The line width of DC signal line 601 is greater than the line width of AC signal line 602, that is, L7 > L8. AC signal line 602 can be a clock signal (CK), a start vertical (STV) signal, or a multiplexer (Mux) signal. AC signal line 602 has a lower risk of being burned, so its width can be appropriately reduced, compressing the area of ​​the circuit trace B18 and providing more space for widening the data line DL. DC signal line 601 requires a wider width to prevent the burning phenomenon from worsening.

[0128] In some exemplary embodiments, as shown in Figures 3, 6 and 17, the circuit trace area B18 includes a first region B18' and a second region B18'". The first region B18' and the second region B18' are arranged sequentially along the circumference of the display area AA. The circumference of the display area AA can be the direction of extension of the outer edge of the display area AA (i.e., the direction surrounding the display area AA). The edge of the circuit trace area B18 close to the display area AA is the second edge 605, and the edge of the circuit trace area B18 away from the display area AA is the third edge 606. The minimum distance between the edge of the first region B18' closest to the display area AA and the edge of the second region B18' furthest from the display area AA can be a third distance L13, that is, the minimum distance between the second edge 605 and the third edge 606 in the first region B18' is the third distance L13; the minimum distance between the edge of the second region B18" closest to the display area AA and the edge of the second region B18" furthest from the display area AA can be a fourth distance L14, that is, the minimum distance between the second edge 605 and the third edge 606 in the second region B18" is the fourth distance L14; wherein, the third distance L13 is smaller than the fourth distance L14, making the width of the first region B18' narrower than that of the second region B18". At least one drive circuit trace 600 includes a first trace 603 and a second trace 604, one end of the first trace 603 is connected to the second trace 604, the first trace 603 is located in the first region B18', and the second trace 604 is located in the second region B18". In some exemplary embodiments, the line width of the first trace 603 may be L9, and the line width of the second trace 604 may be L10. The line width of the first trace 603 is smaller than the line width of the second trace 604, i.e., L9 < L10, so that the wider second region B18” is arranged with the second trace 604 with a larger line width, thereby reducing the resistance of the drive circuit trace 600 and alleviating the phenomenon of redness on heavy load screens.

[0129] Figure 18 is a schematic cross-sectional view of the FF direction in Figure 7, Figure 19 is a schematic cross-sectional view of the HH direction in Figure 7, and Figure 20 is a schematic cross-sectional view of the KK direction in Figure 7. In some exemplary embodiments, as shown in Figures 3, 7, 18, 19, and 20, multiple second fan-out lines 302 are provided. These multiple second fan-out lines 302 include a third routing line 302' and a fourth routing line 302'. Both the third routing line 302' and the fourth routing line 302' extend from the bending area B12 toward the first circuit area B14. The bending area B12 has multiple routing groups 700, and each routing group 700 may include multiple routing lines. These routing lines can be straight, zigzag, twisted, curved, etc. One end of the second fan-out line 302 can be connected to the routing group 700 of the bending area B12. The routing distance of the third trace 302' is greater than that of the other second fan-out traces 302, meaning the length of the third trace 302' in its extension direction is greater than the length of the fourth trace 302" in its extension direction. Furthermore, the linewidth of the third trace 302' can be L11, and the linewidth of the fourth trace 302" can be L12, where the linewidth of the third trace 302' is greater than that of the fourth trace 302" (L11 > L12), thus reducing the resistance of the second fan-out traces 302. In this example, the display substrate can utilize the large free space in the second fan-out area B13 to widen the linewidth of the second fan-out traces 302, reducing the routing resistance in the second fan-out area B13 and further reducing the impedance of the data line DL.

[0130] In some exemplary embodiments, as shown in Figures 3, 7, 18, 19, and 20, at least one second fan-out line 302 may be a two-layer structure stacked in a direction perpendicular to the substrate 10 (i.e., a third direction). Increasing the thickness of the second fan-out line 302 may reduce its resistance. In this example, a portion of the routing of the second fan-out line 302 may include a fourth routing layer 504 and a fifth routing layer 505 stacked in a third direction. The materials of the fourth routing layer 504 and the fifth routing layer 505 may be the same or different. The fourth routing layer 504 may be co-located with the first routing layer 501 described above, and the fifth routing layer 505 may be co-located with the second routing layer 502 described above.

[0131] In some exemplary embodiments, as shown in Figures 3 and 7, the display substrate may include multiple first power lines F1 and a first power pin J1. The multiple first power lines F1 may be located in the display area AA and electrically connected to multiple sub-pixels PX. The first power pin J1 may be located in the first border area C1. One end of the first power pin J1 is electrically connected to the wiring group 700 of the bending area B12 and is led up through the wiring group 700. The other end of the first power pin J1 is arranged in the circuit board bonding area B17. The multiple first power lines F1 may be electrically connected to the first power pin J1. At least one second fan-out line 302 is located on the side of the first power pin J1 near the edge of the display substrate, and the orthographic projection of the at least one second fan-out line 302 on the substrate 10 overlaps with the orthographic projection of the first power pin J1 on the substrate 10. In this example, portions of the multiple third traces 302' may be located on the side of the first power pin J1 near the edge of the display substrate (fourth edge 800). Each third trace 302' includes a first segment 304, which may be located on the side of the first power pin J1 near the edge of the display substrate (fourth edge 800). The orthographic projection of at least one third trace 302' onto the substrate 10 overlaps with the orthographic projection of the first power pin J1 onto the substrate 10.

[0132] In some exemplary embodiments, as shown in Figures 3 and 7, the display substrate may include a second power line F2 and a second power pin J2. The second power line F2 may be located in the peripheral area and at least partially surround the display area AA. The second power pin J2 is located in the first frame area C1. One end of the second power pin J2 is electrically connected to the trace group 700 of the bending area B12 and is led up through the trace group 700. The other end of the second power pin J2 is arranged in the circuit board bonding area B17. The second power line F2 may be electrically connected to the second power pin J2. At least one second fan-out line 302 is located on the side of the second power pin J2 away from the first power pin J1, and the orthographic projection of the at least one second fan-out line 302 on the substrate 10 overlaps with the orthographic projections of the first power pin J1 and the second power pin J2 on the substrate 10. In this example, a portion of the third trace 302' is located on the side of the second power pin J2 away from the first power pin J1, and the orthographic projection of the third trace 302' onto the substrate 10 overlaps with the orthographic projections of both the first power pin J1 and the second power pin J2 onto the substrate 10. The third trace 302' includes a first segment 304, which is located on the side of the second power pin J2 away from the first power pin J1.

[0133] In some exemplary embodiments, as shown in Figures 3 and 7, at least a portion of a segment of at least one second fan-out line 302 is located between the second power supply pin J2 and multiple drive circuit traces 600. In this example, a first segment of the second fan-out line 302 is located between the second power supply pin J2 and multiple drive circuit traces 600, which may be multiple gate drive signal lines (GSTV, GCK, GCB, etc.).

[0134] In some exemplary embodiments, a display device includes the aforementioned display substrate. The display device provided in this disclosure can be applied to electronic devices, which can be mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, in-vehicle displays, or any product or component with display functionality, such as wearable devices, smartwatches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc.

[0135] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0136] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0137] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0138] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0139] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0140] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0141] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, wherein, include: The substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a first border area located on one side of the display area; Multiple sub-pixels are located in the display area; Multiple data lines are located in the display area and extend from the display area to the first border area. The multiple data lines are electrically connected to the multiple sub-pixels. Each of the multiple data lines includes a fan-out line located in the first border area. The resistance of the fan-out line is set to R1, and the preset resistance is set to R0, where R1≤R0 and 2.5kΩ≤R0≤10kΩ.

2. The display substrate according to claim 1, wherein, The first border area includes a first fan-out area, and the fan-out line includes a first fan-out line located in the first fan-out area; The first fan-out line includes a first connecting line and a second connecting line. One end of the first connecting line extends toward the display area, and the other end of the first connecting line is connected to the second connecting line. The cross-sectional area of ​​the first connecting line is larger than that of the second connecting line.

3. The display substrate according to claim 2, wherein, The first fan-out area includes a first corner area and a second corner area, and the connection point of the first connecting line and the second connecting line is located in one of the first corner area and the second corner area; The line width of the first connecting line is greater than the line width of the second connecting line.

4. The display substrate according to claim 3, wherein, The line width of the first connecting line is set to be consistent along the extension direction of the first connecting line.

5. The display substrate according to claim 3, wherein, The line width of the first connecting line is set to gradually decrease along the direction away from the display area.

6. The display substrate according to claim 5, wherein, The first connecting line includes a plurality of sub-connecting lines arranged sequentially along the extension direction of the first connecting line, and the line width of the plurality of sub-connecting lines is set to decrease sequentially from the end closer to the display area to the end connected to the second connecting line.

7. The display substrate according to claim 2, wherein, The first fan-out line is configured as a broken line, and both the first connecting line and the second connecting line extend along a straight line. The included angle between the first connecting line and the second connecting line is set to α, where 100°≤α≤175°.

8. The display substrate according to claim 2, wherein, The first fan-out line is provided with multiple lines, and the multiple first fan-out lines are arranged at intervals in a direction parallel to the base. The distance between the first connecting lines of adjacent first fan-out lines is a first distance, and the distance between the second connecting lines of adjacent first fan-out lines is a second distance. The first distance is greater than the second distance. The line width of the first connecting line is equal to the line width of the second connecting line; The first connecting line includes a first routing layer and a second routing layer stacked in a direction perpendicular to the substrate, and the second connecting line includes a third routing layer, which is configured to be arranged in the same layer as the first routing layer or the second routing layer.

9. The display substrate according to any one of claims 3 to 7, wherein, The first fan-out line is provided with multiple lines, and the multiple first fan-out lines are arranged at equal intervals in a direction parallel to the base. The distance between the first connecting lines of adjacent first fan-out lines is the first distance, and the distance between the second connecting lines of adjacent first fan-out lines is the second distance. The first distance is equal to the second distance.

10. The display substrate according to any one of claims 2 to 8, wherein, The linewidth of the first fan-out line is set to be greater than 2 micrometers; The linewidth of the first fan-out line is set to L0, where 2μm≤L0≤5μm.

11. The display substrate according to any one of claims 2 to 8, wherein, R1≤2.5kΩ.

12. The display substrate according to claim 2, wherein, The display substrate also includes multiple parallel driving circuit traces located in the first frame area. The multiple driving circuit traces are configured to be electrically connected to multiple gate driving circuits. The multiple driving circuit traces include AC signal lines and DC signal lines, and the line width of the DC signal lines is greater than the line width of the AC signal lines.

13. The display substrate according to claim 12, wherein, The first frame area includes a circuit trace area, which is located on the side of the first fan-out area away from the display area; The circuit trace area includes a first area and a second area, which are arranged sequentially along the circumference of the display area. The minimum distance between the edge of the first area near the display area and the edge away from the display area is set as a third distance, and the minimum distance between the edge of the second area near the display area and the edge away from the display area is set as a fourth distance. The third distance is less than the fourth distance. At least one of the multiple drive circuit traces includes a first trace and a second trace, the first trace being located in the first region and the second trace being located in the second region, and the line width of the first trace being smaller than the line width of the second trace.

14. The display substrate according to claim 2, wherein, The first border area also includes a second fan-out area, which is located on the side of the first fan-out area away from the display area; The fan-out line also includes a second fan-out line located in the second fan-out area. There are multiple second fan-out lines, including a third line and a fourth line. The length of the third line is greater than the length of the fourth line, and the width of the third line is greater than the width of the fourth line.

15. The display substrate according to claim 14, wherein, At least one of the second fan-out lines includes a fourth routing layer and a fifth routing layer stacked in a direction perpendicular to the substrate.

16. The display substrate according to claim 14, wherein, The display substrate includes multiple first power lines and a first power pin. The multiple first power lines are located in the display area and are electrically connected to the multiple sub-pixels. The first power pin is located in the first border area, and the multiple first power lines are electrically connected to the first power pin. At least one portion of the second fan-out line is located on the side of the first power pin near the edge of the display substrate, and the orthographic projection of at least one second fan-out line on the substrate overlaps with the orthographic projection of the first power pin on the substrate.

17. The display substrate according to claim 16, wherein, The display substrate includes a second power line and a second power pin. The second power line is located in the peripheral area and at least partially surrounds the display area. The second power pin is located in the first frame area. The second power line and the second power pin are connected. At least one portion of the second fan-out line is located on the side of the second power pin away from the first power pin, and the orthographic projection of at least one second fan-out line on the substrate overlaps with the orthographic projections of the first power pin and the second power pin on the substrate.

18. The display substrate according to claim 17, wherein, It also includes multiple drive circuit traces located in the peripheral area, with at least a portion of the second fan-out line located between the second power supply pin and the multiple drive circuit traces.

19. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 18.

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