New MRAM memory cell and manufacturing method therefor

Abstract

A new MRAM memory cell and a manufacturing method therefor, which relate to the field of data storage. The method includes: sequentially including a reference layer, a magnesium oxide tunnel layer and a free layer in a stacking direction. The free layer sequentially includes an interfacial PMA free layer, a free spacer layer and a bulk PMA free layer in a stacking direction, wherein the interfacial PMA free layer is disposed on the surface of the magnesium oxide tunnel layer; the free spacer layer is configured to ferromagnetically couple the interfacial PMA free layer and the bulk PMA free layer; and the interfacial PMA free layer is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer and a cobalt-iron alloy layer, and the bulk PMA free layer is a manganese-based ternary tetragonal alloy layer. In the present invention, an interfacial PMA free layer and a bulk PMA free layer are combined to provide a higher TMR. In addition, a new manganese-based ternary tetragonal alloy is also used as the bulk PMA free layer, which improves the process compatibility and also improves the data retention capability of a device.

Description

A novel MRAM memory cell and its manufacturing method

[0001] This application claims priority to Chinese Patent Application No. 202411725246.5, filed on November 28, 2024, entitled "A Novel MRAM Memory Cell and a Method for Manufacturing the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of data storage, and in particular to a novel MRAM storage cell and its manufacturing method. Background Technology

[0003] As MRAM advances to advanced technology nodes, the corresponding miniaturization of memory bits and the key dimension miniaturization of the core device MTJ (Magnetic Tunnel Junction) will become a fiercely contested area. However, the rapid reduction of the CD (critical dimension) will also lead to a sharp decline in retention. Therefore, it is urgent to explore new device architectures to improve memory read efficiency and meet the requirements of high data retention and high reliability under smaller CDs.

[0004] The current mainstream MRAM structure uses a dual-interface magnesium oxide structure, but the PMA (perpendicular magnetic anisotropy) of this dual-interface structure is relatively weak, making it difficult to meet the high data retention requirements under small CD. Other MRAM structures also use pure bulk PMA materials as free layers, but the TMR (tunneling magnetoresistance) of bulk PMA materials (such as iron-platinum alloys) is currently low, and the required annealing temperature is high, resulting in poor compatibility between bulk PMA materials and the front-end processes of magnetic tunnel junctions and CMOS (complementary metal-oxide-semiconductor) processes.

[0005] Therefore, how to improve the PMA and TMR of the free layer while continuously reducing the critical size of MRAM memory cells, so as to achieve high data retention and good process compatibility, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a novel MRAM memory cell and its manufacturing method to solve the problems in the prior art where the PMA and TMR of the free layer are poor and process compatibility cannot be taken into account, given that the key dimensions of the MRAM memory cell are constantly decreasing.

[0007] To solve the above-mentioned technical problems, the present invention provides a novel MRAM memory cell, which includes, in the stacking direction, a reference layer, a magnesium oxide tunnel layer and a free layer in sequence;

[0008] The free layer includes, in the stacking direction, an interface PMA free layer, a free spacer layer and a volume PMA free layer in sequence.

[0009] The interface PMA free layer is disposed on the surface of the magnesium oxide-containing tunnel layer;

[0010] The free spacer layer is used to ferromagnetically couple the interface PMA free layer and the bulk PMA free layer;

[0011] The interface PMA free layer is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer; the bulk PMA free layer is a manganese ternary tetragonal alloy layer.

[0012] Optionally, the novel MRAM memory cell further includes a structure-inducing layer;

[0013] The structure-inducing layer is disposed on the surface of the free layer away from the magnesium oxide-containing tunnel layer;

[0014] The structure-inducing layer includes at least one of the following: chromium-molybdenum alloy layer, metallic molybdenum layer, metallic tungsten layer, magnesium fluoride layer, magnesium oxide layer, zinc oxide layer, titanium oxide layer, magnesium-titanium oxide layer, magnesium-aluminum oxide layer, magnesium-iron oxide layer, zirconium nitride layer, and manganese nitride layer.

[0015] Optionally, in the novel MRAM memory cell, the free layer further includes a second interface PMA free layer;

[0016] The second interface PMA free layer is disposed on the surface of the bulk PMA free layer away from the free spacer layer;

[0017] The second interface PMA free layer is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer.

[0018] Optionally, in the novel MRAM memory cell, the interface PMA free layer includes at least one of a cobalt-iron-boron layer, an iron-boron layer, a cobalt-iron layer, and a metallic iron layer;

[0019] And / or,

[0020] The free spacer layer includes at least one of the following: hafnium layer, zirconium layer, tantalum layer, molybdenum layer, tungsten layer, chromium layer, iridium layer, ruthenium layer, rhodium layer, magnesium layer, titanium oxide layer, magnesium oxide layer, and magnesium titanium oxide layer.

[0021] Optionally, in the novel MRAM memory cell, the elements in the bulk PMA free layer that form an alloy with manganese include at least one of magnesium, aluminum, silicon, calcium, scandium, strontium, gallium, germanium, indium, and tin.

[0022] And / or,

[0023] The thickness of the bulk PMA free layer ranges from 2 nanometers to 20 nanometers, including the endpoint values;

[0024] And / or,

[0025] The ternary tetragonal alloy layer of manganese satisfies the following formula:

[0026] Mn 1+a X 1+b Y 1+c ;

[0027] -0.2≤a,b,c≤+0.2;

[0028] Where a, b, and c are the floating parameters of the corresponding elements, and X and Y are the other two elements that form a ternary tetragonal alloy with manganese.

[0029] Optionally, in the novel MRAM memory cell, the novel MRAM memory cell is a top-pinned magnetic tunnel junction cell or a bottom-pinned magnetic tunnel junction cell.

[0030] Optionally, in the novel MRAM memory cell, the reference layer sequentially includes an interface PMA reference layer, a reference spacing layer, and a volume PMA reference layer in the stacking direction.

[0031] The interface PMA reference layer is disposed on the surface of the magnesium oxide-containing tunnel layer;

[0032] The reference spacer layer is used to ferromagnetically couple the interface PMA reference layer and the bulk PMA reference layer.

[0033] The interface PMA reference layer is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer; the bulk PMA reference layer is a manganese ternary tetragonal alloy layer.

[0034] A method for manufacturing a novel MRAM memory cell, the method comprising manufacturing a novel MRAM memory cell as described above, comprising:

[0035] The interface PMA free layer, the free spacer layer, and the bulk PMA free layer are sequentially deposited on the first surface of the magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor; the reference layer is disposed on the second surface of the magnesium oxide tunnel layer opposite to the first surface.

[0036] The magnetic tunnel junction precursor is subjected to annealing heat treatment to obtain the novel MRAM memory cell.

[0037] Optionally, in the method for manufacturing the novel MRAM memory cell, the interface PMA free layer, the free spacer layer, and the bulk PMA free layer are sequentially deposited on the first surface of the magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor, comprising:

[0038] The interface PMA free layer, the free spacer layer, the bulk PMA free layer and the structure-inducing layer are sequentially deposited on the first surface of the magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor.

[0039] Optionally, in the method for manufacturing the novel MRAM memory cell, the annealing heat treatment temperature does not exceed 400 degrees Celsius.

[0040] The present invention provides a novel MRAM memory cell, which sequentially includes a reference layer, a magnesium oxide tunnel layer, and a free layer in the stacking direction; the free layer sequentially includes an interface PMA free layer, a free spacer layer, and a bulk PMA free layer in the stacking direction; the interface PMA free layer is disposed on the surface of the magnesium oxide tunnel layer; the free spacer layer is used to ferromagnetically couple the interface PMA free layer and the bulk PMA free layer; the interface PMA free layer is at least one of a cobalt alloy layer, an iron alloy layer, and a cobalt-iron alloy layer; the bulk PMA free layer is a manganese ternary tetragonal alloy layer.

[0041] This invention divides the free layer into an interface PMA free layer coupled by a free spacer layer and a bulk PMA free layer. A magnesium oxide tunnel layer is combined with the interface PMA free layer, providing a high TMR (Transient Metal Retention Rate). Furthermore, a novel manganese ternary tetragonal alloy is used as the bulk PMA free layer, forming a good lattice arrangement with the magnesium oxide tunnel layer and the interface PMA free layer. This significantly reduces the heat treatment temperature, improves process compatibility, and substantially enhances the PMA and data retention capabilities of devices in small sizes. This invention also provides a method for manufacturing a novel MRAM memory cell with the above-mentioned beneficial effects. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 is a schematic diagram of a specific embodiment of the novel MRAM storage cell provided by the present invention;

[0044] Figure 2 is a schematic diagram of a specific embodiment of the novel MRAM storage unit provided by the present invention;

[0045] Figure 3 is a schematic diagram of a specific embodiment of the novel MRAM storage unit provided by the present invention;

[0046] Figure 4 is a schematic diagram of a specific embodiment of the novel MRAM storage unit provided by the present invention;

[0047] Figure 5 is a schematic diagram of a specific embodiment of the novel MRAM storage unit provided by the present invention;

[0048] Figure 6 is a schematic diagram of the internal structure of a specific embodiment of the novel MRAM storage unit provided by the present invention;

[0049] Figure 7 is a flowchart illustrating a specific embodiment of the manufacturing method of the novel MRAM memory cell provided by the present invention.

[0050] The figure includes 10-reference layer, 11-interface PMA reference layer, 12-reference spacer layer, 13-bulk PMA reference layer, 20-magnesium oxide tunnel layer, 31-interface PMA free layer, 32-free spacer layer, 33-bulk PMA free layer, 40-structure-induced layer, and 50-protective layer. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] The core of this invention is to provide a novel MRAM memory cell. A schematic diagram of one specific embodiment is shown in Figure 1, which is referred to as Specific Embodiment 1. In the stacking direction, it includes a reference layer 10, a magnesium oxide tunnel layer 20, and a free layer in sequence.

[0053] The free layer includes, in the stacking direction, an interface PMA free layer 31, a free spacer layer 32, and a bulk PMA free layer 33 in sequence.

[0054] The interface PMA free layer 31 is disposed on the surface of the magnesium oxide-containing tunnel layer 20;

[0055] The free spacer layer 32 is used to ferromagnetically couple the interface PMA free layer 31 and the bulk PMA free layer 33.

[0056] The interface PMA free layer 31 is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer; the bulk PMA free layer 33 is a manganese ternary tetragonal alloy layer.

[0057] The free spacer layer 32 effectively ferromagnetically couples the interface PMA free layer 31 and the bulk PMA free layer 33, and effectively blocks element diffusion at high temperatures. Additionally, arrows in Figure 1 indicate the magnetization direction of the corresponding layers, and this method will be used to indicate the magnetization direction in subsequent figures without further explanation. Figure 1 also includes a protective layer 50, which can be adjusted according to actual needs.

[0058] The chemical formula of the manganese ternary tetragonal alloy layer can be written as MnXY. The elements in the bulk PMA free layer 33 that form an alloy with manganese (i.e., the aforementioned X and Y) include at least one of magnesium, aluminum, silicon, calcium, scandium, strontium, gallium, germanium, indium, and tin (such as MnCaSn, MnAlGe, MnMgGe, etc.). Of course, the relationship between Mn and the other two elements X and Y is not necessarily a strict 1:1:1, but there is a certain degree of proportional fluctuation. Preferably, the following constraints (1) and (2) are satisfied:

[0059] Mn 1+a X 1+b Y 1+c (1)

[0060] -0.2≤a,b,c≤+0.2; (2)

[0061] Where a, b, and c are the floating parameters of the corresponding elements, and X and Y are the other two elements that form the ternary tetragonal alloy with manganese. For example, the ternary tetragonal alloy layer of manganese can be Mn. 1.02 Sr 0.89 Sn 1.16 .

[0062] Furthermore, the thickness of the bulk PMA free layer 33 ranges from 2 nanometers to 20 nanometers, including endpoint values ​​such as any one of 2.0 nanometers, 1.2 nanometers, or 2.0 nanometers. The above parameter ranges are preferred ranges after extensive theoretical calculations and practical verification. Of course, these ranges can be adjusted according to actual circumstances, which will not be elaborated upon here.

[0063] Furthermore, the interface PMA free layer 31 includes at least one of a cobalt-iron-boron layer, an iron-boron layer, a cobalt-iron layer, and a metallic iron layer; the various cross-section PMA free layers mentioned above are more easily formed with the magnesium oxide-containing tunnel layer 20. <001> The crystal orientation can significantly improve the TMR of the device and provide a suitable growth template for the adjacent bulk PMA free layer 33, helping the bulk PMA free layer 33 to grow in an orderly manner.

[0064] The free spacer layer 32 includes at least one of the following: hafnium metal layer, zirconium metal layer, tantalum metal layer, molybdenum metal layer, tungsten metal layer, chromium metal layer, iridium metal layer, ruthenium metal layer, rhodium metal layer, magnesium metal layer, titanium oxide layer, magnesium oxide layer, and magnesium titanium oxide layer. The aforementioned free spacer layers 32 exhibit strong ferromagnetic coupling and are dense enough to block element diffusion at high temperatures. Of course, other types of free spacer layers 32 can also be selected according to actual conditions, and this invention does not limit their use.

[0065] In a preferred embodiment, a structure-inducing layer 40 is also included;

[0066] The structure-inducing layer 40 is disposed on the surface of the free layer away from the magnesium oxide-containing tunnel layer 20;

[0067] The structure-inducing layer 40 includes at least one of the following: a chromium-molybdenum alloy layer, a molybdenum metal layer, a tungsten metal layer, a magnesium fluoride layer, a magnesium oxide layer, a zinc oxide layer, a titanium oxide layer, a magnesium-titanium oxide layer, a magnesium-aluminum oxide layer, a magnesium-iron oxide layer, a zirconium nitride layer, and a manganese nitride layer.

[0068] A schematic diagram of the structure with added structure-inducing layer 40 can be found in Figure 2. All of the aforementioned structure-inducing layers 40 exhibit good crystal phase and lattice matching with the manganese ternary tetragonal alloy layer. During the annealing heat treatment in the production process, ordered phase formation of the manganese ternary tetragonal alloy layer can be achieved, further enhancing its matching degree and facilitating compatibility with front-end CMOS and MTJ processes. Of course, other material layers with high crystal phase and lattice matching with the manganese ternary tetragonal alloy layer can also be selected according to actual conditions; this invention does not impose limitations on these selections.

[0069] Furthermore, the free layer also includes a second interface PMA free layer 34;

[0070] The second interface PMA free layer 34 is disposed on the surface of the bulk PMA free layer 33 away from the free spacer layer 32;

[0071] The second interface PMA free layer 34 is at least one of a cobalt alloy layer, an iron alloy layer, and a cobalt-iron alloy layer.

[0072] Referring to Figure 3, a second interface PMA free layer 34 is added between the bulk PMA free layer 33 and the structure-inducing layer 40. The material type and related parameters of the second interface PMA free layer 34 can be referenced from the interface PMA free layer 31. Adding the second interface PMA free layer 34 can further improve the TMR of the device and enhance the data retention capability of the device at high temperatures.

[0073] In addition, the novel MRAM storage cell is a top-pinned magnetic tunnel junction cell or a bottom-pinned magnetic tunnel junction cell.

[0074] The free-layer structure provided by the present invention can be used for the top pinned magnetic tunnel junction unit and the bottom pinned magnetic tunnel junction unit. Please refer to Figure 4. Figure 4 shows a magnetic tunnel junction unit with a pinning direction opposite to that in Figures 1, 2 and 3, thereby expanding the application scenarios of the present invention and improving its versatility.

[0075] In another preferred embodiment, the reference layer 10 includes, in the stacking direction, an interface PMA reference layer 1110, a reference spacer layer 12, and a volume PMA reference layer 1310.

[0076] The interface PMA reference layer 1110 is disposed on the surface of the magnesium oxide-containing tunnel layer 20;

[0077] The reference spacer layer 12 is used to ferromagnetically couple the interface PMA reference layer 1110 and the bulk PMA reference layer 1310.

[0078] The interface PMA reference layer 1110 is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer; the bulk PMA reference layer 1310 is a manganese ternary tetragonal alloy layer.

[0079] In this preferred embodiment, the reference layer 10 is further subdivided with reference to the free layer, comprising the interface PMA reference layer 1110, the reference spacer layer 12, and the bulk PMA reference layer 1310. The material type and related parameters of the interface PMA reference layer 1110 can be referenced to the interface PMA free layer 31, the material type and related parameters of the reference spacer layer 12 can be referenced to the free spacer layer 32, and the material type and related parameters of the bulk PMA reference layer 1310 can be referenced to the bulk PMA free layer 33. The reference layer 10 provided in this preferred embodiment can significantly enhance the pinning strength of the device and reduce stray field and external magnetic field interference, greatly improving the operational stability of the device.

[0080] Referring to Figure 5, the novel MRAM memory cell provided by the present invention includes, in the stacking direction, a reference layer 10, a magnesium oxide tunnel layer 20, and a free layer; the free layer includes, in the stacking direction, an interface PMA free layer 31, a free spacer layer 32, and a bulk PMA free layer 33; the interface PMA free layer 31 is disposed on the surface of the magnesium oxide tunnel layer 20; the free spacer layer 32 is used to ferromagnetically couple the interface PMA free layer 31 and the bulk PMA free layer 33; the interface PMA free layer 31 is at least one of a cobalt alloy layer, an iron alloy layer, and a cobalt-iron alloy layer; the bulk PMA free layer 33 is a manganese ternary tetragonal alloy layer. This invention divides the free layer into an interface PMA free layer 31 coupled by a free spacer layer 32 and a bulk PMA free layer 33. A magnesium oxide tunnel layer 20 is combined with the interface PMA free layer 31, providing a high TMR. Furthermore, a novel manganese ternary tetragonal alloy is used as the bulk PMA free layer 33, forming a good lattice arrangement with the magnesium oxide tunnel layer 20 and the interface PMA free layer 31. This significantly reduces the heat treatment temperature, improves process compatibility, and substantially enhances the PMA and data retention capabilities of devices in small sizes. The novel MRAM memory cell defined above can be seen in Figure 6, where the Reference layer is the reference layer 10, the MgO Barrier is the magnesium oxide tunnel layer, Free Layer 1 is the interface PMA free layer 31, the Spacer is the free spacer layer 32, and Free Layer 2 is the bulk PMA free layer 33. x The magnesium titanium oxide layer, serving as the structure-inducing layer 40, is labeled with "XX atom" in the figure. Additionally, the upper right corner of Figure 6 also labels the various types of atoms. At this point, the vertical axis of the lattice constant of the bulk PMA free layer 33 (C in Figure 6) is greater than the horizontal axis of the lattice constant (A in Figure 6), exhibiting a high magnetocrystalline anisotropy constant (Ku), specifically reaching 1.0*10⁻⁶. 7 erg / cc.

[0081] This invention also provides a method for manufacturing a novel MRAM memory cell, one specific embodiment of which is shown in Figure 7, referred to as Specific Embodiment Two. The method for manufacturing the novel MRAM memory cell is used to manufacture the novel MRAM memory cell as described in any of the above embodiments, and includes:

[0082] S101: The interface PMA free layer, the free spacer layer and the bulk PMA free layer are sequentially deposited on the first surface of the magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor; the reference layer is disposed on the second surface of the magnesium oxide tunnel layer opposite to the first surface.

[0083] S102: The magnetic tunnel junction precursor is subjected to annealing heat treatment to obtain the novel MRAM memory cell.

[0084] After setting the interface PMA free layer, the free spacer layer and the bulk PMA free layer, the annealing heat treatment is carried out to enable the various layers in the device to form phases in an orderly manner at a lower temperature, thereby obtaining good process matching and epitaxial quality.

[0085] The manufacturing method of the novel MRAM memory cell in this specific embodiment corresponds to the novel MRAM memory cell described above. For specific technical details, please refer to the relevant description of the novel MRAM memory cell described above, which will not be elaborated here.

[0086] Further, the interface PMA free layer, the free spacer layer, and the bulk PMA free layer are sequentially deposited on the first surface of the magnesium oxide tunneling layer to obtain a magnetic tunnel junction precursor comprising:

[0087] The interface PMA free layer, the free spacer layer, the bulk PMA free layer and the structure-inducing layer are sequentially deposited on the first surface of the magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor.

[0088] The purpose of setting the structure-inducing layer is to adjust the lattice and phase of the bulk PMA free layer during annealing heat treatment, using the lattice and phase of the structure-inducing layer as a template. Therefore, the structure-inducing layer needs to be set on the surface of the bulk PMA free layer before annealing heat treatment.

[0089] Specifically, the annealing heat treatment temperature does not exceed 400 degrees Celsius. A heat treatment temperature not exceeding 400 degrees Celsius is compatible with most front-end processes of MTJ devices, as well as further upstream CMOS manufacturing processes, without concern that excessively high temperatures would damage the structures already fabricated in the front-end processes. Of course, the above temperature range can be adjusted according to actual circumstances, and this invention does not impose limitations on it.

[0090] This invention provides a method for manufacturing a novel MRAM memory cell. The method is used to manufacture a novel MRAM memory cell as described above, comprising sequentially depositing an interface PMA free layer, a free spacer layer, and a bulk PMA free layer on a first surface of a magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor; a reference layer is disposed on a second surface of the magnesium oxide tunnel layer opposite to the first surface; and the magnetic tunnel junction precursor is subjected to annealing heat treatment to obtain the novel MRAM memory cell. This invention divides the free layer into an interface PMA free layer coupled by a free spacer layer and a bulk PMA free layer. The magnesium oxide tunnel layer and the interface PMA free layer are combined to provide a high TMR (Total Motion Registry). Furthermore, a novel manganese ternary tetragonal alloy is used as the bulk PMA free layer, forming a good lattice arrangement with the magnesium oxide tunnel layer and the interface PMA free layer. This significantly reduces the heat treatment temperature, improves process compatibility, and substantially enhances the PMA and data retention capabilities of devices with small sizes.

[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0092] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The novel MRAM memory cell and its manufacturing method provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A novel MRAM storage cell, characterized in that, The stacking direction includes, in sequence, a reference layer, a magnesium oxide tunnel layer, and a free layer; The free layer includes, in the stacking direction, an interface PMA free layer, a free spacer layer and a volume PMA free layer in sequence. The interface PMA free layer is disposed on the surface of the magnesium oxide-containing tunnel layer; The free spacer layer is used to ferromagnetically couple the interface PMA free layer and the bulk PMA free layer; The interface PMA free layer is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer; the bulk PMA free layer is a manganese ternary tetragonal alloy layer.

2. The novel MRAM storage cell as described in claim 1, characterized in that, It also includes a structure-inducing layer; The structure-inducing layer is disposed on the surface of the free layer away from the magnesium oxide-containing tunnel layer; The structure-inducing layer includes at least one of the following: chromium-molybdenum alloy layer, metallic molybdenum layer, metallic tungsten layer, magnesium fluoride layer, magnesium oxide layer, zinc oxide layer, titanium oxide layer, magnesium-titanium oxide layer, magnesium-aluminum oxide layer, magnesium-iron oxide layer, zirconium nitride layer, and manganese nitride layer.

3. The novel MRAM storage cell as described in claim 1, characterized in that, The free layer also includes a second interface PMA free layer; The second interface PMA free layer is disposed on the surface of the bulk PMA free layer away from the free spacer layer; The second interface PMA free layer is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer.

4. The novel MRAM storage cell as described in claim 1, characterized in that, The interface PMA free layer includes at least one of a cobalt-iron-boron layer, an iron-boron layer, a cobalt-iron layer, and a metallic iron layer; And / or, The free spacer layer includes at least one of the following: hafnium layer, zirconium layer, tantalum layer, molybdenum layer, tungsten layer, chromium layer, iridium layer, ruthenium layer, rhodium layer, magnesium layer, titanium oxide layer, magnesium oxide layer, and magnesium titanium oxide layer.

5. The novel MRAM storage cell as described in claim 1, characterized in that, The elements in the free layer of the bulk PMA that form an alloy with manganese include at least one of magnesium, aluminum, silicon, calcium, scandium, strontium, gallium, germanium, indium, and tin. And / or, The thickness of the bulk PMA free layer ranges from 2 nanometers to 20 nanometers, including the endpoint values; And / or, The ternary tetragonal alloy layer of manganese satisfies the following formula: Mn 1+a X 1+b Y 1+c ; -0.2≤a,b,c≤+0.2; Where a, b, and c are the floating parameters of the corresponding elements, and X and Y are the other two elements that form a ternary tetragonal alloy with manganese.

6. The novel MRAM storage cell as described in claim 1, characterized in that, The novel MRAM storage unit is a top-pinned magnetic tunnel junction unit or a bottom-pinned magnetic tunnel junction unit.

7. The novel MRAM memory cell according to any one of claims 1 to 6, characterized in that, The reference layer includes, in the stacking direction, an interface PMA reference layer, a reference spacer layer, and a volume PMA reference layer in sequence. The interface PMA reference layer is disposed on the surface of the magnesium oxide-containing tunnel layer; The reference spacer layer is used to ferromagnetically couple the interface PMA reference layer and the bulk PMA reference layer. The interface PMA reference layer is at least one of a cobalt-containing alloy layer, an iron-containing alloy layer, and a cobalt-iron alloy layer; the bulk PMA reference layer is a manganese ternary tetragonal alloy layer.

8. A method for manufacturing a novel MRAM memory cell, characterized in that, The method for manufacturing the novel MRAM memory cell is used to manufacture the novel MRAM memory cell as described in any one of claims 1 to 7, comprising: The interface PMA free layer, the free spacer layer, and the bulk PMA free layer are sequentially deposited on the first surface of the magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor; the reference layer is disposed on the second surface of the magnesium oxide tunnel layer opposite to the first surface. The magnetic tunnel junction precursor is subjected to annealing heat treatment to obtain the novel MRAM memory cell.

9. The method for manufacturing the novel MRAM memory cell as described in claim 8, characterized in that, The interfacial PMA free layer, the free spacer layer, and the bulk PMA free layer are sequentially deposited on the first surface of the magnesium oxide tunneling layer to obtain a magnetic tunneling junction precursor comprising: The interface PMA free layer, the free spacer layer, the bulk PMA free layer and the structure-inducing layer are sequentially deposited on the first surface of the magnesium oxide tunnel layer to obtain a magnetic tunnel junction precursor.

10. The method for manufacturing the novel MRAM memory cell as described in claim 8, characterized in that, The annealing heat treatment temperature shall not exceed 400 degrees Celsius.

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