Semiconductor device

Abstract

Provided is a semiconductor device with a high operating speed. The present invention comprises: an oxide semiconductor; a first conductor and a second conductor that are separated from each other on the oxide semiconductor; a third conductor that is in contact with one portion of an upper surface of the first conductor; a fourth conductor that is in contact with one portion of an upper surface of the second conductor; a first insulator that is disposed on the third conductor and the fourth conductor and has an opening that overlaps a region between the third conductor and the fourth conductor; a second insulator that is disposed in the opening of the first insulator and is in contact with another portion of the upper surface of the first conductor and another portion of the upper surface of the second conductor; a third insulator that is disposed in the opening of the first insulator; and a fifth conductor that is disposed on the third conductor in the opening of the first insulator. The distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor. The oxide semiconductor contains indium. The first conductor and the second conductor are both conductive oxides.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device using an oxide semiconductor. Another aspect of the present invention relates to a method for manufacturing the above-mentioned semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes which are connection terminals.

[0005] Semiconductor circuits such as LSIs, CPUs, and memory (e.g., IC chips) are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, Patent Document 3 discloses a transistor with a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor.

[0009] Also, In ２ O ３ Its use in thin-film transistors has been reported (Non-Patent Document 1).

[0010] Japanese Patent Publication No. 2012-257187, Japanese Patent Publication No. 2011-151383, International Publication No. 2016-125052

[0011] Dhananjay and C. W. Chu, “Realization of In2O3 thin film transistors through reactive evaporation process.” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, “High-mobility transparent conductive film,” National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0012] One aspect of the present invention aims to provide a semiconductor device with a high operating speed. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with high reliability. Alternatively, one aspect of the present invention aims to provide a semiconductor device with less variation in the electrical characteristics of transistors. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a semiconductor device with high productivity. Furthermore, one aspect of the present invention aims to provide a method for manufacturing a novel semiconductor device.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0014] One aspect of the present invention comprises an oxide semiconductor, a first conductor and a second conductor spaced apart from each other on the oxide semiconductor, a third conductor in contact with a portion of the upper surface of the first conductor, a fourth conductor in contact with a portion of the upper surface of the second conductor, a first insulator disposed on the third and fourth conductors and having an opening that overlaps with the region between the third and fourth conductors, and a second insulator disposed within the opening and in contact with the other portion of the upper surface of the first conductor, the other portion of the upper surface of the second conductor, the side surface of the third conductor, and the side surface of the fourth conductor. A semiconductor device comprising: a body; a third insulator disposed within an opening and in contact with the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator; and a fifth conductor disposed within the opening on the third insulator and having a region that overlaps with the oxide semiconductor via the third insulator, wherein the distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor, the oxide semiconductor contains indium, and the first conductor and the second conductor each contain a conductive oxide.

[0015] Another aspect of the present invention includes an oxide semiconductor, a first conductor and a second conductor spaced apart from each other on the oxide semiconductor, a third conductor in contact with a portion of the upper surface of the first conductor, a fourth conductor in contact with a portion of the upper surface of the second conductor, a first insulator disposed on the third and fourth conductors and having an opening that overlaps with the region between the third and fourth conductors, a second insulator disposed within the opening and in contact with another portion of the upper surface of the first conductor and another portion of the upper surface of the second conductor, and a third insulator disposed within the opening that touches the upper surface of the oxide semiconductor, the side surface of the first conductor, and the third A semiconductor device comprising: a third insulator in contact with the side surface of a second conductor and the side surface of a second insulator; and a fifth conductor disposed within an opening on the third insulator and having a region superimposed on an oxide semiconductor via the third insulator, wherein the distance between the first and second conductors is smaller than the distance between the third and fourth conductors, the oxide semiconductor is indium, the first and second conductors each have a conductive oxide, and oxide is present between the third and second insulators and between the fourth conductor and the second insulator, the oxide being insulating.

[0016] Another aspect of the present invention includes an oxide semiconductor, a first conductor and a second conductor spaced apart from each other on the oxide semiconductor, a third conductor in contact with a portion of the upper surface of the first conductor, a fourth conductor in contact with a portion of the upper surface of the second conductor, a first insulator disposed on the third conductor and the fourth conductor and having an opening that overlaps with the region between the third conductor and the fourth conductor, and disposed within the opening, and a portion of the upper surface of the oxide semiconductor, another portion of the upper surface of the first conductor, a side surface of the first conductor, another portion of the upper surface of the second conductor, a side surface of the second conductor, a side surface of the third conductor, and The semiconductor device comprises a second insulator in contact with the side surface of a fourth conductor, a third insulator disposed within an opening and in contact with the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator, and a fifth conductor disposed within the opening on the third insulator and having a region that overlaps with the oxide semiconductor via the third insulator, wherein the distance between the first and second conductors is smaller than the distance between the third and fourth conductors, the oxide semiconductor contains indium, and the first and second conductors each contain a conductive oxide.

[0017] Another aspect of the present invention includes an oxide semiconductor, a first conductor and a second conductor spaced apart from each other on the oxide semiconductor, a third conductor in contact with the upper surface of the first conductor, a fourth conductor in contact with the upper surface of the second conductor, a first insulator disposed on the third and fourth conductors and having an opening that overlaps with the region between the third and fourth conductors, a second insulator disposed within the opening and in contact with a part of the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, the side surface of the third conductor, and the side surface of the fourth conductor, and a second insulator disposed within the opening and on the upper surface of the oxide semiconductor, the first A semiconductor device comprising: a third insulator in contact with the side surface of a first conductor, the side surface of a second conductor, and the side surface of a second insulator; and a fifth conductor disposed on the third insulator within the opening and having a region superimposed on the oxide semiconductor via the third insulator, wherein the distance between the first and second conductors is smaller than the distance between the third and fourth conductors, the side surface of the first conductor and the side surface of the third conductor are flush, the side surface of the second conductor and the side surface of the fourth conductor are flush, the oxide semiconductor is indium, and the first and second conductors each have a conductive oxide.

[0018] Furthermore, in the above, it is preferable that the distance between the side surface of the third conductor and the third insulator, and the distance between the side surface of the fourth conductor and the third insulator, are each greater than the distance between the side surface of the first insulator and the side surface of the third insulator.

[0019] Furthermore, in the above, it is preferable that the film thickness of the oxide semiconductor in the region overlapping with the third insulator is thinner than the film thickness of the oxide semiconductor in the region overlapping with the first conductor or the second conductor.

[0020] Furthermore, in the above configuration, it is preferable that the second insulator is in contact with a portion of the side surface of the oxide semiconductor.

[0021] Furthermore, in the above, it is preferable that the second insulator has silicon nitride.

[0022] Furthermore, in the above, it is preferable that the second insulator has a first layer and a second layer on the first layer, the first layer has silicon oxide and the second layer has silicon nitride.

[0023] Furthermore, it is preferable that the third conductor has higher conductivity than the first conductor, and the fourth conductor has higher conductivity than the second conductor.

[0024] Furthermore, it is preferable that the first conductor and the second conductor each contain indium and tin, respectively.

[0025] According to one aspect of the present invention, a semiconductor device with high operating speed can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with less variation in the electrical characteristics of transistors can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0027] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B, 1C, and 1D are cross-sectional views showing an example of a semiconductor device. Figures 2A and 2B are cross-sectional views showing an example of a semiconductor device. Figures 3A, 3B, and 3C are cross-sectional views showing an example of a semiconductor device. Figures 4A and 4B are cross-sectional views showing an example of a semiconductor device. Figures 5A, 5B, and 5C are cross-sectional views showing an example of a semiconductor device. Figures 6A and 6B are cross-sectional views showing an example of a semiconductor device. Figure 7A is a plan view showing an example of a semiconductor device. Figures 7B, 7C, and 7D are cross-sectional views showing an example of a semiconductor device. Figure 8A is a plan view showing an example of a semiconductor device. Figures 8B, 8C, and 8D are cross-sectional views showing an example of a semiconductor device. Figures 9A and 9B are cross-sectional views showing an example of a semiconductor device. Figure 10A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 10B, 10C, and 10D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 11A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 11B, 11C, and 11D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 12A is a plan view showing an example of a semiconductor device manufacturing method. Figures 12B, 12C, and 12D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 13A is a plan view showing an example of a semiconductor device manufacturing method. Figures 13B, 13C, and 13D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figures 14B, 14C, and 14D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figures 15B, 15C, and 15D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figures 16B, 16C, and 16D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figures 17B, 17C, and 17D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figures 18B, 18C, and 18D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 19A is a plan view showing an example of a semiconductor device manufacturing method.Figures 19B, 19C, and 19D are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 20A, 20B, 20C, and 20D are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 21A and 21B are diagrams illustrating the carrier concentration dependence of Hall mobility. Figure 21C is a cross-sectional view illustrating an indium oxide film. Figures 22A and 22B are examples of the configuration of a display device. Figure 23 is an example of the configuration of a display device. Figure 24 is an example of the configuration of a display device. Figure 25 is an example of the configuration of a display device. Figures 26A, 26B, 26C, 26D, 26E, and 26F are examples of the configuration of electronic equipment. Figures 27A, 27B, 27C, 27D, 27E, and 27F are examples of the configuration of electronic equipment. Figures 28A, 28B, 28C, 28D, 28E, 28F, and 28G show examples of electronic device configurations. Figure 29 is a block diagram illustrating an example of semiconductor device configuration. Figures 30A, 30B, 30C, 30D, 30E, 30F, 30G, and 30H illustrate examples of memory cell circuit configurations. Figures 31A and 31B show examples of electronic components. Figures 32A, 32B, and 32C show examples of large-scale computers. Figure 32D shows an example of space equipment. Figure 32E shows an example of a storage system applicable to data centers. Figures 33A and 33B are perspective views of semiconductor devices. Figure 34 is a perspective view of a semiconductor device. Figure 35 is a cross-sectional STEM image according to an embodiment. Figure 36 shows the measurement results of the Id-Vg characteristics according to an embodiment.

[0028] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0029] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0030] Furthermore, for the sake of ease of understanding, the position, size, and scope of each component shown in the drawings may not represent their actual position, size, and scope. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0031] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0032] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer." Furthermore, the term "conductor" can be interchanged with the terms "conductive layer" or "conductive film" depending on the context or situation. Similarly, the term "insulator" can be interchanged with the terms "insulating layer" or "insulating film" depending on the context or situation.

[0033] An opening can include, for example, grooves and slits. Furthermore, the area in which an opening is formed may also be referred to as an opening.

[0034] Furthermore, in the drawings used herein, etc., the side walls of the insulator at the opening of the insulator are shown to be perpendicular or approximately perpendicular to the substrate surface or the surface to be formed, but they may also be tapered.

[0035] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0036] (Embodiment 1) In this embodiment, a semiconductor device having an oxide semiconductor and a method for manufacturing the semiconductor device will be described with reference to Figures 1A to 20D.

[0037] <Example of Semiconductor Device Configuration> An example of a semiconductor device configuration will be explained using Figures 1A to 6B. Figures 1A to 1D are plan views and cross-sectional views of a semiconductor device having a transistor 200. Figure 1A is a plan view of the semiconductor device. Figures 1B to 1D are cross-sectional views of the semiconductor device. Here, Figure 1B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 1C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the plan view of Figure 1A, some elements have been omitted for clarity. Figures 2A to 6B show enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0038] The transistor 200 includes a conductor 205 embedded in an insulator 216, an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, conductors 242a1 and 242b1 spaced apart from each other on the oxide semiconductor 230, a conductor 242a2 on the conductor 242a1, a conductor 242b2 on the conductor 242b1, an insulator 250 on the oxide semiconductor 230, and a conductor 260 arranged on the insulator 250 and having a region that overlaps with the oxide semiconductor 230. Conductors 242a1 and 242a2 are sometimes collectively referred to as conductor 242a. Also, conductors 242b1 and 242b2 are sometimes collectively referred to as conductor 242b.

[0039] The oxide semiconductor 230 is made of a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor), and the oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as the first gate electrode of the transistor 200 (can also be called the upper gate electrode or top gate electrode). The insulator 250 has a region that functions as the first gate insulator of the transistor 200. The conductor 205 has a region that functions as the second gate electrode of the transistor 200 (can also be called the lower gate electrode or bottom gate electrode). The insulators 224, 222, and 221 each have a region that functions as the second gate insulator of the transistor 200. The conductor 242a has a region that functions as either the source electrode or the drain electrode of the transistor 200. The conductor 242b has a region that functions as either the source electrode or the drain electrode of the transistor 200.

[0040] An insulator 271a is provided on the conductor 242a2, and an insulator 271b is provided on the conductor 242b2. An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are arranged inside the opening. The conductor 260 is formed self-aligningly so as to fill the opening. By forming the conductor 260 in this way, the conductor 260 can be placed superimposed in the region between the conductors 242a and 242b without the need for alignment. An insulator 255 is also arranged inside the opening. The insulator 255 is in contact with the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2.

[0041] Furthermore, an insulator 282 is provided in contact with the upper surface of insulator 280, the upper end of insulator 255, the upper end of insulator 250, and the upper surface of conductor 260. Insulator 283 is provided on insulator 282. Insulator 285 is provided on insulator 283. Insulator 214 is provided below insulator 216 and conductor 205. Insulator 212 is provided below insulator 214. Insulators 212, 214, 280, 282, 283, and 285 function as interlayer films.

[0042] Insulators 285, 283, 282, 280, 275, and 271a have openings that reach conductor 242a2, and conductor 240a and insulator 241a are provided within these openings. Insulator 241a is provided in contact with the side wall of the opening, and conductor 240a is provided inside insulator 241a. In addition, insulators 285, 283, 282, 280, 275, and 271b have openings that reach conductor 242b2, and conductor 240b and insulator 241b are provided within these openings. Insulator 241b is provided in contact with the side wall of the opening, and conductor 240b is provided inside insulator 241b. Conductors 240a and 240b function as vias that connect wiring or the like provided on the transistor 200 to the source or drain of the transistor 200.

[0043] It is preferable that the conductors 242a1 and 242b1 in contact with the oxide semiconductor 230 are conductors that are not easily oxidized, such as conductive oxides or conductive nitrides. This prevents the conductors 242a1 and 242b1 from becoming highly resistive due to the oxygen contained in the oxide semiconductor 230. Therefore, the contact resistance between conductor 242a1 and the oxide semiconductor 230, and the contact resistance between conductor 242b1 and the oxide semiconductor 230 can be reduced. Furthermore, it is preferable that the conductors 242a2 and 242b2 are conductors such as metals that have higher conductivity than conductors 242a1 and 242b1. This allows conductors 242a2 and 242b2 to function as highly conductive wiring or electrodes. In this way, a semiconductor device can be provided in which conductors 242a and 242b, which function as wiring or electrodes, are provided in contact with the upper surface of the oxide semiconductor 230, which functions as an active layer.

[0044] As shown in Figure 2B, in the conductor 242a1, the portion on which the insulator 255 is formed on the upper surface protrudes toward the conductor 260 from the conductor 242a2. Similarly, in the conductor 242b1, the portion on which the insulator 255 is formed on the upper surface protrudes toward the conductor 260 from the conductor 242b2. Therefore, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between conductors 242a1 and 242b1 is smaller than the distance L1 between conductors 242a2 and 242b2. The difference between L1 and L2 may coincide with or approximately coincide with twice the film thickness of the insulator 255. Here, the film thickness of the insulator 255 refers to the film thickness in the A1-A2 direction in at least a portion of the insulator 255. This configuration makes it possible to shorten the distance between the source and drain, and consequently shorten the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing semiconductor devices, it is possible to provide semiconductor devices with improved operating speeds.

[0045] The openings provided in the insulators 280 and 275 described above overlap with the region between the conductors 242a2 and 242b2. In a top view, the side surface of the insulator 280 at the opening may coincide with or approximately coincide with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Furthermore, parts of the conductors 242a1 and 242b1 are formed to protrude inward from the side surface of the insulator 280, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. Here, a part of the upper surface of the conductor 242a1 is in contact with the conductor 242a2, and a part of the upper surface of the conductor 242b1 is in contact with the conductor 242b2. Therefore, the insulator 255 is in contact with the other part of the upper surface of the conductor 242a1, the other part of the upper surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 inside the opening. The insulator 250 is in contact with the upper surface of the oxide semiconductor 230, the side surface of the conductor 242a1, the side surface of the conductor 242b1, and the side surface of the insulator 255.

[0046] The insulator 255 is formed in a sidewall shape by anisotropic etching in contact with the side walls of the openings provided in the insulator 280 and the like (where the side walls of the openings correspond, for example, to the sides of the insulator 280 and the like in the openings). The insulator 255 is formed in contact with the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the insulator 275, and the side surface of the insulator 280.

[0047] It is preferable to use an insulating material with a relatively low dielectric constant for the insulator 255. For example, silicon nitride, silicon oxide, aluminum oxide, etc., can be used as the insulator 255. By providing such an insulator 255 between the conductor 242a2 and the conductor 260, or between the conductor 242b2 and the conductor 260, the distance between the conductor 242a2 and the conductor 260, and the distance between the conductor 242b2 and the conductor 260 can be increased. This makes it possible to reduce the parasitic capacitance between the conductor 260 and the conductor 242a2, and between the conductor 260 and the conductor 242b2. In addition, it is possible to reduce the leakage current between the conductor 260 and the conductor 242a2, and between the conductor 260 and the conductor 242b2.

[0048] As shown in Figure 2A, the oxide semiconductor 230 can be configured to have an oxide semiconductor 230a on an insulator 224 and an oxide semiconductor 230b on the oxide semiconductor 230a. By having the oxide semiconductor 230a below the oxide semiconductor 230b, the diffusion of impurities from structures formed below the oxide semiconductor 230a to the oxide semiconductor 230b can be suppressed. This makes it possible to improve the crystallinity of the oxide semiconductor 230b.

[0049] In Figure 2A, an example is shown where the oxide semiconductor 230 has a two-layer structure consisting of oxide semiconductor 230a and oxide semiconductor 230b, but it is not limited to this. The oxide semiconductor 230 may have a single-layer structure or a stacked structure of three or more layers.

[0050] In the oxide semiconductor 230, a channel formation region, a source region, and a drain region provided so as to sandwich the channel formation region are formed in the transistor 200. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a1, and the drain region overlaps with the conductor 242b1. Note that the source region and the drain region can be interchanged with each other.

[0051] The channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the source region and the drain region. Therefore, the channel formation region can be said to be of the i-type (intrinsic) or substantially i-type.

[0052] Further, the source region and the drain region are low-resistance regions with a high carrier concentration because they have a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, and metal elements. That is, the source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0053] Note that the carrier concentration of the channel formation region is 1×10 １８ cm −３ or less, 1×10 １７ cm −３ or less, 1×10 １６ cm −３ or less, 1×10 １５ cm −３ or less, 1×10 １４ cm −３ or less, 1×10 １３ cm −３ or less, 1×10 １２ cm −３ or less, 1×10 １１ cm −３ or less, or 1×10 １０ cm −３ or less is preferable. Regarding the lower limit value of the carrier concentration of the channel formation region, there is no particular limitation. For example, it can be 1×10 −９ cm −３

[0054] Furthermore, when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced, thereby reducing the defect level density. In this specification, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0055] To stabilize the electrical characteristics of transistor 200, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor 230. Furthermore, in order to reduce the impurity concentration in the channel formation region of the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in the oxide semiconductor 230 refer to elements other than the main components constituting the oxide semiconductor 230. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0056] Furthermore, the channel formation region, source region, and drain region may each be formed not only on the oxide semiconductor 230b but also on the oxide semiconductor 230a.

[0057] Furthermore, in the oxide semiconductor 230, it can be difficult to clearly detect the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected within each region may not be limited to stepwise changes from region to region, but may also change continuously within each region. In other words, the closer a region is to the channel formation region, the lower the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may be.

[0058] In the oxide semiconductor 230, the band gap of the oxide semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced. A transistor having a metal oxide in the channel formation region in this way is called an OS transistor. Because OS transistors have a small off-current, the power consumption of the semiconductor device can be significantly reduced. In addition, because OS transistors have high frequency characteristics, the semiconductor device can be operated at high speed.

[0059] The oxide semiconductor 230 preferably contains a metal oxide (oxide semiconductor). Examples of metal oxides that can be used in the oxide semiconductor 230 include indium oxide, gallium oxide, and zinc oxide. Indium oxide can be called indium oxide, gallium oxide can be called gallium oxide, and zinc oxide can be called zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is a metal element or metalloid with a high bond energy with oxygen, for example, a metal element or metalloid with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may include metalloid elements.

[0060] The oxide semiconductor 230 is, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO) Other suitable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0061] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be improved.

[0062] Furthermore, the metal oxide may contain one or more metal elements with higher periodic numbers in place of indium, or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, including metal elements with higher periodic numbers can sometimes increase the field-effect mobility of the transistor. Examples of metal elements with higher periodic numbers include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0063] Furthermore, metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can sometimes increase the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0064] Furthermore, by increasing the ratio of zinc atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities in the metal oxide. Therefore, fluctuations in the electrical properties of the transistor are suppressed, and reliability can be improved.

[0065] Furthermore, by increasing the ratio of element M atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, resulting in a transistor with low off-current. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0066] As mentioned above, the electrical characteristics and reliability of the transistor differ depending on the composition of the metal oxide applied to the oxide semiconductor 230. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, it is possible to create a semiconductor device that achieves both excellent electrical characteristics and high reliability.

[0067] The oxide semiconductor 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used in the oxide semiconductor 230a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used in the oxide semiconductor 230b. Furthermore, in the metal oxide used in the oxide semiconductor 230a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used in the oxide semiconductor 230b. This configuration makes it possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide semiconductor 230a into the oxide semiconductor 230b.

[0068] Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for the oxide semiconductor 230b is greater than the atomic ratio of In to element M in the metal oxide used for the oxide semiconductor 230a. With this configuration, the transistor 200 can obtain a large on-current and high frequency characteristics.

[0069] Furthermore, since oxide semiconductors 230a and 230b share a common element other than oxygen as a main component, the defect level density at the interface between oxide semiconductors 230a and 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0070] Specifically, as the oxide semiconductor 230a, a metal oxide with a composition of In:M:Zn = 1:3:2 [atomic ratio] or nearby, In:M:Zn = 1:3:4 [atomic ratio] or nearby, or In:M:Zn = 1:1:0.5 [atomic ratio] or nearby can be used. Furthermore, as the oxide semiconductor 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or nearby, In:M:Zn = 1:1:1.2 [atomic ratio] or nearby, In:M:Zn = 1:1:2 [atomic ratio] or nearby, or In:M:Zn = 4:2:3 [atomic ratio] or nearby can be used. Note that nearby compositions include a range of ±30% of the desired atomic ratio. Also, it is preferable to use gallium as element M.

[0071] Furthermore, the oxide semiconductors 230a and 230b may have a composition that does not contain element M. For example, the metal oxide used as the oxide semiconductor 230b may be In-Zn oxide. Specifically, the oxide semiconductor 230b can have a composition of In:Zn = 1:1 [atomic ratio] or close to that, or a composition of In:Zn = 4:1 [atomic ratio] or close to that. Alternatively, indium oxide may be used as the oxide semiconductor 230b. Furthermore, the above oxide semiconductor 230b may have a composition that contains a trace amount of element M. For example, specifically, the oxide semiconductor 230b can have a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or close to that.

[0072] Furthermore, when the oxide semiconductor 230 is made into a single-layer structure, either the metal oxide that can be used in the oxide semiconductor 230a or oxide semiconductor 230b described above can be applied. Moreover, the composition of the metal oxide that can be used in the oxide semiconductor 230a and oxide semiconductor 230b is not limited to the above. For example, the composition of the metal oxide that can be used in the oxide semiconductor 230a may also be applied to the oxide semiconductor 230b. Similarly, the composition of the metal oxide that can be used in the oxide semiconductor 230b may also be applied to the oxide semiconductor 230a.

[0073] Furthermore, when the oxide semiconductor 230 has a three-layer structure, an oxide semiconductor 230a can be provided on the insulator 224, an oxide semiconductor 230b can be provided on the oxide semiconductor 230a, and a layer having a metal oxide that can be used as the oxide semiconductor 230a can be provided on the oxide semiconductor 230b. For example, indium oxide can be used for the oxide semiconductor 230b, and indium gallium zinc oxide can be used for the layers on the oxide semiconductor 230a and oxide semiconductor 230b. For example, the oxide semiconductor 230a can have a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that. Also, for example, the layer on the oxide semiconductor 230b can have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or In:Ga:Zn = 1:1:1.2 [atomic ratio] or close to that. As described above, by providing the oxide semiconductor 230 with a configuration that includes indium oxide, a semiconductor device with high field-effect mobility can be provided. Furthermore, it is possible to provide a semiconductor device with good electrical characteristics, frequency characteristics, and reliability. With this configuration, a layer having indium gallium zinc oxide, which has low oxygen permeability, can be provided between the oxide semiconductor 230b, which has highly oxygen-permeable indium oxide, and the conductor 242a (conductor 242b). This reduces the extraction of oxygen by the conductor 242a (conductor 242b) from the oxide semiconductor 230b, and reduces the increase in contact resistance between the oxide semiconductor 230b and the conductor 242a (conductor 242b). For detailed configuration when indium oxide is used for the oxide semiconductor 230, please refer to the description in Embodiment 2.

[0074] Furthermore, when the oxide semiconductor 230 has a three-layer structure, it is also possible to use indium oxide with different film properties in at least one of the three layers. Examples of film properties include conductivity, band gap, defect amount, impurity concentration, and crystallinity. For example, it is preferable that the layers on oxide semiconductor 230a and oxide semiconductor 230b are denser and have fewer defects than oxide semiconductor 230b. By sandwiching oxide semiconductor 230b between the layers on oxide semiconductor 230a and oxide semiconductor 230b, it is possible to create a transistor 200 that achieves both high field-effect mobility and high reliability. Thus, it is possible to provide a semiconductor device that achieves both high-speed operation and high reliability.

[0075] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0076] For analyzing the composition of the metal oxide used in the oxide semiconductor 230, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods may be used for the analysis. Furthermore, for elements with low concentrations, the actual concentration may differ from the concentration obtained through analysis due to the effects of analytical accuracy. For example, if the concentration of element M is low, the concentration of element M obtained through analysis may be lower than the actual concentration.

[0077] Examples of crystalline structures for oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), single crystal, and polycrystalline. The oxide semiconductor 230 (particularly oxide semiconductor 230b) is preferably crystalline. For example, CAAC-OS can be used as the oxide semiconductor 230.

[0078] CAAC-OS is a metal oxide with a highly crystalline, dense structure and low levels of impurities and defects (e.g., oxygen deficiencies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0079] Furthermore, it is difficult to identify clear grain boundaries in CAAC-OS. In other words, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0080] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, the extraction of oxygen from the oxide semiconductor 230 by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide semiconductor 230 is reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0081] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities such as hydrogen and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near oxygen vacancies can cause V ＯH can be formed, generating electrons that act as carriers. Therefore, if oxygen vacancies and hydrogen are present in the channel formation region of an oxide semiconductor, the transistor is likely to exhibit normally-on characteristics (a characteristic in which a channel exists and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V are present. Ｏ It is preferable that H is reduced as much as possible. In other words, it is preferable that the channel-forming region in the oxide semiconductor has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0082] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing a heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V Ｏ H can be reduced. Furthermore, an insulator having a barrier property against hydrogen is formed near the transistor 200, and V in the channel formation region of the oxide semiconductor 230 and its vicinity is reduced. Ｏ It is preferable to reduce H.

[0083] Preferably, at least one of insulators 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulator against hydrogen. Furthermore, preferably at least one of insulators 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulator against impurities. Also, preferably at least one of insulators 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulator against oxygen. Note that it is not necessarily required to provide all of insulators 212, 214, 221, 222, 275, 282, and 283. If sufficient barrier properties are provided against hydrogen, impurities, oxygen, etc., the insulators can be appropriately selected from insulators 212, 214, 221, 222, 275, 282, and 283 to form the structure. For example, the insulator 214 can be omitted, and the insulator 216 and conductor 205 can be placed in contact with the upper surface of the insulator 212.

[0084] In this specification, a barrier insulator refers to an insulator that has barrier properties. In this specification, having barrier properties means having the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). Alternatively, it means having the function of capturing or fixing the corresponding substance internally (also called gettering). When hydrogen is described as the corresponding substance, for example, hydrogen atoms, hydrogen molecules, and water molecules and OH − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when an impurity is listed as a corresponding substance, unless otherwise specified, it refers to an impurity in the channel-forming region or semiconductor layer, such as a hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ２ O, NO, NO ２It refers to at least one substance, such as a copper atom. Furthermore, when oxygen is listed as a corresponding substance, it refers to at least one substance, such as an oxygen atom or an oxygen molecule.

[0085] As an insulator that has the function of suppressing hydrogen diffusion, it is preferable to use, for example, silicon nitride or silicon nitride oxide. In addition, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, etc. may also be used.

[0086] In this specification, "oxide nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0087] It is preferable to use insulators 212, 221, 275, and 283 that have the function of suppressing hydrogen diffusion. For example, silicon nitride with higher hydrogen barrier properties may be used for insulators 212, 221, 275, and 283.

[0088] As an insulator having the function of capturing or fixing hydrogen, it is preferable to use metal oxides such as hafnium oxide, aluminum oxide, aluminum and hafnium oxide (hafnium aluminate), or magnesium oxide. The insulator having the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides having such an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen. By adding silicon to the above metal oxide, polycrystallization can be suppressed and it can be made more amorphous. Therefore, it is preferable to use metal oxides to which silicon has been added (for example, hafnium silicate, aluminum silicate, etc.).

[0089] It is preferable to use insulators 214, 222, and 282 that have the function of capturing or fixing hydrogen. For example, aluminum oxide may be used for insulators 214 and 282. Furthermore, for example, it is preferable to use hafnium oxide, which is a high dielectric constant (high-k) material, for insulator 222 that functions as a second gate insulator.

[0090] Furthermore, the inorganic insulators listed as having the function of suppressing hydrogen diffusion, and those having the function of capturing or fixing hydrogen, also possess barrier properties against oxygen.

[0091] As shown in Figure 2A, it is preferable to provide an insulator 212 having the function of suppressing hydrogen diffusion and an insulator 214 having the function of capturing or fixing hydrogen below the transistor 200. By providing the insulator 212 below the transistor 200, the diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Furthermore, by providing the insulator 214 on top of the insulator 212, hydrogen contained in the insulator 216 and the like can be captured or fixed to the insulator 214. This makes it possible to reduce the hydrogen concentration in and near the oxide semiconductor 230.

[0092] Furthermore, as shown in Figure 2A, it is preferable to provide an insulator 221 having the function of suppressing hydrogen diffusion and an insulator 222 having the function of capturing or fixing hydrogen below the transistor 200. By providing the insulator 221 below the transistor 200, the diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Also, by providing the insulator 222 on top of the insulator 221, hydrogen contained in the insulator 224 and the like can be captured or fixed to the insulator 222. This makes it possible to reduce the hydrogen concentration in the oxide semiconductor 230 and its vicinity.

[0093] Furthermore, as shown in Figure 2A, it is preferable to provide an insulator 275 to cover the oxide semiconductor 230, conductor 242a, conductor 242b, etc. By providing the insulator 275 in this way, it is possible to suppress the diffusion of hydrogen from the insulator 280 to the oxide semiconductor 230, conductor 242a, conductor 242b, etc.

[0094] Furthermore, as shown in Figure 2A, it is preferable to provide an insulator 282 having the function of capturing or fixing hydrogen, and an insulator 283 having the function of suppressing hydrogen diffusion, on top of the transistor 200. By providing the insulator 283 on top of the transistor 200, the diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Also, by providing the insulator 282 below the insulator 283, hydrogen contained in the insulator 280 and the like can be captured or fixed to the insulator 282. This makes it possible to reduce the hydrogen concentration in the oxide semiconductor 230 and its vicinity.

[0095] In this way, by surrounding the top and bottom of the transistor 200 with a barrier insulator against hydrogen, the diffusion of hydrogen into the oxide semiconductor is reduced, and the V in the channel formation region is reduced. Ｏ This allows for a reduction in H. This, in turn, improves the electrical characteristics and reliability of transistor 200.

[0096] Furthermore, it is preferable to include oxygen that is desorbed by heating in the insulator 280. By supplying this oxygen to the oxide semiconductor 230 via the insulator 250 through the heat treatment, oxygen vacancies in the channel formation region can be reduced. Similarly, it is preferable to include oxygen that is desorbed by heating in the insulator 224. This allows oxygen to be supplied from the insulator 224 to the oxide semiconductor 230, further reducing oxygen vacancies in the channel formation region.

[0097] In this embodiment, oxygen can be added to the insulator 280 by forming the insulator 282 using a sputtering method in an atmosphere containing oxygen gas.

[0098] As described above, by heat-treating the insulator 280, which contains oxygen that is desorbed by heating, oxygen can be supplied to the oxide semiconductor 230 via the insulator 250. In this heat-treating process, since insulators 282 and 283, which have barrier properties against oxygen, are formed on the insulator 280, it is possible to prevent excessive diffusion of oxygen contained in the insulator 280 from the insulator 280.

[0099] If an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current or field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface can lead to variations in the characteristics of the semiconductor device containing the transistor. In addition, if the amount of oxygen supplied from the insulator to the oxide semiconductor becomes excessively large, it may adversely affect the electrical characteristics and reliability of the transistor. Moreover, oxygen may diffuse into conductors such as the gate electrode, source electrode, and drain electrode, causing oxidation of these conductors and impairing their conductivity.

[0100] In contrast, since an insulator 275 having barrier properties against oxygen is formed between the insulator 280 and the oxide semiconductor 230, conductor 242a, and conductor 242b, it is possible to prevent the oxygen contained in the insulator 280 from excessively diffusing into the oxide semiconductor 230, conductor 242a, and conductor 242b. Furthermore, by performing the heat treatment with openings formed in parts of the insulators 280, 282, and 283, it is possible to diffuse some of the oxygen contained in the insulator 280 outward and adjust the amount of oxygen supplied from the insulator 280 to the oxide semiconductor 230.

[0101] Here, it is preferable that the insulator 250 is configured to diffuse oxygen from the insulator 280 to the oxide semiconductor 230 and to suppress oxidation of the conductors 242a, 242b, and 260.

[0102] As shown in Figures 1B and 1C, the insulator 250 is placed within the openings formed in the insulators 280 and 275. Within these openings, the insulator 250 is formed in contact with the upper surface of the insulator 222, the side surface of the insulator 224, the side and upper surface of the oxide semiconductor 230b, the side surface of the conductor 242a1, the side surface of the conductor 242b1, and the side surface of the insulator 255.

[0103] Here, as shown in Figure 2A, it is preferable that the insulator 250 has a laminated structure consisting of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c.

[0104] It is preferable to use silicon oxide or silicon oxynitride, which have a high dielectric strength, for the insulator 250b. Furthermore, in order to improve the dielectric strength, the film thickness of insulator 250b may be greater than that of insulators 250a and 250d. By using such an oxide insulator, oxygen can be diffused in insulator 250b by performing a high-temperature heat treatment. Therefore, by performing the heat treatment, oxygen contained in insulator 280 can be supplied to the oxide semiconductor 230 via insulator 250b.

[0105] To suppress excessive oxidation of conductors 242a1, 242b1, and 260, it is preferable to provide oxygen barrier insulators near each of them. For example, it is preferable that insulators 250a and 250d are made of insulating materials that have oxygen barrier properties.

[0106] The insulator 250a preferably has barrier properties against oxygen. Preferably, the insulator 250a is less permeable to oxygen than at least the insulator 250b. The insulator 250a has regions that are in contact with the side surfaces of the conductor 242a1 and the conductor 242b1. The oxygen barrier properties of the insulator 250a suppress the excessive oxidation of the side surfaces of the conductor 242a1 and the conductor 242b1, and the formation of an oxide film on those side surfaces. This suppresses a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. Furthermore, with this configuration, the amount of oxygen in the insulator 250b absorbed by the conductor 242a1 and the conductor 242b1 can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulator 250b to the oxide semiconductor 230, and oxygen deficiencies in the channel formation region of the oxide semiconductor 230 can be reduced.

[0107] Furthermore, by providing an insulator 250a between the insulator 280 and the insulator 250b, and between the insulator 250b and the oxide semiconductor 230, it is possible to suppress the excessive supply of oxygen from the insulator 280 to the oxide semiconductor 230 and supply an appropriate amount of oxygen to the oxide semiconductor 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor 230 and its vicinity can be controlled to an appropriate amount, thereby preventing an excessive positive shift in the threshold voltage of the transistor 200 and improving reliability. In addition, it is possible to suppress excessive oxidation of the source region and drain region, which can cause a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0108] Therefore, it is preferable that the insulator 250a has a film thickness that does not excessively hinder the diffusion of oxygen from the insulator 280 to the insulator 250b, and from the insulator 250b to the oxide semiconductor 230. For example, the film thickness of the insulator 250a is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and less than 3.0 nm, and even more preferably 0.5 nm or more and 2.0 nm or less.

[0109] As described above, it is preferable to allow for a moderate amount of oxygen diffusion from the insulator 280 to the insulator 250b and from the insulator 250b to the oxide semiconductor 230, while suppressing the diffusion of oxygen from the insulator 250b to the conductors 242a1 and 242b1 as much as possible. In this embodiment of the semiconductor device, the contact area between the insulator 250a and the conductor 242a1, and the contact area between the insulator 250a and the conductor 242b1 are much smaller than the contact area between the insulator 250a and the oxide semiconductor 230. In other words, it is presumed that the amount of oxygen that diffuses from the insulator 250b to the conductors 242a1 and 242b1 via the insulator 250a is less than the amount of oxygen that diffuses from the insulator 250b to the oxide semiconductor 230 via the insulator 250a. Therefore, by controlling the amount of oxygen contained in the insulator 280 and ensuring that a suitable amount of oxygen is supplied from the insulator 280 to the insulator 250b and the oxide semiconductor 230, excessive oxidation of the conductor 242a1 and conductor 242b1 can be reduced.

[0110] The insulator 250a in contact with the channel formation region in the oxide semiconductor 230 preferably has the function of capturing or fixing hydrogen. This makes it possible to reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Ｏ By reducing H, the channel-forming region can be made i-type or substantially i-type.

[0111] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 250a. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material as the insulator 250a, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also becomes possible to thin the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator. In this embodiment, a hafnium oxide film is used as the insulator 250a. Hafnium oxide has the function of capturing or fixing hydrogen and has barrier properties against oxygen, making it suitable for use as the insulator 250a.

[0112] It is preferable that the insulator 250d also has barrier properties against oxygen. The insulator 250d is provided between the channel-forming region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With this configuration, it is possible to suppress the diffusion of oxygen contained in the channel-forming region of the oxide semiconductor 230 into the conductor 260, thereby preventing the formation of oxygen vacancies in the channel-forming region of the oxide semiconductor 230. Furthermore, it is possible to suppress the diffusion of oxygen contained in the oxide semiconductor 230 and the oxygen contained in the insulator 280 into the conductor 260, thereby preventing the oxidation of the conductor 260. It is preferable that the insulator 250d is at least less permeable to oxygen than the insulator 250b. It is also preferable that the insulator 250d has a function to suppress the diffusion of hydrogen. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230. For example, it is preferable to use a silicon nitride film as the insulator 250d.

[0113] Furthermore, as shown in Figure 2A, it is preferable to have a structure in which an insulator 250c is provided on top of the insulator 250b. In this case, the insulator 250c can be an insulator that can be used for insulator 250a. For example, hafnium oxide can be used as the insulator 250c. By providing the insulator 250c between the insulator 250d and the insulator 250b, hydrogen contained in the insulator 250b and the like can be captured and fixed more effectively.

[0114] By adopting the above configuration, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with good electrical characteristics. Furthermore, with the above configuration, good electrical characteristics can be maintained even when the semiconductor device is miniaturized or highly integrated. In addition, the frequency characteristics can be improved by miniaturizing the transistor 200. Specifically, the cutoff frequency can be improved.

[0115] The insulators 250a to 250d function as part of the first gate insulator. The insulators 250a to 250d are provided together with the conductor 260 in the opening formed in the insulator 280. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulators 250a, 250c, and 250d be thin. The film thickness of the insulators 250a, 250c, and 250d is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that the insulators 250a, 250c, and 250d each only need to have a region with the above-mentioned film thickness in at least a part of it.

[0116] To make the film thickness of insulators 250a to 250d as described above, it is preferable to deposit the film using the atomic layer deposition (ALD) method. Furthermore, in order to form insulators 250a to 250d with good coverage within openings such as insulator 280, it is preferable to deposit the film using the ALD method.

[0117] In the above description, the insulator 250 has been described as having a four-layer structure of insulators 250a to 250d, but the present invention is not limited to this. The insulator 250 can have a configuration having at least one of the insulators 250a to 250d. By configuring the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0118] Furthermore, as shown in Figure 1C, the channel formation region of the oxide semiconductor 230 is enclosed by insulators 250, 224, 222, and 221. By using silicon nitride, which has high hydrogen barrier properties, for the outer insulators 250d and 221, the diffusion of hydrogen into the oxide semiconductor 230 can be prevented. Furthermore, by using hafnium oxide, which can capture or fix hydrogen, for the inner insulators 250c and 222, hydrogen in the region enclosed by insulators 250d and 221 can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor 230. Furthermore, by using silicon oxide, which can supply oxygen, for the inner insulators 250b and 224, oxygen vacancies in the oxide semiconductor 230 can be reduced. As a result, the purity of the channel formation region of the oxide semiconductor 230 can be increased. Therefore, a transistor with good electrical characteristics and reliability can be provided.

[0119] In transistor 200, the conductor 205 is arranged to overlap with the oxide semiconductor 230 and the conductor 260. The conductive material described in the section "Conductive Material" can be used for the conductor 205. Here, it is preferable that the conductor 205 is provided so as to be embedded in an opening formed in the insulator 216. Furthermore, it is preferable that the conductor 205 extends in the channel width direction, as shown in Figures 1A and 1C. With this configuration, when multiple transistors are provided, the conductor 205 functions as wiring.

[0120] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260, without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 reduces the drain current when the potential applied to the conductor 260 is 0V compared to not applying a negative potential.

[0121] Furthermore, the electrical resistivity of the conductor 205 is set considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as the design of the conductor 205 allows. By making the film thickness of the insulator 216 thin, the amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby suppressing the diffusion of such impurities into the oxide semiconductor 230.

[0122] As shown in Figure 2A, it is preferable that the conductor 205 has a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening. Here, it is preferable that the height of the upper surface of the conductor 205 matches or approximately matches the height of the upper surface of the insulator 216.

[0123] Here, the conductor 205a contains oxygen (for example, at least one such as an oxygen atom and an oxygen molecule), hydrogen (for example, at least one such as a hydrogen atom and a hydrogen molecule), water molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable to have a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Examples of conductive materials that have the function of suppressing the diffusion of such impurities include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can be a single-layer structure or a laminated structure of the above conductive material. For example, it is preferable that the conductor 205a has titanium nitride.

[0124] By using a conductive material for the conductor 205a that has the function of reducing hydrogen diffusion, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide semiconductor 230 via the insulator 216, etc. Furthermore, by using a conductive material for the conductor 205a that has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity.

[0125] Although Figure 2A shows a laminated structure of conductor 205a and conductor 205b, the present invention is not limited thereto, and the conductor 205 may be a single layer or a laminated structure of three or more layers. For example, the conductor 205a may be a laminated structure using tantalum or tantalum nitride, which have relatively high hydrogen barrier properties. In this case, the conductor 205a can be a laminated film of a tantalum nitride film and a titanium nitride film on the tantalum nitride film. Alternatively, the conductor 205a can be a laminated film of a tantalum nitride film, a tantalum film on the tantalum nitride film and a titanium nitride film on the tantalum film.

[0126] By using the above configuration, it is possible to prevent impurities such as hydrogen and metallic impurities such as copper contained in the lower layer of transistor 200 from diffusing into conductor 205. Furthermore, it is possible to prevent impurities such as hydrogen and metallic impurities such as copper contained in the lower layer of transistor 200 from diffusing into oxide semiconductor 230 via conductor 205.

[0127] Insulator 224 functions as a second gate insulator together with insulators 221 and 222.

[0128] The insulator 224 in contact with the oxide semiconductor 230 is preferably made of, for example, silicon oxide or silicon oxynitride. This allows oxygen to be supplied from the insulator 224 to the oxide semiconductor 230, thereby reducing oxygen vacancies. Alternatively, the insulator 224 may be made of, for example, gallium oxide. By including gallium, which has a strong bonding force with oxygen, insulator 224 can suppress oxygen vacancies at the interface with the oxide semiconductor 230. The insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials.

[0129] Furthermore, it is preferable that the insulator 224 be processed into an island shape, similar to the oxide semiconductor 230. This ensures that when multiple transistors 200 are provided, each transistor 200 has an insulator 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 in each transistor 200 is approximately the same. Therefore, variations in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0130] Conductive materials described in the section "Conductive Materials" can be used for conductors 242a and 242b. It is preferable to use conductive materials that are resistant to oxidation as conductors 242a and 242b. Examples of such conductive materials include conductive oxides and conductive nitrides. By using these, it is possible to suppress excessive oxidation of conductors 242a and 242b, which would reduce the conductivity of conductors 242a and 242b.

[0131] As shown in Figure 2A and the like, it is preferable that the conductor 242a and the conductor 242b each have a laminated structure of two or more layers. The conductor 242a has a laminated structure of conductor 242a1 and conductor 242a2 on conductor 242a1. The conductor 242b has a laminated structure of conductor 242b1 and conductor 242b2 on conductor 242b1. The conductors 242a1 and conductor 242b1 are provided in contact with the upper surface of the oxide semiconductor 230b. Conductor 242a2 is provided in contact with a part of conductor 242a1, and conductor 242a2 is provided in contact with a part of conductor 242b1. In addition, an insulator 255 is provided in contact with another part of conductor 242a1 and another part of conductor 242b1.

[0132] It is preferable to use conductive materials that are resistant to oxidation as the conductors 242a1 and 242b1 that are in contact with the oxide semiconductor 230b. This suppresses excessive oxidation of the conductors 242a and 242b, which reduces their conductivity. It also suppresses the extraction of oxygen from the oxide semiconductor 230b, which prevents the formation of an excessive amount of oxygen deficiency.

[0133] For example, as conductors 242a1 and 242b1, indium tin oxide (In-Sn oxide, also known as ITO), silicon-containing ITO (In-Sn-Si oxide, also known as ITSO), indium zinc oxide (In-Zn oxide, also known as IZO®), indium titanium oxide (In-Ti oxide), ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., can be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, because these materials are conductive metal oxides, the contact resistance between conductor 242a and oxide semiconductor 230, and the contact resistance between conductor 242b and oxide semiconductor 230 can be reduced. By using such a structure, the on-current of the transistor 200 can be increased.

[0134] Furthermore, it is preferable to use metal nitrides as conductors 242a1 and 242b1, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing titanium and aluminum, etc. For example, tantalum nitride can be used as conductors 242a1 and 242b1.

[0135] Furthermore, it is preferable that conductors 242a2 and 242b2 have higher conductivity than conductors 242a1 and 242b1. For example, it is preferable to make the film thickness of conductors 242a2 and 242b2 greater than the film thickness of conductors 242a1 and 242b1. As conductors 242a2 and 242b2, any conductor that can be used for conductor 205b may be used. For example, tungsten can be used as conductors 242a2 and 242b2. By adopting the above structure, the resistance of conductors 242a2 and 242b2 can be reduced. This makes it possible to improve the operating speed of the semiconductor device according to this embodiment.

[0136] As shown in Figures 1B and 1C, the insulator 255 is positioned inside an opening formed in the insulator 280, etc., and is in contact with the lower surface of the insulator 282, the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, and the upper surface of the insulator 222. Also, as shown in Figure 1C, a portion of the insulator 255 may be formed in contact with the side surface of the oxide semiconductor 230 and the side surface of the insulator 224. In Figure 1C, a portion of the insulator 255 covers the side surface of the oxide semiconductor 230 and the side surface of the insulator 224, but it is not limited to this, and the insulator 255 may also be formed in contact with a portion of the side surface of the oxide semiconductor 230 and a portion of the side surface of the insulator 224. Furthermore, there are cases where a portion of the insulator 255 is not formed on the side surface of the oxide semiconductor 230 and the side surface of the insulator 224.

[0137] As shown in Figures 1A to 1C, the insulators 255 and 250 are provided in accordance with the shape of the opening provided in the insulator 280. Therefore, the insulator 255 is provided so as to cover the side wall of the opening, and the insulator 250 is provided so as to cover the bottom of the opening and the insulator 255.

[0138] The insulator 255 is preferably made of an insulating material with a low dielectric constant, such as silicon nitride, silicon oxide, or aluminum oxide. For example, silicon nitride deposited by the PEALD method can be used as the insulator 255. However, it is not limited to this, and insulating materials described in the section "<<Insulator>>" below can be used. For example, insulating materials that can be used for interlayer insulating films such as the insulator 280 can also be used. With this configuration, the insulator 250 and the insulator 255 can be provided between the conductor 260 and the conductor 242a, and between the conductor 260 and the conductor 242b. Therefore, the parasitic capacitance between the conductor 260 and the conductor 242a, and between the conductor 260 and the conductor 242b can be reduced. In addition, the leakage current between the conductor 260 and the conductor 242a, and between the conductor 260 and the conductor 242b can be reduced.

[0139] Furthermore, an insulating material having barrier properties against oxygen can be provided as the insulator 255. For example, silicon nitride, aluminum oxide, etc., can be used. For example, silicon nitride deposited by the PEALD method can be used as the insulator 255. However, it is not limited to this, and insulating materials described in the section "<<Insulator>>" described later can be used. For example, insulating materials with high barrier properties that can be used for insulators 250a, insulators 250c, insulators 250d, etc., can also be used. With this configuration, the sides of the conductor 242a2 and the sides of the conductor 242b2 can be protected by the insulator 255. Therefore, excessive oxidation of the sides of the conductor 242a2 and the sides of the conductor 242b2 can be suppressed.

[0140] For example, the film thickness of the insulator 255 can be 0.5 nm to 20 nm, 0.5 nm to 10 nm, or 1 nm to 5 nm. By making the insulator 255 to the above film thickness and forming the insulator 255 and conductor 260 in the opening of the insulator 280, the width of the gate electrode of the transistor 200 can be made smaller than the width of the opening of the insulator 280. The insulator 255 only needs to have a region with the above film thickness in at least a part of it. Also, since the insulator 255 is provided in contact with the side wall of the opening formed in the insulator 280, it is preferable to deposit it using a method with good coverage, such as the ALD method. If the film thickness of the insulator 255 is made excessively thick, the film deposition time for the insulator 255 by the ALD method will be longer and productivity will decrease, so it is preferable to keep the film thickness of the insulator 255 within the above range. Note that the film thickness of the insulator 255 is not limited to the above range. It can be set appropriately considering the design values ​​of the transistor 200, etc.

[0141] Furthermore, unlike the structure shown in Figure 2A, etc., the film thickness of the portion of the conductor 242a1 that contacts the insulator 255 may be thinner than the film thickness of other portions, as shown in Figure 3A. Similarly, the film thickness of the portion of the conductor 242b1 that contacts the insulator 255 may be thinner than the film thickness of other portions. When forming the conductors 242a2 and 242b2, etching up to the top of the conductive film that will become the conductors 242a1 and 242b1 may result in the structure shown in Figure 3A. In this case, by increasing the film thickness of the conductive film that will become the conductors 242a1 and 242b1, it is possible to prevent the conductors 242a1 and 242b1 from being separated by etching when forming the conductors 242a2 and 242b2.

[0142] Furthermore, in the structure shown in Figure 2A, the sides of the conductor 242a2 and the insulator 280, and the sides of the conductor 242b2 and the insulator 280 are flush, but the present invention is not limited to this. As shown in Figure 3B, the distance between the conductor 242a2 and the insulator 250, and the distance between the conductor 242b2 and the insulator 250 are also greater than the distance between the insulator 280 and the insulator 250. For example, by selectively side-etching the sides of the conductor 242a2 and the conductor 242b2, the sides of the conductor 242a2 and the conductor 242b2 can be set back relative to the sides of the insulator 280.

[0143] In this case, it is preferable that an insulator 255 is also formed in the region surrounded by the conductor 242a1, the conductor 242a2, and the insulator 271a. Furthermore, it is preferable that an insulator 255 is also formed in the region surrounded by the conductor 242b1, the conductor 242b2, and the insulator 271b.

[0144] By adopting the structure shown in Figure 3B, the distance L1 between conductor 242a2 and conductor 242b2 can be made larger than the distance L1 shown in Figure 2A. Therefore, the parasitic capacitance between conductor 260 and conductor 242a2, and the parasitic capacitance between conductor 260 and conductor 242b2 can be further reduced. In addition, the leakage current between conductor 260 and conductor 242a2, and the leakage current between conductor 260 and conductor 242b2 can be further reduced.

[0145] Furthermore, as shown in Figure 3C, an oxide 243a may be formed between the conductor 242a2 and the insulator 255, and an oxide 243b may be formed between the conductor 242b2 and the insulator 255. In this case, the insulator 255 and the conductors 242a2 and 242b2 will not be in contact. It is preferable that the oxide 243a is formed in the region surrounded by the insulator 255, the conductors 242a1, conductors 242a2, and the insulator 271a. It is also preferable that the oxide 243b is formed in the region surrounded by the insulator 255, the conductors 242b1, conductors 242b2, and the insulator 271b. In Figure 3C, the sides of oxide 243a and oxide 243b are shown flush with the side of the insulator 280, but the present invention is not limited to this. The sides of oxide 243a and oxide 243b may protrude from the side of the insulator 280. Alternatively, the sides of oxides 243a and 243b may be recessed relative to the sides of the insulator 280.

[0146] The oxides 243a and 243b are preferably insulating and have lower conductivity than at least the conductors 242a2 and 242b2. For example, by selectively oxidizing the sides of the conductor 242a2 and the conductor 242b2, oxide 243a can be formed in contact with the side of the conductor 242a2, and oxide 243b can be formed in contact with the side of the conductor 242b2. In this case, oxide 243a becomes an oxide of the conductor 242a2, and therefore oxide 243a contains the metal elements contained in the conductor 242a2. Similarly, oxide 243b contains the metal elements contained in the conductor 242b2.

[0147] By adopting the structure shown in Figure 3C, the distance between conductor 242a2 and conductor 260 can be increased by the amount of oxide 243a. Also, the distance between conductor 242b2 and conductor 260 can be increased by the amount of oxide 243b. Therefore, the parasitic capacitance between conductor 260 and conductor 242a2, and between conductor 260 and conductor 242b2 can be further reduced. Furthermore, the leakage current between conductor 260 and conductor 242a2, and between conductor 260 and conductor 242b2 can be further reduced.

[0148] In the structure shown in Figure 3B, etc., the insulator 255 is arranged in contact with the upper surface of the conductor 242a1 and the upper surface of the conductor 242b1, but the present invention is not limited thereto. As shown in Figure 4A, the insulator 255 may be arranged in contact with the upper surface of the oxide semiconductor 230. In the structure shown in Figure 4A, the insulator 255 is in contact with a part of the upper surface of the oxide semiconductor 230, another part of the upper surface of the conductor 242a1, a side surface of the conductor 242a1, another part of the upper surface of the conductor 242b1, a side surface of the conductor 242b1, a side surface of the conductor 242a2, and a side surface of the conductor 242b2.

[0149] As shown in Figure 4A, the film thickness of the oxide semiconductor 230 in the region overlapping with the insulator 250 may be thinner than the film thickness of the oxide semiconductor 230 in the region in contact with the insulator 255. Furthermore, the film thickness of the oxide semiconductor 230 in the region in contact with the insulator 255 may be thinner than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductors 242a1 and 242b1.

[0150] By using the structure shown in Figure 4A, an insulator 255 can be placed between the conductor 242a1 and the insulator 250, and between the conductor 242b1 and the insulator 250. This allows the distance between the conductor 242a1 and the conductor 260, and the distance between the conductor 242b1 and the conductor 260 to be increased. Therefore, the parasitic capacitance between the conductor 260 and the conductor 242a, and the parasitic capacitance between the conductor 260 and the conductor 242b can be further reduced. In addition, the leakage current between the conductor 260 and the conductor 242a, and the leakage current between the conductor 260 and the conductor 242b can be further reduced.

[0151] In addition, in the structure shown in Figure 4A, the insulators 255, 250, and 260 may also reflect the shape in which the side surface of the conductor 242a2 is recessed relative to the side surface of the insulator 280, and the side surface of the conductor 242b2 is recessed relative to the side surface of the insulator 280.

[0152] Furthermore, in the structure shown in Figure 4A, the conductor 242a1 is formed to protrude from the conductor 242a2, and the conductor 242b1 is formed to protrude from the conductor 242b2, but the present invention is not limited to this. As shown in Figure 4B, the conductors 242a1 and 242b1 can also be formed to be recessed relative to the side surface of the insulator 280, similar to the conductors 242a2 and 242b2. In the structure shown in Figure 4B, the insulator 255 is in contact with a part of the upper surface of the oxide semiconductor 230, the side surface of the conductor 242a1, the side surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. In this case, the side surface of the conductor 242a1 and the side surface of the conductor 242a2 may be flush, and the side surface of the conductor 242b1 and the side surface of the conductor 242b2 may be flush. In this specification, "symmetrical" refers to a state in which two surfaces are on the same plane or substantially on the same plane.

[0153] For example, by side etching the sides of conductor 242a1 and conductor 242b1, similar to the sides of conductor 242a2 and conductor 242b2, it is possible to create a shape in which the sides of conductor 242a1, conductor 242b1, conductor 242a2, and conductor 242b2 are recessed relative to the sides of the insulator 280.

[0154] By adopting the structure shown in Figure 4B, the distance between conductor 242a1 and conductor 260, and the distance between conductor 242b1 and conductor 260 can be made larger than in the structure shown in Figure 4A. Therefore, the parasitic capacitance between conductor 260 and conductor 242a, and the parasitic capacitance between conductor 260 and conductor 242b can be further reduced. In addition, the leakage current between conductor 260 and conductor 242a, and the leakage current between conductor 260 and conductor 242b can be further reduced.

[0155] Furthermore, in the structure shown in Figure 2A, the insulator 255 is a single layer, but the present invention is not limited to this, and the insulator 255 can also be a laminated structure of two or more layers. In this case, it is preferable that at least one layer is an insulator with the low dielectric constant mentioned above. For example, as shown in Figure 5A, the insulator 255 can also be a two-layer structure of insulator 255a and insulator 255b on top of insulator 255a. This can also be viewed as a structure in which insulator 255b is arranged inside insulator 255a. Thus, insulator 255a is in contact with the upper surface of conductor 242a1, the upper surface of conductor 242b1, the side surface of conductor 242a2, the side surface of conductor 242b2, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of insulator 275, and the side surface of insulator 280. Insulator 255b is in contact with the side surface of insulator 250. The lower surface of insulator 255b may be in contact with insulator 255a. For example, an oxide insulator such as silicon oxide can be used for insulator 255a, and an insulator with high oxygen barrier properties such as silicon nitride can be used for insulator 255b. It is preferable that insulator 255a has a lower dielectric constant than insulator 255b.

[0156] By arranging the insulator 255a, which has an oxide insulator such as silicon oxide, in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, the side surfaces of the conductor 242a2 and the conductor 242b2 can be oxidized relatively easily. Therefore, similar to the structure shown in Figure 3C, oxide can be formed between the conductor 242a2 and the insulator 255a, and between the conductor 242b2 and the insulator 255a. Furthermore, by providing silicon nitride or the like as the insulator 255b, it is possible to prevent an excess amount of oxygen in the insulator 255 from being supplied to the oxide semiconductor 230 via the insulator 250. This makes it possible to suppress the reduction of the on-current of the transistor 200.

[0157] Although Figure 5A shows a configuration in which the insulator 255a is placed on the outside and the insulator 255b is placed on the inside, the present invention is not limited to this. For example, it is also possible to have a configuration in which the insulator 255b, which has high oxygen barrier properties, is placed on the outside and the insulator 255a, which has an oxide insulator, is placed on the inside. In this case, the lower surface of the insulator 255a may be in contact with the insulator 255b.

[0158] Furthermore, in the transistor 200 shown in Figure 2A, the opposing sides of conductor 242a1 and conductor 242b1, and the opposing sides of conductor 242a2 and conductor 242b2 are perpendicular or approximately perpendicular to the upper surface of the oxide semiconductor 230b, but the present invention is not limited thereto. For example, as shown in Figure 5B, the opposing sides of conductor 242a1 and conductor 242b1, and the opposing sides of conductor 242a2 and conductor 242b2 may be tapered. In this case, the sides of insulator 271a, insulator 271b, insulator 275, and insulator 280 may be tapered. Note that in Figure 5B, the taper angles of insulator 280, insulator 275, insulator 271a, insulator 271b, conductor 242a2, and conductor 242b2 are equal, but the invention is not limited thereto, and their respective taper angles may be different. For example, the taper angles of the conductors 242a1 and 242b1 may be acuter than the taper angles of the conductors 242a2 and 242b2.

[0159] Furthermore, as shown in Figure 5C, the upper part of the side surface of the insulator 255 may have a curved shape. Also, as shown in Figure 5C, the upper part of the insulator 280 may also have a curved shape that is continuous with or substantially continuous with the curved shape of the side surface of the insulator 255. Here, the insulator 250 may be in contact with the curved parts of the upper part of the insulator 255 and the upper part of the insulator 280.

[0160] Furthermore, as shown in Figure 6A, the structure shown in Figure 4A, like the structure shown in Figure 5C, can also have curved surfaces on the upper parts of the insulators 255 and 280. In addition, the sides of the conductor 242a2, conductor 242b2, conductor 242a1, conductor 242b1, and the recesses on the upper surface of the oxide semiconductor 230b can also have curved surfaces. In this case, the curved surfaces of the side of the conductor 242a1 and the recesses on the upper surface of the oxide semiconductor 230b may be continuous or approximately continuous. Similarly, the curved surfaces of the side of the conductor 242b1 and the recesses on the upper surface of the oxide semiconductor 230b may be continuous or approximately continuous.

[0161] Furthermore, as shown in Figure 6B, the structure shown in Figure 4B, like the structure shown in Figure 5C, can also have curved surfaces on the upper parts of the insulators 255 and 280. In addition, the sides of the conductor 242a2, conductor 242b2, conductor 242a1, conductor 242b1, and the recesses on the upper surface of the oxide semiconductor 230b can also have curved surfaces. In this case, the curved surfaces of the sides of the conductor 242a2, conductor 242a1, and the recesses on the upper surface of the oxide semiconductor 230b may be continuous or approximately continuous. Similarly, the curved surfaces of the sides of the conductor 242b2, conductor 242b1, and the recesses on the upper surface of the oxide semiconductor 230b may be continuous or approximately continuous.

[0162] Insulators 271a and 271b are inorganic insulators that function as etching stoppers during processing of conductors 242a2 and 242b2, protecting them. Furthermore, since insulator 271a is in contact with conductor 242a2 and insulator 271b is in contact with conductor 242b2, it is preferable that insulators 271a and 271b are inorganic insulators that do not easily oxidize conductors 242a2 and 242b2. Therefore, as shown in Figure 2A, it is preferable that insulator 271a has a laminated structure of insulator 271a1 and insulator 271a2 on insulator 271a1, and insulator 271b has a laminated structure of insulator 271b1 and insulator 271b2 on insulator 271b1. Here, it is preferable to use nitride insulators that can be used for insulator 250d for insulators 271a1 and 271b1 so as to prevent oxidation of conductors 242a2 and 242b2. Furthermore, it is preferable to use oxide insulators that can be used for insulator 250b for insulators 271a2 and 271b2 so as to function as etching stoppers.

[0163] Here, insulator 271a1 is in contact with the upper surface of conductor 242a2 and a part of insulator 275, and insulator 271b1 is in contact with the upper surface of conductor 242b2 and a part of insulator 275. In addition, insulator 271a2 is in contact with the upper surface of insulator 271a1 and the lower surface of insulator 275, and insulator 271b2 is in contact with the upper surface of insulator 271b1 and the lower surface of insulator 275. For example, silicon nitride can be used as insulator 271a1 and insulator 271b1, and silicon oxide can be used as insulator 271a2 and insulator 271b2.

[0164] The insulators that form insulators 271a and 271b function as masks for the conductors that form conductors 242a2 and 242b2. As shown in Figure 1D, conductor 242b2 does not have a curved surface between its side and top surfaces. The same applies to conductor 242a2. As a result, the ends where the side and top surfaces of conductors 242a2 and 242b2 intersect are angular. The angular shape of the ends where the side and top surfaces of conductors 242a2 and 242b2 intersect increases the cross-sectional area of ​​conductors 242a2 and 242b2 compared to when these ends have a curved surface. Furthermore, by using nitride insulators that are less likely to oxidize metals for insulators 271a1 and 271b1, it is possible to prevent excessive oxidation of conductors 242a2 and 242b2. As a result of the above, the resistance of conductors 242a2 and 242b2 is reduced, making it possible to increase the on-current of the transistor.

[0165] The conductor 260 can be any conductive material as described in the section on "Conductors," similar to conductors 242a and 242b. It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function to suppress oxygen diffusion as the conductor 260. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This helps to suppress a decrease in the conductivity of the conductor 260.

[0166] As shown in Figures 1B and 1C, the conductor 260 is placed together with the insulators 250 and 255 within the openings formed in the insulators 280 and 275. Within these openings, the conductor 260 is provided so as to cover the upper surface of the insulator 222, the side surface of the insulator 224, and the side surface and upper surface of the oxide semiconductor 230, via the insulator 250. Also, as shown in Figure 1C, the conductor 260 may cover the insulator 255 that is in contact with the side surface of the insulator 224 and the side surface of the oxide semiconductor 230. Furthermore, the upper surface of the conductor 260 is positioned so that its height matches or approximately matches that of the upper end of the insulator 250, the upper end of the insulator 255, and the upper surface of the insulator 280.

[0167] In the opening where the conductor 260 and the insulator 250 are arranged, the side wall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or it may be tapered. By making the side wall tapered, the coverage of the insulator 250 provided in the opening of the insulator 280 is improved, and defects such as porosity can be reduced.

[0168] The conductor 260 functions as the first gate electrode of the transistor 200. Here, it is preferable that the conductor 260 extends in the channel width direction, as shown in Figures 1A and 1C. With this configuration, when multiple transistors are provided, the conductor 260 functions as wiring.

[0169] When the structure described above is adopted, as shown in Figure 1C, a curved surface may be present between the side surface and the top surface of the oxide semiconductor 230 in a cross-sectional view in the channel width direction of the transistor 200. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded). By adopting such a shape, the coverage of the oxide semiconductor 230 by the insulator 250 and the conductor 260 can be improved.

[0170] In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. By adopting an S-channel structure, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur.

[0171] By making the transistor 200 an S-channel structure as described above, the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said that it is essentially equivalent to a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making the transistor 200 an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be made the entire bulk. Therefore, it becomes possible to improve the current density flowing through the transistor, which can be expected to improve the transistor's on-current or increase its field-effect mobility.

[0172] In this embodiment, the insulator 224 is arranged in an island-like configuration. Therefore, as shown in Figure 1C, at least a portion of the lower surface of the conductor 260 can be positioned below the lower surface of the oxide semiconductor 230. This allows the conductor 260 to be positioned opposite the upper and side surfaces of the oxide semiconductor 230, so that the electric field of the conductor 260 can act on the upper and side surfaces of the oxide semiconductor 230. In this way, by arranging the insulator 224 in an island-like configuration, the transistor 200 can be made into an S-channel structure.

[0173] Although the transistor 200 shown in Figure 1C is an example of an S-channel structure, the semiconductor device of one aspect of the present invention is not limited to this. For example, the transistor structure that can be used in one aspect of the present invention may be one or more selected from the planar structure, Fin structure, and GAA structure.

[0174] As shown in Figure 2A, it is preferable to have a two-layer structure for the conductor 260. Here, it is preferable that the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is disposed in contact with the lower surface and side surface of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0175] The conductor 260a, like the conductor 205a, contains oxygen (for example, at least one such as an oxygen atom and an oxygen molecule), hydrogen (for example, at least one such as a hydrogen atom and a hydrogen molecule), water molecules, and nitrogen oxide molecules (N). ２ O, NO, NO ２ It is preferable to have a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Examples of conductive materials that have the function of suppressing the diffusion of such impurities include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0176] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b and the resulting decrease in conductivity due to oxygen contained in the insulator 280, etc. By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 260a, it is possible to prevent impurities such as hydrogen contained in the conductor 260b from diffusing into the oxide semiconductor 230 via the insulator 250.

[0177] Furthermore, it is preferable that the conductor 260a has a low hydrogen concentration. When forming a conductive film with a low hydrogen concentration as the conductor 260a, it is preferable to form the film using an ALD method with an inorganic precursor that does not contain hydrogen. For example, using TiCl as the precursor. ４ A titanium nitride film can be formed using the thermal ALD method.

[0178] In this way, by reducing the hydrogen concentration of the conductor 260a, the conductor 260a itself becomes a hydrogen source, and the diffusion of hydrogen into the oxide semiconductor 230 can be suppressed. As a result, the V in the oxide semiconductor 230 Ｏ This prevents the channel formation region from becoming n-type due to H. Therefore, the electrical characteristics of transistor 200 can be improved.

[0179] Furthermore, it is preferable to use a highly conductive material for the conductor 260b. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0180] It is preferable that insulators 216, 280, and 285 each have a lower dielectric constant than insulator 222. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0181] For example, it is preferable that insulators 216, 280, and 285 each contain one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids.

[0182] In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide-nitride, and silicon oxide with vacancies are especially preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0183] Furthermore, the upper surfaces of the insulator 216 and the insulator 280 may be flattened.

[0184] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, it is preferable that the insulator 280 has a silicon-containing oxide such as silicon oxide or silicon oxynitride.

[0185] Conductors 240a and 240b can be made from conductive materials as described in the section "Conductors". Also, as shown in Figure 2A, the upper surfaces of conductors 240a and 240b can be formed to coincide with or approximately coincide with the upper surface of the insulator 285. Also, as shown in Figure 2A, the lower part of conductor 240a (for example, conductor 240a1) may be formed to be embedded in conductor 242a2. Similarly, the lower part of conductor 240b (for example, conductor 240b1) may be formed to be embedded in conductor 242b2.

[0186] Conductors 240a and 240b are formed by being embedded in openings formed in the surface to be formed. For this reason, it is preferable that these conductors have a laminated structure consisting of a rod-shaped conductor with good conductivity and embedding properties, and a film-like conductor that has good adhesion to the rod-shaped conductor and is formed to cover the openings well. As shown in Figure 2A, it is preferable that conductor 240a has a conductor 240a2 and a conductor 240a1 that is in contact with the side and bottom surfaces of conductor 240a2. It is also preferable that conductor 240b has a conductor 240b2 and a conductor 240b1 that is in contact with the side and bottom surfaces of conductor 240b2.

[0187] It is preferable that the conductors 240a2 and 240b2 have better conductivity than conductor 240a1, etc. For example, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, it is preferable to deposit the conductors 240a2 and 240b2 using a method that provides good embedding properties, for example, by chemical vapor deposition (CVD). For example, tungsten deposited by CVD can be used as the conductors 240a2 and 240b2.

[0188] Furthermore, it is preferable that the conductors 240a1 and 240b1 have good adhesion to the conductors 240a2 and 240b2. For example, it is preferable to use a conductive material whose main component is one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. It is also preferable to deposit the conductors 240a1 and 240b1 using a method that provides good coverage, for example, by the ALD method. For example, titanium nitride deposited by the thermal ALD method can be used as the conductors 240a1 and 240b1.

[0189] Furthermore, it is preferable that the conductors 240a1 and 240b1 have barrier properties against impurities. For example, it is preferable to use the conductive materials described above for the conductors 240a1 and 240b1. By making the conductors 240a1 and 240b1 have a structure that has barrier properties against oxygen, oxidation of the conductors 240a2 and 240b2 can be suppressed, and an increase in wiring resistance can be prevented.

[0190] Furthermore, it is preferable that the conductors 240a1 and 240b1 have a structure that provides a barrier to hydrogen. For example, it is preferable that the hydrogen diffusion distance per unit film thickness of conductors 240a1 and 240b1 is shorter than that of conductors 240a2 and 240b2, respectively. Conductors 240a and 240b are connected to wiring or electrodes, and there is a risk that hydrogen may diffuse to the vicinity of the transistor 200 via such wiring or electrodes. However, by providing conductors 240a1 and 240b1 with a structure that provides a barrier to hydrogen, it is possible to suppress the diffusion of such hydrogen to the oxide semiconductor 230.

[0191] Here, it is preferable that the conductors 240a1 and 240b1 have low hydrogen concentrations. When forming a conductive film with a low hydrogen concentration, it is preferable to form the film using an ALD method with an inorganic precursor that does not contain hydrogen. For example, using TiCl as the precursor. ４A titanium nitride film can be formed using the thermal ALD method. By reducing the hydrogen concentration of conductors 240a1 and 240b1, conductors 240a and 240b themselves become hydrogen sources, suppressing the diffusion of hydrogen into the oxide semiconductor 230. Therefore, the electrical characteristics of the transistor 200 can be improved.

[0192] Furthermore, while Figure 2A shows an example in which a recess is formed on the upper surface of the conductor 242a2 and a portion of the conductor 240a1 is embedded in the upper surface of the conductor 242a2, the present invention is not limited to this. There are cases in which no recess is formed on the upper surface of the conductor 242a2 and a portion of the conductor 240a1 is not embedded in the upper surface of the conductor 242a2. For example, depending on the conditions of the anisotropic dry etching process when forming the insulator 241a, there are cases in which almost no recess is formed on the upper surface of the conductor 242a2. The same applies to the conductor 240b1 as to the conductor 240a1.

[0193] As insulators 241a and 241b, barrier insulators that can be used for insulator 275 and the like may be used. For example, silicon nitride may be used as insulators 241a and 241b. Insulators 241a and 241b are provided in contact with insulators 285, 283, 282, 275, 271a, 271b, 222, and 221. This makes it possible to suppress the mixing of impurities such as water and hydrogen contained in insulators 280 and the like into the oxide semiconductor 230 through conductors 240a and 240b. Silicon nitride is particularly suitable because it has high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0194] Furthermore, the insulators 241a and 241b may be arranged in a laminated structure. In this case, it is preferable that the first insulator in contact with the side wall of the opening such as the insulator 280 and the second insulator inside it use a combination of an oxygen barrier insulator (e.g., aluminum oxide) and a hydrogen barrier insulator (e.g., silicon nitride).

[0195] Furthermore, although Figure 1B and others show a configuration in which the insulator 224 is in an island shape, the present invention is not limited to this. For example, as shown in Figures 7A to 7D, the insulator 224 may not be in an island shape, but rather in a shape in which an opening is formed in part. Here, Figures 7A to 7D correspond to Figures 1A to 1D, respectively, and are the same as Figures 1A to 1D except that the shape of the insulator 224 is different.

[0196] Insulators 224, as shown in Figures 7A to 7D, have a thinner film thickness in the region that does not overlap with the oxide semiconductor 230 than in the region that does overlap with the oxide semiconductor 230. Furthermore, insulators 224 have openings in the region that does not overlap with the oxide semiconductor 230 but overlaps with insulator 250. When multiple transistors are provided on the same substrate, forming insulators 224 in this way ensures that the oxide semiconductor 230 of each transistor is formed on the same insulator 224. With this structure, it is also possible to adjust the amount of oxygen supplied from insulators 224 to the oxide semiconductor 230 of each transistor.

[0197] In the insulator 224 shown in Figures 7A to 7D, an opening is formed in the region that does not overlap with the oxide semiconductor 230 but overlaps with the insulator 250; however, a configuration without such an opening is also possible.

[0198] Furthermore, while Figure 1A and others show a configuration in which the top view widths of conductors 240a and 240b are smaller than the top view width of the channel formation region of the oxide semiconductor 230, the present invention is not limited to this. For example, as shown in Figures 8A to 8D, the top view widths of conductors 240a and 240b can be larger than the top view width of the channel formation region of the oxide semiconductor 230. Figures 8A to 8D correspond to Figures 1A to 1D, respectively, and are the same as Figures 1A to 1D except that the top surface shapes of the insulator 224, oxide semiconductor 230, conductors 242a1, conductors 242a2, conductors 242b1, conductors 242b2, insulators 271a, insulators 271b, conductors 240a, and conductors 240b are different.

[0199] As shown in Figure 8A and other figures, it is preferable that the top view width L4 in the A5-A6 direction of the source region (drain region) of the oxide semiconductor 230 is greater than the top view width L3 in the A3-A4 direction near the channel formation region of the oxide semiconductor 230. Note that width L3 can also be defined as the top view width in the A3-A4 direction in the region overlapping with the conductor 260 of the oxide semiconductor 230. Furthermore, width L4 can also be defined as the top view width in the A5-A6 direction near the region overlapping with the conductor 240a (conductor 240b) of the oxide semiconductor 230. By adopting such a configuration, the margin when forming the opening for embedding the wide conductors 240a and 240b can be increased. Therefore, the productivity of semiconductor devices can be improved. In addition, the contact area between the conductor 240a (conductor 240b) and the conductor 242a2 (conductor 242b2) can be increased, and contact resistance can be reduced. Furthermore, the contact area between the conductor 242a2 (conductor 242b2) and the oxide semiconductor 230 can be increased, thereby reducing contact resistance. This increases the on-current of the transistor 200 and improves the electrical characteristics of the semiconductor device.

[0200] Furthermore, as shown in Figure 8A, it is preferable that the insulator 224, conductor 242a1, conductor 242a2, conductor 242b1, conductor 242b2, insulator 271a, and insulator 271b are formed so as to overlap the upper surface shape of the oxide semiconductor 230.

[0201] <Modified Example> Figures 9A and 9B show a semiconductor device in which wiring and capacitive elements are formed on the upper and lower layers of the semiconductor device shown in Figure 1B.

[0202] Using Figures 9A and 9B, a modified example of the semiconductor device described in <Example of Semiconductor Device Configuration> will be explained. Figures 9A and 9B are cross-sectional views of a semiconductor device having a transistor 200, and have parts corresponding to the semiconductor device shown in Figure 1B, etc. Figure 9A corresponds to the cross-section of the transistor 200 in the channel length direction. Figure 9B corresponds to the cross-section of the transistor 200 in the channel width direction.

[0203] The configuration of transistor 200 and its vicinity shown in Figures 9A and 9B corresponds to the transistor 200 shown in Figures 1A to 1D. Hereafter, we will mainly explain the parts that differ from the previously described <Example of Semiconductor Device Configuration>, and for overlapping parts, please refer to that section, and explanations may be omitted.

[0204] As shown in Figure 9A, a conductor 218 that functions as wiring can be provided in the same layer as the conductor 205. Openings reaching the conductor 218 are formed in the insulators 285, 283, 282, 280, 275, 222, and 221, and the conductor 240c and insulator 241c are provided within these openings. Insulator 241c is provided in contact with the side wall of the opening, and the conductor 240c is provided inside insulator 241c. The conductor 218 can be formed in the same process as the conductor 205, and the same material is used. The conductor 240c can be formed in the same process as conductors 240a and 240b, and the same material is used. The insulator 241c can be formed in the same process as insulators 241a and 241b, and the same material is used.

[0205] Furthermore, an insulator 213, which functions as an interlayer film, is formed beneath the insulator 212 below the transistor 200. The insulator 213 is formed to cover the conductor 219, which functions as wiring. The insulator 213 can be formed using the same material as the insulator 280. The conductor 217 is formed inside the openings formed in the insulators 214, 212, and 213. These openings reach the upper surface of the conductor 219, and the conductor 217 is in contact with the upper surface of the conductor 219. Therefore, the conductor 219 and the conductor 218 are electrically connected via the conductor 217, which functions as a via. The conductor 217 can be formed using the same material as the conductors 240a to 240c. The conductor 219 can also be connected to wiring, circuit elements, etc., located in a lower layer.

[0206] As described above, the transistor 200 is located in a region sandwiched between the highly hydrogen-barrier insulator 212 and insulator 283, preventing hydrogen from diffusing from the layer above or below the transistor 200. However, as shown in Figure 9A, since the conductor 217 penetrates the insulator 212, there is a possibility that impurities such as hydrogen may diffuse into the region above the insulator 212 via the conductor 217. For example, since the conductor 219 connected to the conductor 217 is in contact with the insulator 213, there is a possibility that hydrogen contained in the insulator 213 may diffuse through the conductor 219 and the conductor 217. Furthermore, since the conductor 219 is connected to a circuit element in a lower layer, there is a possibility that hydrogen contained in the interlayer film of that circuit element and its vicinity may diffuse through the conductor 219.

[0207] In contrast, by using a conductive film with hydrogen barrier properties on the conductor 218 and covering the upper part of the conductor 217, it is possible to prevent hydrogen from diffusing through the conductors 219 and 217. Furthermore, even if some of the hydrogen diffuses from the conductor 218 to the insulator 216, the highly hydrogen-barrier insulator 221 provided below the transistor 200 can prevent it from diffusing into the oxide semiconductor 230. Furthermore, even if another portion of the hydrogen diffuses from the conductor 218 to the conductor 240c, the hydrogen-barrier conductive film used on the conductor 240c and the insulator 241c can prevent it from diffusing into the insulator 280. With this configuration, excess V in the channel formation region of the oxide semiconductor 230 Ｏ H is formed, preventing the transistor from exhibiting normally-on characteristics. Therefore, a semiconductor device with good electrical characteristics can be provided.

[0208] Furthermore, as shown in Figures 9A and 9B, insulators 450, 488, and 487, which function as interlayer films, are formed on the insulator 285 on the transistor 200. Insulator 450 can be formed using the same material as insulator 280. Insulator 487 is formed covering conductors 412, 413, and 414, which function as wiring, and the capacitive element 400. Insulator 488 is formed covering insulator 487. Insulator 450 is formed covering insulator 488. The capacitive element 400 has a conductor 410, an insulator 430 covering the conductor 410, and a conductor 420 on the insulator 430.

[0209] Here, conductor 410 is formed in contact with the upper surface of conductor 240a, conductor 413 is formed in contact with the upper surface of conductor 240b, conductor 412 is formed in contact with the upper surface of conductor 240c, and conductor 414 is formed in contact with the upper surface of conductor 240d. In other words, conductor 410 is electrically connected to conductor 242a, conductor 413 is electrically connected to conductor 242b, conductor 412 is electrically connected to conductor 218, and conductor 414 is electrically connected to conductor 260. Conductor 240d is formed inside the openings formed in insulators 285, 283, and 282. These openings reach the upper surface of conductor 260, and conductor 240d is in contact with the upper surface of conductor 260. Insulator 241d is formed to cover the side walls of these openings. The conductor 240d can be formed in the same process as the conductors 240a to 240c, and the same materials are used. The insulator 241d can be formed in the same process as the insulators 241a to 241c, and the same materials are used.

[0210] An insulator 470, which functions as an interlayer film, is formed on the insulator 450. The insulator 470 is formed to cover the conductor 462, which functions as wiring. The insulator 470 can be formed using the same material as the insulator 280. The conductor 462 is formed in contact with the upper surfaces of the conductors 440a and 440b. The conductors 440a and 440b are formed inside openings formed in the insulators 450, 488, and 487. The opening in which the conductor 440a is formed reaches the upper surface of the conductor 420, and the conductor 440a is in contact with the upper surface of the conductor 420. In addition, an insulator 441a is formed so as to cover the side wall of the opening in which the conductor 440a is formed. The opening in which the conductor 440b is formed reaches the upper surface of the conductor 412, and the conductor 440b is in contact with the upper surface of the conductor 412. Furthermore, an insulator 441b is formed to cover the side wall of the opening in which the conductor 440b is formed. Conductors 440a and 440b can be formed in the same way as conductors 240a to 240d, and the same materials can be used. Insulators 441a and 441b can be formed in the same way as insulators 241a to 241d, and the same materials can be used. Note that since conductors 440a and 440b are in a layer above the insulator 283, if impurities such as hydrogen diffusing into the layers of conductors 240a to 240d can be sufficiently reduced, a configuration without insulators 441a and 441b is also possible.

[0211] The capacitive element 400 includes a conductor 410 that functions as a first electrode, a conductor 420 that functions as a second electrode, and an insulator 430 that functions as a dielectric. In other words, the capacitive element 400 constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0212] Conductors 410 and 420 can be made of any conductive material that can be used for conductor 260. For example, tungsten can be used for conductors 410 and 420. Here, by creating a structure in which conductor 420 covers conductor 410, the side surface of conductor 410 can be made to function as a capacitive element 400. This makes it possible to increase the capacitance of the capacitive element 400. Conductors 412, 413, and 414 can be formed in the same process as conductor 410.

[0213] In Figure 9, conductors 410, 412, 413, 414, and 420 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers may be used. For example, a laminated structure of a barrier conductor and a highly conductive conductor may be used. For example, a laminated structure of titanium nitride and tungsten on titanium nitride can be used.

[0214] It is preferable to use a material with a high dielectric constant (high-k) for the insulator 430 of the capacitive element 400. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium. By using such a high-k material, the insulator 430 can be made thick enough to suppress leakage current, while ensuring sufficient capacitance of the capacitive element 400. Furthermore, since the insulator 430 is formed by covering the conductor 410, it is preferable to form the film using a film deposition method with good coverage, such as the ALD method or the CVD method.

[0215] Furthermore, the insulator 430 may have a laminated structure. It is preferable to use a laminated structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the material with a high dielectric constant (high-k). Examples of materials with high dielectric strength (materials with a low dielectric constant) include silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. For example, the insulator 430 can be configured such that the first layer uses aluminum oxide, which is a material with a high dielectric constant (high-k), and the second layer on top of the first layer uses silicon oxide, which has a high dielectric strength.

[0216] Furthermore, for example, an insulator 430 can be made by laminating zirconium oxide, aluminum oxide, and zirconium oxide in that order. Alternatively, an insulator can be made by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in that order. Alternatively, an insulator can be made by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in that order. By laminating and using an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element 400 can be suppressed.

[0217] Furthermore, a material capable of ferroelectricity may be used as the insulator 430. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO ＸExamples of metal oxides include those where X is a real number greater than 0. Furthermore, a material that may possess ferroelectric properties is a material obtained by adding element J1 (where element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately; for example, the ratio can be 1:1 or close to it. Another example of a material that may possess ferroelectric properties is a material obtained by adding element J2 (where element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of zirconium atoms to the number of element J2 atoms can also be set appropriately; for example, the ratio can be 1:1 or close to it. Furthermore, as a material that can possess ferroelectric properties, lead titanate (PbTiO) Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0218] Furthermore, metal nitrides containing element M1, element M2, and nitrogen can be cited as materials that may possess ferroelectric properties. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. In addition, metal oxides containing element M1 and nitrogen may possess ferroelectric properties even without containing element M2. Furthermore, materials in which element M3 is added to the above metal nitrides can be cited as materials that may possess ferroelectric properties. Element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.

[0219] Furthermore, SrTaO is an example of a material that may possess ferroelectric properties. ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, and GaFeO with a κ-alumina structure. ３ These are some examples.

[0220] While the above explanation uses metal oxides and metal nitrides as examples, it is not limited to these. For example, metal oxynitrides obtained by adding nitrogen to the above-mentioned metal oxides, or metal nitrogen oxides obtained by adding oxygen to the above-mentioned metal nitrides, may be used.

[0221] Furthermore, as a material that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Alternatively, the insulator 430 can be a laminated structure consisting of multiple materials selected from the materials listed above. Incidentally, the crystal structure (properties) of the materials listed above may change not only depending on the film formation conditions but also on various processes, so in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0222] In the semiconductor device shown in Figure 9, the shape of the capacitive element 400 is planar, but the semiconductor device shown in this embodiment is not limited to this. For example, the shape of the capacitive element 400 may be cylindrical.

[0223] An insulator 487 is provided to cover the capacitive element 400, and an insulator 488 is provided to cover the insulator 487. It is preferable to use an insulator 487 that has the function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulator 487. It is preferable to use an insulator 488 that has the function of suppressing hydrogen diffusion. For example, silicon nitride, which has higher hydrogen barrier properties, may be used for the insulator 488.

[0224] Furthermore, it is preferable to have a laminated structure for the insulator 487. For example, the first layer of the insulator 487 can be aluminum oxide deposited by thermal ALD, and the second layer on top of the first layer can be aluminum oxide deposited by sputtering. By depositing the second layer of the insulator 487 using sputtering while the first layer of the insulator 487 is deposited, the capacitive element 400 can be protected from the impact of ion collisions caused by sputtering. In addition, by depositing the first layer of the insulator 487 using the ALD method, which has good step coverage, it is possible to prevent the formation of pinholes or step breaks at steps in the capacitive element 400.

[0225] Furthermore, it is preferable to have a laminated structure for the insulator 488. For example, the insulator 488 can be made of silicon nitride deposited by sputtering as the first layer, and silicon nitride deposited by PEALD as the second layer on top of the first layer. Even if pinholes or step breaks are formed in the first layer of the insulator 488 near steps such as those of the capacitive element 400, the barrier properties against hydrogen can be maintained by covering them with the second layer of the insulator 488, which is deposited by the ALD method and has good step coverage properties.

[0226] In this way, by providing the insulator 488 on top of the capacitive element 400, the diffusion of hydrogen from the upper layer of the capacitive element 400 can be suppressed. Furthermore, by providing the insulator 487 below the insulator 488, hydrogen contained in the capacitive element 400, the insulator 285, etc., can be captured or fixed to the insulator 487.

[0227] In Figure 9A, the conductor 462 is shown as a single-layer structure, but the structure is not limited to this configuration and may be a laminated structure of two or more layers. For example, a highly conductive metal material can be sandwiched between highly heat-resistant metal materials. Aluminum, copper, etc., can be used as the highly conductive metal material. Molybdenum, titanium, tungsten, and nitrides thereof can be used as the highly heat-resistant metal material.

[0228] The wiring and circuit element connection configurations of the semiconductor device shown in this embodiment are not limited to those shown in Figure 9A and the like. For example, in Figure 9A, conductors 219, 218, 412, and 462, which function as wiring for each layer, are all connected by conductors 217, 240c, and 440b, which function as vias, but the invention is not limited to this, and any circuit can be formed by selecting wiring and vias from the above configurations. Also, for example, in Figure 9A, conductor 219 and conductor 420, which functions as the upper electrode of the capacitive element 400, are connected via conductor 462, etc., but the invention is not limited to this. For example, by dividing conductor 462 and providing one end of conductor 462 in contact with conductor 440b and the other end of conductor 462 in contact with conductor 440a, it is possible to create a configuration in which conductor 219 and conductor 420 are not electrically connected. Furthermore, although Figure 9A shows a configuration in which one wiring layer is provided below the transistor 200 and above the capacitive element 400, the present invention is not limited to this, and two or more wiring layers can be provided below the transistor 200 and above the capacitive element 400. Also, although Figure 9A shows a configuration in which the conductor 410, which functions as one of the electrodes of the capacitive element 400, and the conductors 412 and 413, which function as wiring, are provided on the same layer, the present invention is not limited to this. For example, the conductor 410 can be formed on a layer above the conductors 412 and 413, and the capacitive element 400 can be formed above the wiring layer containing the conductors 412 and 413. As described above, in this embodiment, the transistors, circuit elements and wiring of each layer can be connected to each other via vias to form a circuit of any configuration. For example, a pixel circuit of a display device can be formed.

[0229] <Materials for semiconductor devices> The following describes materials that can be used in semiconductor devices. Note that each layer constituting a semiconductor device may be a single-layer structure or a multilayer structure.

[0230] <<Substrates>> For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate for forming the transistor. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates equipped with one or more types of elements may be used. Examples of elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0231] <<Insulators>> In this embodiment, insulators 212, 214, 216, 221, 222, 224, 250, 275, 280, 282, 283, 285, 241a, 241b, 241c, 271a, 271b, 255, 213, 430, 487, 488, 450, 441a, 441b, and 470 can be any of the insulators listed below as appropriate. Examples of insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0232] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

[0233] Examples of insulators with a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxide nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0234] Examples of insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0235] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing one or more of the following: boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or in a multilayer structure. Specifically, examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride, and silicon nitride.

[0236] Furthermore, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide semiconductor 230, the oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0237] <<Conductors>> In this embodiment, conductors 205, 242a, 242b, 260, 240a, 240b, 240c, 218, 217, 219, 412, 410, 420, 413, 440a, 440b, and 462 can be any of the conductors listed below as appropriate. As conductors, it is preferable to use metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys composed of the above-mentioned metal elements, or alloys combining the above-mentioned metal elements. Examples of conductors include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0238] When using a laminated conductor, for example, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing nitrogen, or a laminated structure combining a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be applied.

[0239] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is more easily supplied to the channel formation region.

[0240] Furthermore, conductive materials containing metal elements and oxygen from the metal oxide in which the channel is formed can be used. Conductive materials containing the aforementioned metal elements and nitrogen may also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Additionally, one or more of the following may be used: indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide. Indium gallium zinc oxide containing nitrogen may also be used. Using such materials may allow for the capture of hydrogen contained in the metal oxide in which the channel is formed, or for the capture of hydrogen introduced from an external insulator. Therefore, the above conductive materials may be preferable for use in conductors that function as gate electrodes.

[0241] <<Other Semiconductor Materials>> The semiconductor layer of the transistor may use semiconductor materials with a bandgap (semiconductor materials that are not zero-gap semiconductors). For example, semiconductors of single elements such as silicon, or compound semiconductors such as gallium arsenide may be used.

[0242] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor in the semiconductor layer of the transistor. Specifically, as a transition metal chalcogenide applicable to the semiconductor layer of the transistor, molybdenum sulfide (MoS) is a typical example. ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ Examples include the above. By applying the aforementioned transition metal chalcogenides to the semiconductor layer of a transistor, a semiconductor device with a high on-current can be provided.

[0243] <Example of Semiconductor Device Fabrication Method> An example of a semiconductor device fabrication method according to one embodiment of the present invention will be described using Figures 10A to 19D. Here, the case of fabricating the semiconductor device shown in Figures 1A to 1D will be used as an example.

[0244] (A) in each figure shows a plan view. (B) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in (A), and is also a cross-sectional view of transistor 200 in the channel length direction. (C) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in (A), and is also a cross-sectional view of transistor 200 in the channel width direction. (D) in each figure is a cross-sectional view of the area indicated by the dashed line A5-A6 in (A), and is also a cross-sectional view of transistor 200 in the channel width direction. Note that in the plan view (A) of each figure, some elements have been omitted for clarity.

[0245] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be deposited using methods such as sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD as appropriate.

[0246] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0247] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD) methods depending on the source gas used.

[0248] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitive elements, etc.) in semiconductor devices can be charged up by receiving charge from the plasma. This accumulated charge can damage these components. In contrast, thermal CVD, which does not use plasma, avoids such plasma damage, resulting in higher yields for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0249] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses a plasma-excited reactant.

[0250] Some precursors used in the ALD method contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other deposition methods. The quantity of impurities can be quantified using SIMS, XPS, or Auger electron spectroscopy (AES).

[0251] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0252] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple chambers, because time is not required for transport or pressure adjustment. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0253] Furthermore, the ALD method allows for the deposition of films with any desired composition by introducing multiple different types of precursors. Alternatively, when introducing multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0254] First, a substrate (not shown) is prepared, an insulator 212 is deposited on the substrate, and an insulator 214 is deposited on top of the insulator 212. The insulator 212 and insulator 214 can be made from the insulating materials described above. For example, sputtering, CVD, MBE, PLD, or ALD can be used to deposit the insulators 212 and 214. It is preferable to use a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, as this can reduce the hydrogen concentration in the insulators 212 and 214.

[0255] In this embodiment, silicon nitride is deposited as the insulator 212 using a sputtering method, and aluminum oxide is deposited as the insulator 214 using a sputtering method. By using silicon nitride, which has the function of suppressing hydrogen diffusion, for the insulator 212, the diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has the function of capturing or fixing hydrogen, for the insulator 214, hydrogen contained in the insulator 216 and the like can be captured or fixed to the insulator 214. As a result, the hydrogen concentration in and near the oxide semiconductor 230 can be reduced.

[0256] Furthermore, it is preferable to perform a heat treatment before forming the insulator 212 to reduce water and hydrogen adsorbed on the substrate (including the circuit elements and interlayer film formed on the substrate). Also, when forming an insulating layer (for example, the insulator 213 shown in Figure 9A) between the substrate and the insulator 212, the heat treatment may be performed with the underlying insulating layer formed on the substrate. This can also reduce water and hydrogen adsorbed on the underlying insulating layer. The heat treatment conditions can be the same as those for the heat treatment of the oxide semiconductor 230, which will be described later. In this embodiment, the heat treatment temperature is set to 400°C.

[0257] Next, an insulating film 216 is formed on the insulator 214. The insulating material 216 can be any insulating material that can be used for the insulating film 216 described above. It is preferable to form the insulating film 216 using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 216 can be reduced. However, the formation of the insulating film 216 is not limited to the sputtering method, and CVD, MBE, PLD, ALD, etc. may be used as appropriate. In this embodiment, silicon oxide is formed as the insulating film 216 using a sputtering method.

[0258] It is preferable to continuously deposit insulators 212, 214, and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0259] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening is formed in the region where the conductor 205 is formed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216. For example, if silicon oxide or silicon oxynitride is used for the insulator 216, then silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0260] After the opening is formed, a conductive film to become the conductor 205 is deposited, and a CMP (Chemical Mechanical Polishing) treatment is performed until the insulator 216 is exposed, removing a portion of the conductive film that will become the conductor 205. This makes it possible to form the conductor 205 embedded in the insulator 216.

[0261] The conductive film that will become the conductor 205 can be formed using the above-mentioned conductive material by methods such as sputtering, CVD, MBE, PLD, and ALD.

[0262] For example, in the configuration shown in Figure 2A, titanium nitride can be deposited as the conductive film conductor 205a using the ALD method. Furthermore, tungsten can be deposited as the conductive film conductor 205b using the CVD method. The conductive film conductor 205a can be deposited using the thermal ALD method with an inorganic precursor, without using a hydrogen-containing gas. For example, TiCl can be used as the inorganic precursor. ４ In this case, NH can be used as the nitride agent. ３ A gas can be used. By forming the film using the method described above, the conductor 205a can be made into a conductive film with a low hydrogen concentration. Therefore, these conductive films can act as a hydrogen source, preventing hydrogen from diffusing into the oxide semiconductor.

[0263] Next, an insulating film 221 is formed on the insulating film 216 and the conductive film 205.

[0264] The insulator 221 may be any insulator having barrier properties against oxygen, hydrogen, and water as described above. The insulator 221 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon nitride is formed as the insulator 221 using the PEALD method.

[0265] Next, an insulating film 222 is formed on the insulating film 221.

[0266] It is preferable to form an insulator 222 containing an oxide of either or both aluminum and hafnium. For example, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing both aluminum and hafnium (hafnium aluminate) as the insulator containing either or both aluminum and hafnium oxide. Alternatively, it is preferable to use hafnium zirconium oxide. The insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor through the insulator 222 into the inside of the transistor is suppressed, thereby suppressing the generation of oxygen vacancies in the oxide semiconductor 230.

[0267] The insulator 222 can be formed using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is formed as the insulator 222 using the thermal ALD method.

[0268] In this embodiment, silicon nitride is deposited as the insulator 221 using the PEALD method, and hafnium oxide is deposited as the insulator 222 using the thermal ALD method. By using silicon nitride, which has the function of suppressing hydrogen diffusion, for the insulator 221, the diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has the function of capturing or fixing hydrogen, for the insulator 222, hydrogen contained in the insulator 224 and the like can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in and near the oxide semiconductor 230 can be reduced.

[0269] Next, an insulating film 224f is deposited on the insulator 222. The insulating film 224f can be the same insulator as the insulator 224.

[0270] The insulating film 224f can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is deposited as the insulating film 224f using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f will come into contact with the oxide semiconductor 230 in a later process, it is preferable that the hydrogen concentration is reduced in this way.

[0271] Next, an oxide semiconductor film 230f is deposited on the insulating film 224f. The oxide semiconductor film 230f can be made from the oxide semiconductor material described above. The oxide semiconductor film 230f can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. It is also preferable to deposit the film while heating the substrate. This improves the crystallinity of the oxide semiconductor film 230f.

[0272] Furthermore, it is preferable to use an indium-containing oxide (for example, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide) for the oxide semiconductor film 230f. By configuring the oxide semiconductor film 230f to have an indium-containing oxide, a semiconductor device with high field-effect mobility can be provided. In addition, a semiconductor device with good electrical characteristics, frequency characteristics, and reliability can be provided.

[0273] For example, as shown in Figure 2A, when creating a stacked structure of oxide semiconductor 230a and oxide semiconductor 230b, the film that will become the oxide semiconductor 230 can be deposited as follows. The film that will become the oxide semiconductor 230a is deposited by sputtering using an oxide target with an In:Ga:Zn = 1:3:2 [atomic ratio] or an In:Ga:Zn = 1:3:4 [atomic ratio]. The film that will become the oxide semiconductor 230b is deposited by sputtering using an indium oxide target, an oxide target with an In:Ga:Zn = 1:1:1 [atomic ratio], an oxide target with an In:Ga:Zn = 1:1:1.2 [atomic ratio], an oxide target with an In:Ga:Zn = 4:2:4.1 [atomic ratio], or an oxide target with an In:Ga:Zn = 1:1:2 [atomic ratio]. Furthermore, the deposition conditions and atomic ratio of the oxide film can be appropriately selected to match the desired properties of the oxide semiconductor 230 (oxide semiconductor 230a and oxide semiconductor 230b).

[0274] Thus, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the oxide semiconductor film 230f can be reduced. When forming a multilayer film of oxide semiconductor film 230f, it is preferable to deposit the film continuously by sputtering without exposing it to the atmosphere. It is also preferable to deposit the insulating film 224f and the oxide semiconductor film 230f continuously by sputtering. By depositing the film without exposing it to the atmosphere, the interface or vicinity of the interface of the multilayer film can be kept clean.

[0275] Furthermore, although the above describes an example of depositing oxide semiconductors 230a and 230b by sputtering, the method is not limited to this. Part or all of oxide semiconductors 230a and 230b may be deposited by ALD. For example, indium oxide may be deposited as the film that becomes oxide semiconductor 230b using ALD.

[0276] When forming an indium-containing oxide semiconductor film using the ALD method, an indium-containing precursor can be used. When using an indium-containing precursor, it is preferable to use the thermal ALD method. Alternatively, the PEALD method can also be used.

[0277] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0278] Furthermore, inorganic precursors that do not contain hydrocarbons may be used as indium precursors. Examples of indium-containing inorganic precursors include halogenated indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0279] Furthermore, the oxide semiconductor film 230f may be arranged in a three-layer stacked structure. For example, when depositing the film using the sputtering method, each layer of the oxide semiconductor film 230f can be deposited using the above-mentioned target, etc. as appropriate. Also, for example, when depositing the film using the ALD method, each layer of the oxide semiconductor film 230f can be deposited using the above-mentioned precursor, etc. as appropriate. Furthermore, the oxide semiconductor film 230f may be configured to include both a layer deposited by the sputtering method and a layer deposited by the ALD method.

[0280] Furthermore, by using a sputtering target made of the same material to deposit each layer of the oxide semiconductor film 230f under different conditions, oxide semiconductor films 230f with different film qualities for each layer can be deposited. For example, since the time required to change deposition conditions such as power density, pressure, gas type, and gas flow rate is short, the film quality of each layer can be changed without excessively reducing productivity. Note that power density is the value obtained by dividing the power applied to the substrate by the magnet area. The magnet area is the area of ​​the surface of the magnet that overlaps with the sputtering target.

[0281] For example, when the oxide semiconductor film 230f is formed in a stacked structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer, it is preferable to make the power density of the deposition of the first and third layers higher than that of the deposition of the second layer. It is also preferable to make the pressure of the deposition of the first and third layers lower than that of the deposition of the second layer. By depositing the film under the above conditions, the first and third layers can be made into dense oxide semiconductors with few defects. By depositing the oxide semiconductor film 230f in this way, the reliability of the transistor 200 can be improved.

[0282] Furthermore, when using indium oxide for the oxide semiconductor film 230f, the deposition gas should contain a gas containing hydrogen (for example, H ２ or H ２ A mixed gas containing O) may be used. Furthermore, it is preferable that the deposition temperature of the oxide semiconductor film 230f be low (for example, around room temperature). This makes it possible to reduce the number of crystal grains produced during the deposition of the oxide semiconductor film 230f. In this way, by reducing the number of crystal grains in the oxide semiconductor film 230f and performing the heat treatment described later, the number of crystal grains in the oxide semiconductor film 230f can be increased.

[0283] Next, a heat treatment is preferable. The temperature of the heat treatment (or the temperature of the substrate) can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When using an RTA device, the treatment time can be, for example, 1 second to 5 minutes.

[0284] There are no special limitations on the heating device used for the heat treatment; it may be a device that heats the object to be treated by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0285] By performing a heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. This improves the on-current, S-value, field-effect mobility, and frequency characteristics of the transistor 200, making it possible to provide a semiconductor device with good electrical characteristics. Furthermore, it is possible to provide a highly reliable semiconductor device.

[0286] The heat treatment should be carried out in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an atmosphere of nitrogen gas or an inert gas, the heat treatment may be carried out again in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed.

[0287] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide semiconductor film 230f, etc. In addition, a highly purified gas can be used in the heat treatment before and after this step as well.

[0288] By performing a heat treatment containing oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f can be reduced. By reducing impurities in the film in this way, the crystallinity of the oxide semiconductor film 230f can be improved, resulting in a denser, more compact structure. This increases the crystalline region in the oxide semiconductor film 230f and reduces in-plane variation of the crystalline region within the oxide semiconductor film 230f. Therefore, in-plane variation in the electrical characteristics of the transistor can be reduced.

[0289] Furthermore, by performing a heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, thereby reducing oxygen vacancies in the oxide semiconductor film 230f. This improves the reliability of the transistor 200.

[0290] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, insulating film 224f, and oxide semiconductor film 230f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, insulating film 224f, and oxide semiconductor film 230f diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, insulating film 224f, and oxide semiconductor film 230f decrease. By providing an insulator 221 in contact with the lower surface of the insulator 222, it is possible to prevent moisture or impurities such as hydrogen from entering from below the insulator 221 during the heat treatment.

[0291] In particular, the insulating film 224f (later referred to as insulator 224) functions as a second gate insulator of the transistor 200, and the oxide semiconductor film 230f (later referred to as oxide semiconductor 230) functions as a channel formation region of the transistor 200. A transistor 200 formed using insulating film 224f and oxide semiconductor film 230f with reduced hydrogen concentration is preferred because it has good reliability.

[0292] Next, a conductive film 242_1f is deposited on the oxide semiconductor film 230f, and then a conductive film 242_2f is deposited on the conductive film 242_1f. For the conductive film 242_1f, a conductor corresponding to the conductors 242a1 and 242b1 may be used. Similarly, for the conductive film 242_2f, a conductor corresponding to the conductors 242a2 and 242b2 may be used. By depositing the conductive film 242_1f in contact with the oxide semiconductor film 230f after the deposition of the oxide semiconductor film 230f, without an etching process or the like, the upper surface of the oxide semiconductor film 230f can be protected by the conductive film 242_1f. This reduces the diffusion of impurities into the oxide semiconductor 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0293] The conductive films 242_1f and 242_2f can be deposited using sputtering, CVD, MBE, PLD, or ALD, respectively.

[0294] In this embodiment, ITO is deposited as a conductive film 242_1f and tungsten as a conductive film 242_2f using a sputtering method. Note that a heat treatment may be performed before depositing the conductive film 242_1f. This heat treatment may be performed under reduced pressure, and the conductive film 242_1f may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide semiconductor 230 can be removed, and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be further reduced. The heat treatment temperature is preferably between 100°C and 400°C.

[0295] Next, an insulating film 271f is deposited on the conductive film 242_2f (see Figures 10A to 10D). The insulating film 271f can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 271f that has the function of suppressing oxygen permeation. For example, as the insulating film 271f, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film can be deposited by sputtering. With such a configuration, the insulator 271a (insulator 271b) can be made into a laminated structure of a silicon nitride insulator 271a1 (insulator 271b1) and a silicon oxide insulator 271a2 (insulator 271b2).

[0296] Here, when forming a laminated film of the insulating film 271f, it is preferable to deposit the film continuously without exposing it to the atmosphere. By depositing the film without exposing it to the atmosphere, the interface or vicinity of the interface of the laminated film of insulating film 271f can be kept clean. Furthermore, it is even more preferable to deposit the film continuously from the conductive film 242_1f to the insulating film 271f without exposing it to the atmosphere.

[0297] Furthermore, a heat treatment may be performed before the deposition of the insulating film 271f. This heat treatment may be carried out under reduced pressure, and the insulating film 271f may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242_2f can be removed, and the moisture and hydrogen concentrations in the conductive films 242_1f and 242_2f can be further reduced. The temperature for the heat treatment is preferably between 100°C and 400°C.

[0298] Next, using lithography, the insulating film 224f, oxide semiconductor film 230f, conductive film 242_1f, conductive film 242_2f, and insulating film 271f are processed into island-like structures to form insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A (see Figures 11A to 11D).

[0299] The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 224f, oxide semiconductor film 230f, conductive film 242_1f, conductive film 242_2f, and insulating film 271f may be carried out under different conditions.

[0300] Here, it is preferable to process the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A together in an island shape. In this case, it is preferable that the side edge of conductor 242_2 coincides with or roughly coincides with the side edge of conductor 242_1. Furthermore, it is preferable that the side edge of conductor 242_1 coincides with or roughly coincides with the side edge of oxide semiconductor 230. Furthermore, it is preferable that the side edge of insulator 224 coincides with or roughly coincides with the side edge of oxide semiconductor 230. Furthermore, it is preferable that the side edge of insulator 271A coincides with or roughly coincides with the side edge of conductor 242_2. By adopting such a configuration, the number of processes for the semiconductor device according to one aspect of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with good productivity can be provided.

[0301] Furthermore, the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A are formed so that at least a portion of them overlaps with the conductor 205. Also, the insulator 222 is exposed in regions that do not overlap with the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A. However, the configuration is not limited to this, and the insulator 224 may remain on top of the insulator 222 in regions that do not overlap with the oxide semiconductor 230. In this case, as in the transistor 200 of Figures 7A to 7D, the insulator 224 will not be island-shaped, but will have an opening in part.

[0302] As shown in Figure 11B, the sides of the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A may be tapered. The taper angle of the sides of the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A may be, for example, 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as porosity can be reduced.

[0303] Furthermore, although not limited to the above, the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and the side surfaces of the insulator 271A may be perpendicular or approximately perpendicular to the upper surface of the insulator 222. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors.

[0304] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by etching through this resist mask, conductors, semiconductors, or insulators can be processed into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology may be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask may not be necessary in some cases.

[0305] Furthermore, the resist mask that is no longer needed after processing can be removed by dry etching, such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0306] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When a hard mask is used, an insulating film or conductive film that will serve as the hard mask material is formed on the insulating film 271f, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. For example, tungsten may be used as the hard mask material. Etching of the insulating film 271f may be performed after removing the resist mask, or it may be performed while the resist mask is still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the oxide semiconductor film 230f or the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0307] Alternatively, a configuration may be used in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are deposited between the workpiece and the resist mask. By using the SOC film and SOG film as masks, the adhesion to the resist mask can be improved, and the durability of the mask pattern can be enhanced. For example, lithography can be performed by depositing the SOC film, SOG film, and resist mask in that order on the workpiece.

[0308] For dry etching, an etching gas containing halogens can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as an etching gas, C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３ Gases can be used individually or in mixtures of two or more gases. Furthermore, oxygen, carbon dioxide, nitrogen, helium, argon, hydrogen, or hydrocarbon gases can be added to the etching gas as appropriate. Depending on the material being treated in the dry etching process, a gas containing hydrocarbons or hydrogen gas but without halogen gases can be used as the etching gas. Examples of hydrocarbons used in etching gases include methane (CH4). ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C２ H ２ ), and propine (C ３ H ４ One or more of the following can be used. The etching conditions can be set as appropriate according to the object to be etched.

[0309] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Furthermore, a configuration in which multiple different high-frequency voltages are applied to the parallel plate electrodes may be used. Such a CCP etching apparatus is called a dual-frequency excited capacitively coupled plasma (DF-CCP) etching apparatus. In a DF-CCP etching apparatus, a configuration in which high-frequency voltages of different frequencies are applied to each of the parallel plate electrodes may be used. Alternatively, a configuration in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source. The etching apparatus can be appropriately configured according to the object to be etched. In addition, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side of the dry etching apparatus to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thus enabling highly anisotropic etching.

[0310] Furthermore, in the etching process described above, the insulator 271A can function as an etching stopper to protect the conductors 242_1 and 242_2. For example, if a metallic hard mask is formed on the insulator 271A in the etching process described above, it may be difficult to obtain a suitable etching selectivity ratio with respect to the conductor 242_2 when removing the hard mask. However, by forming the insulator 271A on the conductor 242_2, the insulator 271A can function as an etching stopper to protect the conductor 242_2 during the etching process for removing the hard mask. This prevents the formation of a curved surface between the side and top surfaces of the conductor 242_2, so that the ends where the side and top surfaces of the conductors 242a2 and 242b2 are formed later have a angular shape, as shown in Figure 1D. The angular shape of the ends where the side and top surfaces of the conductor 242_2 intersect increases the cross-sectional area of ​​the conductor 242_2 compared to the case where the ends have a curved surface. Furthermore, by using a nitride insulator that is less likely to oxidize metals for the insulator 271A, it is possible to prevent excessive oxidation of the conductor 242_2. As a result, the resistance of conductors 242a2 and 242b2 is reduced, and the on-current of the transistor can be increased.

[0311] Furthermore, the dry etching of the insulator 271A, conductor 242_2, conductor 242_1, oxide semiconductor 230, and insulator 224 can be carried out continuously without exposure to the outside air. Here, when a metal oxide is used for conductor 242_1, it is preferable to perform plasma treatment after the dry etching of conductor 242_2. This plasma treatment can be carried out, for example, in a mixed atmosphere of argon gas and oxygen gas.

[0312] When a metal oxide is used for the conductor 242_1, the oxygen contained in the conductor 242_1 may oxidize the metal contained in the conductor 242_2, and a metal oxide layer (hereinafter sometimes referred to as the interfacial oxide layer) may be formed at the interface between the conductor 242_1 and the conductor 242_2. For example, when ITO is used for the conductor 242_1 and tungsten is used for the conductor 242_2, tungsten oxide may be formed as the interfacial oxide layer. The interfacial oxide layer may not be removed by the etching process of the conductor 242_2 and may remain. If the remaining interfacial oxide layer functions as a mask in the etching process of the conductor 242_1, etc., then a portion of the conductor 242_1, the oxide semiconductor 230, and the insulator 224 will not be removed by the etching process and will remain as residue.

[0313] In contrast, the interfacial oxide layer can be removed by performing plasma treatment as described above. Therefore, the generation of residue in the etching process of the conductor 242_1, oxide semiconductor 230, and insulator 224 can be suppressed.

[0314] Furthermore, by processing the insulator 224 into an island shape, the insulator 275 can be provided in contact with the side surface of the insulator 224 and the upper surface of the insulator 222 in a process described later. In other words, the insulator 224 can be separated from the insulator 280 by the insulator 275. With this configuration, it is possible to prevent excess amounts of oxygen and hydrogen and other impurities from entering the oxide semiconductor 230 from the insulator 280 through the insulator 224.

[0315] Next, an insulator 275 is formed by covering the insulator 224, oxide semiconductor 230, conductor 242_1, conductor 242_2, and insulator 271A, and then an insulator 280 is formed on top of the insulator 275 (see Figures 12A to 12D). The insulating materials described above can be used for insulators 275 and 280.

[0316] In this case, it is preferable that the insulator 275 is in contact with the upper surface of the insulator 222.

[0317] Preferably, the insulator 280 is formed by creating an insulating film that will serve as the insulator 280, and then performing a CMP treatment on the insulating film to form an insulator with a flat top surface. Alternatively, silicon nitride may be deposited on the insulator 280, for example, by sputtering, and then the silicon nitride may be subjected to a CMP treatment until it reaches the insulator 280.

[0318] The insulators 275 and 280 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD.

[0319] It is preferable to use an insulator 275 that has the function of suppressing oxygen permeation. For example, it is preferable to deposit silicon nitride as the insulator 275 using the PEALD method. Alternatively, the insulator 275 may be configured by depositing aluminum oxide using the sputtering method and then depositing silicon nitride on top of it using the PEALD method. By making the insulator 275 such a structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0320] In this way, the oxide semiconductor 230 and the conductors 242_1 and 242_2 can be covered with an insulator 275 that has the function of suppressing the diffusion of oxygen. This makes it possible to suppress the direct diffusion of oxygen from the insulator 280 or the like to the oxide semiconductor 230, conductor 242_1, and conductor 242_2 in a later process.

[0321] Furthermore, it is preferable to deposit silicon oxide as the insulator 280 using a sputtering method. By depositing the insulating film that will become the insulator 280 using a sputtering method in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. In addition, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Before depositing the insulating film, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed. The heat treatment conditions described above can be used for this heat treatment.

[0322] Next, lithography is used to process the conductor 242_2, insulator 271A, insulator 275, and insulator 280 to form openings that reach the conductor 242_1 and insulator 222 (see Figures 13A to 13D). Here, the conductor 242_2 is divided to form conductors 242a2 and 242b2, and the insulator 271A is divided to form insulators 271a and 271b. The opening that reaches the conductor 242_1 is formed in the region where the oxide semiconductor 230b and the conductor 205 overlap. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is L1, which corresponds to the distance L1 between the conductors 242a2 and 242b2 shown in Figure 2B. In other words, the width of the opening is greater than the distance L2 between the conductors 242a1 and 242b1 shown in Figure 2B.

[0323] The lithography method can be appropriately adapted to the above method. To finely process the aperture of the insulator 280, it is preferable to use a lithography method that uses short-wavelength light such as i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), ultraviolet light, KrF laser light, ArF laser light, EUV light, or an electron beam.

[0324] For example, a lithography method can be performed by depositing an SOC film, an SOG film, and a resist mask in that order on an insulator 280. A resist mask with an aperture is formed using short-wavelength light such as EUV light or an electron beam, and the SOG film, SOC film, insulator 280, insulator 275, insulator 271A, and conductor 242_2 are processed using the resist mask.

[0325] The above processing is preferably carried out using a dry etching method. Since the dry etching method allows for anisotropic etching, it is suitable for forming an opening with a width L1 as shown in Figure 2B, which has a high aspect ratio. The conditions for the dry etching method and the dry etching apparatus can be found in the description above. Furthermore, the etching treatment of the SOG film, SOC film, insulator 280, insulator 275, insulator 271A, and conductor 242_2 may be carried out under different conditions.

[0326] For example, when tungsten is used for the conductor 242_2 and ITO is used for the conductor 242_1, in an ICP etching apparatus, CF ４ and Cl ２ and O ２ are used as etching gases to perform the etching process on the conductor 242_2. Here, since the conductor 242_2 is etched while overlapping an opening with a width L1 formed in the insulator 280 or the like, the distance between the divided conductors 242a2 and 242b2 becomes L1.

[0327] Here, by performing an etching process with high anisotropy using an ICP etching apparatus, as shown in FIG. 13B, the side surfaces of the insulator 285, the side surfaces of the insulator 275, the side surfaces of the insulator 271a (the side surfaces of the insulator 271b), and the side surfaces of the conductor 242a2 (the side surfaces of the conductor 242b2) can be made flush.

[0328] Note that in the above etching process, the conductor 242_1 may be etched up to the upper part. In this case, as shown in FIG. 3A, the film thickness of the portions of the conductors 242a1 and 242b1 in contact with the insulator 255 becomes thinner than the film thickness of other portions.

[0329] Also, by performing an etching process with high isotropy, the side surfaces of the conductors 242a2 and 242b2 can be side-etched. In this case, for example, the bias power may be made smaller than in the anisotropic etching process for etching. Here, by side-etching the side surfaces of the conductors 242a2 and 242b2, a structure can be formed in which the distances between the conductor 242a2 and the insulator 250 and between the conductor 242b2 and the insulator 250 are each larger than the distance between the insulator 280 and the insulator 250, as shown in FIG. 3B. Thereby, the parasitic capacitance between the conductor 260 and the conductor 242a2 and the parasitic capacitance between the conductor 260 and the conductor 242b2 can be reduced. Furthermore, the leakage current between the conductor 260 and the conductor 242a2 and the leakage current between the conductor 260 and the conductor 242b2 can be reduced.

[0330] Furthermore, after processing the sides of the conductor 242a2 and the conductor 242b2 into the shape shown in Figure 13B, the exposed sides of the conductor 242a2 and conductor 242b can be oxidized. In this case, the above oxidation can be performed by continuously carrying out an ashing treatment using oxygen plasma, a heating treatment in an oxygen-containing atmosphere, or a microwave plasma treatment described later, following the etching treatment. This makes it possible to create a structure in which oxide 243a is formed between the conductor 242a2 and the insulator 255, and oxide 243b is formed between the conductor 242b2 and the insulator 255, as shown in Figure 3C. This makes it possible to reduce the parasitic capacitance between the conductor 260 and the conductor 242a2, and between the conductor 260 and the conductor 242b2. Furthermore, it makes it possible to reduce the leakage current between the conductor 260 and the conductor 242a2, and between the conductor 260 and the conductor 242b2.

[0331] Furthermore, the processing of the insulator 271A and the conductor 242_2, and the removal of the SOC film, can be carried out continuously without exposure to the atmosphere. For example, the process can be performed without exposure to the atmosphere using a multi-chamber etching apparatus.

[0332] As described above, the conductor 242_2, insulator 271A, insulator 275, and insulator 280 can be processed to form an opening with a width of L1.

[0333] Next, an insulating film 255f is formed by covering the insulator 280, the conductor 242_1, and the insulator 222 (see Figures 14A to 14D). The insulating film 255f is an insulating film that will become the insulator 255 in a later step, and the above-mentioned nitride insulator can be used. The insulating film 255f can be formed using sputtering, CVD, MBE, PLD, or ALD.

[0334] Since the insulating film 255f is formed along openings formed in the conductor 242a2, conductor 242b2, insulator 271A, insulator 275, and insulator 280, it is preferable that it has good coverage. Therefore, it is preferable to form the insulating film 255f using the ALD method or the like, which has good coverage. For example, it is preferable to form silicon nitride as the insulating film 255f using the PEALD method.

[0335] Furthermore, as shown in Figure 5A, when the insulator 255 is made into a laminated structure of insulator 255a and insulator 255b, the film that becomes insulator 255a can be formed by depositing silicon oxide using the PEALD method. The film that becomes insulator 255b is preferably formed under the same conditions as the insulating film 255f described above. In this way, by providing a silicon oxide film in contact with the side surfaces of conductor 242a2 and conductor 242b2, the side surfaces of conductor 242a2 and conductor 242b2 can be oxidized relatively easily. Therefore, as shown in Figure 3C, an oxide 243a is formed between conductor 242a2 and insulator 255, and an oxide 243b is formed between conductor 242b2 and insulator 255.

[0336] Next, a portion of the insulating film 255f is removed by anisotropic etching to form an insulator 255 in contact with the side wall of the opening (see Figures 15A to 15D). As a result, the insulator 255 is formed in contact with the side surface of insulator 280, the side surface of insulator 275, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of conductor 242a2, the side surface of conductor 242b2, the upper surface of conductor 242_1, and the upper surface of insulator 222. In addition, as shown in Figure 15C, a portion of the insulator 255 may be formed in contact with the side surface of insulator 224, the side surface of oxide semiconductor 230, the side surface of conductor 242_1, and the upper surface of insulator 222.

[0337] In a cross-sectional view along the channel length, the insulator 255 is formed inside an opening with width L1. Therefore, if L2 is the distance between the insulator 255 on side A1 and the insulator 255 on side A2, then L2 is shorter than L1.

[0338] For anisotropic etching of the insulating film 255f, a dry etching method is preferable. The conditions for the dry etching method and the dry etching apparatus can be considered in reference to the above description. For example, when silicon nitride is used for the insulating film 255f, an ICP etching apparatus is used, and CHF ３ and O ２ Etching can be performed by using this as the etching gas.

[0339] Furthermore, during etching of the insulating film 255f, generated ions may collide with the corners of the edges of the openings in the insulator 280 and insulator 255. As a result, these corners may be shaved off, resulting in a curved shape, as shown in Figure 5C and other figures. For example, by including an easily ionizable gas such as argon in the etching gas, or by applying bias power to the electrodes on the substrate side, these corners can be more easily removed.

[0340] Next, anisotropic etching is used to remove the portion of the conductor 242_1 exposed from the insulator 255, thereby forming the conductor 242a1 and the conductor 242b1 (see Figures 16A to 16D). In other words, the conductor 242_1 is processed using the insulator 255 as a mask, and the conductor 242_1 is divided into the conductor 242a1 and the conductor 242b1. By processing the conductor 242_1 using anisotropic etching, side etching of the insulator 255 can be suppressed. In this way, by processing the conductor 242_1 using the insulator 255 as a mask, the side edges of the conductor 242a1 and the conductor 242b1 are formed so that they coincide with or roughly coincide with the side edges of the insulator 255 in a cross-sectional view of the transistor 200.

[0341] In this way, in a cross-sectional view along the channel length, the distance between the conductor 242a1 and the conductor 242b1 is also L2. L2 is shorter than L1, and the difference between L1 and L2 may coincide with or approximately coincide with twice the film thickness of the insulator 255.

[0342] For anisotropic etching, it is preferable to use a dry etching method. The conditions for the dry etching method and the dry etching apparatus can be considered in reference to the above description. For example, when using ITO for the conductor 242_1, an ICP etching apparatus can be used. ２ Etching can be performed using Ar as the etching gas.

[0343] As described above, by using anisotropic etching to form an insulator 255 on the conductor 242_1, and then using the insulator 255 as a mask to divide the conductor 242_1, the insulator 255 that functions as a mask can be formed self-aligned. This makes it possible to reduce the number of masks and the number of processes in the semiconductor device manufacturing process shown in this embodiment. Therefore, a highly productive method for manufacturing semiconductor devices can be provided.

[0344] Furthermore, by using the above method, the island-shaped oxide semiconductor 230 can be exposed to dry etching only during the processing of the conductor 242_1. In other words, the upper surface of the island-shaped oxide semiconductor 230 can be prevented from being exposed to dry etching during the formation of the insulator 255. This reduces the damage (for example, damage due to ion collisions) that the oxide semiconductor 230b, which functions as the channel formation region of the transistor 200, suffers from dry etching. During the dry etching process of the conductor 242_1, the damage to the oxide semiconductor 230 can be further reduced by lowering the bias power midway through the process.

[0345] Furthermore, as shown in Figure 16B, recesses may be formed in the oxide semiconductor 230 in the portions exposed from the conductors 242a1 and 242b1. For example, if indium oxide is used for the oxide semiconductor 230 and ITO is used for the conductor 242_1, both the oxide semiconductor 230 and the conductor 242_1 contain indium oxide, making it difficult to selectively etch the conductor 242_1 relative to the oxide semiconductor 230. In this case, as shown in Figure 2A, the film thickness of the oxide semiconductor 230 in the region overlapping with the insulator 250 becomes thinner than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a1 or conductor 242b1.

[0346] Furthermore, as shown in Figure 16C, when the conductor 242_1 is removed, the upper part of the insulator 255 near the side surface of the oxide semiconductor 230 is also removed. In Figure 16C, the insulator 255 is formed so as to cover the side surface of the oxide semiconductor 230 and the side surface of the insulator 224, but the present invention is not limited to this. For example, depending on the anisotropic etching conditions of the insulating film 255f and the conductor 242_1, and the tapered shape of the side surface of the oxide semiconductor 230, the insulator 255 may be formed so as to cover a part of the side surface of the oxide semiconductor 230, or the insulator 255 may disappear near the side surface of the oxide semiconductor 230. In this case, the side surface of the oxide semiconductor 230 will be exposed.

[0347] Furthermore, an ashing treatment using oxygen plasma may be performed after processing the conductor 242_1. By performing such oxygen plasma treatment, impurities generated in the etching process and diffused into the oxide semiconductor 230 can be removed. These impurities are caused by components contained in the workpiece subjected to the etching process and components contained in the gas used for etching. Examples include chlorine, fluorine, tantalum, silicon, and hafnium. In particular, as shown in the etching process, if chlorine gas is used in processing the conductor 242_1, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove the chlorine adhering to the oxide semiconductor 230. By removing impurities adhering to the oxide semiconductor 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0348] Furthermore, the above-mentioned oxygen plasma treatment may cause at least a portion of the insulator 255 to be oxidized. In other words, the insulator 255 may contain oxygen. Note that if the oxidation of the insulator 255 progresses, at least a portion of the insulator 255 may become silicon oxidized nitride or silicon nitride oxide after the formation of the transistor 200.

[0349] Furthermore, the processing of the insulating film 255f and the conductor 242_1, as well as the oxygen plasma treatment, can be carried out continuously without exposure to the atmosphere. For example, the processing can be performed without exposure to the atmosphere using a multi-chamber etching apparatus.

[0350] As described above, conductors 242a1 and 242b1 with low contact resistance with the oxide semiconductor 230 can be formed under the conductors 242a2 and 242b2 with good conductivity. Further, an oxidation-resistant insulator 255 can be formed in contact with the side surfaces of the conductors 242a2 and 242b2. With such a configuration, the conductors 242a2 and 242b2 with good conductivity can be used as the source electrode and drain electrode of the transistor 200, and further, the parasitic capacitance between the conductor 260 and the conductor 242a2 and the parasitic capacitance between the conductor 260 and the conductor 242b2 can be reduced. Therefore, the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device can be improved.

[0351] In addition, in order to remove impurities and the like attached to the surface of the oxide semiconductor 230 in the above etching process, it is preferable to perform a cleaning process. Examples of the cleaning method include wet cleaning using a cleaning liquid or the like (which can also be referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The above cleaning may be appropriately combined. Note that the groove portion may become deeper by the cleaning process.

[0352] The wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water. The wet cleaning may also be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water. The wet cleaning may also be performed using pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning using these aqueous solutions, pure water, or carbonated water may be performed. Alternatively, these cleanings may be appropriately combined. In this specification and the like, an aqueous solution in which hydrofluoric acid is diluted with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution in which ammonia water is diluted with pure water may be referred to as diluted ammonia water. The concentration, temperature, and the like of the aqueous solution are appropriately adjusted according to the impurities to be removed, the configuration of the semiconductor device to be cleaned, and the like.

[0353] Also, the above cleaning process may be performed multiple times, and the cleaning liquid may be changed for each cleaning process. For example, as the first cleaning process, a process using diluted hydrofluoric acid or diluted ammonia water may be performed, and as the second cleaning process, a process using pure water or carbonated water may be performed.

[0354] It is preferable to perform a heat treatment after the above etching or after the above cleaning. The temperature of the heat treatment (or the temperature of the substrate) is 100°C or higher and 650°C or lower, preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 550°C or lower, and even more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen. For example, it is preferable to perform a treatment at a temperature of 350°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. Thereby, oxygen can be supplied to the oxide semiconductor 230 to reduce oxygen deficiency. Further, by performing such a heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, the oxygen supplied to the hydrogen remaining in the oxide semiconductor 230 reacts, so that the hydrogen can be removed (dehydrated) as H ２ O. Thereby, it is possible to suppress the recombination of the hydrogen remaining in the oxide semiconductor 230 with oxygen deficiency to form V Ｏ H. Therefore, the electrical characteristics of the transistor provided with the oxide semiconductor 230 can be improved, and the reliability can be enhanced. Also, variations in the electrical characteristics of a plurality of transistors formed on the same substrate can be suppressed. Note that the above heat treatment may be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere.

[0355] Here, as described above, an insulator 255 having an inorganic insulator that is resistant to oxidation is provided in contact with the side surfaces of the conductor 242a2 and the conductor 242b2. This prevents the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment, even if relatively easily oxidized tungsten films or the like are used for the conductors 242a2 and 242b2. Furthermore, it prevents the interfaces between the conductor 242a2 and conductor 242a1, and between the conductor 242b2 and conductor 242b1 from being excessively oxidized.

[0356] Furthermore, when heat treatment is performed on the oxide semiconductor 230 while the conductors 242a1 and 242b1 are in contact, the sheet resistance may decrease in the regions of the oxide semiconductor 230 that overlap with conductor 242a1 and conductor 242b1, respectively. Also, the carrier concentration may increase. Therefore, the resistance of the regions of the oxide semiconductor 230 that overlap with conductor 242a1 and conductor 242b1 can be reduced.

[0357] Next, an insulating film 250f, which will become an insulator 250, is formed to cover the openings formed in the insulator 280 and the like (see Figures 17A to 17D). Here, the insulating film 250f is formed along the openings of the insulator 280 and the insulator 275. The insulating film 250f is in contact with the insulator 280, the insulator 255, the conductor 242a1, the conductor 242b1, the insulator 222, and the oxide semiconductor 230.

[0358] The insulating film 250f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, it is preferable to form the insulating film 250f using the ALD method. The insulating film 250f is preferably formed with a thin film thickness, and it is necessary to reduce the variation in the film thickness. On the other hand, the ALD method is a film formation method in which a precursor and a reactant (such as an oxidizing agent) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so precise film thickness adjustment is possible. Also, the insulating film 250f needs to be formed with good coverage on the bottom surface and the side surface of the above-described opening. By using the ALD method, atomic layers can be deposited one by one on the bottom surface and the side surface of the above-described opening, so the insulating film 250f can be formed with good coverage with respect to the opening.

[0359] Also, when forming the insulating film 250f by the ALD method, as the oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), etc. can be used. By using ozone (O ３ ), oxygen (O ２ ) etc. that do not contain hydrogen as the oxidizing agent, the hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0360] As shown in FIG. 2A etc., the insulator 250 can have a laminated structure. Hereinafter, as in FIG. 2A, the method of forming the insulating film 250f when the insulator 250 has a four-layer structure of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d will be described.

[0361] First, a film that becomes the insulator 250a is formed so as to cover the opening formed in the insulator 280 etc., and further, a film that becomes the insulator 250b is formed on the film that becomes the insulator 250a. In the present embodiment, as the film that becomes the insulator 250a, hafnium oxide is formed by the thermal ALD method, and as the film that becomes the insulator 250b, silicon oxide is formed by the PEALD method.

[0362] Next, it is preferable to perform microwave plasma treatment in an oxygen-containing atmosphere. Here, microwave plasma treatment refers to treatment using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0363] In microwave plasma processing, it is preferable to use a microwave plasma processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave plasma processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave plasma processing apparatus is preferably 1000 W to 10000 W, more preferably 2000 W to 5000 W. The microwave plasma processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide semiconductor 230.

[0364] Furthermore, the above microwave plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, around 250°C. In addition, after the oxygen plasma treatment, a continuous heat treatment may be performed without exposure to the outside air. The heat treatment temperature is preferably, for example, 100°C to 750°C, and more preferably 300°C to 500°C.

[0365] Furthermore, for example, the above microwave plasma treatment can be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / ( O ２ The oxygen flow rate ratio (O) is greater than 0% and less than or equal to 100%. Preferably, the oxygen flow rate ratio (O) ２ / ( O ２The oxygen flow rate ratio (O) is greater than 0% and 50% or less. ２ / ( O ２ The oxygen flow rate ratio (O) is set to 10% or more and 40% or less. More preferably, the oxygen flow rate ratio (O) ２ / ( O ２ The amount of +Ar) is set to 10% or more and 30% or less. In this way, by performing microwave plasma treatment in an oxygen-containing atmosphere, the carrier concentration in the region exposed from the aperture of the oxide semiconductor 230 can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave plasma treatment, it is possible to prevent an excessive decrease in the carrier concentration in the oxide semiconductor 230.

[0366] By performing microwave plasma treatment in an oxygen-containing atmosphere, the oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region of the oxide semiconductor 230 between the conductor 242a and the conductor 242b. Due to the action of the plasma, microwaves, etc., the V in that region Ｏ H can be separated into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, it is preferable to use an insulating film (for example, aluminum oxide) that has the function of capturing or fixing hydrogen as the film that becomes the insulator 250a. With this configuration, the hydrogen generated by microwave plasma treatment can be captured or fixed to the film that becomes the insulator 250a. In this way, the V included in the channel formation region Ｏ H can be reduced. As a result, oxygen deficiency in the channel formation region and V Ｏ This reduces H and lowers the carrier concentration. Furthermore, by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0367] The oxygen injected into the channel-forming region can take various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with unpaired electrons). The oxygen injected into the channel-forming region may be one or more of the above forms, with oxygen radicals being particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby increasing the reliability of the transistor. Additionally, the above microwave plasma treatment can supply oxygen to the insulators 250a and 250b. Excess oxygen from the insulators 250a and 250b can be supplied to the channel-forming region of the oxide semiconductor 230 by subsequent heat treatment.

[0368] On the other hand, the oxide semiconductor 230 has a region that overlaps with either the conductor 242a or the conductor 242b. This region can function as a source region or a drain region. Here, it is preferable that the conductors 242a and 242b function as shielding films against the effects of microwaves, high frequencies such as RF, and oxygen plasma when performing microwave plasma processing in an oxygen-containing atmosphere. For this reason, it is preferable that the conductors 242a and 242b have the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example, between 2.4 GHz and 2.5 GHz.

[0369] Conductors 242a and 242b shield against the effects of microwaves, RF or other high-frequency waves, oxygen plasma, etc., so these effects do not extend to the region of the oxide semiconductor 230 that overlaps with either conductor 242a or conductor 242b. As a result, the microwave plasma treatment does not affect the source region and drain region. Ｏ Because H is reduced and excessive oxygen supply does not occur, a decrease in carrier concentration can be prevented.

[0370] Furthermore, an insulator 255 is provided in contact with the sides of the conductors 242a2 and 242b2, providing a barrier against oxygen. Additionally, a film forming an insulator 250a and a film forming an insulator 250b are provided covering the conductors 242a1, 242b1, and the insulator 255. This suppresses the formation of oxide films on the sides of the conductors 242a2 and 242b2 by microwave plasma treatment.

[0371] As described above, oxygen vacancies and V are selectively formed in the channel formation region of the oxide semiconductor. Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to the region that functions as the source or drain region, and maintain the conductivity (low resistance state) before microwave plasma treatment. This suppresses variations in the electrical properties of the transistor and prevents variations in the electrical properties of the transistor within the substrate surface.

[0372] Furthermore, by modifying the film quality of the insulator 250a and the insulator 250b by performing microwave plasma treatment, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, by post-processing such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., into the oxide semiconductor 230, etc., through the insulator 250 can be suppressed. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0373] Next, a film that will become an insulator 250c is deposited on the film that will become an insulator 250b. In this embodiment, hafnium oxide is deposited as the film that will become an insulator 250c by thermal ALD. Microwave plasma treatment may be performed again after the deposition of the film that will become an insulator 250c.

[0374] Next, a film that will become an insulator 250d is formed on the film that will become an insulator 250c. In this embodiment, silicon nitride is formed as the film that will become an insulator 250d by the PEALD method. In this way, an insulating film 250f having a film that will become an insulator 250a to an insulator 250d can be formed.

[0375] In the above, an example was shown in which microwave plasma treatment is performed after the film that will become the insulator 250b and after the film that will become the insulator 250c is formed, but the present invention is not limited to this. It is also possible to configure the device to perform microwave plasma treatment after the film that will become the insulator 250b and the film that will become the insulator 250c are formed. It is also possible to configure the device to perform microwave plasma treatment after the film that will become the insulator 250d is formed. Alternatively, it is possible to configure the device to perform microwave plasma treatment before the film that will become the insulator 250a is formed. Furthermore, it is also possible to configure the device to perform microwave plasma treatment three or more times.

[0376] Alternatively, a heat treatment may be performed while maintaining a reduced pressure state after microwave plasma treatment. By performing such a heat treatment, hydrogen in the insulating film and oxide semiconductor 230 can be efficiently removed. Furthermore, by performing such a heat treatment, excess oxygen supplied to the insulators 250a, 250b, and 250c during microwave plasma treatment can be supplied to the channel formation region of the oxide semiconductor 230. Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave plasma treatment may be repeated multiple times. By repeating the heat treatment, hydrogen in the insulating film and oxide semiconductor 230 can be removed even more efficiently. The heat treatment temperature is preferably 300°C to 500°C.

[0377] Next, a conductive film 260f, which will become the conductor 260, is deposited (see Figures 18A to 18D). The conductive film 260f can be deposited using the conductive material described above by sputtering, CVD, MBE, PLD, plating, or ALD. For example, as shown in Figure 2A, when forming a laminated structure of conductor 260a and conductor 260b, titanium nitride can be deposited as the conductive film for conductor 260a using the ALD method. Furthermore, tungsten can be deposited as the conductive film for conductor 260b using the CVD method.

[0378] The conductive film that will become the conductor 260a can be formed by thermal ALD using an inorganic precursor, without using a hydrogen-containing gas. For example, TiCl ４ In this case, NH can be used as the nitride agent. ３ A gas can be used. By forming the film using the method described above, the conductor 260a can be made into a conductive film with a low hydrogen concentration as described above. Therefore, these conductive films can act as a hydrogen source, preventing hydrogen from diffusing into the oxide semiconductor.

[0379] Here, the conductor 260a overlaps with the oxide semiconductor 230 via a thin insulator 250, and is close to the channel formation region of the oxide semiconductor 230. Therefore, if a hydrogen-containing treatment is performed during the film formation process of the conductor 260a, hydrogen will easily diffuse into the channel formation region of the oxide semiconductor 230. For this reason, it is preferable to make the conductor 260a a conductive film with a low hydrogen concentration, as described above.

[0380] Next, the insulating film 250f and the conductive film 260f are polished by CMP treatment until the insulators 280 and 255 are exposed. In other words, the portions of the insulating film 250f and the conductive film 260f that are exposed from the opening are removed. This forms the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) inside the opening that overlaps with the conductor 205.

[0381] As a result, the insulator 250 is provided in contact with the insulator 255, the conductor 242a1, the conductor 242b1, the oxide semiconductor 230, and the insulator 222 within the opening. The conductor 260 is also arranged to fill the opening via the insulator 250. In this way, the transistor 200 is formed.

[0382] Next, an insulator 282 is deposited on the insulator 255, the insulator 250, the conductor 260, and the insulator 280. The deposition of the insulator 282 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0383] Here, by using a sputtering method to form the insulator 282 in an atmosphere containing oxygen, oxygen can be added to the insulator 280 while forming the film. As a result, the insulator 280 can be made to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate.

[0384] Further, the insulator 282 can also have a laminated structure. In this case, it is preferable that the lower layer is a thin aluminum oxide film formed by the ALD method and the upper layer is a thick aluminum oxide film formed by the sputtering method. By forming the aluminum oxide film by the sputtering method on top of the thin aluminum oxide film in this way, the amount of oxygen injected into the insulator 280 can be controlled. Thereby, a sufficient amount of oxygen can be supplied to the oxide semiconductor 230, and it is possible to prevent an excessive amount of oxygen from being supplied to the oxide semiconductor 230.

[0385] Next, an insulator 283 is formed on the insulator 282. The insulator 283 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The formation of the insulator 283 is preferably performed using a sputtering method. By using a sputtering method that does not require the use of a molecule containing hydrogen in the film-forming gas, the hydrogen concentration in the insulator 283 can be reduced. In the present embodiment, silicon nitride is formed as the insulator 283 using a sputtering method.

[0386] In the present embodiment, silicon nitride is formed as the insulator 283 and aluminum oxide is formed as the insulator 282. By using silicon nitride having a function of suppressing the diffusion of hydrogen for the insulator 283 in this way, it is possible to suppress the diffusion of hydrogen from the upper layer of the transistor 200 to the oxide semiconductor 230. Further, by using aluminum oxide having a function of capturing or fixing hydrogen for the insulator 282, the hydrogen contained in the insulator 280 or the like can be captured or fixed by the insulator 282. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0387] Next, an insulator 285 is formed on the insulator 283 (see Figures 19A to 19D). The insulator 285 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced. In this embodiment, silicon oxide is deposited as the insulator 285 using sputtering.

[0388] Here, it is preferable to deposit the insulators 282, 283, and 285 continuously by sputtering without exposing them to the atmospheric environment. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 282, 283, and 285, and to keep the interface or vicinity of the interface between insulator 282 and insulator 283, and the interface or vicinity of the interface between insulator 283 and insulator 285 clean.

[0389] Next, openings reaching the conductor 242a2 are formed in insulators 271a, 275, 280, 282, 283, and 285, and openings reaching the conductor 242b2 are formed in insulators 271b, 275, 280, 282, 283, and 285. These openings may be formed using lithography. It is preferable to process the workpiece using a dry etching method for forming these openings. Dry etching is suitable for forming openings with a high aspect ratio because it allows for anisotropic etching. When performing anisotropic etching, it is preferable to perform reactive ion etching, for example. The conditions for the dry etching method and the dry etching apparatus can be found in the description above. The shape of the opening in a top view can be a circle, an ellipse or other approximate circle, a quadrilateral or other polygon, or a quadrilateral or other polygon with rounded corners.

[0390] Next, after the openings are formed, a heat treatment can be performed. The temperature of the heat treatment can be 100°C to 600°C, preferably 250°C to 550°C, and more preferably 350°C to 450°C. The heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas. Furthermore, since the heat treatment is performed with the conductors 242a2 and 242b2 exposed, it is preferable to perform it in an atmosphere that does not contain oxidizing gases or oxygen gas. For example, it is preferable to perform the heat treatment in a nitrogen gas atmosphere at a temperature of 400°C for 1 hour. The heat treatment may also be performed under reduced pressure. Through the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 via the insulator 250. This reduces oxygen vacancies in the channel formation region of the oxide semiconductor 230.

[0391] Here, since the side surface of the insulator 280 is exposed at the opening, the amount of oxygen contained in the insulator 280 can be controlled by the heat treatment by diffusing the oxygen contained in the insulator 280 outward. On the other hand, since insulators 282 and 283, which have barrier properties against oxygen, are provided on top of the insulator 280, oxygen does not diffuse outward from the upper surface of the insulator 280. This prevents excessive oxygen from diffusing outward from the insulator 280 and prevents the formation of oxygen vacancies in the insulator 280. In addition, the oxide semiconductor 230, conductor 242a, and conductor 242b are covered by the insulator 275. This prevents an excessive amount of oxygen from directly diffusing from the insulator 280 to the oxide semiconductor 230, conductor 242a, and conductor 242b during the heat treatment.

[0392] As described above, in the deposition of the insulator 282, oxygen is added to the insulator 280, and the oxygen is diffused outward from the side surface of the insulator 280 by the heat treatment described above, thereby allowing for a more favorable adjustment of the oxygen content in the insulator 280. By supplying oxygen from the insulator 280 with the adjusted oxygen content in this way to the oxide semiconductor 230, a suitable amount of oxygen can be supplied to the oxide semiconductor 230. This reduces oxygen deficiency in the oxide semiconductor 230 and prevents an excessive amount of oxygen from being supplied to the oxide semiconductor 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, since the step of exposing the side surface of the insulator 280 can be combined with the step of forming the openings for embedding the conductors 240a and 240b, the manufacturing process of the semiconductor device can be simplified.

[0393] Furthermore, by performing the above heat treatment, some of the hydrogen contained in insulator 280, insulator 250, and oxide semiconductor 230 can be diffused outward through the opening. In addition, some of the remaining hydrogen moves to insulator 282 and is captured within insulator 282. In other words, the hydrogen contained in insulator 280, insulator 250, and oxide semiconductor 230 diffuses into insulator 282. Therefore, the hydrogen concentration in insulator 282 increases, but the hydrogen concentrations in insulator 280, insulator 250, and oxide semiconductor 230 each decrease. By providing insulator 283 in contact with the upper surface of insulator 282, it is possible to prevent moisture or impurities such as hydrogen from entering from above insulator 283 during the heat treatment. Furthermore, by performing the heat treatment, the hydrogen contained in insulator 216, insulator 224, and oxide semiconductor 230 moves to insulator 222 and is captured within insulator 222. In other words, hydrogen contained in insulator 216, insulator 224, and oxide semiconductor 230 diffuses into insulator 222. Consequently, the hydrogen concentration in insulator 222 increases, while the hydrogen concentrations in insulator 216, insulator 224, and oxide semiconductor 230 decrease. Furthermore, by providing insulator 221 in contact with the lower surface of insulator 222, it is possible to prevent moisture or impurities such as hydrogen from entering from below insulator 221 during the heat treatment.

[0394] Next, a film that will become the insulator 241 is formed along the shape of the opening. The film that will become the insulator 241 can be formed using sputtering, CVD, MBE, PLD, or ALD. Since the film that will become the insulator 241 is formed inside the opening with a large aspect ratio, it is preferable to form it using the ALD method. As the film that will become the insulator 241, it is preferable to use an insulating film that has the function of suppressing oxygen permeability. For example, it is preferable to form silicon nitride using the PEALD method. Silicon nitride is preferred because it has high barrier properties against hydrogen.

[0395] Next, the film that will become the insulator 241 is anisotropically etched to form insulators 241a and 241b. Here, insulator 241a is formed to cover the side wall of the opening on the conductor 242a2, and insulator 241b is formed to cover the side wall of the opening on the conductor 242b2. For the anisotropic etching of the film that will become the insulator 241, a dry etching method or the like may be used. For example, reactive ion etching is preferred. By providing insulators 241a, 241b, and 241c on the side walls of the openings, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b that will be formed next can be prevented. In addition, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the conductors 240a and 240b. Note that, as a result of this anisotropic etching, recesses may be formed on a part of the upper surface of the conductors 242a2 and 242b2.

[0396] Next, a film that will become the conductor 240 is formed. The film that will become the conductor 240 is a laminated film consisting of films that will become conductors 240a1 and 240b1, and films that will become conductors 240a2 and 240b2, as shown in Figure 2A. The film that will become the conductor 240 can be formed using the conductive material described above, using sputtering, CVD, MBE, PLD, ALD, or the like.

[0397] Titanium nitride can be deposited as conductive films 240a1 and 240b1 using the thermal ALD method. Furthermore, tungsten can be deposited as conductive films 240a2 and 240b2 using the CVD method. The conductive films 240a1 and 240b1 can be deposited using the thermal ALD method with an inorganic precursor, without using a hydrogen-containing gas. For example, TiCl can be used as the inorganic precursor. ４ In this case, NH can be used as the nitride agent. ３ A gas can be used. By forming the film using the method described above, the conductor 240a1 and conductor 240b1 can be made into conductive films with a low hydrogen concentration as described above. Therefore, these conductive films can act as a hydrogen source, preventing hydrogen from diffusing into the oxide semiconductor.

[0398] Next, the film that will become the conductor 240 is subjected to CMP treatment, which removes a portion of the film that will become the conductor 240, exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figures 1A to 1D). As described above, conductors 240a and 240b can be formed in parallel in the same process. For this reason, conductors 240a1 and 240b1 are each formed using the same conductive material. Similarly, conductors 240a2 and 240b2 are each formed using the same conductive material. Note that in some cases, a portion of the upper surface of the insulator 285 may be removed by the CMP treatment.

[0399] Furthermore, it is preferable to perform a further heat treatment after forming the conductors 240a and 240b. The same conditions as those used for the above heat treatment can be used for this heat treatment.

[0400] Based on the above, the semiconductor devices shown in Figures 1A to 1D can be manufactured.

[0401] In the above, a method for fabricating a structure in which the insulator 255 is in contact with the upper surface of the conductor 242a1 and the upper surface of the conductor 242b1 has been described, but the present invention is not limited thereto. A structure in which the insulator 255 is in contact with the upper surface of the oxide semiconductor 230 can also be fabricated. Below, as an example, the fabrication process of the semiconductor device shown in Figure 4A will be described with reference to Figures 20A to 20D.

[0402] First, the process is carried out in the same manner as above up to the steps shown in Figures 13A to 13D to form the conductors 242a2 and 242b2. Here, by performing a highly isotropic etching process, the sides of the conductor 242a2 and the conductor 242b2 are side-etched (see Figure 20A). As a result, as shown in Figure 20A, the distance L1 between the conductor 242a2 and the conductor 242b2 becomes larger than the distance L1 shown in Figure 13B. To perform a highly isotropic etching process, for example, the bias power can be reduced compared to the anisotropic etching process described above. By side-etching the sides of the conductor 242a2 and the conductor 242b2, a structure can be formed in which the distance between the conductor 242a2 and the insulator 250, and the distance between the conductor 242b2 and the insulator 250, are each larger than the distance between the insulator 280 and the insulator 250, as shown in Figure 4A. This makes it possible to reduce the parasitic capacitance between conductor 260 and conductor 242a2, and between conductor 260 and conductor 242b2.

[0403] Next, the portion of the conductor 242_1 that does not overlap with the insulator 280 is removed in the same manner as in Figures 16A to 16D to form the conductors 242a1 and 242b1 (see Figure 20B). By forming the conductors 242a1, 242a2, 242b1, and 242b2 as described above, curved surfaces may be formed on the sides of the conductors 242a1, 242a2, 242b1, and 242b2, as shown in Figure 6A.

[0404] As shown in Figure 20B, recesses may be formed in the oxide semiconductor 230 in the portions exposed from the conductors 242a1 and 242b1. For example, if indium oxide is used for the oxide semiconductor 230 and ITO is used for the conductor 242_1, both the oxide semiconductor 230 and the conductor 242_1 contain indium oxide, making it difficult to selectively etch the conductor 242_1 relative to the oxide semiconductor 230. In this case, as shown in Figure 4A, the film thickness of the oxide semiconductor 230 in the region in contact with the insulator 255 becomes thinner than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a1 or conductor 242b1.

[0405] Furthermore, by performing an etching process with high isotropy, the sides of the conductor 242a1 and the conductor 242b1 can be side-etched. For example, etching can be done with a lower bias power than the anisotropic etching process described above. Also, when ITO is used for conductor 242_1, BCl ３ A gas with high etching properties for conductor 242_1 may be used. By side etching the sides of conductor 242a1 and conductor 242b1, a structure can be formed in which the distance between conductors 242a1 and conductor 242a2 and the insulator 250, and the distance between conductors 242b1 and conductor 242b2 and the insulator 250 are greater than the distance between insulator 280 and insulator 250, as shown in Figure 4B. This reduces the parasitic capacitance between conductor 260 and conductor 242a, and between conductor 260 and conductor 242b. In addition, as shown in Figure 6B, curved surfaces may be formed on the sides of conductor 242a1, conductor 242a2, conductor 242b1, and conductor 242b2.

[0406] Next, an insulating film 255f is formed by covering the insulator 280, conductor 242a1, conductor 242a2, oxide semiconductor 230, and insulator 222 in the same manner as in Figures 14A to 14D (see Figure 20C). It is preferable to form the insulating film 255f using a method that provides good coverage. For example, it is preferable to form silicon nitride as the insulating film 255f using the PEALD method. By forming an insulating film 255f with good coverage, the insulating film 255f can be formed in the recesses on the side surface of the conductor 242a2 and the recesses on the side surface of the conductor 242b2, as shown in Figure 20C.

[0407] Next, a portion of the insulating film 255f is removed by anisotropic etching in the same manner as in the methods shown in Figures 15A to 15D to form an insulator 255 in contact with the side wall of the opening (see Figure 20D). As a result, the insulator 255 is formed in contact with the side surface of insulator 280, the side surface of insulator 275, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of conductor 242a2, the side surface of conductor 242b2, the upper surface of conductor 242a1, the side surface of conductor 242a1, the upper surface of conductor 242b1, the side surface of conductor 242b1, the upper surface of oxide semiconductor 230, and the upper surface of insulator 222.

[0408] In a cross-sectional view along the channel length, the insulator 255 is formed inside the opening. Therefore, if L2 is the distance between the insulator 255 on side A1 and the insulator 255 on side A2, then L2 is shorter than L1.

[0409] Furthermore, during etching of the insulating film 255f, generated ions may collide with the corners of the edges of the openings in the insulator 280 and insulator 255. As a result, these corners may be removed, resulting in a curved shape, as shown in Figure 6A and other figures. For example, by including an easily ionizable gas such as argon in the etching gas, or by applying bias power to the electrodes on the substrate side, the removal of these corners becomes easier.

[0410] Furthermore, as shown in Figure 20D, recesses may be formed in the portion of the oxide semiconductor 230 that is exposed from the insulator 255. In this case, as shown in Figure 4A, the film thickness of the oxide semiconductor 230 in the region in contact with the insulator 250 becomes thinner than the film thickness of the oxide semiconductor 230 in the region in contact with the insulator 255.

[0411] The steps after the formation of the insulator 255 can be carried out in the same manner as the steps shown in Figures 17A to 19D.

[0412] The semiconductor device according to this embodiment has an OS transistor. In this embodiment, by reducing the parasitic capacitance between the gate electrode of the OS transistor and the source and drain electrodes, a semiconductor device with high frequency characteristics and high operating speed can be provided.

[0413] This embodiment can be appropriately combined with other embodiments and examples. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, the configuration examples can be appropriately combined.

[0414] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0415] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0416] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0417] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 21A shows silicon (Si) and indium oxide (InO ＸFigure 21B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0418] First, as indicated by the arrows in Figure 21B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 21A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 2). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 21A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 21A.

[0419] In Figure 21A, the range R1 with low carrier concentration exhibits extremely high hole mobility, making it a suitable range of carrier concentration for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0420] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0421] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0422] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0423] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, sometimes resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 21A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0424] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0425] Furthermore, the i-type nature of a semiconductor can be rephrased as the Fermi level (Ef) and the intrinsic Fermi level (Ei) being the same (Ef = Ei). As shown in Figure 21B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 21A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Moreover, transistors containing indium oxide tend to be normally off due to their low carrier concentration. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0426] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic, where Vth is 1nA (1 × 10⁻¹⁰). −９ Let Vsh be the gate voltage (Vg) when A) is true. Also, Vsh is the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0427] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, that is, for achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0428] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0429] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0430] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0431] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0432] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0433] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0434] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0435] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0436] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0437] Furthermore, the indium oxide film described herein has a high film density. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0438] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0439] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0440] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 21C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. ＯIf oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0441] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0442] Furthermore, as shown in Figure 21C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0443] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0444] Table 1 shows single crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in an environment at room temperature or 25°C. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0445]

[0446] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0447] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0448] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0449] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0450] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0451] This embodiment can be appropriately combined with other embodiments and examples. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, the configuration examples can be appropriately combined.

[0452] (Embodiment 3) This embodiment describes an example of the configuration of a display device to which a transistor according to one aspect of the present invention can be applied.

[0453] Since the transistor according to one aspect of the present invention can be made extremely small, a display device to which the transistor according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, the display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as VR (Virtual Reality) devices such as head-mounted displays and AR (Augmented Reality) devices such as glasses.

[0454] [Display Module] Figure 22A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590. Note that the display panel of the display module 580 is not limited to the display device 500A, but may be the display device 500B or the display device 500C described later.

[0455] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0456] Figure 22B shows a schematic perspective view illustrating the configuration of the substrate 591. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586, which is composed of multiple wires.

[0457] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 22B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0458] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0459] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0460] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0461] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are superimposed on the lower side of the pixel section 584, thereby making the aperture ratio (effective display area ratio) of the display section 581 extremely high. For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that the pixels 584a in the display section 581 are arranged at a density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0462] Because such a display module 580 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as wristwatches.

[0463] [Display device 500A] The display device 500A shown in Figure 23 has a substrate 201, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitive element 140, and a transistor 520.

[0464] Substrate 201 corresponds to substrate 591 in Figure 22A.

[0465] The transistor 520 is a transistor in which an oxide semiconductor is applied to the semiconductor layer where the channel is formed. The transistor 520 has an oxide semiconductor 230, a conductor 205, an insulator 222, an insulator 224, a conductor 242a, a conductor 242b, an insulator 250, and a conductor 260, etc. Interlayer films are formed on the substrate 201 in the order of insulator 212, an insulator 216, an insulator 222, an insulator 280, an insulator 282, an insulator 283, and an insulator 285. Conductors 240 and insulator 241 are formed inside openings formed in insulators 280, 282, 283, and 285.

[0466] The transistor 520 can be any of the various transistors exemplified in Embodiment 1. This reduces the parasitic capacitance and leakage current of the transistor 520. As a result, the power consumption of the display device 500A can be reduced.

[0467] Furthermore, although the transistor 520 is simplified in Figure 23, the structure of the transistor 200 and its vicinity as described in Figure 9A can also be used. For example, as shown in Figure 9A, an insulator having barrier properties against impurities such as hydrogen can be provided on the upper and lower layers of the transistor. This prevents hydrogen contained in the substrate and its vicinity, as well as in the light-emitting element and its vicinity, from diffusing into the transistor 520. Also, by providing an insulator 241 covering the side surface of the conductor 240 and using a conductive film with reduced hydrogen concentration on the conductor 240, it is possible to prevent hydrogen contained in the light-emitting element and its vicinity from diffusing into the insulator 280 via the conductor 240. This prevents impurities, oxygen vacancies, and V in the channel formation region of the oxide semiconductor 230. Ｏ By reducing H and other parameters, the electrical characteristics and reliability of the transistor 520 can be improved. Therefore, a display device with good display performance and reliability can be provided. The conductor 240 and the insulator 241 correspond to the conductors 240a to 240d and the insulators 241a to 241d described in Embodiment 1, respectively.

[0468] Furthermore, a capacitive element 140 is provided on the insulator 285. The capacitive element 140 has a conductive layer 141, a conductive layer 145, and an insulating layer 143 located between them. The conductive layer 141 functions as one electrode of the capacitive element 140, the conductive layer 145 functions as the other electrode of the capacitive element 140, and the insulating layer 143 functions as the dielectric of the capacitive element 140.

[0469] The conductive layer 141 is provided on the insulator 285 and embedded in the insulating layer 154. The conductive layer 141 is electrically connected to the conductor 242a of the transistor 520 by the conductor 240. The insulating layer 143 is provided covering the conductive layer 141. The conductive layer 145 is provided in the region that overlaps with the conductive layer 141 via the insulating layer 143.

[0470] Capacitive element 140 corresponds to capacitive element 400 shown in Figure 9A, etc. Although the capacitive element 140 is simplified in Figure 23, the structure of the capacitive element 400 and its vicinity as described in Figure 9A, etc., can also be used. For example, as shown in Figure 9A, an insulator that has barrier properties against impurities such as hydrogen can be provided to cover the capacitive element. This prevents hydrogen contained in the light-emitting element and its vicinity from diffusing to the lower-layer transistor 520. Thus, a highly reliable display device can be provided.

[0471] Furthermore, as shown in Figure 9A, a wiring layer can also be provided on top of the capacitive element 140. Also, the connection relationships of circuit elements, wiring, vias, etc., in the display device according to this embodiment are not limited to those shown in Figure 23. The connection relationships of circuit elements, wiring, vias, etc., can be appropriately set to match the pixel circuit of the display device.

[0472] An insulating layer 155a is provided to cover the capacitive element 140, an insulating layer 155b is provided on the insulating layer 155a, and an insulating layer 155c is provided on the insulating layer 155b.

[0473] Insulating layers 155a, 155b, and 155c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 155a and 155c, and silicon nitride films for insulating layer 155b. This allows insulating layer 155b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 155c is etched and a recess is formed, but the insulating layer 155c does not necessarily have to have a recess.

[0474] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 155c.

[0475] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting elements 110R, 110G, and 110B.

[0476] The organic layer 112R of the light-emitting element 110R contains at least a luminescent organic compound that emits red light. The organic layer 112G of the light-emitting element 110G contains at least a luminescent organic compound that emits green light. The organic layer 112B of the light-emitting element 110B contains at least a luminescent organic compound that emits blue light. The organic layers 112R, 112G, and 112B can each also be called EL layers and each contains at least a luminescent organic compound (luminescent layer).

[0477] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 112R, 112G, and 112B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0478] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0479] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductor 242a of the transistor 520 by a plug 156 embedded in the insulating layer 155a, insulating layer 155b, and insulating layer 155c, a conductive layer 141 embedded in the insulating layer 154, and a conductor 240. The height of the upper surface of the insulating layer 155c and the height of the upper surface of the plug 156 are equal or approximately equal. Various conductive materials can be used for the plug.

[0480] Furthermore, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. The substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0481] There is no insulating layer covering the upper edge of the pixel electrode 111 between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0482] [Display Device 500B] The following describes a display device with some configuration differences from the one described above. Note that parts common to the above will be referred to and may be omitted from the explanation.

[0483] The display device 500B shown in Figure 24 has a configuration in which a transistor 520A on a substrate 201 and a transistor 520B on top of transistor 520A are stacked. Here, transistors 520A and 520B have the same configuration as transistor 520. In other words, the display device 500B has a structure in which, in the display device 500A shown in Figure 23, another layer containing transistor 520 is added between the layer containing transistor 520 and the substrate 201.

[0484] Similar to the display device 500A, the transistors 520A and 520B can be the various transistors exemplified in Embodiment 1. This reduces the parasitic capacitance and leakage current of transistors 520A and 520B. Therefore, the power consumption of the display device 500B can be reduced.

[0485] Furthermore, in the layer containing transistor 520A and the layer containing transistor 520B, as shown in Figure 9A, an insulator having barrier properties against impurities such as hydrogen can be provided on the upper and lower layers of the transistors. This prevents hydrogen contained in the substrate and its vicinity, as well as in the light-emitting element and its vicinity, from diffusing into transistors 520A and 520B. Additionally, by providing an insulator 241 covering the side surface of the conductor 240 and using a conductive film with reduced hydrogen concentration on the conductor 240, it is possible to prevent hydrogen contained in the light-emitting element and its vicinity from diffusing into the insulator 280 via the conductor 240. In this way, a display device with good display performance and reliability can be provided.

[0486] Furthermore, although simplified in Figure 24, transistors 520A and 520B can be electrically connected by connecting wiring and vias, as shown in Figure 9A with conductors 412, 240c, 218, and 217. Here, by using a conductive film with high hydrogen barrier properties and a low hydrogen concentration for conductor 240, it is possible to prevent impurities such as hydrogen from diffusing to transistors 520A and 520B through the wiring and vias. Moreover, the connection relationships of circuit elements, wiring, vias, etc. in the display device according to this embodiment are not limited to the connection relationships shown in Figure 24. The connection relationships of circuit elements, wiring, vias, etc. can be appropriately set according to the pixel circuit of the display device.

[0487] [Display Device 500C] The display device 500C shown in Figure 25 has a configuration in which a transistor 310 with a channel formed on a semiconductor substrate and a transistor 520B on the transistor 310 are stacked. Here, the transistor 520B has the same configuration as the transistor 520. In other words, the display device 500C has a structure in which a layer including the transistor 310 is provided instead of the layer including the transistor 520A in the display device 500B shown in Figure 24.

[0488] The transistor 310 is a transistor having a channel-forming region in the substrate 311. The substrate 311 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 310 comprises a portion of the substrate 311, a conductor 316, a low-resistance region 314, an insulator 315, and an insulator 317. The conductor 316 functions as a gate electrode. The insulator 315 is located between the substrate 311 and the conductor 316 and functions as a gate insulating layer. The low-resistance region 314 is a region of the substrate 311 doped with impurities and functions as either a source or a drain. The insulator 317 is provided covering the side surface of the conductor 316.

[0489] Furthermore, an element isolation layer 318 is provided between two adjacent transistors 310 so as to be embedded in the substrate 311.

[0490] Similar to the display device 500A, the transistor 520B can be one of the various transistors exemplified in Embodiment 1. This reduces the parasitic capacitance and leakage current of the transistor 520B. Therefore, the power consumption of the display device 500C can be reduced.

[0491] Furthermore, in the layer containing transistor 520B, as shown in Figure 9A, an insulator having barrier properties against impurities such as hydrogen can be provided above and below the transistor. This prevents hydrogen contained in the light-emitting element and its vicinity from diffusing into transistor 520B. It also prevents hydrogen contained in transistor 310 and its vicinity from diffusing into transistor 520B. In addition, by providing an insulator 241 covering the side surface of the conductor 240, it is possible to prevent hydrogen contained in the light-emitting element and its vicinity from diffusing into the insulator 280 via the conductor 240. In this way, a highly reliable display device can be provided.

[0492] Furthermore, although simplified in Figure 25, the transistor 520B and transistor 310 can be electrically connected by connecting the wiring and vias, as shown in Figure 9A with conductors 412, 240c, 218, and 217. By using a conductive film with high hydrogen barrier properties and low hydrogen concentration for the wiring and vias, it is possible to prevent impurities such as hydrogen and copper from diffusing into transistor 520B through the wiring and vias connected to transistor 310. This makes it possible to provide a display device with good display performance and reliability. Moreover, the connection relationships of circuit elements, wiring, vias, etc. in the display device according to this embodiment are not limited to the connection relationships shown in Figure 24. The connection relationships of circuit elements, wiring, vias, etc. can be appropriately set according to the pixel circuit of the display device.

[0493] This embodiment can be appropriately combined with other embodiments and examples. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, the configuration examples can be appropriately combined.

[0494] (Embodiment 4) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 26A to 28G.

[0495] The electronic device of this embodiment has a display panel (display device) to which a transistor according to one aspect of the present invention is applied in the display unit. The display device according to one aspect of the present invention can be easily made high-definition and high-resolution, and can achieve high display quality. Therefore, it can be used in the display unit of various electronic devices.

[0496] Examples of electronic devices include television sets, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0497] In particular, a display panel according to one embodiment of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR (Mixed Reality) devices.

[0498] A display panel according to one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore...

Claims

1. An oxide semiconductor; a first conductor and a second conductor spaced apart from each other on the oxide semiconductor; a third conductor in contact with a part of the upper surface of the first conductor; a fourth conductor in contact with a part of the upper surface of the second conductor; a first insulator disposed on the third conductor and the fourth conductor, having an opening that overlaps with the region between the third conductor and the fourth conductor; a second insulator disposed within the opening, in contact with another part of the upper surface of the first conductor, another part of the upper surface of the second conductor, the side surface of the third conductor, and the side surface of the fourth conductor; a third insulator disposed within the opening, in contact with the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator; and a fifth conductor disposed within the opening on the third insulator, having a region that overlaps with the oxide semiconductor via the third insulator. A semiconductor device wherein the distance between the first conductor and the second conductor is less than the distance between the third conductor and the fourth conductor, the oxide semiconductor contains indium, and the first conductor and the second conductor each contain a conductive oxide.

2. The semiconductor device according to claim 1, wherein the distance between the side surface of the third conductor and the third insulator, and the distance between the side surface of the fourth conductor and the third insulator are each greater than the distance between the side surface of the first insulator and the side surface of the third insulator.

3. The material comprises: an oxide semiconductor; a first conductor and a second conductor spaced apart from each other on the oxide semiconductor; a third conductor in contact with a part of the upper surface of the first conductor; a fourth conductor in contact with a part of the upper surface of the second conductor; a first insulator disposed on the third conductor and the fourth conductor, having an opening that overlaps with the region between the third conductor and the fourth conductor; a second insulator disposed within the opening, in contact with another part of the upper surface of the first conductor and another part of the upper surface of the second conductor; a third insulator disposed within the opening, in contact with the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator; and a fifth conductor disposed within the opening on the third insulator, having a region that overlaps with the oxide semiconductor via the third insulator. A semiconductor device wherein the distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor, the oxide semiconductor contains indium, the first conductor and the second conductor each contain a conductive oxide, there is an oxide between the third conductor and the second insulator, and between the fourth conductor and the second insulator, and the oxide is insulating.

4. An oxide semiconductor; a first conductor and a second conductor spaced apart from each other on the oxide semiconductor; a third conductor in contact with a part of the upper surface of the first conductor; a fourth conductor in contact with a part of the upper surface of the second conductor; a first insulator disposed on the third conductor and the fourth conductor and having an opening that overlaps with the region between the third conductor and the fourth conductor; a second insulator disposed within the opening and in contact with a part of the upper surface of the oxide semiconductor, another part of the upper surface of the first conductor, a side surface of the first conductor, another part of the upper surface of the second conductor, a side surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator disposed within the opening and in contact with the upper surface of the oxide semiconductor, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second insulator. A semiconductor device comprising: a fifth conductor disposed on the third insulator within the opening and having a region superimposed on the oxide semiconductor via the third insulator, wherein the distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor, the oxide semiconductor comprises indium, and the first conductor and the second conductor each comprise a conductive oxide.

5. A semiconductor device according to claim 4, wherein the distance between the side surface of the third conductor and the third insulator, and the distance between the side surface of the fourth conductor and the third insulator are each greater than the distance between the side surface of the first insulator and the side surface of the third insulator.

6. The material comprises: an oxide semiconductor; a first conductor and a second conductor spaced apart from each other on the oxide semiconductor; a third conductor in contact with the upper surface of the first conductor; a fourth conductor in contact with the upper surface of the second conductor; a first insulator disposed on the third conductor and the fourth conductor, having an opening that overlaps with the region between the third conductor and the fourth conductor; a second insulator disposed within the opening, in contact with a part of the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, the side surface of the third conductor, and the side surface of the fourth conductor; a third insulator disposed within the opening, in contact with the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator; and a fifth conductor disposed within the opening on the third insulator, having a region that overlaps with the oxide semiconductor via the third insulator. A semiconductor device wherein the distance between the first conductor and the second conductor is less than the distance between the third conductor and the fourth conductor, the side surface of the first conductor and the side surface of the third conductor are flush, the side surface of the second conductor and the side surface of the fourth conductor are flush, the oxide semiconductor contains indium, and the first conductor and the second conductor each contain a conductive oxide.

7. The semiconductor device according to claim 6, wherein the distance between the side surface of the third conductor and the third insulator, and the distance between the side surface of the fourth conductor and the third insulator are each greater than the distance between the side surface of the first insulator and the side surface of the third insulator.

8. A semiconductor device according to any one of claims 1 to 7, wherein the film thickness of the oxide semiconductor in the region overlapping with the third insulator is thinner than the film thickness of the oxide semiconductor in the region overlapping with the first conductor or the second conductor.

9. The semiconductor device according to claim 8, wherein the second insulator is in contact with a part of the side surface of the oxide semiconductor.

10. The semiconductor device according to claim 8, wherein the second insulator is silicon nitride.

11. The semiconductor device according to claim 8, wherein the second insulator comprises a first layer and a second layer on the first layer, the first layer having silicon oxide and the second layer having silicon nitride.

12. The semiconductor device according to claim 8, wherein the third conductor has higher conductivity than the first conductor, and the fourth conductor has higher conductivity than the second conductor.

13. The semiconductor device according to claim 12, wherein the first conductor and the second conductor each comprise indium and tin.

Images