Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device comprising a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type provided above the drift region, an emitter region of the first conductivity type provided above the base region and having a higher doping concentration than the drift region, and a plurality of trench parts provided in trenches of the semiconductor substrate above the drift region. The plurality of trench parts may include a gate trench part and a dummy trench part. The gate trench part and the dummy trench part may have a trench oxide film and a trench conductive part provided inside the trench oxide film. The trench oxide film may include an upper region in contact with the base region, a bottom region provided at the bottom of the plurality of trench parts, and an intermediate region provided between the upper region and the bottom region in the depth direction of the semiconductor substrate. The thickness of the intermediate region may be larger than the thickness of the bottom region.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Conventionally, a semiconductor device in which the thickness of an insulating film provided in a trench varies, or a semiconductor device in which two or more conductive portions separated by an insulating film are provided inside a trench is known (see, for example, Patent Documents 1-5). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-209505 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-523454 [Patent Document 3] Japanese Patent Application Laid-Open No. 2023-90034 [Patent Document 4] Japanese Patent Application Laid-Open No. 2020-25050 [Patent Document 5] Japanese Patent Application Laid-Open No. 2022-62502 General disclosure

[0003] (Problems to be Solved by the Invention) It is desirable to improve the trade-off between the turn-on loss and the reverse recovery dV / dt of a semiconductor device. (Means for Solving the Problems)

[0004] In a first aspect of the present invention, a drift region of a first conductivity type provided on a semiconductor substrate, a base region of a second conductivity type provided above the drift region, and a first conductivity type provided above the base region and having a higher doping concentration than the drift region. An emitter region, and a plurality of trench portions provided in a trench of the semiconductor substrate above the drift region are provided. The plurality of trench portions may include a gate trench portion and a dummy trench portion. The gate trench portion and the dummy trench portion may include a trench oxide film and a trench conductive portion provided inside the trench oxide film. The trench oxide film may include an upper region in contact with the base region, a bottom region provided at the bottom of the plurality of trench portions, and an intermediate region provided between the upper region and the bottom region in the depth direction of the semiconductor substrate. The thickness of the intermediate region may be greater than the thickness of the bottom region.

[0005] In the semiconductor device described above, dummy trenches may be provided on both sides of the gate trench in the trench arrangement direction of the plurality of trenches.

[0006] In any of the above semiconductor devices, a second conductivity type collector region may be provided below the drift region and having a higher doping concentration than the base region.

[0007] In any of the above semiconductor devices, a first conductivity type storage region may be provided below the base region and having a higher doping concentration than the drift region. The doping concentration of the storage region is 1E14cm². －３ Above, 5E17cm －３ The following is possible: In the depth direction of the semiconductor substrate, the depth position of the lower end of the storage region may be deeper than the depth position of the bottom of the plurality of trenches.

[0008] In any of the above semiconductor devices, a first conductivity type storage region may be provided below the base region and having a higher doping concentration than the drift region. The bottom region may be provided below the lower end of the storage region.

[0009] In any of the semiconductor devices described above, the thickness of the intermediate region may be 50% or more and 80% or less of the trench width of the plurality of trenches.

[0010] In any of the above semiconductor devices, the length of the intermediate region in the depth direction of the semiconductor substrate may be 10% or more and 70% or less of the trench depth of the plurality of trenches.

[0011] In any of the above semiconductor devices, a second conductivity type trench bottom region may be provided below the gate trench portion and having a lower doping concentration than the base region.

[0012] In any of the semiconductor devices described above, a trench contact portion may be provided in the mesa portion between the gate trench portion and the dummy trench portion, which is located closer to the dummy trench portion than the gate trench portion, and which electrically connects the semiconductor substrate with a front-side electrode provided above the semiconductor substrate.

[0013] In any of the semiconductor devices described above, the trench conductive portion may include a first conductive region provided in the plurality of trench portions, and a second conductive region separated in the plurality of trench portions by the first conductive region and the trench oxide film.

[0014] In any of the above-described semiconductor devices, the potentials of the first conductive region and the second conductive region may be the gate potential.

[0015] In any of the above-described semiconductor devices, the potentials of the first conductive region and the second conductive region may be the emitter potential.

[0016] In any of the semiconductor devices described above, the trench conductive portion may have a third conductive region separated by the first conductive region and the trench oxide film in the plurality of trench portions. The first conductive region, the second conductive region and the third conductive region may be arranged in the depth direction of the semiconductor substrate.

[0017] In any of the semiconductor devices described above, the trench conductive portion may have a third conductive region separated by the first conductive region and the trench oxide film in the plurality of trench portions. The first conductive region, the second conductive region and the third conductive region may be arranged in the trench arrangement direction of the plurality of trench portions.

[0018] In any of the semiconductor devices described above, the width of the trench conductive portion at the depth position where the upper region and the bottom region are provided in the trench arrangement direction of the plurality of trench portions may be greater than the width of the trench conductive portion at the depth position where the intermediate region is provided.

[0019] In any of the semiconductor devices described above, the plurality of trenches may have curved portions that narrow in width and have curvature in the depth direction of the semiconductor substrate. The bottom region may be provided over the entirety of the curved portion.

[0020] A second aspect of the present invention provides a semiconductor device comprising: a drift region of a first conductivity type provided on a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; and a plurality of trench portions provided in the trenches of the semiconductor substrate above the drift region. The plurality of trench portions may include gate trench portions and dummy trench portions. The gate trench portions and the dummy trench portions may include a trench oxide film and a trench conductive portion provided inside the trench oxide film. The trench conductive portion may include a first conductive region provided in the plurality of trench portions and a second conductive region separated in the plurality of trench portions by the first conductive region and the trench oxide film. The potentials of the first conductive region and the second conductive region may be the gate potential.

[0021] A third aspect of the present invention provides a semiconductor device comprising: a drift region of a first conductivity type provided on a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; and a plurality of trench portions provided in the trenches of the semiconductor substrate above the drift region. The plurality of trench portions may include gate trench portions and dummy trench portions. The gate trench portions and the dummy trench portions may each include a trench oxide film and a trench conductive portion provided inside the trench oxide film. The trench oxide film may include an upper region in contact with the base region, a bottom region provided at the bottom of the plurality of trench portions, and an intermediate region provided between the upper region and the bottom region in the depth direction of the semiconductor substrate. In the trench arrangement direction of the plurality of trenches, the width of the trench conductive portion at the depth position where the upper region and the bottom region are provided may be greater than the width of the trench conductive portion at the depth position where the intermediate region is provided.

[0022] Any of the above semiconductor devices may further include a diode section.

[0023] In any of the semiconductor devices described above, the diode portion may be provided with a plurality of dummy trench portions having the same structure as the dummy trench portion.

[0024] A fourth aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having a drift region of a first conductivity type; providing a base region of a second conductivity type above the drift region; providing an emitter region of a first conductivity type having a higher doping concentration than the drift region above the base region; and providing a plurality of trenches, including a gate trench and a dummy trench, in the semiconductor substrate above the drift region. The step of providing the plurality of trenches may include the steps of providing a trench oxide film and providing a trench conductive portion inside the trench oxide film. The step of providing the trench oxide film may include the steps of providing an upper region in contact with the base region, providing a bottom region at the bottom of the plurality of trenches, and providing an intermediate region between the upper region and the bottom region in the depth direction of the semiconductor substrate, having a greater thickness than the bottom region.

[0025] In the above-described method for manufacturing a semiconductor device, the step of providing the trench oxide film may include the step of thermally oxidizing the trenches of the semiconductor substrate and the step of removing the trench oxide film provided on the bottom of the trenches and a part of the side walls of the trenches using anisotropic etching.

[0026] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention.

[0027] This is an example of a top view of semiconductor device 100. This shows an example of the a-a' cross section in Figure 1A. This is an example of a top view of semiconductor device 100. This shows an example of the b-b' cross section in Figure 1C. This is an enlarged view of region A in Figures 1B and 1D. This is a modified example of region A in Figures 1B and 1D. This is a modified example of region A in Figures 1B and 1D. This is a modified example of region A in Figures 1B and 1D. This is a modified example of region A in Figures 1B and 1D. This is a graph showing the relationship between on-loss Eon and reverse recovery dV / dt. This is a graph showing the relationship between on-loss Eon and reverse recovery dV / dt. This is a graph showing the relationship between on-loss Eon and reverse recovery dV / dt. This is a modified example of the a-a' cross section in Figure 1A. This shows a modified example of the b-b' cross section in Figure 1C. This is a diagram representing a modified top view of semiconductor device 100. This is a diagram representing a modified top view of semiconductor device 100. This shows an example of a method for manufacturing semiconductor device 100. This shows an example of a method for manufacturing semiconductor device 100. An example of a method for manufacturing the semiconductor device 100 is shown. A modified example of the method for manufacturing the semiconductor device 100 is shown. A modified example of the method for manufacturing the semiconductor device 100 is shown.

[0028] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0029] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction of attachment to the substrate, etc., when mounting a semiconductor device.

[0030] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0031] In this specification, the plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. The depth direction of the semiconductor substrate may also be referred to as the Z axis. In this specification, the view of the semiconductor substrate in the Z axis direction is referred to as a plan view. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may also be referred to as the horizontal direction.

[0032] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will have opposite polarities.

[0033] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0034] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0035] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium.

[0036] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0037] FIG. 1A is a diagram showing an example of a top view of the semiconductor device 100 of this example. The semiconductor device 100 of this example is a semiconductor chip including a transistor portion 70 and a diode portion 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT). The transistor portion 70 of this example includes a boundary portion 90 at a portion adjacent to the diode portion 80.

[0038] The transistor portion 70 is an area obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. The collector region 22 is, as an example, P+-type. The transistor portion 70 includes a transistor such as an IGBT.

[0039] The diode portion 80 is an area obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. The cathode region 82 is, as an example, N+-type. The diode portion 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor portion 70 on the upper surface of the semiconductor substrate 10.

[0040] The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80. That is, a collector region 22 is provided below the boundary portion 90 of this example.

[0041] In FIG. 1A, an area around the chip end portion, which is the edge side of the semiconductor device 100, is shown, and other areas are omitted. For example, an edge termination structure portion is provided in a region on the negative side in the Y-axis direction of the semiconductor device 100 of this example. The edge termination structure portion relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion has, for example, a guard ring, a field plate, a RESURF, and a structure combining these. In this example, for the sake of convenience, although the edge on the negative side in the Y-axis direction is described, the same applies to other edges of the semiconductor device 100. The edge termination structure portion may be provided so as to surround an active region including the transistor portion 70.

[0042] The semiconductor substrate 10 may be a silicon substrate, may be a silicon carbide substrate, or may be a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.

[0043] In the semiconductor device 100 of this example, on the front surface 21 of the semiconductor substrate 10, there are provided a gate trench portion 40, a dummy trench portion 30, an anode region 11, an emitter region 12, a base region 14, a contact region 15, and a well region 17. The front surface 21 will be described later. Further, the semiconductor device 100 of this example includes a front surface side electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0044] The front surface side electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Also, the gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0045] The front surface side electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a part of the front surface side electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). At least a part of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). The front surface side electrode 52 and the gate metal layer 50 may have a barrier metal layer formed of titanium or a titanium compound or the like under a region formed of aluminum or the like. The front surface side electrode 52 and the gate metal layer 50 are provided separately from each other.

[0046] The front surface side electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 interposed therebetween. The interlayer insulating film 38 is omitted in FIG. 1A. Contact holes 54, 55, and 56 penetrate through the interlayer insulating film 38.

[0047] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive part within the transistor section 70 via the connection section 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55.

[0048] The contact hole 56 connects the front-side electrode 52 to the dummy conductive part in the dummy trench portion 30. A plug layer made of tungsten or the like may be formed inside the contact hole 56.

[0049] The connection portion 25 is connected to the front-side electrode 52 or a front-side metal layer such as the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 may be provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the front-side electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0050] The front surface 21 of the semiconductor substrate 10 is provided with a plurality of trenches extending in a predetermined direction (in this example, the Y-axis direction) and arranged in a predetermined direction (in this example, the X-axis direction). The plurality of trenches include a gate trench 40 to which the gate potential is applied and a dummy trench 30 to which a potential different from the gate potential is applied. The potential applied to the dummy trench 30 is, for example, the emitter potential.

[0051] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined stretching direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 in this example may have two extended portions 41 that extend along a stretching direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 43 that connects the two extended portions 41.

[0052] Preferably, at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0053] The dummy trench portion 30 is an example of a plurality of trench portions extending in a predetermined stretching direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the front surface side electrode 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench portion 30 may have an I-shape on the front surface 21 of the semiconductor substrate 10, and like the gate trench portion 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extended portions 31 extending along the stretching direction and a connecting portion 33 connecting the two extended portions.

[0054] The transistor section 70 in this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are arranged in a repeating pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. In the transistor section 70 in this example, dummy trench sections 30 are provided on both sides of the gate trench section 40 in the trench arrangement direction of the multiple trench sections.

[0055] However, the ratio of the gate trench section 40 to the dummy trench section 30 is not limited to this example. The ratio of the gate trench section 40 may be greater than the ratio of the dummy trench section 30, and vice versa. The ratio of the gate trench section 40 to the dummy trench section 30 may be 2:3 or 2:4.

[0056] The well region 17 is a region of a second conductivity type located on the front surface 21 side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region located on the periphery side of the active region. The well region 17 is, for example, of the P+ type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0057] The contact holes 54 are formed above the emitter region 12 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. One or more contact holes 54 may penetrate the interlayer insulating film and be formed inside the semiconductor substrate 10.

[0058] The trench contact portion 27 is provided in the contact hole 54. The trench contact portion 27 extends from the upper surface of the interlayer insulating film, through the front surface 21 of the semiconductor substrate 10, into the interior of the semiconductor substrate 10. The trench contact portion 27 has a conductive material that fills the contact hole 54. The trench contact portion 27 may have the same material as the front surface electrode 52. The trench contact portion 27 may include a tungsten plug and may include a barrier metal such as Ti or TiN.

[0059] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is the part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as one trench portion. That is, the region sandwiched between two extended portions may be considered as the mesa portion.

[0060] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, and a base region 14 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 is provided extending in the trench extension direction of the plurality of trench portions.

[0061] The base region 14 is a second conductivity type region located above the drift region 18. The base region 14 is, for example, P-type. The doping concentration of the base region 14 is 1E14cm². －３ Above, 1E18cm －３ The following may apply: The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30. The base region 14 may be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that Figure 1A shows only one end of the base region 14 in the Y-axis direction.

[0062] The emitter region 12 is located above the base region 14 and is a first conductivity type region with a higher doping concentration than the drift region 18. The emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 may be arsenic (As). The emitter region 12 is located on the front surface 21 of the mesa portion 71 and is in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 may also be located below the contact hole 54.

[0063] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0064] The contact region 15 is located above the base region 14 and is a region of a second conductivity type with a higher doping concentration than the base region 14. The contact region 15 is, for example, of the P+ type. In this example, the contact region 15 is located on the front surface 21 of the mesa portion 71. The contact region 15 may be located in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other.

[0065] The contact area 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact area 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40. The contact area 15 is also provided below the contact hole 54.

[0066] In the depth direction of the semiconductor substrate 10, the thickness of the contact region 15 may be greater than the thickness of the emitter region 12. The lower end of the contact region 15 may be located deeper than the lower end of the emitter region 12.

[0067] The contact region 15 may be omitted. If the contact region 15 is not provided, a base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 instead of the contact region 15. By omitting the contact region 15, the number of injections of the second conductivity type dopant can be reduced, thereby lowering the manufacturing cost of the semiconductor device 100.

[0068] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has an anode region 11 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has an anode region 11 and a well region 17 on the negative side in the Y-axis direction. The dummy trench portion 30 provided in the diode portion 80 may have the same structure as the dummy trench portion 30 provided in the transistor portion 70.

[0069] The anode region 11 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The doping concentration of the anode region 11 may be lower than that of the base region 14. The anode region 11 is, for example, P-type. In this example, the anode region 11 is provided on the front surface 21 of the mesa portion 81. The anode region 11 may be provided in the X-axis direction from one of the two dummy trench portions 30 that sandwich the mesa portion 81 to the other. The anode region 11 may or may not be in contact with the dummy trench portion 30. In this example, the anode region 11 is in contact with the dummy trench portion 30.

[0070] The boundary region 90 is provided in the transistor region 70 and is adjacent to the diode region 80. The boundary region 90 does not necessarily have an emitter region 12. In one example, the trench portion of the boundary region 90 is a dummy trench portion 30. In this example, the boundary region 90 is arranged such that both ends in the X-axis direction are dummy trench portions 30. In the boundary region 90, at least one of the dummy trench portions 30 may be set to a potential different from the gate potential.

[0071] The mesa portion 91 is provided at the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0072] Figure 1B shows an example of the a-a' cross-section in Figure 1A. The a-a' cross-section is the XZ plane passing through the emitter region 12. The semiconductor device 100 in this example has an emitter region 12, a base region 14, a storage region 16, a drift region 18, a plug region 19, a buffer region 20, a collector region 22, and a trench bottom region 65 in the a-a' cross-section, an interlayer insulating film 38, a front-side electrode 52, and a collector electrode 24.

[0073] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0074] The buffer region 20 is a first conductivity type region located on the back surface 23 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the underside of the base region 14 from reaching the collector region 22 of the second conductivity type. The buffer region 20 may be omitted.

[0075] The collector region 22 is located below the drift region 18 and is a second conductivity type region with a higher doping concentration than the base region 14. The collector region 22 is, for example, a P+ type. The collector region 22 may be located on the back surface 23 of the semiconductor substrate 10 in the transistor section 70.

[0076] The cathode region 82 is located below the drift region 18 and is a first conductivity type region with a higher doping concentration than the drift region 18. The cathode region 82 is, for example, N+ type. The cathode region 82 may be located on the back surface 23 of the semiconductor substrate 10 in the diode portion 80.

[0077] The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The front-side electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0078] The storage region 16 is located below the base region 14 and is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the storage region 16 is N+ type. By providing the storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0079] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. The gate trenches 40 and dummy trenches 30 are examples of multiple trenches provided in the trenches of the semiconductor substrate 10 above the drift region 18. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to those manufactured in the order of forming the doping region before forming the trenches. Even when doping regions are formed between the trenches after the trenches have been formed, the trenches are still included in the statement that a trench penetrates a doping region.

[0080] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is an example of a trench oxide film 120. The gate insulating film 42 is formed covering the inner wall of the gate trench. The gate insulating film 42 may be formed by thermal oxidation of the semiconductor on the inner wall of the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate insulating film 42 in this example has regions with different thicknesses. Details of the film thickness of the gate insulating film 42 will be described later.

[0081] The gate conductive portion 44 is formed inside the gate trench, on the side of the gate insulating film 42. The gate conductive portion 44 is an example of the trench conductive portion 140. The gate conductive portion 44 is made of a conductive material such as polysilicon. In the depth direction of the semiconductor substrate 10, the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in contact with the gate trench within the base region 14.

[0082] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is an example of a trench oxide film 120, and the dummy conductive portion 34 is an example of a trench conductive portion 140. The dummy insulating film 32 is formed covering the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.

[0083] The dummy trench portion 30 and the gate trench portion 40 are covered on the front surface 21 by an interlayer insulating film 38. The interlayer insulating film 38 is provided on the front surface 21. A front surface side electrode 52 is provided above the interlayer insulating film 38. Contact holes 54 are provided in the interlayer insulating film 38.

[0084] The semiconductor device 100 in this example includes a trench contact portion 27 in the mesa portion 71 for electrically connecting the front-side electrode 52 and the semiconductor substrate 10. That is, the trench contact portion 27 is provided in the mesa portion between a plurality of trench portions.

[0085] The trench contact portion 27 may be provided in the mesa portion 71 between the gate trench portion 40 and the dummy trench portion 30, closer to the dummy trench portion 30 than to the gate trench portion 40. In the example of Figure 1B, the distance d30 between the dummy trench portion 30 and the upper end of the trench contact portion 27 is smaller than the distance d40 between the gate trench portion 40 and the upper end of the trench contact portion 27. The upper end of the trench contact portion 27 may be the position of the opening end of the contact hole 54 on the front surface 21 of the semiconductor substrate 10, or it may be the position of the opening end of the contact hole 54 on the upper surface of the interlayer insulating film 38. By providing the trench contact portion 27 closer to the dummy trench portion 30 than to the gate trench portion 40, miniaturization of the semiconductor device 100 becomes easier.

[0086] The plug region 19 is a second conductivity type region located in contact with the lower end of the trench contact portion 27. The doping concentration of the plug region 19 is higher than that of the base region 14. The plug region 19 is, for example, of P+ type. The doping concentration of the plug region 19 is 1E17cm². －３ The above is sufficient; 1E20cm －３ The following is acceptable:

[0087] The plug region 19 may be provided so as to cover the bottom and part of the side wall of the trench contact portion 27. The plug region 19 may be provided spaced apart from the emitter region 12, or it may be provided in contact with the emitter region 12. In this example, the plug region 19 is provided in contact with the emitter region 12. By providing the plug region 19 on the lower surface of the trench contact portion 27, the latch-up tolerance of the semiconductor device 100 can be improved.

[0088] The plug region 19 may be spaced apart from adjacent trenches in the trench arrangement direction of the multiple trenches. The plug region 19 may also be spaced apart from the gate trench 40. This ensures that the gate voltage required to form the channel inversion region remains constant, thereby uniformizing the characteristics of the semiconductor device 100.

[0089] The plug region 19 may be provided in contact with an adjacent trench portion in the trench arrangement direction of the multiple trench portions. In this example, the plug region 19 is provided in contact with the dummy trench portion 30. In a mesa portion 71 whose ends are dummy trench portions 30, the plug region 19 may extend in the trench arrangement direction from the side wall of one dummy trench portion 30 to the side wall of the other dummy trench portion 30. Even in such a case, if the plug region 19 is provided spaced apart from the gate trench portion 40, the characteristics of the semiconductor device 100 can be made uniform.

[0090] The plug region 19 may be formed by injecting a dopant through the contact hole 54. Alternatively, the trench contact portion 27 may be provided after the plug region 19 has been provided.

[0091] The plug region 19 may be provided continuously in the transistor section 70, extending in the direction of trench extension of the multiple trench sections. The plug region 19 may be provided in the transistor section 70, extending over the entire area below the trench contact section 27.

[0092] The plug region 19 may be provided discretely in the diode section 80 in the direction of trench extension of the multiple trench sections. That is, below the trench contact section 27 provided in the diode section 80, regions with the plug region 19 and regions without the plug region 19 may be arranged alternately.

[0093] The trench bottom region 65 is located below the multiple trench sections and is a second-conductivity region with a lower doping concentration than the base region 14. In this example, the trench bottom region 65 is P-type. The trench bottom region 65 may be located in contact with the accumulation region 16, or it may be located at a distance from the accumulation region 16. In this example, the trench bottom region 65 is located at a distance from the accumulation region 16.

[0094] The trench bottom region 65 is provided below the gate trench portion 40. The trench bottom region 65 does not need to be provided below the dummy trench portion 30. By providing the trench bottom region 65 below the gate trench portion 40, the trade-off between the on-loss Eon of the semiconductor device 100 and the reverse recovery dV / dt can be improved.

[0095] Figure 1C shows an example of a top view of the semiconductor device 100 in this example. The semiconductor device 100 in this example differs from that in Figure 1A in that it is an IGBT (Insulated Gate Bipolar Transistor) equipped only with a transistor section 70.

[0096] Figure 1D shows an example of a b-b' cross-section in Figure 1C. The b-b' cross-section is the XZ plane passing through the emitter region 12. The semiconductor device 100 in this example has an emitter region 12, a base region 14, a storage region 16, a drift region 18, a plug region 19, a buffer region 20, a collector region 22, and a trench bottom region 65 in the b-b' cross-section, an interlayer insulating film 38, a front-side electrode 52, and a collector electrode 24. The semiconductor device 100 in this example may have the same structure as the transistor section 70 shown in Figures 1A and 1B.

[0097] The semiconductor device 100 in this example has a structure in which one gate trench portion 40 and one dummy trench portion 30 are repeatedly arranged. That is, the transistor portion 70 in this example has gate trench portions 40 and dummy trench portions 30 in a 1:1 ratio. In the semiconductor device in this example, dummy trench portions 30 are provided on both sides of the gate trench portion 40 in the trench arrangement direction of the multiple trench portions.

[0098] However, the ratio of the gate trench section 40 to the dummy trench section 30 is not limited to this example. The ratio of the gate trench section 40 may be greater than the ratio of the dummy trench section 30, and vice versa. The ratio of the gate trench section 40 to the dummy trench section 30 may be 2:3 or 2:4.

[0099] The semiconductor device 100 in this example can achieve the same effects as in Figures 1A and 1B by providing a storage region 16, a plug region 19, and a trench bottom region 65.

[0100] Figure 2A is an enlarged view of region A enclosed by the dashed line in Figures 1B and 1D. The trench oxide film 120 and trench conductive portion 140 of this example will be described in detail using Figure 2A.

[0101] The trench oxide film 120 in this example has two or more regions with different thicknesses. The trench oxide film 120 in this example includes an upper region 121. The upper region 121 is in contact with the base region 14 of the trench oxide film 120. In the depth direction of the semiconductor substrate 10, the depth position of the upper end of the upper region 121 may be the position of the front surface 21 of the semiconductor substrate 10, and the depth position of the lower end of the upper region 121 may be the depth position of the lower end of the base region 14.

[0102] The upper region 121 has a predetermined thickness W121 in the trench arrangement direction of the plurality of trenches. The thickness W121 of the upper region 121 may be the sum of the shortest distance W121a from one trench sidewall to the trench conductive portion 140 and the shortest distance W121b from the other trench sidewall to the trench conductive portion 140 in the trench arrangement direction at the depth position where the upper region 121 is provided. The shortest distance W121a from one trench sidewall to the trench conductive portion 140 and the shortest distance W121b from the other trench sidewall to the trench conductive portion 140 may be the same or different. In the example of Figure 2A, W121a and W121b are the same. The thickness W121 of the upper region 121 may satisfy the following condition: 5.0 × Vge ≤ thickness W121 (nm) ≤ 8.0 × Vge, where Vge (V) is the voltage applied between the gate and emitter when the semiconductor device 100 is in use. For example, if Vge is 15V, the thickness W121 of the upper region 121 is 100 nm.

[0103] In this example, the trench oxide film 120 includes a bottom region 123. The bottom region 123 is provided at the bottom of a plurality of trenches in the trench oxide film 120. The bottom region 123 may be located below the lower end of the accumulation region 16. In the depth direction of the semiconductor substrate 10, the depth position of the upper end of the bottom region 123 may be the depth position of the lower end of the trench conductive portion 140. The depth position of the upper end of the bottom region 123 may be the position where the trench width W40 begins to change so as to narrow toward the depth direction of the semiconductor substrate 10. The depth position of the upper end of the bottom region 123 may be below the lower end of the upper region 121, where the width of the trench conductive portion 140 begins to change so as to narrow toward the depth direction of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the depth position of the lower end of the bottom region 123 may be the depth position of the lower end of the trench portion.

[0104] The bottom region 123 has a predetermined thickness W123 in the depth direction of the semiconductor substrate 10. The thickness W123 of the bottom region 123 may be the shortest distance from the lower end of the trench conductive portion 140 to the lower end of the trench portion in the depth direction of the semiconductor substrate 10. The thickness W123 of the bottom region 123 may be smaller than the thickness W121 of the upper region 121. In one example, the thickness W123 of the bottom region 123 is 90 nm.

[0105] In this example, the trench oxide film 120 includes an intermediate region 122. The intermediate region 122 is provided in the trench oxide film 120 between the upper region 121 and the bottom region 123 in the depth direction of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the depth position of the upper end of the intermediate region 122 may be the depth position of the lower end of the upper region 121, and the depth position of the lower end of the intermediate region 122 may be the depth position of the upper end of the bottom region 123. That is, the depth position of the upper end of the intermediate region 122 may be the depth position of the lower end of the base region 14, and the depth position of the lower end of the intermediate region 122 may be the depth position of the portion of the trench conductive part 140 that has curvature.

[0106] In the depth direction of the semiconductor substrate 10, the length L122 of the intermediate region 122 may be 10% or more and 70% or less of the trench depth L40 of the multiple trenches. The length L122 of the intermediate region 122 may be the distance from the upper end of the intermediate region 122 to the lower end of the intermediate region 122 in the depth direction of the semiconductor substrate 10. That is, the length L122 of the intermediate region 122 may be the distance from the lower end of the upper region 121 to the upper end of the bottom region 123 in the depth direction of the semiconductor substrate 10. In one example, the length L122 of the intermediate region 122 is 3.3 μm.

[0107] The length L122 of the intermediate region 122 may be the length from the lower end of the base region 14 to the lower end of the trench conductive portion 140, where the thickness of the trench oxide film 120 is greater than W121. The length L122 of the intermediate region 122 may be the length below the lower end of the base region 14 to the lower end of the trench conductive portion 140, where the thickness of the trench oxide film 120 is greater than W121. The length L122 of the intermediate region 122 may be the length from the upper end of the trench oxide film 120 with a thickness greater than W121 to the lower end of the trench conductive portion 140, below the lower end of the base region 14.

[0108] The intermediate region 122 has a predetermined thickness W122 in the trench arrangement direction of the multiple trench sections. The thickness W122 of the intermediate region 122 may be the sum of the maximum distance W122a from one trench sidewall to the trench conductive section 140 and the maximum distance W122b from the other trench sidewall to the trench conductive section 140 in the trench arrangement direction at the depth position where the intermediate region 122 is provided. The maximum distance W122a from one trench sidewall to the trench conductive section 140 and the maximum distance W122b from the other trench sidewall to the trench conductive section 140 may be the same or different. In the example of Figure 2A, W122a and W122b are the same.

[0109] In this example, the thickness W122 of the intermediate region 122 is greater than the thickness W123 of the bottom region 123. This makes it easier for the potential of the side walls of the trench portion of the semiconductor device 100 to rise, and the potential becomes higher as the trench depth increases. As a result, the displacement current in the bottom region 123 increases, and the gate potential tends to increase during turn-on, improving the turn-on speed and improving the trade-off between the on-loss Eon of the semiconductor device 100 and the reverse recovery dV / dt.

[0110] The thickness W122 of the intermediate region 122 may be 50% or more and 65% or less of the trench width W40 of the multiple trench sections. The thickness W122 of the intermediate region 122 may be 50% or more and 80% or less of the trench width W40 of the multiple trench sections. In one example, the thickness W122 of the intermediate region 122 is 800 nm. By increasing the thickness W122 of the intermediate region 122, the displacement current from the drift region 18 tends to concentrate more near the bottom region 123, thereby improving the trade-off between the on-loss Eon of the semiconductor device 100 and the reverse recovery dV / dt.

[0111] Figure 2B is a modified example of region A enclosed by the dashed line in Figures 1B and 1D. The differences between Figure 2B and Figure 2A will be explained using Figure 2B.

[0112] The trench oxide film 120 in this example includes an upper region 121 provided in contact with the base region 14, a bottom region 123 provided at the bottom of the trench, and an intermediate region 122 provided between the upper region 121 and the bottom region 123. The structures of the upper region 121 and the intermediate region 122 are the same as those in Figure 2A, so their description is omitted.

[0113] In this example, the bottom region 123 is provided over the entire curved portion 105 of the trench. The curved portion 105 of the trench is the part in the depth direction of the semiconductor substrate 10 where the trench width of the trench narrows with curvature. In this example, the depth position of the upper end of the bottom region 123 is the depth position of the upper end of the curved portion 105.

[0114] In the example of Figure 2B, the shape of the trench conductive portion 140 differs from that of the example of Figure 2A due to the different configuration of the bottom region 123. In this example, in the trench arrangement direction of the multiple trench portions, the width W1 of the trench conductive portion 140 at the depth position where the upper region 121 is provided, and the width W3 of the trench conductive portion 140 at the depth position where the bottom region 123 is provided, are larger than the width W2 of the trench conductive portion 140 at the depth position where the intermediate region 122 is provided. By doing so, when the semiconductor device 100 is turned on, the displacement current from the drift region 18 tends to concentrate more near the bottom region 123, improving the trade-off between the on-loss Eon of the semiconductor device 100 and the reverse recovery dV / dt.

[0115] Figure 2C is a modified example of area A enclosed by the dashed line in Figures 1B and 1D. The differences between Figure 2C and Figure 2A will be explained using Figure 2C.

[0116] The trench conductive portion 140 in this example includes a plurality of regions separated by the trench oxide film 120. The trench conductive portion 140 may include a first conductive region 141 provided in the trench portion and a second conductive region 142 separated in the trench portion from the first conductive region 141 by the trench oxide film 120. In the example of Figure 2C, the first conductive region 141 is provided at the depth position where the upper region 121 is provided, and the second conductive region 142 is provided at the depth position where the intermediate region 122 is provided, but the example is not limited to this.

[0117] The first conductive region 141 and the second conductive region 142 are set to the same potential inside the trench. Inside the gate trench 40, the potentials of the first conductive region 141 and the second conductive region 142 may be the gate potential. Inside the dummy trench 30, the potentials of the first conductive region 141 and the second conductive region 142 may be the emitter potential. The same effect as in Figure 2A can be obtained by having the trench conductive region 140 inside the trench include multiple regions of the same potential separated by the trench oxide film 120, thereby simplifying the manufacturing process.

[0118] In the depth direction of the semiconductor substrate 10, the length L142 of the second conductive region 142 may be shorter than the length L122 of the intermediate region 122. The distance between the upper end of the second conductive region 142 and the lower end of the first conductive region 141 may be greater than or equal to the thickness of the oxide film in the depth direction (Z-axis direction) of the bottom region 123, and less than the thickness of the oxide film in the lateral direction (X-axis direction) of the portion of the intermediate region 122 where the second conductive region 142 is formed (whichever is thicker, W122a or W122b). In one example, the length L142 of the second conductive region 142 is 3.5 μm.

[0119] Figure 2D is a modified example of area A enclosed by the dashed line in Figures 1B and 1D. The differences between Figure 2D and Figure 2C will be explained using Figure 2D.

[0120] The trench conductive portion 140 in this example includes a plurality of regions separated by the trench oxide film 120. The trench conductive portion 140 may have a first conductive region 141 and a second conductive region 142 and a third conductive region 143 separated by the trench oxide film 120 in the trench portion.

[0121] In this example, the first conductive region 141, the second conductive region 142, and the third conductive region 143 are arranged in the depth direction of the semiconductor substrate 10. In the example of Figure 2C, the first conductive region 141 is provided at the depth position where the upper region 121 is provided, the second conductive region 142 is provided at the depth position where the intermediate region 122 is provided, and the third conductive region 143 is provided at the depth position where the bottom region 123 is provided, but the example is not limited to this. Even if the trench conductive portion 140 is separated into three or more regions by the trench oxide film 120, the trade-off between on-loss Eon and reverse recovery dV / dt can be improved by making all of them the same potential.

[0122] Figure 2E is a modified example of region A enclosed by the dashed line in Figures 1B and 1D. The differences between Figure 2E and Figure 2D will be explained using Figure 2E.

[0123] In the example shown in Figure 2E, the first conductive region 141, the second conductive region 142, and the third conductive region 143 are arranged in the trench arrangement direction of the multiple trenches. Even in this case, the trade-off between the on-loss Eon of the semiconductor device 100 and the reverse recovery dV / dt can be improved.

[0124] Figure 3A is a graph showing the relationship between on-loss Eon and reverse recovery dV / dt. In Figure 3A, the points indicated by squares represent the trade-off between on-loss Eon and reverse recovery dV / dt in the comparative semiconductor device. The comparative semiconductor device has a trench oxide film 120 with a uniform thickness. That is, the thickness of the trench oxide film 120 is the same in the upper region 121, the intermediate region 122, and the bottom region 123 of the comparative semiconductor device.

[0125] In Figure 3A, the points indicated by triangles represent the trade-off between on-loss Eon and reverse recovery dV / dt in the semiconductor device 100 shown in Figure 2A. In Figure 3A, the points indicated by circles represent the trade-off between on-loss Eon and reverse recovery dV / dt in the semiconductor device 100 shown in Figure 2B. From Figure 3A, it can be seen that the points in the embodiment are located lower and to the left than the points in the comparative example, indicating that in both embodiments, the trade-off between on-loss Eon and reverse recovery dV / dt is improved compared to the semiconductor device of the comparative example.

[0126] In Figure 3A, the point indicated by the circle is located lower and to the left than the point indicated by the triangle, indicating that the semiconductor device 100 shown in Figure 2B has a better trade-off between on-loss Eon and reverse recovery dV / dt than the semiconductor device 100 shown in Figure 2A. Thus, by increasing the width of the trench conductive portion 140 at the depth position where the bottom region 123 is provided, the trade-off between on-loss Eon and reverse recovery dV / dt can be further improved.

[0127] Figure 3B is a graph showing the relationship between on-loss Eon and reverse recovery dV / dt. In Figure 3B, the points indicated by squares represent the trade-off between on-loss Eon and reverse recovery dV / dt in the comparative semiconductor device. In Figure 3B, the points indicated by triangles and circles represent the trade-off between on-loss Eon and reverse recovery dV / dt in the example semiconductor device 100.

[0128] In Figure 3B, the points indicated by triangles and circles both represent the trade-off between the on-loss Eon and reverse recovery dV / dt of the semiconductor device 100 shown in Figure 2B. The points indicated by triangles and circles have different thicknesses of the intermediate region 122. In this example, the intermediate region 122 is thicker at the points indicated by circles than at the points indicated by triangles. In this example, the thickness of the intermediate region 122 at the points indicated by triangles is 50% of the trench width, and at the points indicated by circles, the thickness of the intermediate region 122 is 65% of the trench width. From Figure 3B, it can be seen that increasing the thickness of the intermediate region 122 can further improve the trade-off between the on-loss Eon and reverse recovery dV / dt.

[0129] Figure 3C is a graph showing the relationship between on-loss Eon and reverse recovery dV / dt. In Figure 3C, the points indicated by squares represent the trade-off between on-loss Eon and reverse recovery dV / dt in the comparative semiconductor device. In Figure 3C, the points indicated by triangles and circles represent the trade-off between on-loss Eon and reverse recovery dV / dt in the example semiconductor device 100.

[0130] In Figure 3C, the points indicated by triangles and the points indicated by circles both represent the trade-off between the on-loss Eon and reverse recovery dV / dt of the semiconductor device 100 shown in Figure 2B. The points indicated by triangles and the points indicated by circles have different thicknesses of the bottom region 123. In this example, the bottom region 123 is thinner at the points indicated by circles than at the points indicated by triangles. In this example, the thickness of the bottom region 123 at the points indicated by triangles is the same as the thickness of the upper region 121, while the thickness of the bottom region 123 at the points indicated by circles is thinner than the thickness of the upper region 121. From Figure 3C, it can be seen that the trade-off between the on-loss Eon and reverse recovery dV / dt can be further improved by reducing the thickness of the bottom region 123.

[0131] Figure 4A shows a modified example of the a-a' section in Figure 1A. The differences between Figure 4A and Figure 1B will be explained using Figure 4A.

[0132] In the example shown in Figure 4A, the doping concentration in the accumulation region 16 is smaller than in the example shown in Figure 1B. In this example, the accumulation region 16 is N-type. The doping concentration in the accumulation region 16 is 1E14cm². －３ Above, 5E17cm －３ The following is acceptable:

[0133] In the example shown in Figure 4A, the lower end of the storage region 16 is deeper than in the example shown in Figure 1B. In this example, the depth position of the lower end of the storage region 16 in the depth direction of the semiconductor substrate 10 is deeper than the depth position of the bottom of the multiple trench sections. This makes it possible to reduce the on-voltage of the semiconductor device 100 while maintaining the breakdown voltage of the semiconductor device 100.

[0134] Figure 4B shows a modified example of the b-b' cross-section in Figure 1C. The semiconductor device 100 in this example differs from Figure 4A in that it does not have a diode section 80 and a boundary section 90, and has a structure in which one gate trench section 40 and one dummy trench section 30 are repeatedly arranged and the gate trench sections 40 and dummy trench sections 30 are arranged in a 1:1 ratio. However, the ratio of gate trench sections 40 to dummy trench sections 30 is not limited to this example. The ratio of gate trench sections 40 may be greater than the ratio of dummy trench sections 30, and the ratio of dummy trench sections 30 may be greater than the ratio of gate trench sections 40. The ratio of gate trench sections 40 to dummy trench sections 30 may be 2:3 or 2:4. The semiconductor device 100 in this example can obtain the same effect as Figure 4A even without having a diode section 80 and a boundary section 90.

[0135] Figure 5A shows a modified top view of the semiconductor device 100. The differences between Figure 5A and Figure 1A will be explained using Figure 5A.

[0136] In the example shown in Figure 5A, the emitter region 12 is provided extending in the direction of trench extension of the multiple trench sections. The emitter region 12 is provided in contact with the gate trench section 40 and spaced apart from the dummy trench section 30. The emitter region 12 may also be in contact with the dummy trench section 30.

[0137] In the example shown in Figure 5A, the contact area 15 is provided extending in the trench extension direction of multiple trench sections. In this example, the contact area 15 is provided in contact with the dummy trench section 30. The contact area 15 may be provided extending in the trench extension direction from a base area 14 provided at the negative end in the Y-axis direction to a base area 14 provided at the positive end in the Y-axis direction.

[0138] Figure 5B shows a modified top view of the semiconductor device 100. The semiconductor device 100 in this example differs from Figure 5A in that it does not have a diode portion 80 and a boundary portion 90, and has a structure in which one gate trench portion 40 and one dummy trench portion 30 are repeatedly arranged and the gate trench portions 40 and dummy trench portions 30 are arranged in a 1:1 ratio. However, the ratio of gate trench portions 40 to dummy trench portions 30 is not limited to this example. The ratio of gate trench portions 40 may be greater than the ratio of dummy trench portions 30, and the ratio of dummy trench portions 30 may be greater than the ratio of gate trench portions 40. The ratio of gate trench portions 40 to dummy trench portions 30 may be 2:3 or 2:4.

[0139] In the example of Figure 5B, similar to the example of Figure 5A, the emitter region 12 is provided extending in the trench extension direction of the multiple trench sections. The emitter region 12 is provided in contact with the gate trench section 40 and spaced apart from the dummy trench section 30. The emitter region 12 may also be in contact with the dummy trench section 30.

[0140] In the example of Figure 5B, similar to the example of Figure 5A, the contact region 15 is provided extending in the trench extension direction of the multiple trench sections. In this example, the contact region 15 is provided in contact with the dummy trench section 30. The contact region 15 may be provided extending in the trench extension direction from the base region 14 provided at the negative end in the Y-axis direction to the base region 14 provided at the positive end in the Y-axis direction.

[0141] Figure 6 shows an example of a method for manufacturing the semiconductor device 100. In this example, the order of each step may be changed as appropriate.

[0142] In step S100, a semiconductor substrate 10 having a first conductivity type drift region 18 is prepared. The drift region 18 may be a region remaining in the semiconductor substrate 10 where other doping regions have not been formed. That is, in step S100 in which the semiconductor substrate 10 having the drift region 18 is prepared, the semiconductor substrate 10 may be manufactured by growing single crystal silicon.

[0143] In step S110, a base region 14 of a second conductivity type is provided above the drift region 18. In step S120, an emitter region 12 of a first conductivity type with a higher doping concentration than the drift region 18 is provided above the base region 14. Steps S110 and S120 may be performed in reverse order. That is, the emitter region 12 may be formed on the semiconductor substrate 10, and then the base region 14 may be formed below the emitter region 12. Steps S110 and S120 may be performed after step S130, which will be described later.

[0144] In step S130, a plurality of trenches, including a gate trench 40 and a dummy trench 30, are provided in the semiconductor substrate 10. The plurality of trenches are provided above the drift region 18. Step S130, in which the plurality of trenches are provided, may include step S140, in which a trench oxide film 120 is provided, and step S150, in which a trench conductive portion 140 is provided inside the trench oxide film 120.

[0145] In step S140, a trench oxide film 120 is formed in the trenches of the semiconductor substrate 10. Step S140 for providing the trench oxide film 120 may include the steps of providing an upper region 121 that is in contact with the base region 14, providing bottom regions 123 at the bottom of a plurality of trenches, and providing an intermediate region 122 between the upper region 121 and the bottom region 123 in the depth direction of the semiconductor substrate 10, having a greater thickness than the bottom region 123. Details of each step for providing the upper region 121, the bottom region 123, and the intermediate region 122 will be described later.

[0146] In step S150, the trench conductive portion 140 is formed. The trench conductive portion 140 may be formed by filling the inside of the trench oxide film 120 with a conductive material such as polysilicon. Details of step S150 in which the trench conductive portion 140 is formed will be described later.

[0147] Figure 7A shows an example of a manufacturing method for the semiconductor device 100. Using Figure 7A, the details of step S130, in which multiple trenches are provided, will be explained.

[0148] In step S132, a resist mask 60 is formed on the front surface 21 of the semiconductor substrate 10, and the resist mask 60 is exposed to light. The resist mask 60 is a photosensitive mask such as a photoresist. This allows for selective exposure of the front surface 21 of the semiconductor substrate 10 above the portion where the trench is formed.

[0149] In step S134, trenches are formed in the semiconductor substrate 10. The trenches are formed by etching the semiconductor substrate 10. The etching may be dry etching or wet etching.

[0150] In step S142, the trenches of the semiconductor substrate 10 are thermally oxidized. Step S142 is part of step S140 in which the trench oxide film 120 is formed. As a result, the trench oxide film 120 is formed on the side walls and bottom of the trenches of the semiconductor substrate 10, and on the front surface 21 of the semiconductor substrate 10.

[0151] Figure 7B shows an example of a method for manufacturing the semiconductor device 100. Figure 7B shows the process following step S142 described in Figure 7A.

[0152] In step S144, a portion of the trench oxide film 120 is removed. Step S144 is part of step S140, which forms the trench oxide film 120. In step S144, anisotropic etching is used to remove the trench oxide film 120 provided on the bottom of the trench and a portion of the side walls of the trench. The anisotropic etching may be dry etching. In step S144, by removing a portion of the trench oxide film 120 and leaving a portion behind, the trench oxide film 120 can be made to have multiple regions with different thicknesses.

[0153] In step S146, the semiconductor substrate 10 is thermally oxidized again. Step S146 is part of step S140, in which the trench oxide film 120 is formed. In step S146, the thickness of the already formed trench oxide film 120 increases. This forms the upper region 121, the intermediate region 122, and the bottom region 123. By adjusting the thickness of the trench oxide film 120 formed in step S146, the thicknesses of the upper region 121, the intermediate region 122, and the bottom region 123 can be adjusted.

[0154] In step S152, the trench conductive portion 140 is formed. Step S152 is part of step S150, in which the trench conductive portion 140 is formed. In step S152, the trench conductive portion 140 may be formed by depositing polysilicon on the trench oxide film 120 formed in step S146. In step S152, excess trench oxide film 120 and trench conductive portion 140 may be removed. This results in the formation of multiple trench portions having trench oxide film 120 and trench conductive portion 140.

[0155] Figure 8A shows a modified example of the manufacturing method of the semiconductor device 100. Figure 8A shows the process following step S142 described in Figure 7A. The differences from Figure 7B will be explained using Figure 8A.

[0156] In step S144, a portion of the trench oxide film 120 is removed. In this example, unlike the example in Figure 7B, the trench oxide film 120 formed on the bottom of the trench and on the front surface 21 of the semiconductor substrate 10 is removed using anisotropic etching, while the trench oxide film 120 provided on the side walls of the trench is not removed. However, in step S144, a portion of the trench oxide film 120 provided on the side walls of the trench may also be removed.

[0157] In step S146, the semiconductor substrate 10 is thermally oxidized again. Then, in step S152, polysilicon is filled to form the trench conductive portion 140. In step S152, the trench conductive portion 140 is formed only on a portion of the inside of the trench oxide film 120 formed in the trench. In step S152, polysilicon may be filled to cover only a portion of the inside of the trench oxide film 120, or polysilicon may be filled to cover the entire inside of the trench oxide film 120 and then some of the polysilicon may be removed.

[0158] Figure 8B shows an example of a method for manufacturing the semiconductor device 100. Figure 8B shows the process following step S152 described in Figure 8A.

[0159] In step S145, a portion of the trench oxide film 120 is removed. In step S145, a portion of the trench oxide film 120 formed on the trench sidewall is removed up to the depth of the upper surface of the trench conductive portion 140 formed in step S152. In step S145, the trench oxide film 120 may be removed by anisotropic etching. Step S145 may be performed using the same procedure as step S144.

[0160] In step S147, the semiconductor substrate 10 is thermally oxidized again. This forms the upper region 121, the intermediate region 122, and the bottom region 123. Thus, the trench oxide film 120 may be formed after the trench conductive portion 140 has been formed. That is, the trench oxide film 120 may be formed on the trench conductive portion 140. By adjusting the thickness of the trench oxide film 120 formed in step S146, the thicknesses of the upper region 121, the intermediate region 122, and the bottom region 123 can be adjusted. Step S147 may be performed using the same procedure as step S146.

[0161] In step S153, the trench conductive portion 140 is formed. In step S153, the trench conductive portion 140 may be formed by depositing polysilicon on the trench oxide film 120 formed in step S147. In step S153, excess trench oxide film 120 and trench conductive portion 140 may be removed. Step S153 may be performed in the same procedure as step S152. As a result, a trench oxide film 120 and a plurality of trench portions having trench conductive portions 140 including a first conductive region 141 and a second conductive region 142 are formed.

[0162] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0163] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.

[0164] 10... Semiconductor substrate, 11... Anode region, 12... Emitter region, 14... Base region, 15... Contact region, 16... Storage region, 17... Well region, 18... Drift region, 19... Plug region, 20... Buffer region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Collector electrode, 25... Connection portion, 27... Trench contact portion, 30... Dummy trench portion, 31... Extending portion, 32... Dummy insulating film, 33... Connection portion, 34... Dummy conductive portion, 38... Interlayer insulating film, 40... Gate trench portion, 41... Extending portion, 42... Gate insulating film, 43... Connection portion, 44 ...Gate conductive part, 50...Gate metal layer, 52...Front side electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 60...Resist mask, 65...Trench bottom region, 70...Transistor part, 71...Mesa part, 80...Diode part, 81...Mesa part, 82...Cathode region, 90...Boundary part, 91...Mesa part, 100...Semiconductor device, 105...Curved part, 120...Trench oxide film, 121...Upper region, 122...Intermediate region, 123...Bottom region, 140...Trench conductive part, 141...First conductive region, 142...Second conductive region, 143...Third conductive region

Claims

1. A semiconductor device comprising: a drift region of a first conductivity type provided on a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; and a plurality of trench portions provided in the trench of the semiconductor substrate above the drift region, wherein the plurality of trench portions have a gate trench portion and a dummy trench portion, and the gate trench portion and the dummy trench portion have a trench oxide film and a trench conductive portion provided inside the trench oxide film, wherein the trench oxide film includes an upper region in contact with the base region, a bottom region provided at the bottom of the plurality of trench portions, and an intermediate region provided between the upper region and the bottom region in the depth direction of the semiconductor substrate, wherein the thickness of the intermediate region is greater than the thickness of the bottom region.

2. The semiconductor device according to claim 1, wherein, in the trench arrangement direction of the plurality of trenches, dummy trenches are provided on both sides of the gate trench.

3. The semiconductor device according to claim 1, comprising a second conductivity type collector region provided below the drift region and having a higher doping concentration than the base region.

4. A first conductivity type storage region is provided below the base region and has a higher doping concentration than the drift region, wherein the doping concentration of the storage region is 1E14cm². －３ Above, 5E17cm －３ The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the depth position of the lower end of the storage region is deeper than the depth position of the bottom of the plurality of trenches.

5. The semiconductor device according to claim 1, comprising a first conductivity type storage region provided below the base region and having a doping concentration higher than that of the drift region, wherein the bottom region is provided below the lower end of the storage region.

6. The semiconductor device according to claim 1, wherein the thickness of the intermediate region is 50% or more and 80% or less of the trench width of the plurality of trenches.

7. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the length of the intermediate region is 10% or more and 70% or less of the trench depth of the plurality of trenches.

8. The semiconductor device according to claim 1, comprising a second conductivity type trench bottom region provided below the gate trench portion and having a lower doping concentration than the base region.

9. The semiconductor device according to claim 1, further comprising a trench contact portion in the mesa portion between the gate trench portion and the dummy trench portion, which is provided closer to the dummy trench portion than to the gate trench portion, and electrically connects the semiconductor substrate and a front-side electrode provided above the semiconductor substrate.

10. The semiconductor device according to any one of claims 1 to 9, wherein the trench conductive portion includes a first conductive region provided in the plurality of trench portions and a second conductive region separated from the first conductive region by the trench oxide film in the plurality of trench portions.

11. The semiconductor device according to claim 10, wherein the potentials of the first conductive region and the second conductive region are gate potentials.

12. The semiconductor device according to claim 10, wherein the potentials of the first conductive region and the second conductive region are emitter potentials.

13. The semiconductor device according to claim 10, wherein the trench conductive portion has a third conductive region separated from the first conductive region and the second conductive region by the trench oxide film in the plurality of trench portions, and the first conductive region, the second conductive region and the third conductive region are arranged in the depth direction of the semiconductor substrate.

14. The semiconductor device according to claim 10, wherein the trench conductive portion has a third conductive region separated from the first conductive region and the second conductive region by the trench oxide film in the plurality of trench portions, and the first conductive region, the second conductive region and the third conductive region are arranged in the trench arrangement direction of the plurality of trench portions.

15. The semiconductor device according to any one of claims 1 to 9, wherein, in the trench arrangement direction of the plurality of trenches, the width of the trench conductive portion at the depth position where the upper region and the bottom region are provided is greater than the width of the trench conductive portion at the depth position where the intermediate region is provided.

16. The semiconductor device according to any one of claims 1 to 9, wherein the plurality of trenches have curved portions that narrow in width with curvature in the depth direction of the semiconductor substrate, and the bottom region is provided over the entire curved portion.

17. A semiconductor device comprising: a drift region of a first conductivity type provided on a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; and a plurality of trench portions provided in the trench of the semiconductor substrate above the drift region, wherein the plurality of trench portions have a gate trench portion and a dummy trench portion, and the gate trench portion and the dummy trench portion have a trench oxide film and a trench conductive portion provided inside the trench oxide film, wherein the trench conductive portion includes a first conductive region provided in the plurality of trench portions and a second conductive region separated in the plurality of trench portions by the first conductive region and the trench oxide film, and the potential of the first conductive region and the second conductive region is the gate potential.

18. A semiconductor substrate comprising: a drift region of a first conductivity type provided on the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; and a plurality of trench portions provided in the trench of the semiconductor substrate above the drift region, wherein the plurality of trench portions have a gate trench portion and a dummy trench portion, and the gate trench portion and the dummy trench portion have a trench oxide film and a trench conductive portion provided inside the trench oxide film, wherein the trench oxide film includes an upper region in contact with the base region, a bottom region provided at the bottom of the plurality of trench portions, and an intermediate region provided between the upper region and the bottom region in the depth direction of the semiconductor substrate. A semiconductor device in which, in the trench arrangement direction of the plurality of trenches, the width of the trench conductive portion at the depth position where the upper region and the bottom region are provided is greater than the width of the trench conductive portion at the depth position where the intermediate region is provided.

19. The semiconductor device according to any one of claims 1, 17, or 18, further comprising a diode section.

20. The semiconductor device according to claim 19, wherein the diode portion is provided with a plurality of dummy trench portions having the same structure as the dummy trench portion.

21. A method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate having a drift region of a first conductivity type; providing a base region of a second conductivity type above the drift region; providing an emitter region of a first conductivity type having a higher doping concentration than the drift region above the base region; and providing a plurality of trenches in the semiconductor substrate above the drift region, including a gate trench and a dummy trench, wherein the step of providing the plurality of trenches comprises: providing a trench oxide film; and providing a trench conductive portion inside the trench oxide film; and the step of providing the trench oxide film comprises: providing an upper region in contact with the base region; providing a bottom region at the bottom of the plurality of trenches; and providing an intermediate region between the upper region and the bottom region in the depth direction of the semiconductor substrate, having a greater thickness than the bottom region.

22. The method for manufacturing a semiconductor device according to claim 21, wherein the step of providing the trench oxide film includes the steps of thermally oxidizing the trenches of the semiconductor substrate and removing the trench oxide film provided on the bottom of the trenches and a part of the side walls of the trenches using anisotropic etching.

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