Substrate dicing method

Abstract

The present disclosure relates to a substrate dicing method. The substrate dicing method according to one embodiment of the present disclosure may comprise the steps of: forming a first trench on an upper surface of the substrate; forming an active layer on the upper surface of the substrate, adjacent to the first trench; forming a second trench above the first trench; forming a conductive wiring layer above the active layer; and performing etching along a trench line including the first trench and the second trench, so as to generate a plurality of semiconductor chips.

Description

Dicing method of a substrate

[0001] The present disclosure relates to a semiconductor process method, and more specifically, to a dicing method of a substrate for producing a semiconductor chip based on an etching process using a trench.

[0002] Semiconductor processes can be classified into a front-end process for fabricating devices and a back-end process for separating devices to fabricate individual devices. The semiconductor back-end process includes a dicing process (or sawing process) that cuts a semiconductor wafer, on which the front-end process is completed, into individual chips. Conventionally, various technologies such as scribe dicing, blade dicing, laser dicing, and plasma dicing have been used for the dicing process to produce semiconductor chips.

[0003] Recently, as the integration density of semiconductors has increased and wafer thickness has decreased, dicing processes using mechanical or laser methods have caused damage such as chipping or cracking. In addition, dicing processes using mechanical or laser methods also have the problem that the cut surface becomes rough because burrs on the metal layer are not sufficiently removed. To reduce defects caused by this, dicing processes using plasma methods have been introduced, and various methods to improve the dicing quality of substrates are being proposed.

[0004] In this regard, Korean Published Patent Application 10-2021-0064444A and Korean Registered Patent Application 10-2036708B1 may be referenced.

[0005] The present invention is derived from research conducted as part of the Semiconductor Advanced Packaging Core Technology Development Project of the Ministry of Science and ICT (Project No.: 2710006590, Project No.: 00423802, Project Management Agency: National Research Foundation of Korea, Research Project Title: Development of Core Technology for Ultra-thin Wafer Dicing Process Equipment Using Ultra Short Pulse Laser Grooving and Plasma Dry Etch, Project Performing Agency: PSK Holdings Co., Ltd., Research Period: 2024.04.01~2024.12.31).

[0006] Meanwhile, the Korean government, the provider of the problem, has no property interest in all aspects of the present invention.

[0007] The present disclosure aims to provide a dicing method for a substrate for producing a semiconductor chip based on an etching process using a trench.

[0008] The present disclosure aims to provide a method for dicing a substrate for producing a semiconductor chip based on plasma dicing technology.

[0009] The problems that this disclosure aims to solve are not limited to those described above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below.

[0010] A dicing method of a substrate according to one embodiment of the present disclosure may include the steps of forming a first trench on the upper surface of a substrate, forming an active layer on the upper surface of the substrate adjacent to the first trench, forming a second trench on top of the first trench, forming a conductive wiring layer on top of the active layer, and performing etching along a trench line including the first trench and the second trench to produce a plurality of semiconductor chips.

[0011] In an embodiment, the first trench and the second trench may be included in a scribe line, which is a predetermined area on the substrate, to produce a plurality of semiconductor chips.

[0012] In an embodiment, the trench line may correspond to one of the two ends of the scribe line.

[0013] In an embodiment, the first trench and the second trench, respectively, may each be composed of at least one of a nitride, an oxide, polysilicon, and a metal oxide.

[0014] In an embodiment, the step of generating the plurality of semiconductor chips may include the step of forming a mask on the conductive wiring layer to cover the conductive wiring layer and expose the second trench to the outside.

[0015] In an embodiment, the step of creating the plurality of semiconductor chips may further include the step of irradiating a laser into the second trench to create a crack in the second trench.

[0016] In an embodiment, the step of producing the plurality of semiconductor chips may include the step of removing the first trench and the second trench by performing wet etching along the trench line and the step of removing the substrate formed along the trench line by performing dry etching along the trench line.

[0017] In an embodiment, the step of removing a substrate formed along the trench line may include the step of irradiating plasma along the trench line.

[0018] A dicing method for a substrate according to one embodiment of the present disclosure may include the steps of forming a trench on the upper surface of a substrate, forming an active layer on the upper surface of the substrate adjacent to the trench, forming a conductive wiring layer on top of the active layer, and performing etching along a trench line including the trench to produce a plurality of semiconductor chips.

[0019] A dicing method for a substrate according to one embodiment of the present disclosure may include the steps of: forming a mask on a substrate having a trench line formed therein to expose the trench to the outside; irradiating a laser along the trench line to create a crack in the trench; irradiating plasma onto the trench where the crack was created to remove the trench where the crack was created; and irradiating plasma onto the substrate along the trench line to create a plurality of semiconductor chips.

[0020] According to an embodiment of the present disclosure, by producing a semiconductor chip based on plasma dicing technology using a trench, the occurrence of defects such as chipping and cracking can be reduced and the dicing quality can be improved.

[0021] The effects according to the present disclosure are not limited to those described above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below.

[0022] FIG. 1 is a drawing for illustrating a substrate processing system according to an embodiment of the present disclosure.

[0023] FIG. 2 is a flowchart for explaining a dicing method of a substrate according to an embodiment of the present disclosure.

[0024] FIGS. 3 to 11 are drawings for specifically explaining a process process applying a dicing method of a substrate according to an embodiment of the present disclosure.

[0025] FIG. 12 is a flowchart for explaining a dicing method of a substrate according to another embodiment of the present disclosure.

[0026] FIG. 13 is a drawing for explaining a process for applying a dicing method of a substrate according to another embodiment of the present disclosure.

[0027] FIG. 14 is a flowchart for explaining a dicing method of a substrate according to another embodiment of the present disclosure.

[0028] FIG. 15 is a drawing for explaining a process for applying a dicing method of a substrate according to another embodiment of the present disclosure.

[0029] Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the contents described in the attached drawings. However, the present invention is not limited or restricted by exemplary embodiments. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall be used in a meaning that is commonly understood by those skilled in the art to which this disclosure belongs, but this may vary depending on the intent of those skilled in the art, case law, the emergence of new technology, etc.

[0030] Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. In certain cases, terms have been selected at the applicant's discretion, and in such cases, their meanings will be described in detail in the relevant explanatory sections. Accordingly, terms used in this disclosure should be defined not merely by their names, but based on their meanings and the content throughout this disclosure.

[0031] Throughout this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, the singular form used in this specification includes the plural form unless specifically stated otherwise. Additionally, the expression "at least one of a, b, and / or c" as used throughout this specification may encompass 'a alone', 'b alone', 'c alone', 'a and b', 'a and c', 'b and c', or 'a, b, and c all'.

[0032] Meanwhile, terms such as "first and / or second" used in this specification may be used to describe various components, but they are used solely for the purpose of distinguishing one component from another and are not intended to limit the scope to the components referred to by such terms. For example, without departing from the scope of the present invention, the first component may be named the second component, and the second component may also be named the first component.

[0033] Additionally, terms such as “…part,” “…module,” etc., as described in this specification refer to a unit that processes at least one function or operation, which may be implemented in hardware or software, or a combination of hardware and software. Furthermore, embodiments of this disclosure may be represented in this specification by functional block configurations and various processing steps. These functional blocks may be implemented by various numbers of hardware and / or software configurations that execute specific functions. For example, embodiments of this disclosure may employ integrated circuit configurations such as memory, processing, logic, look-up tables, etc., which can execute various functions under the control of one or more microprocessors or other control devices.

[0034] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In describing the embodiments, technical details that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to ensure that the essence of the present invention is conveyed more clearly without obscuring it by omitting unnecessary explanations. For the same reason, some components in the accompanying drawings may be exaggerated, omitted, or schematically depicted. Furthermore, the size of each component does not entirely reflect its actual size. Throughout this specification, the same reference numerals may refer to the same or corresponding components.

[0035] FIG. 1 is a drawing for showing a substrate processing system (1) according to an embodiment of the present disclosure.

[0036] Referring to FIG. 1, a substrate processing system (1) according to an embodiment of the present disclosure may include a dicing device (10) and a substrate processing device (20).

[0037] A dicing device (10) according to an embodiment of the present disclosure can perform a dicing (or sawing) process on a substrate provided by a substrate processing device (20). In an embodiment, the substrate provided by the substrate processing device (20) may be a semiconductor wafer. According to an embodiment of the present disclosure, the dicing device (10) can produce a plurality of semiconductor chips by performing a dicing process on a substrate provided by the substrate processing device (20). A process method of the dicing device (10) according to an embodiment of the present disclosure will be described in detail through FIGS. 2 to 15, which will be described later.

[0038] A substrate processing device (20) according to an embodiment of the present disclosure can form a substrate on which a plurality of semiconductor chips are arranged, and the substrate formed from the substrate processing device (20) can be provided to a dicing device (10). In one embodiment, the substrate processing device (20) may be a device that performs a fab process. The substrate processing device (20) can perform a manufacturing process for a fab-in substrate, and a fab-out substrate from the substrate processing device (20) can be provided to a dicing device (10). In an embodiment of the present disclosure, the substrate processing device (20) can perform a detailed process for a dicing process for a plurality of semiconductor chips on the substrate, and a detailed process method according to an embodiment of the present disclosure will be explained in detail through FIGS. 2 to 15, which will be described later.

[0039] In FIG. 1, the dicing device (10) and the substrate processing device (20) included in the substrate processing system (1) are shown as physically separated configurations, but this is for convenience of explanation only and does not limit the configuration of the substrate processing system (1) according to the present disclosure. In some embodiments, the dicing device (10) and the substrate processing device (20) included in the substrate processing system (1) may be logically separated configurations.

[0040] A substrate processing system (1) according to an embodiment of the present disclosure can produce a semiconductor chip based on an etching process using a trench. Additionally, a substrate processing system (1) according to an embodiment of the present disclosure can produce a semiconductor chip based on plasma dicing technology. By producing a semiconductor chip based on plasma dicing technology using a trench, the substrate processing system (1) according to an embodiment of the present disclosure can reduce the occurrence of defects such as chipping and cracking and can improve dicing quality.

[0041] FIG. 2 is a flowchart (S100) for explaining a dicing method of a substrate according to an embodiment of the present disclosure. FIGS. 3 to 11 are drawings for specifically explaining a process for applying a dicing method of a substrate according to an embodiment of the present disclosure. Hereinafter, a dicing method of a substrate according to an embodiment of the present disclosure will be explained with reference to FIGS. 3 to 11.

[0042] In step S110, as illustrated in FIG. 3, a substrate processing system according to an embodiment of the present disclosure may form a first trench (120) on the upper surface of a substrate (110). In the substrate processing system, the substrate (110) may be placed on top of a base filling (131), and an adhesive filling (130) for holding the substrate (110) may be placed between the substrate (110) and the base filling (131). In an embodiment, the first trench (120) may be placed based on substrate design information, and the substrate design information may refer to design information related to the placement of semiconductor chips and wiring on the substrate (110), the location of scribe lines (or scribe regions), etc. In an embodiment, the first trench (120) may be included in at least a part of the scribe region and may include at least one of nitride, oxide, polysilicon, and metal oxide. Meanwhile, in some embodiments, as shown in FIG. 4, the substrate processing system may perform an encapsulation process for the first trench (120). When the encapsulation process is performed, at least one side of the first trench (120) may be surrounded by a protective layer (121).

[0043] In step S120, as illustrated in FIG. 5, a substrate processing system according to an embodiment of the present disclosure may form an active layer (140) on the upper surface of a substrate (110) adjacent to a first trench (120). Specifically, the substrate processing system may perform a Front End Of Line (FEOL) process to process the substrate (110) through oxidation, diffusion, and ion implantation, and during the FEOL process, the active layer (140) may be formed to be spaced apart from the first scribe line (141) based on substrate design information. In some embodiments, the height of the active layer (140) formed on the substrate may correspond to the height of the first trench (120).

[0044] In step S130, as illustrated in FIG. 6, a substrate processing system according to an embodiment of the present disclosure may form a second trench (122) on top of a first trench (120). In an embodiment, the second trench (122) may be included in at least a portion of the second scribe line (151) and may include at least one of a nitride, an oxide, polysilicon, or a metal oxide. In some embodiments, the thickness of the second trench (122) may correspond to the thickness of the first trench (120) or the capsule area for the first trench (120). In an embodiment, the first trench (120) and the second trench (122) may form a trench line (T) for the substrate (110), and in some embodiments, the trench line (T) may correspond to either end of the scribe lines (141, 151).

[0045] Meanwhile, in step S140, as illustrated in FIG. 6, the substrate processing system according to an embodiment of the present disclosure can form a conductive wiring layer (150) on top of the active layer (140). Specifically, the substrate processing system can perform a Back End Of Line (BEOL) process to perform wiring on the active layer (140) based on substrate design information, and through the BEOL process, metal wiring can be formed between the devices created in the FEOL process and with external contacts. In the embodiment, the active layer (140) and the conductive wiring layer (150) on the active layer (140) can form a single chip die.

[0046] Meanwhile, in some embodiments, as illustrated in FIG. 7, the substrate processing system may perform a masking process. Specifically, the mask (160) formed by the substrate processing system may be formed on at least a portion of the conductive wiring layer (150) and the second scribe line (151), and a photoresist (PR) and a hard mask may be used in the masking process. The substrate processing system may form a mask to cover at least a portion of the conductive wiring layer (150) and the second scribe line (151) and to expose the second trench (122) to the outside.

[0047] In step S150, a substrate processing system according to an embodiment of the present disclosure may perform an etching process along a trench line (T) comprising a first trench (120) and a second trench (122). As illustrated in FIG. 8, a substrate processing system according to an embodiment of the present disclosure may perform a dry or wet etching process on the trench line (T). In some embodiments, as illustrated in FIG. 9, the first trench (120) and the second trench (122) may be removed from the substrate (110) according to the etching process of the substrate processing system. In one embodiment, the first trench (120) and the second trench (122) may be removed by a wet etching process. Meanwhile, in some embodiments, as illustrated in FIG. 10, the substrate processing system may perform an etching process on the substrate (110) corresponding to the trench line (T). In one embodiment, the substrate processing system can selectively remove an area of ​​the substrate (110) corresponding to a trench line (T) through a dry etching process. In one embodiment, the substrate processing system can produce a plurality of semiconductor chips by separating a separated chip die from the substrate (110) as at least a portion of the substrate (110) is removed.

[0048] FIG. 12 is a flowchart (S200) for explaining a dicing method of a substrate according to another embodiment of the present disclosure. FIG. 13 is a diagram for explaining a process for applying a dicing method of a substrate according to another embodiment of the present disclosure. Hereinafter, a dicing method of a substrate according to another embodiment of the present disclosure will be described with reference to FIG. 12 and FIG. 13.

[0049] In step S210, as illustrated in FIG. 13, a substrate processing system according to an embodiment of the present disclosure may form a trench (220) on the upper surface of a substrate (210). In the substrate processing system, the substrate (210) may be placed on top of a base filling (230), and an adhesive filling (231) for holding the substrate (210) may be placed between the substrate (210) and the base filling (230). In an embodiment, the trench (220) may be placed based on substrate design information, and the substrate design information may refer to design information related to the placement of semiconductor chips and wiring on the substrate (210), the location of scribe lines (or scribe regions), etc. In an embodiment, the trench (220) may be included in at least a part of the scribe region and may include at least one of a nitride, an oxide, polysilicon, or a metal oxide. Meanwhile, in some embodiments, the substrate processing system can perform an encapsulation process for the trench (220).

[0050] In step S220, as illustrated in FIG. 13, a substrate processing system according to an embodiment of the present disclosure may form an active layer (240) on the upper surface of a substrate (210) adjacent to a trench (220). Specifically, the substrate processing system may perform a FEOL process, and during the FEOL process, the active layer (240) may be formed to be spaced apart from the first scribe line (241) based on substrate design information. In some embodiments, the height of the active layer (240) formed on the substrate may be lower than the height of the trench (220).

[0051] In step S230, as illustrated in FIG. 13, a substrate processing system according to an embodiment of the present disclosure can form a conductive wiring layer (250) on top of an active layer (240). Specifically, the substrate processing system can perform a BEOL process on the active layer (240), and the active layer (240) and the conductive wiring layer (250) on the active layer (240) can form a single chip die.

[0052] In step S240, as illustrated in FIG. 13, a substrate processing system according to an embodiment of the present disclosure may perform an etching process along a trench line including a trench (220). Specifically, a substrate processing system according to an embodiment of the present disclosure may perform a dry or wet etching process, and as in the embodiment described above through FIG. 2, a trench (220) may be removed through a first etching process, and a region of the substrate (210) corresponding to the trench (220) may be removed through a second etching process, and a chip die may be separated to produce a plurality of semiconductor chips.

[0053] FIG. 14 is a flowchart illustrating a dicing method of a substrate according to another embodiment of the present disclosure. FIG. 15 is a diagram illustrating a process for applying a dicing method of a substrate according to another embodiment of the present disclosure. Hereinafter, a dicing method of a substrate according to another embodiment of the present disclosure will be described with reference to FIG. 14 and FIG. 15.

[0054] In step S310, a substrate processing system according to an embodiment of the present disclosure may form a mask on a substrate having a trench line formed thereon so that at least a portion of the trench may be exposed to the outside. In an embodiment, the trench line formed by the substrate processing system may include a first trench and a second trench as described in FIG. 2 above, or may include a single trench as described in FIG. 12 above. In an embodiment, the mask formed by the substrate processing system may be formed on at least a portion of the conductive wiring layer and the scribe line.

[0055] In step S320, a substrate processing system according to an embodiment of the present disclosure may create a crack in a trench by irradiating a laser along a trench line. The crack formed by the substrate processing system may be formed on at least a portion of the trench. In some embodiments, where the trench line includes a first trench and a second trench, the substrate processing system may remove the second trench by performing laser irradiation on the second trench disposed on the first trench.

[0056] In step S330, the substrate processing system according to an embodiment of the present disclosure may remove the remaining trench by irradiating plasma onto the trench where the crack has been formed. Specifically, in step S320, if the substrate processing system removes the second trench among the trench lines including the first trench and the second trench, the substrate processing system may remove the remaining first trench by irradiating plasma onto the substrate. Alternatively, in step S320, if the substrate processing system removes at least a portion of the trench to form a crack, the substrate processing system may remove the entire remaining trench by irradiating plasma onto the substrate.

[0057] In step S340, the substrate processing system according to an embodiment of the present disclosure may irradiate plasma onto the substrate to remove at least a portion of the substrate corresponding to the trench line. The substrate processing system may produce a plurality of semiconductor chips by removing at least a portion of the substrate and separating the chip die.

[0058] Meanwhile, the embodiments disclosed in this specification may be implemented in the form of a recording medium that stores instructions executable by a computer. The instructions may be stored in the form of program code and, when executed by a processor, may generate a program module to perform the operations of the disclosed embodiments. The recording medium may be implemented as a computer-readable recording medium. A computer-readable recording medium may include all types of recording media that store instructions decipherable by a computer. Examples include ROM, RAM, magnetic tape, magnetic disk, flash memory, optical data storage devices, etc.

[0059] The above descriptions are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present disclosure will include technologies that can be easily modified and implemented using the embodiments described above. Accordingly, the scope of the present disclosure should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of the present disclosure.

Claims

1. A step of forming a first trench on the upper surface of the substrate; A step of forming an active layer on the upper surface of the substrate adjacent to the first trench; A step of forming a second trench on top of the first trench; A step of forming a conductive wiring layer on top of the above active layer; and A dicing method for a substrate comprising the step of producing a plurality of semiconductor chips by performing etching along a trench line including the first trench and the second trench.

2. In Paragraph 1, A dicing method of a substrate in which the first trench and the second trench are included in a scribe line, which is a predetermined area on the substrate, to produce a plurality of semiconductor chips.

3. In Paragraph 2 The above trench line is a dicing method of a substrate corresponding to one of the two ends of the above scribe line.

4. In Paragraph 1, A dicing method for a substrate in which each of the first trench and the second trench is composed of at least one of a nitride, an oxide, polysilicon, and a metal oxide.

5. In Paragraph 1, The step of generating the above plurality of semiconductor chips is, A method for dicing a substrate comprising the step of forming a mask on the conductive wiring layer to cover the conductive wiring layer and expose the second trench to the outside.

6. In Paragraph 1, The step of generating the above plurality of semiconductor chips is, A method for dicing a substrate, further comprising the step of irradiating a laser into the second trench to create a crack in the second trench.

7. In Paragraph 1, The step of generating the above plurality of semiconductor chips is, A step of removing the first trench and the second trench by performing wet etching along the trench line; and A method for dicing a substrate comprising the step of removing a substrate formed along the trench line by performing dry etching along the trench line.

8. In Paragraph 7, The step of removing the substrate formed along the trench line is, A method for dicing a substrate comprising the step of irradiating plasma along the trench line.

9. A step of forming a trench on the upper surface of the substrate; A step of forming an active layer on the upper surface of the substrate adjacent to the trench; A step of forming a conductive wiring layer on top of the above active layer; and A dicing method for a substrate comprising the step of producing a plurality of semiconductor chips by performing etching along a trench line including the above trench.

10. A step of forming a mask on a substrate having a trench line formed thereon to expose the trench to the outside; A step of creating a crack in the trench by irradiating a laser along the trench line; A step of removing the cracked trench by irradiating the cracked trench with plasma; and A method for dicing a substrate comprising the step of generating a plurality of semiconductor chips by irradiating plasma onto the substrate along the trench line.

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