Clock data recovery circuit and method suitable for high-speed serdes

Abstract

Disclosed in the present invention are a clock data recovery (CDR) circuit and method suitable for high-speed SerDes. The CDR circuit comprises: an analog front end, inputting a received signal and outputting phase detector results; a phase detector accumulator, used for accumulating the phase detector results; a gain control unit, used for adjusting a gain of a trunk signal; a first branch, comprising a ratio decision device and a phase gain unit; a second branch, comprising a weight decision device and a frequency integration unit; an adder, used for adding an output result of the phase gain unit and an output result of the frequency integration unit, an output of the adder sequentially passing through a phase accumulator and a phase interpolator; and the phase interpolator, used for outputting a sampling clock for use by the analog front end. The present invention can achieve a timely response in the case of a small error and a fast CDR locking speed within short time, reduce accumulation errors of a system, enhance clock jitter tracking effects, and ensure overall performance improvement of the system.

Description

Clock data recovery circuit and recovery method for high-speed SerDes Technical Field

[0001] This invention relates to the field of high-speed SerDes communication technology, and in particular to a clock data recovery circuit and recovery method suitable for high-speed SerDes. Background Technology

[0002] Clock Data Recovery (CDR) is a core component of the SerDes system. Related technologies are primarily suited for high-speed serial data communication, such as PCIe / USB 3.0 / SRIO / JESD204 / automotive Ethernet, etc. CDR performance directly determines the bit error rate (BER) of the SerDes system. In certain applications, such as digital equalizers, failure to track phase can directly lead to equalization misalignment and increased inter-symbol interference (ISI). In practical applications, fixed parameters are often used to maintain system stability, and the structure tends to be a linear system. This allows for qualitative analysis of system performance through system modeling. However, due to rounding errors in the digital implementation of the algorithm and circuit nonlinearity, the system generally exhibits nonlinear characteristics. Analysis using a linear system model often results in significant discrepancies with actual performance, and the BER fails to meet the required specifications.

[0003] In existing CDR loops, the phase gain unit and frequency integration unit share the same proportional decision unit. This allows for the derivation of a set of definite parameters for each part of the system, enabling linear prediction of the overall CDR loop performance. However, in real-world systems, since digital circuits are fixed-point, rounding errors are inevitable, especially in the frequency integration unit. These rounding errors cause random jitter in the entire CDR system, resulting in accumulated frequency errors. The phase accumulator also has rounding errors, and the nonlinearity of the phase interpolator generates periodic jitter, while another part generates random jitter. This introduces significant jitter into the entire CDR system. This jitter, due to the loop, is fed back to the front end of the phase detector. After amplification by the gain control unit and then linear amplification by the proportional decision unit, it impacts the phase gain unit and frequency integration unit, creating a vicious cycle that ultimately degrades the overall system performance. This contradicts the expectation of an ideal linear system, leading to system modeling failure and difficulties in parameter selection. Summary of the Invention

[0004] Purpose of the invention: In order to solve the problem of difficulty in selecting CDR loop parameters and easy generation of frequency offset error in the prior art, the present invention provides a clock data recovery circuit and recovery method suitable for high-speed SerDes.

[0005] Technical solution: A clock data recovery circuit suitable for high-speed SerDes, comprising:

[0006] The analog front end receives the received signal as input and outputs the phase detector result.

[0007] A phase detector accumulator is used to accumulate the results of the phase detector.

[0008] Gain control unit, used to adjust the gain of the main circuit signal;

[0009] The first branch includes a proportional decision unit and a phase gain unit;

[0010] The second branch includes a weight decision unit and a frequency integration unit;

[0011] The adder is used to add the outputs of the phase gain unit and the frequency integration unit. The output of the adder passes through the phase accumulator and the phase interpolator in sequence.

[0012] A phase interpolator is used to output a sampling clock for use by the analog front end.

[0013] Furthermore, the weighted decision-maker is used to linearly amplify the value when the absolute value of the phase detection accumulation exceeds the weight limit, and to make no adjustment when the absolute value of the phase detection accumulation does not exceed the weight limit. The weighted decision-maker is expressed as follows:

[0014] γ is the gain coefficient of the weighted decision unit, α is the set weight limit, pd is the phase detection accumulation value, and Kv2 is the output of the weighted decision unit.

[0015] Furthermore, the proportional decision device is used to perform linear amplification under any phase accumulation value, and the proportional decision device is expressed as: Kv1=β (2)

[0016] β is the gain coefficient of the proportional decision circuit, and Kv1 is the output of the proportional decision circuit.

[0017] Furthermore, the frequency integration unit is also provided with a frequency offset limiter, which sets a maximum allowable frequency offset.

[0018] Furthermore, the phase interpolator is also provided with a jump step size limiter, which sets the maximum allowable phase jump value.

[0019] A clock data recovery method for high-speed SerDes using the aforementioned clock data recovery circuit for high-speed SerDes includes the following steps:

[0020] After receiving the signal, the analog front end performs front-end processing on the received signal under the action of the sampling clock, outputs the results of the multiple phase detectors, and accumulates the results of the multiple phase detectors to obtain the phase detection accumulation value.

[0021] When the phase detection accumulation value is less than the preset weight limit, adjustment is made solely by the phase gain unit; when the phase detection accumulation value exceeds the preset weight limit, both the phase gain unit and the frequency integration unit are adjusted simultaneously.

[0022] The results of the phase gain unit and the frequency integration unit are added together by an adder and then sequentially passed through a phase accumulator and a phase interpolator to output an adjusted sampling clock, which is used by the analog front end.

[0023] With continuous adjustment of the sampling clock, the sampling clock is restored when the CDR is locked, and the analog front end realizes the recovery of the data.

[0024] Furthermore, the specific adjustment method includes: simultaneously inputting the phase detection accumulation value into the first branch and the second branch. In the first branch, under the action of the proportional decision unit, if the phase detection accumulation value is positive, the phase gain unit is adjusted in the positive direction; if the phase detection accumulation value is negative, the phase gain unit is adjusted in the negative direction; if the phase detection accumulation value is zero, it indicates that the current sampling clock phase is appropriate and no adjustment is made.

[0025] In the second branch, under the action of the weight decision unit, if the absolute value of the phase detection accumulation value exceeds the preset weight limit, the frequency integration unit is positively adjusted when the phase detection accumulation value is positive and negatively adjusted when the phase detection accumulation value is negative. If the absolute value of the phase detection accumulation value does not exceed the preset weight limit, the frequency integration unit is not adjusted.

[0026] Furthermore, the specific adjustment method includes: during the adjustment process of the frequency integration unit, there is a maximum limit on the frequency offset, and the frequency offset step size must be within the range of the maximum value.

[0027] Furthermore, specific adjustment methods include: during the phase interpolation process, there is a maximum limit on the step size of the phase interpolator, and the step size of the phase must be within the range of the maximum value.

[0028] Compared with the prior art, the clock data recovery circuit and recovery method for high-speed SerDes provided by the present invention have the following advantages:

[0029] Depending on the magnitude of the phase detection accumulation value, different adjustment methods are selected. When the phase detection accumulation value is small, only the phase gain unit is used for timely adjustment. When the phase detection accumulation value is large, both the phase gain unit and the frequency integration unit are adjusted simultaneously. This effectively avoids the problem of the system failing to respond in time due to small errors, resulting in fast CDR locking speed and short time. Simultaneously, it shields a large amount of non-ideal jitter, greatly reducing the system's frequency offset error and cumulative error. Ultimately, it brings the recovered clock as close as possible to the data edge, thereby enhancing the tracking effect of clock jitter and ensuring an overall performance improvement for the system. Attached Figure Description

[0030] Figure 1 is a schematic diagram of a clock data recovery circuit suitable for high-speed SerDes;

[0031] [Corrected according to Rule 91, 11.07.2025] Figure 2 shows the experimental results using this method under different jitter inputs;

[0032] [Corrected according to Rule 91, 11.07.2025] Figure 3 shows the experimental results using the traditional method under different jitter inputs;

[0033] [Corrected according to Rule 91, 11.07.2025] In Figure 2, (a) is the experimental result of using this method with an input jitter of 2.4 UI@500K; (b) is the experimental result of using this method with an input jitter of 1.2 UI@1M; (c) is the experimental result of using this method with an input jitter of 0.6 UI@2M; and (d) is the experimental result of using this method with an input jitter of 0.24 UI@4. Figure 2 shows the experimental results at 9M; Figure 2(e) shows the experimental results using this method at an input jitter of 0.24UI@10M; Figure 2(f) shows the experimental results using this method at an input jitter of 0.24UI@20M; Figure 2(g) shows the experimental results using this method at an input jitter of 0.24UI@33M; Figure 2(h) shows the experimental results using this method at an input jitter of 0.24UI@50M.

[0034] [Corrected according to Rule 91, 11.07.2025] Figure 3(a) shows the experimental results of the traditional method with an input jitter of 2.4 UI@500K; Figure 3(b) shows the experimental results of the traditional method with an input jitter of 1.2 UI@1M; Figure 3(c) shows the experimental results of the traditional method with an input jitter of 0.6 UI@2M; Figure 3(d) shows the experimental results of the traditional method with an input jitter of 0.24 UI@4.9M; Figure 3(e) shows the experimental results of the traditional method with an input jitter of 0.24 UI@10M; Figure 3(f) shows the experimental results of the traditional method with an input jitter of 0.24 UI@20M; Figure 3(g) shows the experimental results of the traditional method with an input jitter of 0.24 UI@33M; Figure 3(h) shows the experimental results of the traditional method with an input jitter of 0.24 UI@50M.

[0035] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0036] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0037] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0038] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0039] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0040] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0041] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0042] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0043] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0044] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0045] [Corrected according to Rule 91, 11.07.2025] has been deleted.

[0046] [Corrected according to Rule 91, 11.07.2025] has been deleted. Detailed Implementation

[0047] The present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments.

[0048] A clock data recovery circuit suitable for high-speed SerDes, as shown in Figure 1, includes:

[0049] The analog front end receives the received signal as input and outputs the phase detector result.

[0050] A phase detector accumulator is used to accumulate the results of the phase detector.

[0051] Gain control unit, used to adjust the gain of the main circuit signal;

[0052] The first branch includes a proportional decision unit and a phase gain unit;

[0053] The second branch includes a weight decision unit and a frequency integration unit;

[0054] The adder is used to add the outputs of the phase gain unit and the frequency integration unit. The output of the adder passes through the phase accumulator and the phase interpolator in sequence.

[0055] A phase interpolator is used to output a sampling clock for use by the analog front end.

[0056] The weighted decision unit is used to linearly amplify the value when the absolute value of the phase detection accumulation exceeds the weight limit, and to make no adjustment when the absolute value of the phase detection accumulation does not exceed the weight limit. The weighted decision unit is expressed as follows:

[0057] γ is the gain coefficient of the weighted decision unit, α is the set weight limit, pd is the phase detection accumulation value, and Kv2 is the output of the weighted decision unit.

[0058] The proportional decision unit is used to perform linear amplification at any phase accumulation value. The proportional decision unit is expressed as: Kv1=β (2)

[0059] β is the gain coefficient of the proportional decision circuit, and Kv1 is the output of the proportional decision circuit.

[0060] The proportional decision unit is used to perform basic filtering on the phase gain unit, which is used to compensate for large phase offsets, so that the received clock can quickly approach the edge of the transmitting clock at the other end in a short period of time.

[0061] The weighted decision maker makes a weighted decision based on the accumulated value of the phase detection based on a certain weight coefficient, rather than linearly amplifying each accumulated value of the phase detection.

[0062] The frequency integration unit is used to accumulate the potential energy during phase branch adjustment. Essentially, it performs a statistical analysis of the past phase adjustment trend to achieve a similar purpose as predicting the phase offset of the next cycle, thus enabling the system to track larger frequency offsets.

[0063] Considering that the error accumulation in the system loop mainly affects the frequency integration unit, and that the cumulative error of this branch has a long-lasting impact on the CDR system, thus having the greatest impact on performance, the phase gain unit and the frequency integration unit are isolated using a proportional decision unit and a weighted decision unit, respectively. This results in the loop gain and jitter tolerance being expressed as equations (3) and (4), respectively:

[0064] In this way, regardless of the range of the phase detection accumulation value, the system is in a linear adjustment state. When the phase detection accumulation value is less than α, the phase gain unit is mainly used for timely adjustment. When the phase detection accumulation value is greater than α, the frequency integration unit and the phase gain unit are adjusted synchronously. This can effectively avoid the problem that the system cannot respond in time for small phase differences, while shielding a large amount of non-ideal jitter, greatly reducing the cumulative error of the system, thereby ensuring the overall performance improvement of the system.

[0065] Furthermore, considering that extreme situations may arise during engineering implementation, such as the presence of interference signals that could cause excessive phase frequency offset, potentially leading to overflow or failure to track the peer clock jitter, a frequency offset limiter can be set on the frequency integration unit. This limiter has a maximum frequency offset value set according to SPEC specifications. This limiter ensures that the system can track the peer clock jitter under any initial state.

[0066] However, phase interpolators can also suffer from issues such as excessively large adjustment step sizes, insufficient circuit response speed, and missed edges in the interpolation clock. Therefore, a phase transition step size limiter can be set on the phase interpolator, which sets the maximum value of the phase transition. This ensures that the maximum allowable phase adjustment step size per cycle is limited while meeting the maximum jitter rate specified by SPEC.

[0067] A clock data recovery method for high-speed SerDes using the aforementioned clock data recovery circuit for high-speed SerDes includes the following steps:

[0068] After receiving the signal, the analog front end performs front-end processing on the received signal under the action of the sampling clock, outputs the results of the multiple phase detectors, and accumulates the results of the multiple phase detectors to obtain the phase detection accumulation value.

[0069] When the phase detection accumulation value is less than the preset weight limit, adjustment is made solely by the phase gain unit; when the phase detection accumulation value exceeds the preset weight limit, both the phase gain unit and the frequency integration unit are adjusted simultaneously.

[0070] The specific adjustment method includes: inputting the phase detection accumulation value into the first branch and the second branch at the same time. In the first branch, under the action of the proportional decision unit, if the phase detection accumulation value is positive, the phase gain unit is adjusted in the positive direction; if the phase detection accumulation value is negative, the phase gain unit is adjusted in the negative direction; if the phase detection accumulation value is zero, it indicates that the current sampling clock phase is appropriate and no adjustment is made.

[0071] In the second branch, under the action of the weight decision unit, if the absolute value of the phase detection accumulation value exceeds the preset weight limit, the frequency integration unit is positively adjusted when the phase detection accumulation value is positive and negatively adjusted when the phase detection accumulation value is negative. If the absolute value of the phase detection accumulation value does not exceed the preset weight limit, the frequency integration branch is not adjusted.

[0072] The results of the phase gain unit and the frequency integration unit are added together by an adder and then sequentially passed through a phase accumulator and a phase interpolator to output an adjusted sampling clock, which is used by the analog front end.

[0073] With continuous adjustment of the sampling clock, the sampling clock is restored when the CDR is locked, and the analog front end realizes the recovery of the data.

[0074] In addition, to avoid the negative impact of extreme situations that may be encountered during engineering implementation, there is a maximum limit on the frequency offset during the adjustment of the frequency integration unit. The frequency offset step size must be within the maximum value range. For example, in this embodiment, the maximum value of the frequency offset is limited to ±5000ppm.

[0075] During the phase interpolation process, there can be a maximum limit on the step size of the phase interpolator. The adjustment step size of the phase interpolation must be less than the maximum value. For example, in this embodiment, the maximum adjustment step size of the phase interpolation is ±2.

[0076] To verify the effectiveness of the clock data recovery method applicable to high-speed SerDes, the following comparative simulation experiments were conducted. Figures 2 and 3 show the simulation test results of this method and the prior art, respectively. Under the same test conditions, the α value was set to 4, and the channel attenuation was -21.9dB@2.5G. (a) to (h) show the eye diagram opening of the recovered data under various jitter conditions (1.2 times the spec specified) of 2.4UI@500K, 1.2UI@1M, 0.6UI@2M, 0.24UI@4.9M, 0.24UI@10M, 0.24UI@20M, 0.24UI@33M, and 0.24UI@50M, respectively. It can be seen that the probability of error in Figure 2 is significantly reduced compared to Figure 3 (after convergence, there are no more messy spikes; the vertical axis represents the CDR locking state, 1: locked, 0: unlocked).

Claims

1. A clock data recovery circuit suitable for high-speed SerDes, characterized in that, include: The analog front end receives the received signal as input and outputs the phase detector result. A phase detector accumulator is used to accumulate the results of the phase detector. Gain control unit, used to adjust the gain of the main circuit signal; The first branch includes a proportional decision unit and a phase gain unit; The second branch includes a weight decision unit and a frequency integration unit; The adder is used to add the outputs of the phase gain unit and the frequency integration unit. The output of the adder passes through the phase accumulator and the phase interpolator in sequence. A phase interpolator is used to output a sampling clock for use by the analog front end. The weighted decision unit is used to linearly amplify the value when the absolute value of the phase detection accumulation exceeds the weight limit, and to make no adjustment when the absolute value of the phase detection accumulation does not exceed the weight limit. The weighted decision unit is expressed as follows: γ is the gain coefficient of the weighted decision unit, α is the set weight limit, pd is the phase detection accumulation value, and Kv2 is the output of the weighted decision unit. The proportional decision unit is used to perform linear amplification at any phase accumulation value. The proportional decision unit is expressed as follows: Kv1=β (2) β is the gain coefficient of the proportional decision circuit, and Kv1 is the output of the proportional decision circuit.

2. The clock data recovery circuit suitable for high-speed SerDes according to claim 1, characterized in that, The frequency integration unit is also equipped with a frequency offset limiter, which sets the maximum allowable frequency offset.

3. The clock data recovery circuit suitable for high-speed SerDes according to claim 1 or 2, characterized in that, The phase interpolator also includes a step size limiter, which sets the maximum allowable phase jump value.

4. A clock data recovery method for high-speed SerDes using a clock data recovery circuit as described in any one of claims 1-3, characterized in that, Includes the following steps: After receiving the signal, the analog front end performs front-end processing on the received signal under the action of the sampling clock, outputs the results of the multiple phase detectors, and accumulates the results of the multiple phase detectors to obtain the phase detection accumulation value. When the phase detection accumulation value is less than the preset weight limit, adjustment is made solely by the phase gain unit; when the phase detection accumulation value exceeds the preset weight limit, both the phase gain unit and the frequency integration unit are adjusted simultaneously. The results of the phase gain unit and the frequency integration unit are added together by an adder and then sequentially passed through a phase accumulator and a phase interpolator to output an adjusted sampling clock, which is used by the analog front end. With continuous adjustment of the sampling clock, the sampling clock is restored when the CDR is locked, and the analog front end realizes the recovery of the data.

5. The clock data recovery method for high-speed SerDes according to claim 54, characterized in that, The specific adjustment method includes: inputting the phase detection accumulation value into the first branch and the second branch at the same time. In the first branch, under the action of the proportional decision unit, if the phase detection accumulation value is positive, the phase gain unit is adjusted in the positive direction; if the phase detection accumulation value is negative, the phase gain unit is adjusted in the negative direction; if the phase detection accumulation value is zero, it indicates that the current sampling clock phase is appropriate and no adjustment is made. In the second branch, under the action of the weight decision unit, if the absolute value of the phase detection accumulation value exceeds the preset weight limit, the frequency integration unit is positively adjusted when the phase detection accumulation value is positive and negatively adjusted when the phase detection accumulation value is negative. If the absolute value of the phase detection accumulation value does not exceed the preset weight limit, the frequency integration unit is not adjusted.

6. The clock data recovery method for high-speed SerDes according to claim 4 or 5, characterized in that, Specific adjustment methods include: during the adjustment of the frequency integration unit, there is a maximum limit on the frequency offset, and the frequency offset step size must be within the range of the maximum value.

7. The clock data recovery method for high-speed SerDes according to claim 4 or 5, characterized in that, Specific adjustment methods include: during phase interpolation, there is a maximum limit on the step size of the phase interpolator, and the step size of the phase must be within the range of the maximum value.

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