Circuit board and semiconductor package comprising same

Abstract

Disclosed is a circuit board comprising: a first circuit pattern; a thin-film layer disposed on the first circuit pattern; an insulating layer disposed on the thin-film layer; a second circuit pattern disposed on the insulating layer; and a via electrode disposed between the second circuit pattern and the first circuit pattern, wherein the via electrode is connected to the first circuit pattern through the thin-film layer and the insulating layer, the via electrode includes a first via region overlapping the insulating layer in the horizontal direction and a second via region overlapping the thin-film layer in the horizontal direction, and the width of the first via region is different from the width of the second via region.

Description

Circuit board and semiconductor package including the same

[0001] An embodiment according to the present invention relates to a circuit board and a semiconductor package.

[0002] As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or package board consists of a processor package housing a processor chip and a memory package housing a memory chip, connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, such package boards offer the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these benefits, such package boards are widely applied in mobile devices and the like.

[0004] Meanwhile, recently, due to the high specifications of electronic devices such as servers and PCs, the size of packages is increasing. In addition, as the functions required of processors increase, there is a demand for circuit boards capable of configuring these functions separately as processor chips, mounting these processor chips, and interconnecting the processor chips. Furthermore, regarding the above processor, even when it is separated into two processor chips according to function, the number of terminals (Input / Output) provided on each processor chip is increasing.

[0005] Recently, due to reasons such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing as the number of power and signals increases. Consequently, the area, thickness, and density of circuit patterns on circuit boards are also increasing. When the area and thickness of a circuit board increase, it becomes difficult to miniaturize the product, and there are problems such as increased reliability, yield, and product cost due to the bending of the circuit board.

[0006] In particular, as the number and / or types of semiconductor devices and / or semiconductor chiplets mounted on circuit boards become more diverse, semiconductor devices and / or semiconductor chiplets are mounted on circuit boards in various ways. For example, to ensure inter-processor chips, circuit pattern miniaturization is applied to circuit boards to align the pitch between the processor chips and the circuit board. As such, increasing the density of circuit patterns rather than increasing the area or thickness of the circuit board may be more advantageous in terms of product price, reliability (such as warping), and product characteristics. Accordingly, there is currently a significant increase in the demand for miniaturization of circuit patterns and through-electrodes.

[0007] However, while attempting to perform a large amount of calculations, increase the number of I / Os, and form high-density wiring layers, the miniaturization of these circuit patterns increases wiring density and reduces the spacing between patterns. Consequently, the distance over which metal migration (e.g., Cu migration) can occur due to the application of electricity, such as plating, becomes shorter. This significantly reduces the reliability of the circuit board, and thus, improvements are required.

[0008] In this regard, performing etching to remove metal residues present in the pattern results in a reduction in the pattern width and causes problems such as signal loss. Additionally, if a barrier layer is further formed using various plating layers, signal loss and heat generation increase due to the heterogeneous metals, leading to a decrease in adhesion to the insulating layer. Furthermore, there is a difficulty in reducing reliability due to reduced adhesion resulting from the formation of fine line widths or small circuit patterns.

[0009] Therefore, the formation of fine patterns that suppress signal loss between patterns and improve adhesion strength is required.

[0010] An embodiment of the present invention provides a circuit board with improved electrical reliability in a fine pattern by lowering the mobility of metal ions through a thin film layer on a circuit pattern and reducing the reduction rate of the metal, and a semiconductor package including the same.

[0011] In addition, the embodiment can provide a circuit board with improved reliability by having via electrodes on a fine pattern in contact with a thin film layer, and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board with improved structural reliability by improving the bonding strength between the circuit pattern and the insulating layer through the shape of the circuit pattern, and a semiconductor package including the same.

[0013] The problems intended to be solved in the embodiments are not limited thereto, and may also include objectives or effects that can be identified from the means of solving the problems or the forms of implementation described below.

[0014] A circuit board according to an embodiment of the present invention comprises a first circuit pattern; a thin film layer disposed on the first circuit pattern; an insulating layer disposed on the thin film layer; a second circuit pattern disposed on the insulating layer; and a via electrode disposed between the second circuit pattern and the first circuit pattern, wherein the via electrode penetrates the thin film layer and the insulating layer and is connected to the first circuit pattern, and the via electrode includes a first via region overlapped along a horizontal direction with the insulating layer and a second via region overlapped along a horizontal direction with the thin film layer, and the widths of the first via region and the second via region are different from each other.

[0015] The first via region penetrates the insulating layer, and the second via region can penetrate the thin film layer.

[0016] The minimum width in the first via region may be smaller than the maximum width in the second via region.

[0017] The above via electrode may include a third via region that penetrates at least a portion of the upper surface of the first circuit pattern.

[0018] The curvature of the outer surface in the second via region may be greater than the curvature in the third via region.

[0019] It may further include a pattern portion having a maximum width greater than that of the first circuit pattern and the second circuit pattern.

[0020] The above thin film layer can be spaced apart from the above pattern portion.

[0021] The first circuit pattern and the second circuit pattern may include a seed layer and a plating layer on the seed layer.

[0022] In the first circuit pattern above, the plating layer and the seed layer may have different widths from each other.

[0023] In the first circuit pattern above, the maximum width of the plating layer may be greater than the maximum width of the seed layer.

[0024] A portion of the plating layer of the first circuit pattern may overlap with the seed layer and the thin film layer of the first circuit pattern in a vertical direction.

[0025] The second circuit pattern is disposed on the upper surface of the insulating layer, and the via electrode can penetrate the insulating layer.

[0026] The first circuit pattern may include a first region in which the width gradually increases from the upper surface toward the lower surface, a second region in which the width gradually decreases from the first region toward the lower surface of the first circuit pattern, and a third region in which the width gradually increases from the second region toward the lower surface of the first circuit pattern.

[0027] The maximum width of the first circuit pattern above may be the width at the boundary between the first region and the second region.

[0028] An embodiment of the present invention can improve the bonding strength between the via electrode, the insulating layer, and the circuit pattern by having the via electrode disposed between an adjacent first circuit pattern and a second circuit pattern penetrate both the insulating layer and the thin film layer on the first circuit pattern.

[0029] In addition, the embodiment provides a circuit board and a semiconductor package including the same, wherein the movement of metal ions between fine circuit patterns is suppressed through a thin film layer on the circuit pattern even though the spacing between fine circuit patterns is small, thereby forming the shape of the fine pattern in a balanced manner, suppressing the occurrence of electrical short circuits between adjacent patterns, and minimizing signal loss.

[0030] In addition, the embodiment can provide a circuit board and a semiconductor package including the same in which reliability issues such as peeling of the micro pattern are improved by preventing the deterioration of the bonding between the micro pattern and the insulating layer by having a shape with different widths according to the first region and the second region in the micro pattern.

[0031] The various and beneficial advantages and effects of the present invention are not limited to those described above and may be more easily understood in the process of explaining specific embodiments of the present invention.

[0032] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, and

[0033] FIG. 2 is an enlarged view of the K1 portion in FIG. 1, and

[0034] FIG. 3 is a cross-sectional view of a first circuit pattern on a circuit board according to an embodiment, and

[0035] FIG. 4 is a perspective view of a first circuit pattern on a circuit board according to an embodiment, and

[0036] FIG. 5 is a diagram illustrating a first circuit pattern, a second circuit pattern, a thin film layer, and an insulating layer in a circuit board according to an embodiment, and

[0037] Fig. 6 is another example of Fig. 5, and

[0038] FIGS. 7 to 11 are drawings illustrating a method for manufacturing a circuit board according to an embodiment of the present invention, and

[0039] FIG. 12 is a cross-sectional view showing a semiconductor package according to a first embodiment, and

[0040] FIG. 13 is a cross-sectional view showing a semiconductor package according to a second embodiment, and

[0041] FIG. 14 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0042] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0043] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0044] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0045] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0046] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a meaning that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0047] Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “and at least one of B and C (or more than one),” it may include one or more of all combinations that can be combined with A, B, and C.

[0048]

[0049] Terms including ordinal numbers, such as second, first, etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of multiple related described items or any of the multiple related described items. Such terms are intended only to distinguish the component from other components and are not limited by the essence, order, sequence, etc. of the component.

[0050] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0051] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0052] Furthermore, when described as being formed or placed "above or below" each component, "above or below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0053] In addition, the expression that configuration A is positioned between configuration B and configuration C must include the meaning that configuration A is positioned such that at least a portion of it overlaps with configurations B and C in the horizontal and / or vertical directions.

[0054] Expressions referring to directions include horizontal and vertical directions, and the horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of being superimposed along the horizontal direction must include the meaning of being superimposed along the first horizontal direction and / or superimposed along the second horizontal direction.

[0055] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration A is covered by at least a portion of Configuration C.

[0056] Furthermore, when it is stated that Component A 'contacts' Component B, this may include not only cases where the component 'contacts' the other component directly, but also cases where it 'contacts' due to another component located between the component and the other component. Therefore, if Component A is to be understood only as 'directly contacting' Component B, it is described as 'directly contacting'.

[0057] In addition, when it is stated that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part intended for the function and purpose to be resolved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0058] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0059] Before describing the embodiments, the electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and a semiconductor device, and the semiconductor device may be mounted on the circuit board.

[0060] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions or more of devices are integrated into a single chip. Semiconductor chips may be logic chips, memory chips, etc. Logic chips may be non-memory chips such as central processors (CPUs), graphics processors (GPUs), and FPGAs (Field Programmable Gate Arrays). For example, a logic chip may be an application processor (AP) chip comprising at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set comprising a specific combination of those listed above.

[0061] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0062] Meanwhile, the product family to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0063] In addition, electronic devices may include smartphones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, automotive devices, etc. However, they are not limited to these, and it goes without saying that they may be any other electronic devices that process data in addition to these.

[0064] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view of the K1 portion in FIG. 1, FIG. 3 is a cross-sectional view of a first circuit pattern in a circuit board according to an embodiment, FIG. 4 is a perspective view of a first circuit pattern in a circuit board according to an embodiment, FIG. 5 is a diagram illustrating a first circuit pattern, a second circuit pattern, a thin film layer, and an insulating layer in a circuit board according to an embodiment, FIG. 6 is another example of FIG. 5.

[0065] Referring to FIG. 1, a circuit board (100) according to an embodiment may include an insulating layer (110) and an electrode portion (120). In the following embodiments of the present invention, the insulating layer (110) may be provided in a structure in which a plurality of insulating layers are stacked. The electrode portion (120) is embedded in each insulating layer of the insulating layer (110) and thus can function to transmit signals and / or power from a main board (not shown), etc., to a semiconductor device.

[0066] And if the circuit board includes a core layer, it may include a build-up insulating layer laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a core layer (111), a build-up insulating layer (112, 113), a core electrode layer (121), and a build-up electrode layer (122, 123). Additionally, the circuit board (100) may further include a thin film layer (BL). The thin film layer (BL) may be located on one side of each insulating layer (110) and may be located on the circuit pattern of the build-up electrode layer (122, 123).

[0067] In an embodiment, the insulating layer (110) may be composed of a core layer (111) and a build-up insulating portion (112, 113) consisting of at least one insulating layer disposed above and below the core layer (111). Accordingly, the build-up insulating portion (112, 113) stacked on the core layer may include a plurality of vertically stacked insulating layers. The build-up insulating portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be provided with a plurality of insulating layers stacked thereon. Additionally, the build-up layer may be referred to as a build-up structure. The following description is based on this.

[0068] And as another example, the insulating layer (110) is described as including a core layer, but the circuit board may be made of a coreless structure.

[0069] In an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). Additionally, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110). This will be described later.

[0070] And the upper build-up layer (112) may be an 'upper build-up structure'. The lower build-up layer (113) may be a 'lower build-up structure'. In this embodiment, the core layer (111) may be positioned in the center in the vertical direction of the insulating layer (110). When the build-up layer is laminated on both sides of the core layer (111), the core layer (111) may be located in the center of the insulating layer (110). That is, the upper build-up layer (112) may be positioned on the core layer (111), and the lower build-up layer (113) may be positioned below the core layer (111).

[0071] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer forming the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include reinforced or flexible plastics such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed from a material comprising a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a silica or alumina filler is disposed in a thermosetting resin or a thermoplastic resin.

[0072] The insulating layer (110) may have a structure in which multiple different insulating materials are laminated, and an exemplary arrangement structure is described in more detail as follows.

[0073] In one embodiment, the insulating layer (110) may include a core layer (111) that includes a reinforcing member. Here, the core layer (111) may include a reinforcing member, and its thickness in the vertical direction (X-axis direction, or stacking direction) may be in the range of tens of micrometers to hundreds of micrometers. Additionally, the upper build-up layer (112) and the lower build-up layer (113) may each be disposed above and below the core layer (111) and may include a plurality of layers that do not include a reinforcing member. The reinforcing member may also be a reinforcing fiber or glass fiber embedded within the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (Y-axis direction) of the insulating layer and may have a different meaning from spaced-apart fillers. For example, the insulating layer (110) may be composed of a resin, a filler and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0074] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to a copper clad laminate. Furthermore, the core layer (111) may be composed of multiple layers, and the multiple layers may be made of the same or different materials. Additionally, the core layer (111) may include via electrodes penetrating the upper and lower surfaces of the core layer (111).

[0075] And the upper build-up layer (112) or the lower build-up layer (113) may be provided with any insulating resin, such as a thermosetting and / or photocurable resin. As a thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, may be used, and materials such as prepreg (PPG) containing glass fibers may be used. As a photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin may be used. The aforementioned any insulating resin may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and may include inorganic fillers such as silica. When an insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fibers or aramid fibers. For example, when manufacturing the insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric Resin), BT, etc. may be used. For example, if the circuit board (100) is coreless, the insulating layer (110) may be provided by laminating ABF without a core layer.

[0076] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor device, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0077] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion will be described interchangeably with 'circuit pattern' and 'pattern portion'. Also, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. Furthermore, the wiring portion of the electrode portion (120) may be designed in various forms for signal and / or power transmission with a semiconductor device and is disposed within each insulating layer of the stacked build-up layers (112, 113).

[0078] In the electrode portion (120), the via electrode (or via portion) is positioned to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns placed in each insulating layer of the build-up layer (112, 113). The via electrode can connect multiple circuit patterns (wiring portions) to each other. The via electrode can also be made up of multiple units, just like the wiring portion. That is, the insulating layer may include via holes for the placement of the via electrode. And the via electrode may have a wider width than the circuit pattern for optimizing impedance or heat dissipation, but is not limited thereto and can be freely designed.

[0079] In the electrode portion (120), the wiring portion (circuit pattern) can be placed on each insulating layer. The circuit pattern can be electrically connected to the circuit pattern. Additionally, the wiring portion (circuit pattern) can be connected to each via electrode. Furthermore, the circuit pattern placed on the upper and lower surfaces of the insulating layer within the build-up layer (112, 113) can be electrically connected to a semiconductor device and / or a main board or substrate, etc. For example, such an electrode portion (120) can be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0080] In the embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. The upper electrode portion (122) is disposed in each insulating layer of the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. The lower electrode portion (123) is disposed in each insulating layer of the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0081] The core electrode portion (121) may include a core pattern (121a) disposed on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111).

[0082] The upper electrode portion (122) may include wiring portions (122a, 122b) disposed on the upper and lower surfaces of each insulating layer of the upper build-up layer (112). The wiring portions may include a first pattern portion (122b) and a second pattern portion (122a). Additionally, the upper electrode portion (122) may include a first via portion (122c) penetrating the upper build-up layer (112).

[0083] The first via portion (122c) may be in contact with the second pattern portion (122a). Furthermore, the first pattern portion (122b), the second pattern portion (122a), and the first via portion (122c) may be electrically connected. And as previously described, the maximum width of the first pattern portion (122b) may be smaller than the maximum width of the second pattern portion (122a). The first pattern portion (122b) may be a fine pattern. For example, the first pattern portion (122b) may have a line width of several micrometers (μm) or less, or a pitch of several tens of μm or less.

[0084] The lower electrode portion (123) may include a third pattern portion (123b) and a fourth pattern portion (123a) disposed on the upper and lower surfaces of the lower build-up layer (113). Additionally, the lower electrode portion (123) may include a second via portion (123c) penetrating the lower build-up layer (113).

[0085] The second via section (123c) may be in contact with the fourth pattern section (123a). Furthermore, the third pattern section (123b), the fourth pattern section (123a), and the second via section (123c) may be electrically connected. And as previously described, the maximum width of the third pattern section (123b) may be smaller than the maximum width of the fourth pattern section (123a). The third pattern section (123b) may be a fine pattern. And the description of the first and second circuit patterns may be applied identically to the third pattern section (123b) and the fourth pattern section (123a). However, the third pattern section (123b) and the fourth pattern section (123a) may be located in the lower build-up layer (113).

[0086] As such, in the embodiment, the circuit pattern of the upper electrode portion (or lower electrode portion) may include a wiring portion having a fine pitch (first pattern portion) and a wiring portion having a larger pitch than the wiring portion having a fine pattern (e.g., first pattern portion) (e.g., second pattern portion).

[0087] For example, the second circuit pattern (or fourth circuit pattern) may refer to a pattern having the same width and spacing as a pattern used in a conventional circuit board, and the first circuit pattern (or third circuit pattern) may refer to a fine circuit pattern having a narrower width and spacing than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or the formation of an inductor. For example, the line width and spacing (LXS, Line and Space) of the first circuit pattern (or third circuit pattern) may be 5 μm X 5 μm or less.

[0088] Additionally, semiconductor devices (CH1, CH2) may be placed on the upper build-up layer (112). The semiconductor devices (CH1, CH2) may be electrically connected to the first pattern section (122b), etc. The circuit board may be arranged to have a high wiring density for signal connection with the semiconductor devices (CH1, CH2). Additionally, the first pattern section (122b) may be provided to function as a line for signal connection between the semiconductor devices (CH1, CH2), thereby preventing the semiconductor devices from becoming unnecessarily large and improving the yield of the semiconductor devices.

[0089] In addition, the circuit board according to the embodiment can be classified into a package board and an interposer depending on its function. The package board serves the function of mounting semiconductor devices and / or an interposer. As data increases, the area of ​​the circuit board expands, or as the number of stacked insulating layers increases, the yield of the circuit board may significantly decrease. Therefore, to improve the yield of a circuit board with a high number of stacked layers, the yield of the circuit board can be improved by separating it into an interposer and a package board. Furthermore, as the density of terminals of semiconductor devices increases, it may be difficult to implement pads on the package board that have an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer for the pad size of the package board and the fine pattern size of the terminals of the semiconductor devices.

[0090] The package substrate and interposer described above can be classified into a core substrate and a coreless substrate, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer containing a reinforcing member among the stacked insulating layers. The reinforcing member may refer to glass fiber. By being positioned thicker than other insulating layers, the core layer may have the function of preventing warping of the circuit board during the manufacturing process. However, the core layer may cause problems such as voltage drop and signal loss, or make thinning difficult. Therefore, depending on the application, a coreless substrate that does not include a core layer may be used as the insulating layer of the circuit board.

[0091] The protective layer (SR) can function to protect the pad from external moisture or contaminants, and to prevent short-circuit problems during bonding between the semiconductor device and / or main board and the circuit board, the protective layer (SR) may, for example, be provided as a solder resist. Specifically, the semiconductor device and / or main board, etc., have multiple terminals for connecting the circuit board. In addition, multiple terminals may be arranged at a high density. When multiple terminals and the pad of the circuit board are bonded, solder may be used, for example. When solder is used, solder short-circuit problems may occur between terminals with high density; therefore, to solve such short-circuit problems, a solder resist with poor wettability with solder may be placed. In addition, the protective layer (SR) may be made of a material that has insulating properties for electrical connections. The protective layer (SR) may include resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. Additionally, the lower build-up layer (not shown) may include any one of a photosolder resist layer, a cover-lay, and a polymer material. The protective layer (not shown) may have at least one opening for connection between the terminal of the semiconductor device and the pad of the circuit board.

[0092] The thin film layer (BL) is disposed along the surface where the pattern portion is placed in the build-up layer (112, 113) and can cover the wiring portion. In particular, the thin film layer (BL) can be disposed on the first pattern portion (122b), which is a fine pattern. And when the wiring portion (e.g., the first pattern portion) comes into contact with a via portion of another insulating layer, the via portion can penetrate the thin film layer (BL). For example, the thin film layer (BL) can be disposed on the upper surface of the upper build-up layer (112). The following description of the thin film layer (BL), etc., is based on the upper build-up layer. In addition, the thin film layer (BL) can be disposed along the upper surface of the upper build-up layer (112) and can be disposed on the wiring portion (first pattern portion) disposed in the upper build-up layer. Furthermore, the thin film layer (BL) is disposed on the surface where the first via portion is placed

[0093] Referring further to FIGS. 2 and FIGS. 3, the upper build-up layer (112) may include a first insulating layer (112a) and a second insulating layer (112b). The following description is based on one insulating layer and another insulating layer laminated on the one insulating layer in the upper build-up layer (112). However, the following description may also apply to other insulating layers of the upper build-up layer. The second insulating layer (112b) may be placed on the first insulating layer (112a). Additionally, the first insulating layer (112a) and the second insulating layer (112b) may be arranged sequentially along the stacking direction or the vertical direction (X-axis direction).

[0094] And the first insulating layer (112a) may include an upper surface (US1) and a lower surface (BS1). The lower surface (BS1) of the first insulating layer (112a) may be in contact with the upper surface of the core layer (111) or may be placed on the upper surface of the core layer (111). And the upper surface (US1) of the first insulating layer (112a) may be a surface facing or opposite to the lower surface (BS1) of the first insulating layer (112a). A first pattern portion (122b) and a second pattern portion (122a) may be located on the upper surface (US1) of the first insulating layer (112a). Hereinafter, the first pattern portion located on the first insulating layer (112a) is described as the first circuit pattern (122ba). And the first pattern portion located on the second insulating layer (112b) is described as the second circuit pattern (122bb).

[0095] The thin film layer (BL) is in contact with the upper surface of each insulating layer in the upper build-up layer (112), and may also cover and be in contact with the first pattern portion. Depending on the process, the thin film layer (BL) may cover and be in contact with the second pattern portion placed on the same layer. However, to improve bonding strength, the thin film layer (BL) may cover or be in contact only with the first pattern portion and be spaced apart from the second pattern portion.

[0096] Additionally, the thin film layer (BL) may not come into contact with a via electrode or via portion penetrating the insulating layer on which the wiring portion contacted by the thin film layer (BL) is mounted. For example, the thin film layer (BL) is placed on a first insulating layer (112a) that is in contact with the thin film layer (BL) and may come into contact with a first pattern portion (122b) and a second pattern portion (122a). At this time, it may not come into contact with a first via portion penetrating the first insulating layer (112a) on which the first pattern portion (122b) and the second pattern portion (122a) are mounted. However, the thin film layer (BL) may come into contact with a first via portion penetrating the second insulating layer (112b), which is an upper insulating layer. A detailed explanation of this will be provided later.

[0097] First, in the circuit board according to the embodiment, the first pattern portion (122b) and the second pattern portion (122a) may include groove portions (G1, G2) formed on the lower portion. The first pattern portion (122b) may include the first groove portion (G2). The second pattern portion (122a) may include the second groove portion (G1). Furthermore, the width (or area) of the first pattern portion (122b) may increase from the upper surface toward the lower portion to a portion of the area, and decrease from a portion of the area toward the lower surface. Then, the width (or area) of the first pattern portion (122b) may again increase toward the lower surface.

[0098] At this time, the part where the width (or area) decreases may be the first groove (G2). The second pattern part (122a) may decrease in width (or area) toward the bottom surface in some area. Then, the second pattern part (122a) may increase in width (or area) again toward the bottom surface. At this time, the part where the width (or area) decreases may be the second groove (G1).

[0099] And the first pattern portion (122b) may include a seed layer and a plating layer. The first pattern portion (122b) may include a seed layer (SL) and a plating layer (EL) on the seed layer. The plating layer (EL) and the seed layer (SL) may have different widths. For example, the seed layer (SL) may be placed at the bottom of the first pattern portion (122b). The seed layer (SL) may be located in the third region or the second and third regions described later. Accordingly, the maximum width of the seed layer (SL) may be smaller than the maximum width of the plating layer (EL). Conversely, the maximum width of the plating layer (EL) may be larger than the maximum width of the seed layer (SL). This corresponds to the description of the width of the first pattern portion (122b) described later.

[0100] Furthermore, at least a portion of the plating layer (EL) may overlap with the seed layer (SL) and thin film layer (BL) of the first pattern portion (or first circuit pattern) in a direction perpendicular (X-axis direction).

[0101] Referring further to FIG. 4, the first pattern section (122b) may be divided into multiple regions depending on the increase or decrease in width (or area). In an embodiment, the first pattern section (122b) may include a first region (AR1), a second region (AR2), and a third region (AR3). Hereinafter, the upper surface of the first pattern section (122b) is denoted as 'US'. And the lower surface of the first pattern section (122b) is denoted as 'BS'.

[0102] In the embodiment, the first pattern portion (122b) may be composed of a first area (AR1) to a third area (AR3) according to an increase or decrease in width (or area) along the vertical direction or the direction opposite to the vertical direction.

[0103] First, the first region (AR1) may be an area where the width gradually increases from the upper surface (US) of the first pattern part (122b) toward the lower surface (BS). The second region (AR2) may be one of the areas other than the first region (AR1). Additionally, the second region (AR2) may be an area where the width gradually decreases from the first region (AR1) toward the lower surface (BS) of the first pattern part (122b). The third region (AR3) may be an area other than the first region (AR2) and the second region (AR2). The third region (AR3) may be an area where the width gradually increases from the lower part of the second region (AR2) toward the lower surface (BS). Additionally, the first region (AR1) may be an area from the region having the maximum width (W3) to the upper surface. The second region (AR2) may be an area from the region having the maximum width (W3) to the region having the minimum width (W5). And the third region (AR3) may be the area from the region having the minimum width (W5) to the bottom surface.

[0104] For example, the width (or area) of the first pattern portion (122b) may differ between the upper surface (US) of the first pattern portion (122b) and the lower surface (BS) of the first area (AR1). In an embodiment, the width (W3) of the first pattern portion (122b) may be maximum at the boundary between the first area (AR1) and the second area (AR2). That is, the width of the first pattern portion (122b) may be maximum at the boundary.

[0105] In an example, the maximum width (W3) in the first pattern section (122b) may be greater than the width (W4) on the upper surface (US) of the first pattern section (122b) in the first area (AR1). The width (or area) of the circuit pattern in the first area (AR1) may decrease as it moves from the maximum width toward the upper surface (US). Also, the difference (W6) between the maximum width (W3) in the first pattern section (122b) and the width (W4) on the upper surface (US) of the first pattern section (122b) may be less than 0.25 times the width (W4) (or maximum width) of the upper surface (US). For example, the difference (W6) between the maximum width (W3) in the first pattern section (122b) and the width (W4) on the upper surface (US) of the first pattern section (122b) may have a range of 0.1 to 0.25 times the width (W4) (or maximum width) of the upper surface (US).

[0106] Additionally, the maximum width (W3) in the first pattern section (122b) may be greater than the width on the lower surface (BS) of the first pattern section (122b) in the second area (AR2). Additionally, the width (W4) of the upper surface (US) in the first pattern section (122b) may be greater than the minimum width (W3).

[0107] Additionally, as an embodiment, the first pattern portion (122b) may include a side (SS) positioned between the upper surface (US) and the lower surface (or lower surface) (BS). The side (SS) may be partitioned based on a boundary. The side (SS) may include a first side (SS1), a second side (SS2), and a third side (SS3). The first side (SS1) may be a side of the first pattern portion (122b) in the first area (AR1). The second side (SS2) may be a side of the first pattern portion (122b) in the second area (AR2). The third side (SS3) may be a side of the first pattern portion (122b) in the third area (AR3).

[0108] In an embodiment, the angle formed by the upper surface (US) and the lower surface (BS) of the first pattern part (122b) with the contacting side surface (SS) may be different. In the second area (AR2), the second angle formed by the lower surface (BS) of the first pattern part (122b) and the second side surface (SS2) may be different from the first angle formed by the upper surface (US) of the first pattern part (122b) and the first side surface (SS1) in the first area (AR1). Additionally, in the third area (AR3), the third angle formed by the lower surface (BS) of the first pattern part (122b) and the third side surface (SS3) may be different from the first angle formed by the upper surface (US) of the first pattern part (122b) and the first side surface (SS1) in the first area (AR1).

[0109] Additionally, the area (S1) of the upper surface (US) of the first pattern part (122b) may differ from the area (S2) of the lower surface (BS). For example, the area (S1) of the upper surface (US) of the first pattern part (122b) may be larger than the area (S2) of the lower surface (BS).

[0110] With this configuration, the width (W4) on the upper surface (US) of the first pattern section (122b) can be formed to be smaller in proportion to the length in the vertical direction (X-axis direction) of the first pattern section (122b). This allows the spacing between adjacent first pattern sections (122b) to be reduced. Consequently, the line width and spacing of the circuit pattern in the electrode section can be refined.

[0111] In an embodiment, the upper surface (US) of the first pattern part (122b) may not overlap at least partially with the lower surface (BS) of the first pattern part (122b) in a vertical direction (X-axis direction). Additionally, the lower surface (BS) of the first pattern part (122b) may not overlap at least partially with the upper surface (US) of the first pattern part (122b).

[0112] The width (W4) on the upper surface (US) of the first pattern part (122b) may be larger than the width on the lower surface (BS) of the first pattern part (122b). As a variation, the width (W4) on the upper surface (US) of the first pattern part (122b) may be formed to be smaller than the width on the lower surface (BS) of the first pattern part (122b).

[0113] In the embodiment, by positioning the boundary between the first region (AR1) and the second region (AR2) of the first pattern part (122b) adjacent to the lower surface (BS) of the first pattern part (122b), the undercut issue of the first pattern part (122b) caused by etching is reduced, thereby suppressing an excessive reduction in the contact area between the first pattern part (122b) and the core layer, and thus improving physical bonding strength. According to the embodiment, in the process of placing the first pattern part (122b), after placing a seed layer (not shown), the first pattern part (122b) is formed or placed by using an electroplating method. Accordingly, the first pattern part (122b) includes a seed layer (not shown) and an electroplated layer formed by electroplating. When a process of removing a seed layer (not shown) is performed after forming the first pattern portion (122b), the etching rates over time may differ due to the difference in grain between the seed layer (not shown) and the electroplating layer. This undercut issue occurs because the etching rate of the seed layer (not shown) is greater than the etching rate of the electroplating layer. Therefore, by positioning the boundary between the first region (AR1) and the second region (AR2) adjacent to the lower surface (BS) of the first pattern portion (122b), the aforementioned undercut issue can be reduced.

[0114] In addition, in the embodiment, the thickness of the second region (AR2) (or the thickness of the third region) may be greater than the thickness of the first region (AR1).

[0115] And the second pattern section (122a) may have a maximum width (W1) at the top. Furthermore, the second pattern section (122a) may have a minimum width (W2) at the bottom.

[0116] The second pattern section (122a) may have a width (W1) on the upper surface that is larger than the width (W2) on the lower surface. As a result, the first pattern section (122b) can have a larger ratio between the width on the lower surface and the width on the upper surface compared to the second pattern section (122a). That is, the first pattern section (122b) can have a larger width on the lower surface compared to the upper surface. By doing so, the bonding strength between the first pattern section (122b) and the upper build-up layer (112) is further improved, thereby further improving the electrical reliability of the circuit board.

[0117] Thus, even though the first pattern part (122b) and the second pattern part (122a) have the same groove formed on their lower surfaces by etching, etc., the first pattern part (122b), which has a relatively smaller pitch (or width), may have a smaller difference between the maximum width and the lower width compared to the second pattern part (122a). In other words, the width of the first groove part (G2) may be smaller than the width of the second groove part (g1). As a result, the area lost by etching, etc. in the first pattern part (122b) can be reduced compared to the second pattern part (122a). In particular, the bonding area in contact with the upper build-up layer (112) of the first pattern part (122b) with a fine pitch may not be significantly reduced even if etching is performed. That is, the bonding area between the upper build-up layer (112) and the first pattern part (122b) can be maximized. Thus, the structural reliability of the first pattern part (122b) can be improved.

[0118] Furthermore, the thin film layer (BL) may be an organic promoter. In an example, the thin film layer (BL) may be composed of a material containing various azole groups. For instance, the thin film layer (BL) may include at least one or a combination of imidazole and derivatives, triazole and derivatives, tetrazol and derivatives, oxazole and derivatives, thiazole and derivatives, and benzothiazole.

[0119] The thin film layer (BL) covers the first pattern portion (122b) and the second pattern portion (122a), allowing it to come into contact with the first pattern portion (122b) and the second pattern portion (122a). Accordingly, in the thin film layer (BL), an Azole group (a heterocyclic compound mainly containing N and S atoms) can come into contact with copper ions (Cu 2+ It can form complexes by forming strong coordinate bonds with ). For example, the azole group contains electron-donating atoms such as nitrogen (N) or sulfur (S), so copper ions (Cu / Cu 2+ It can form strong coordination bonds with ). As a result, copper ions are stabilized from a state where they can move freely into a complex state, which can reduce their mobility. In other words, the reduction in copper charge can decrease the migration speed. Consequently, the migration of copper ions can be suppressed. Therefore, the electrical reliability of the circuit board can be improved. In particular, electrical reliability can be improved in fine patterns.

[0120] Furthermore, it can be adsorbed onto the copper surface with an azole-based organic material to form a chemical protective layer. And the formed protective layer is Cu / Cu on the copper surface. 2+The process of ions being released into the solution can be physically blocked. Consequently, as the rate at which copper ions are released into the electrolyte slows down, the reduction rate slows down, which can suppress dendrite formation. As a result, deposition can proceed uniformly.

[0121] With this configuration, corrosion of the wiring section is prevented, and protection of the wiring section can be easily implemented. Furthermore, electrical insulation by the thin film layer (BL) can be further improved. For example, electrical short circuits between fine patterns can be suppressed. In addition, electrical interference (signal interference, leakage current) between wiring or patterns is reduced, thereby providing a circuit board with improved signal transmission stability and performance. Furthermore, since the thin film layer (BL) is made of an organic material, the bonding strength with other insulating layers can also be improved.

[0122] Furthermore, the thin film layer (BL) may be disposed not only on the upper surface of each insulating layer but also on the upper surface and side of the first pattern section (122b) and the second pattern section (122a). The thin film layer (BL) may be positioned along the side of the first pattern section (122b) and the second pattern section (122a), and its thickness may increase along the upper or vertical direction. For example, the thickness of the thin film layer (BL) on the upper surface of each of the first pattern section (122b) and the second pattern section (122a) may be greater than its thickness on the side of each of the first pattern section (122b) and the second pattern section (122a).

[0123] Referring to FIG. 5, the first pattern portion (122b) may be located on the upper surface of the first insulating layer (112a). Below, the first circuit pattern (122ba) and the second circuit pattern (122bb) of the first pattern portion (122b), which is a fine pattern, will be described based on these. The first circuit pattern (122ba) is in contact with the first via electrode (122ca) penetrating the first insulating layer (112a) and may be electrically connected to the first via electrode (122ca).

[0124] And a thin film layer (BL) may be positioned on the upper surface of the first pattern portion (122b) and the upper surface of the first insulating layer (112a). The thin film layer (BL) is placed in the groove of the first pattern portion (122b) and may not have a concave outer surface corresponding to the groove. For example, the thin film layer (BL) may maintain a uniform thickness toward the top even in the groove.

[0125] And a second circuit pattern (122bb) may be located on the upper surface of the second insulating layer (112b). The second circuit pattern (122bb) may be located on top of the first circuit pattern (122ba). And a second via electrode (122cb) may penetrate the second insulating layer (112b). And the second via electrode (122cb) may be in contact with the first circuit pattern (122ba) and the second circuit pattern (122bb). That is, the second via electrode (122cb) may connect the first circuit pattern (122ba) and the second circuit pattern (122bb) located on different insulating layers to each other.

[0126] The second via electrode (122cb) can penetrate the thin film layer (BL). That is, the via hole where the second via electrode (122cb) is located can be formed in the thin film layer (BL) and the second insulating layer (112bb). The second via electrode (122cb) may include a first via region (VA1) penetrating the second insulating layer (112b) and a second via region (VA2) penetrating the thin film layer (BL). At this time, at the interface between the thin film layer (BL) and the second insulating layer (112b), the second via electrode (122cb) may have a first convex portion that is convex toward the outside from the center of the second via electrode (122cb).

[0127] That is, the convex portion of the second via electrode (122cb) may be located in the second via region (VA2). And the convex portion of the second via electrode (122cb) may overlap horizontally with the thin film layer (BL) and the second insulating layer (112b). The convex portion of the second via electrode (122cb) may not overlap horizontally with the first circuit pattern (122ba).

[0128] Furthermore, the convex portion of the second via electrode (122cb) may overlap with the second via electrode (122cb) in a vertical direction or in a stacking direction, and may also overlap with the first circuit pattern (122ba) in a vertical direction or in a stacking direction.

[0129] In addition, in the embodiment, the width (W8) in the first via region (VA1) may differ from the width (W7) in the second via region (VA2). As described below, depending on the process, for example, a convex portion may not be formed in the second via region (VA2). In this case, the width (W8) in the first via region (VA1) may be greater than the width (W7) in the second via region (VA2). For example, the width in the vertical bisector of the first via region (VA1) may be greater than the width in the vertical bisector of the second via region (VA2). Also, the minimum width in the first via region (VA1) may be greater than the minimum width in the second via region (VA2).

[0130] Additionally, the minimum width (Wa) in the first via region (VA1) of the second via electrode (122cb) may be smaller than the maximum width (Wb) in the second via region (VA2). With this configuration, the bonding strength between the second via electrode (122cb), the thin film layer (BL), and the second insulating layer (112b) can be improved.

[0131] In addition, the second via electrode (122cb) may include a third via region (VA3) that penetrates the first circuit pattern (122ba). The third via region (VA3) may be a region that penetrates at least a portion of the first circuit pattern (122ba). That is, the second via electrode (122bc) may penetrate at least a portion of the first circuit pattern (122ba). Accordingly, the second via electrode (122bc) may overlap at least a portion of the first circuit pattern (122ba) in the horizontal direction. And the third via region (VA3) may be a region where the second via electrode (122cb) protrudes downward from the second via region (VA2).

[0132] And the curvature (i.e., the curvature of the convex portion, r1) in the second via region (VA2) of the second via electrode (122bc) may be greater than the curvature (r2) in the third via region (VA3).

[0133] Furthermore, corresponding to the third via region (VA3), the upper surface of the first circuit pattern (122ba) may have a concave portion. On the upper surface of the first circuit pattern (122ba), the concave portion may have a higher roughness compared to the area other than the concave portion. Also, a portion of the chemical copper of the second via electrode (122bc) may be located below the upper surface of the first circuit pattern (122ba).

[0134] With this configuration, the contact area between the via electrode and the circuit pattern is increased, allowing for a more stable electrical connection. Furthermore, the via electrode is deeply inserted into the circuit pattern, which further improves the mechanical bonding between the via electrode and the circuit pattern. This reduces cracks that may occur between the via electrode and the circuit pattern. Additionally, a thin film layer (BL) is placed to partially restrict the space between the via electrode and the pad, further reducing the occurrence of copper dendrites and minimizing the possibility of an electrical short circuit.

[0135] Referring further to FIG. 6, the above-described second via electrode (122bc) may have a first via region (VA1) and a second via region (VA2). The second via electrode (122bc) may have a convex portion extending outward from the second via region (VA2).

[0136] Accordingly, when forming via electrodes on a circuit pattern, the plating and etching processes can be performed more uniformly.

[0137] FIGS. 7 to 11 are drawings illustrating a method for manufacturing a circuit board according to an embodiment of the present invention.

[0138] A circuit board according to an embodiment may include the steps of forming a core layer, a core layer and an electrode portion, forming a mask and a mask pattern on the core layer; forming a circuit pattern, removing the mask, and removing a seed electrode layer. Except for the details described below, the description of each component may be applied as described above.

[0139] Referring to FIG. 7, a core layer (111) is formed, and a core electrode portion (121), which is a via electrode and a pad, can be formed on the core layer (111). The core layer (111) can form a cavity (not shown) depending on the circuit board or package substrate. A laser light or a cutting mechanism (e.g., mechanical etching) can be irradiated onto the core layer (111) to form the cavity.

[0140] And an upper build-up layer (112) may be formed on the core layer (111). Additionally, a lower build-up layer (113) may be formed on the lower part of the core layer (111). Here, the upper build-up layer (112) may be composed of a plurality of insulating layers. And below, the explanation will be based on the 'upper build-up layer'.

[0141] Referring to FIG. 8, an upper build-up layer (112) is formed, and via holes for forming via portions can be formed in the upper build-up layer (112). The via holes can be formed by various methods such as masking and etching.

[0142] Referring to FIG. 9, wiring portions can be formed on the upper build-up layer (112) by means of a mask and etching, etc. Here, the pattern formed on the upper build-up layer (112) may include a first pattern portion (122b) which is a fine pattern and a second pattern portion (122a) which is wider than the first pattern portion (122b).

[0143] The circuit pattern at the electrode portion can be formed using manufacturing processes for printed circuit boards, such as the additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process). Additionally, the pattern can be formed using a dry film or the like.

[0144] A seed electrode layer may be formed on the upper build-up layer (112), and a mask may be formed on the seed electrode layer. The mask may include, for example, a dry film. The mask may form a pattern by exposure, etc.

[0145] At this time, the pattern can be formed into a Gaussian structure of the laser by controlling the exposure amount through the exposure material. For example, the pattern can be formed with a structure that increases its width toward a portion of the lower area, corresponding to the structure of the circuit pattern described above.

[0146] In other words, the pattern of the mask has a predetermined shape (e.g., a hole) at the location where the wiring portion is formed, and the hole can correspond to the structure of the wiring portion described above. For example, based on the first circuit pattern, the hole (or groove) may have a first region in which the width gradually decreases toward the top (upper surface), a second region in which the width gradually decreases toward the bottom (lower surface), and a third region in which the width increases again.

[0147] A first pattern portion (122b) and a second pattern portion (122a) may be formed on the pattern of such a mask. For example, the first pattern portion (122b) and the second pattern portion (122a) may be formed through copper plating. Plating made of copper or the like may be performed on the pattern or hole of the mask described above.

[0148] Referring to FIG. 10, a thin film layer (BL) may be further formed on the upper surface of the insulating layer and the upper surface of the wiring portion of the upper build-up layer (112). Additionally, an insulating layer may be further disposed on the thin film layer (BL). Furthermore, an electrode portion may be further formed on the insulating layer above the thin film layer (BL). For example, as described above, the via electrode may penetrate both the thin film layer (BL) and the insulating layer. The method of forming such an electrode portion may be applied in the same manner as described above.

[0149] Referring to FIG. 11, the upper build-up layer (112) may be composed of a plurality of insulating layers, and a plurality of insulating layers may be further formed on the core layer. A thin film layer (BL) may be formed on each insulating layer of the upper build-up layer. Furthermore, the same may be applied to the lower build-up layer (113). Additionally, an upper electrode portion may be formed on each upper build-up layer. And a lower electrode portion may be formed on each lower build-up layer.

[0150] FIG. 12 is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 13 is a cross-sectional view showing a semiconductor package according to a second embodiment, and FIG. 14 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0151] In the various semiconductor packages described below, the circuit board described above may be located in a portion of the area or correspond to a single substrate. For example, the circuit board according to the various embodiments described above may be located on a single substrate of the semiconductor package. In particular, the circuit board according to the various embodiments described above may be applied to a package having an FC-BGA (Flip Chip Ball Grid Array). In particular, the circuit board according to the various embodiments described above may be applied to a second substrate (1200) in the package. In particular, the circuit board according to the various embodiments described above may be applied to an interposer substrate. Furthermore, the circuit board according to the various embodiments described above may be applied to a bridge substrate. For example, the shape of the circuit pattern in the circuit board may also be applied to a connecting member (1210, FIG. 13) described below. Accordingly, the circuit board described above may be applied to a package substrate or to an interposer substrate and / or a bridge substrate within the semiconductor package.

[0152] Referring to FIG. 12, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor device (1300).

[0153] The first substrate (1100) may mean a 'package substrate' or a 'circuit board', or may include such meanings. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). Additionally, the external substrate may mean a main board included in an electronic device coupled to the lower part of the first substrate (1100).

[0154] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space for mounting at least one semiconductor device.

[0155] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0156] A second substrate (1200) can be placed on the first substrate (1100).

[0157] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space for mounting at least one semiconductor device. The second substrate (1200) may be connected to at least one semiconductor device (1300). For example, the second substrate (1200) may provide a space for mounting a first semiconductor device (1310) and a second semiconductor device (1320). The second substrate (1200) may electrically connect the first semiconductor device (1310) and the second semiconductor device (1320), and electrically connect the first and second semiconductor devices (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between multiple semiconductor devices and a vertical connection function between a semiconductor device and a package substrate.

[0158] In FIG. 12, two semiconductor devices (1310, 1320) are shown disposed on the second substrate (1200), but this is not limited thereto. For example, one semiconductor device may be disposed on the second substrate (1200), or three or more semiconductor devices may be disposed therein.

[0159] The second substrate (1200) can be placed between at least one semiconductor device (1300) and the first substrate (1100).

[0160] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a stacked structure in a vertical direction on the first substrate (1100) and may have the function of a plurality of logic chips. Having the function of a logic chip may mean having the function of an active device and a passive device. In addition, in the case of an active interposer, it may have the function of an active device. Furthermore, while the active interposer functions as a logic chip, it may perform the function of a signal transmission between the second logic chip placed on top of it and the first substrate (1100).

[0161] According to another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, capacitor, or inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IOT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between multiple terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of an electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for being connected to the semiconductor device (1300) and the main board, respectively, there is a problem in that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complex. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor device (1300). The second substrate (1200) may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device (1300).

[0162] The semiconductor device (1300) may be a logic chip, a memory chip, etc. Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0163] For example, the semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) can electrically connect the two substrates while coupling the second substrate (1200) to the first substrate (1100).

[0164] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor device (1300). The second connection portion (1420) can electrically connect the semiconductor device (1300) while coupling it to the second substrate (1200).

[0165] The semiconductor package may include a third connection portion (1430) disposed on the lower surface of the first substrate (1100). The third connection portion (1430) can electrically connect the first substrate (1100) to the main board while coupling them together.

[0166] At this time, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can electrically connect multiple components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection part (1410), the second connection part (1420), and the third connection part (1430) have the function of electrically connecting multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as an electrically connected part rather than solder or wire.

[0167] Wire bonding may refer to electrically connecting multiple components using a conductor such as gold (Au). Additionally, solder bonding may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. Furthermore, direct metal-to-metal bonding may refer to directly bonding multiple components by applying heat and pressure between them to cause recrystallization without the use of solder, wire, conductive adhesive, etc. And direct metal-to-metal bonding may refer to a bonding method using the second connection part (1420). In this case, the second connection part (1420) may refer to a metal layer formed between multiple components by recrystallization.

[0168] Specifically, the first connection part (1410), the second connection part (1420), and the third connection part (1430) can join multiple components together by a thermal compression bonding method. A thermal compression bonding method may refer to a method of directly joining multiple components by applying heat and pressure to the first connection part (1410), the second connection part (1420), and the third connection part (1430).

[0169] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrode on which the first connection part (1410), the second connection part (1420), and the third connection part (1430) are disposed may be provided with a protrusion extending outwardly away from the insulating layer of the corresponding substrate. The protrusion may extend outwardly from the first substrate (1100) or the second substrate (1200).

[0170] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor device (1300) is disposed among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor device (1300) is reduced, a short circuit may occur between a plurality of second connection portions (1420) that are each connected to a plurality of terminals of the semiconductor device (1300) by a conductive adhesive such as solder. Therefore, the embodiment may perform thermal compression bonding to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion on the electrode of the second substrate (1200) on which the second connection portion (1420) is disposed, in order to secure a degree of alignment, diffusion power, and a diffusion prevention power that prevents an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or substrate.

[0171] Additionally, looking further at FIG. 13, the semiconductor package of the second embodiment may further include a connecting member (1210).

[0172] The connecting member (1210) can be a bridge. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) can function to electrically connect multiple semiconductor devices. Since the semiconductor package and the semiconductor device have a large difference in the width or breadth of their circuit patterns, a buffering role for the circuit pattern is required for electrical connection. The buffering role may mean having an intermediate size between the size of the circuit pattern width or breadth of the semiconductor package and the size of the circuit pattern width or breadth of the semiconductor device.

[0173] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate containing an organic material instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0174] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be disposed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements disposed on the second substrate (1200).

[0175] Referring to FIG. 14, the semiconductor package of the third embodiment may include a second substrate (1200) and a semiconductor device (1300). In this case, the semiconductor package of the third embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0176] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0177] The first connection part (1410) disposed on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0178] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0179] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0180] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0181] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0182] Although the above description has focused on the embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First circuit pattern; A thin film layer disposed on the first circuit pattern above; An insulating layer disposed on the above thin film layer; A second circuit pattern disposed on the insulating layer above; and It includes a via electrode disposed between the second circuit pattern and the first circuit pattern, and The above via electrode penetrates the thin film layer and the insulating layer and is connected to the first circuit pattern, and The above via electrode includes a first via region superimposed along the horizontal direction with the insulating layer and a second via region superimposed along the horizontal direction with the thin film layer, A circuit board in which the widths of the first via region and the second via region are different from each other.

2. In Paragraph 1, The first via region penetrates the insulating layer, and The second via region is a circuit board penetrating the thin film layer.

3. In Paragraph 1, A circuit board in which the minimum width in the first via region is smaller than the maximum width in the second via region.

4. In Paragraph 1, A circuit board comprising: a third via region that penetrates at least a portion of the upper surface of the first circuit pattern, wherein the via electrode comprises the above-mentioned circuit board.

5. In Paragraph 4, A circuit board in which the curvature of the outer surface in the second via region is greater than the curvature in the third via region.

6. In Paragraph 1, A circuit board further comprising a pattern portion having a maximum width greater than that of the first circuit pattern and the second circuit pattern.

7. In Paragraph 6, The above thin film layer is a circuit board spaced apart from the above pattern portion.

8. In Paragraph 1, The above first circuit pattern and the above second circuit pattern are a circuit board comprising a seed layer and a plating layer on the seed layer.

9. In Paragraph 8, In the first circuit pattern above, the plating layer and the seed layer are circuit boards having different widths from each other.

10. In Paragraph 8, A circuit board in which the maximum width of the plating layer in the first circuit pattern is greater than the maximum width of the seed layer.

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